diff --git a/src/config.c b/src/config.c index aa35bd4de..bb68ebdbf 100644 --- a/src/config.c +++ b/src/config.c @@ -537,7 +537,7 @@ load_video(void) } gfxcard = video_get_video_from_internal_name(p); - video_speed = config_get_int(cat, "video_speed", 3); + video_speed = config_get_int(cat, "video_speed", -1); voodoo_enabled = !!config_get_int(cat, "voodoo", 0); } diff --git a/src/machine/m_at_scat.c b/src/machine/m_at_scat.c index 5ee1aaefc..bf8bfdb51 100644 --- a/src/machine/m_at_scat.c +++ b/src/machine/m_at_scat.c @@ -10,7 +10,7 @@ * * Re-worked version based on the 82C235 datasheet and errata. * - * Version: @(#)m_at_scat.c 1.0.8 2018/01/16 + * Version: @(#)m_at_scat.c 1.0.9 2018/01/28 * * Authors: Original by GreatPsycho for PCem. * Fred N. van Kempen, @@ -487,6 +487,7 @@ ics_write(uint8_t idx, uint8_t val) pclog("SCAT: icr_write(%02x, %02x)\n", idx, val); #endif switch (idx) { + case SCAT_DMA_WS_CTL: case SCAT_CLOCK_CTL: case SCAT_PERIPH_CTL: reg_valid = 1; @@ -631,7 +632,7 @@ scat_init(void) for (i=0; i<128; i++) scat_regs[i] = 0xff; scat_regs[SCAT_DMA_WS_CTL] = 0x00; - scat_regs[SCAT_VERSION] = 0x0a; + scat_regs[SCAT_VERSION] = 0x04; scat_regs[SCAT_CLOCK_CTL] = 0x02; scat_regs[SCAT_PERIPH_CTL] = 0x80; scat_regs[SCAT_MISC_STATUS] = 0x37; @@ -717,7 +718,7 @@ scat_init(void) (i<<14) + 0xFC0000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_null, mem_write_nullw, mem_write_nulll, - rom+(i<<14), + rom + ((i << 14) & biosmask), 0, NULL); } diff --git a/src/machine/machine_table.c b/src/machine/machine_table.c index 456290407..c2aaa7b28 100644 --- a/src/machine/machine_table.c +++ b/src/machine/machine_table.c @@ -11,7 +11,7 @@ * NOTES: OpenAT wip for 286-class machine with open BIOS. * PS2_M80-486 wip, pending receipt of TRM's for machine. * - * Version: @(#)machine_table.c 1.0.15 2018/01/25 + * Version: @(#)machine_table.c 1.0.16 2018/01/28 * * Authors: Sarah Walker, * Miran Grca, @@ -105,13 +105,13 @@ machine_t machines[] = { { "[486 ISA] AMI WinBIOS 486", ROM_WIN486, "win486", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 64, 1, 127, machine_at_ali1429_init, NULL, nvr_at_close }, { "[486 ISA] Award 486 clone", ROM_AWARD486_OPTI495, "award486", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 64, 1, 127, machine_at_opti495_init, NULL, nvr_at_close }, { "[486 ISA] DTK PKM-0038S E-2", ROM_DTK486, "dtk486", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 128, 1, 127, machine_at_dtk486_init, NULL, nvr_at_close }, - { "[486 ISA] IBM PS/1 model 2133", ROM_IBMPS1_2133, "ibmps1_2133", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 1, 64, 1, 127, machine_ps1_m2133_init, NULL, nvr_at_close }, + { "[486 ISA] IBM PS/1 model 2133", ROM_IBMPS1_2133, "ibmps1_2133", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 1, 64, 1, 127, machine_ps1_m2133_init, NULL, nvr_at_close }, #ifdef WALTJE { "[486 MCA] IBM PS/2 model 80-486", ROM_IBMPS2_M80_486, "ibmps2_m80-486", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, 1, MACHINE_MCA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC_PS2, 1, 32, 1, 63, machine_ps2_model_80_486_init, NULL, nvr_at_close }, #endif - { "[486 PCI] Rise Computer R418", ROM_R418, "r418", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 255, 1, 127, machine_at_r418_init, NULL, nvr_at_close }, + { "[486 PCI] Rise Computer R418", ROM_R418, "r418", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, 0, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 255, 1, 127, machine_at_r418_init, NULL, nvr_at_close }, #ifdef DEV_BRANCH #ifdef USE_GREENB diff --git a/src/network/net_ne2000.c b/src/network/net_ne2000.c index 4b4db6fde..a2304c375 100644 --- a/src/network/net_ne2000.c +++ b/src/network/net_ne2000.c @@ -6,11 +6,15 @@ * * This file is part of the 86Box distribution. * - * Implementation of an NE2000/RTL8029AS network controller. + * Implementation of the following network controllers: + * - Novell NE1000 (ISA 8-bit) (Dev branch); + * - Novell NE2000 (ISA 16-bit); + * - Realtek RTL8019AS (ISA 16-bit, PnP); + * - Realtek RTL8029AS (PCI). * * NOTE: The file will also implement an NE1000 for 8-bit ISA systems. * - * Version: @(#)net_ne2000.c 1.0.26 2018/01/12 + * Version: @(#)net_ne2000.c 1.0.27 2018/01/26 * * Authors: Fred N. van Kempen, * Peter Grehan, @@ -48,13 +52,24 @@ #include "bswap.h" +enum { + PNP_PHASE_WAIT_FOR_KEY = 0, + PNP_PHASE_CONFIG, + PNP_PHASE_ISOLATION, + PNP_PHASE_SLEEP +}; + + /* ROM BIOS file paths. */ #define ROM_PATH_NE1000 L"roms/network/ne1000/ne1000.rom" #define ROM_PATH_NE2000 L"roms/network/ne2000/ne2000.rom" +#define ROM_PATH_RTL8019 L"roms/network/rtl8019as/rtl8019as.rom" #define ROM_PATH_RTL8029 L"roms/network/rtl8029as/rtl8029as.rom" /* PCI info. */ +#define PNP_VENDID 0x4a8c /* Realtek, Inc */ #define PCI_VENDID 0x10ec /* Realtek, Inc */ +#define PNP_DEVID 0x8019 /* RTL8029AS */ #define PCI_DEVID 0x8029 /* RTL8029AS */ #define PCI_REGSIZE 256 /* size of PCI space */ @@ -67,6 +82,15 @@ #define NE2K_MEMSTART (16*1024) #define NE2K_MEMEND (NE2K_MEMSTART+NE2K_MEMSIZ) +#define NE1K_MEMSIZ (16*1024) +#define NE1K_MEMSTART (8*1024) +#define NE1K_MEMEND (NE1K_MEMSTART+NE1K_MEMSIZ) + +uint8_t pnp_init_key[32] = { 0x6A, 0xB5, 0xDA, 0xED, 0xF6, 0xFB, 0x7D, 0xBE, + 0xDF, 0x6F, 0x37, 0x1B, 0x0D, 0x86, 0xC3, 0x61, + 0xB0, 0x58, 0x2C, 0x16, 0x8B, 0x45, 0xA2, 0xD1, + 0xE8, 0x74, 0x3A, 0x9D, 0xCE, 0xE7, 0x73, 0x39 }; + typedef struct { /* Page 0 */ @@ -205,13 +229,15 @@ typedef struct { uint8_t mem[NE2K_MEMSIZ]; /* on-chip packet memory */ int board; - int is_pci; + int is_pci, is_8bit; const char *name; uint32_t base_address; int base_irq; uint32_t bios_addr, bios_size, bios_mask; + uint8_t pnp_regs[256]; + uint8_t pnp_res_data[256]; bar_t pci_bar[2]; uint8_t pci_regs[PCI_REGSIZE]; int tx_timer_index; @@ -221,8 +247,22 @@ typedef struct { rom_t bios_rom; int card; /* PCI card slot */ int has_bios; + uint8_t pnp_phase; + uint8_t pnp_magic_count; + uint8_t pnp_address; + uint8_t pnp_res_pos; + uint8_t pnp_csn; + uint8_t pnp_activate; + uint8_t pnp_io_check; + uint8_t pnp_csnsav; + uint16_t pnp_read; + uint64_t pnp_id; + uint8_t pnp_id_checksum; + uint8_t pnp_serial_read_pos; + uint8_t pnp_serial_read_pair; + uint8_t pnp_serial_read; - /* RTL8029AS registers */ + /* RTL8019AS/RTL8029AS registers */ uint8_t config0, config2, config3; uint8_t _9346cr; } nic_t; @@ -273,23 +313,37 @@ nic_reset(void *priv) nelog(1, "%s: reset\n", dev->name); - /* Initialize the MAC address area by doubling the physical address */ - dev->macaddr[0] = dev->physaddr[0]; - dev->macaddr[1] = dev->physaddr[0]; - dev->macaddr[2] = dev->physaddr[1]; - dev->macaddr[3] = dev->physaddr[1]; - dev->macaddr[4] = dev->physaddr[2]; - dev->macaddr[5] = dev->physaddr[2]; - dev->macaddr[6] = dev->physaddr[3]; - dev->macaddr[7] = dev->physaddr[3]; - dev->macaddr[8] = dev->physaddr[4]; - dev->macaddr[9] = dev->physaddr[4]; - dev->macaddr[10] = dev->physaddr[5]; - dev->macaddr[11] = dev->physaddr[5]; + if (dev->board >= NE2K_NE2000) { + /* Initialize the MAC address area by doubling the physical address */ + dev->macaddr[0] = dev->physaddr[0]; + dev->macaddr[1] = dev->physaddr[0]; + dev->macaddr[2] = dev->physaddr[1]; + dev->macaddr[3] = dev->physaddr[1]; + dev->macaddr[4] = dev->physaddr[2]; + dev->macaddr[5] = dev->physaddr[2]; + dev->macaddr[6] = dev->physaddr[3]; + dev->macaddr[7] = dev->physaddr[3]; + dev->macaddr[8] = dev->physaddr[4]; + dev->macaddr[9] = dev->physaddr[4]; + dev->macaddr[10] = dev->physaddr[5]; + dev->macaddr[11] = dev->physaddr[5]; - /* ne2k signature */ - for (i=12; i<32; i++) - dev->macaddr[i] = 0x57; + /* ne2k signature */ + for (i=12; i<32; i++) + dev->macaddr[i] = 0x57; + } else { + /* Initialize the MAC address area by doubling the physical address */ + dev->macaddr[0] = dev->physaddr[0]; + dev->macaddr[1] = dev->physaddr[1]; + dev->macaddr[2] = dev->physaddr[2]; + dev->macaddr[3] = dev->physaddr[3]; + dev->macaddr[4] = dev->physaddr[4]; + dev->macaddr[5] = dev->physaddr[5]; + + /* ne1k signature */ + for (i=6; i<16; i++) + dev->macaddr[i] = 0x57; + } /* Zero out registers and memory */ memset(&dev->CR, 0x00, sizeof(dev->CR) ); @@ -362,28 +416,46 @@ chipmem_read(nic_t *dev, uint32_t addr, unsigned int len) } /* ROM'd MAC address */ - if (addr <= 31) { - retval = dev->macaddr[addr % 32]; - if ((len == 2) || (len == 4)) { - retval |= (dev->macaddr[(addr + 1) % 32] << 8); - } - if (len == 4) { - retval |= (dev->macaddr[(addr + 2) % 32] << 16); - retval |= (dev->macaddr[(addr + 3) % 32] << 24); - } - return(retval); - } + if (dev->board >= NE2K_NE2000) { + if (addr <= 31) { + retval = dev->macaddr[addr % 32]; + if ((len == 2) || (len == 4)) { + retval |= (dev->macaddr[(addr + 1) % 32] << 8); + } + if (len == 4) { + retval |= (dev->macaddr[(addr + 2) % 32] << 16); + retval |= (dev->macaddr[(addr + 3) % 32] << 24); + } + return(retval); + } - if ((addr >= NE2K_MEMSTART) && (addr < NE2K_MEMEND)) { - retval = dev->mem[addr - NE2K_MEMSTART]; - if ((len == 2) || (len == 4)) { - retval |= (dev->mem[addr - NE2K_MEMSTART + 1] << 8); - } - if (len == 4) { - retval |= (dev->mem[addr - NE2K_MEMSTART + 2] << 16); - retval |= (dev->mem[addr - NE2K_MEMSTART + 3] << 24); - } - return(retval); + if ((addr >= NE2K_MEMSTART) && (addr < NE2K_MEMEND)) { + retval = dev->mem[addr - NE2K_MEMSTART]; + if ((len == 2) || (len == 4)) { + retval |= (dev->mem[addr - NE2K_MEMSTART + 1] << 8); + } + if (len == 4) { + retval |= (dev->mem[addr - NE2K_MEMSTART + 2] << 16); + retval |= (dev->mem[addr - NE2K_MEMSTART + 3] << 24); + } + return(retval); + } + } else { + if (addr <= 15) { + retval = dev->macaddr[addr % 16]; + if (len == 2) { + retval |= (dev->macaddr[(addr + 1) % 16] << 8); + } + return(retval); + } + + if ((addr >= NE1K_MEMSTART) && (addr < NE1K_MEMEND)) { + retval = dev->mem[addr - NE1K_MEMSTART]; + if (len == 2) { + retval |= (dev->mem[addr - NE1K_MEMSTART + 1] << 8); + } + return(retval); + } } nelog(3, "%s: out-of-bounds chipmem read, %04X\n", dev->name, addr); @@ -410,17 +482,28 @@ chipmem_write(nic_t *dev, uint32_t addr, uint32_t val, unsigned len) nelog(3, "%s: unaligned chipmem word write\n", dev->name); } - if ((addr >= NE2K_MEMSTART) && (addr < NE2K_MEMEND)) { - dev->mem[addr-NE2K_MEMSTART] = val & 0xff; - if ((len == 2) || (len == 4)) { - dev->mem[addr-NE2K_MEMSTART+1] = val >> 8; - } - if (len == 4) { - dev->mem[addr-NE2K_MEMSTART+2] = val >> 16; - dev->mem[addr-NE2K_MEMSTART+3] = val >> 24; + if (dev->board >= NE2K_NE2000) { + if ((addr >= NE2K_MEMSTART) && (addr < NE2K_MEMEND)) { + dev->mem[addr-NE2K_MEMSTART] = val & 0xff; + if ((len == 2) || (len == 4)) { + dev->mem[addr-NE2K_MEMSTART+1] = val >> 8; + } + if (len == 4) { + dev->mem[addr-NE2K_MEMSTART+2] = val >> 16; + dev->mem[addr-NE2K_MEMSTART+3] = val >> 24; + } + } else { + nelog(3, "%s: out-of-bounds chipmem write, %04X\n", dev->name, addr); } } else { - nelog(3, "%s: out-of-bounds chipmem write, %04X\n", dev->name, addr); + if ((addr >= NE1K_MEMSTART) && (addr < NE1K_MEMEND)) { + dev->mem[addr-NE1K_MEMSTART] = val & 0xff; + if (len == 2) { + dev->mem[addr-NE1K_MEMSTART+1] = val >> 8; + } + } else { + nelog(3, "%s: out-of-bounds chipmem write, %04X\n", dev->name, addr); + } } } @@ -622,7 +705,9 @@ page0_read(nic_t *dev, uint32_t off, unsigned int len) break; case 0x0a: /* reserved / RTL8029ID0 */ - if (dev->is_pci) { + if (dev->board == NE2K_RTL8019AS) { + retval = 0x50; + } else if (dev->board == NE2K_RTL8029AS) { retval = 0x50; } else { nelog(3, "%s: reserved Page0 read - 0x0a\n", dev->name); @@ -631,7 +716,9 @@ page0_read(nic_t *dev, uint32_t off, unsigned int len) break; case 0x0b: /* reserved / RTL8029ID1 */ - if (dev->is_pci) { + if (dev->board == NE2K_RTL8019AS) { + retval = 0x70; + } else if (dev->board == NE2K_RTL8029AS) { retval = 0x43; } else { nelog(3, "%s: reserved Page0 read - 0x0b\n", dev->name); @@ -1110,7 +1197,7 @@ page2_write(nic_t *dev, uint32_t off, uint32_t val, unsigned len) static uint32_t page3_read(nic_t *dev, uint32_t off, unsigned int len) { - if (dev->board == NE2K_RTL8029AS) switch(off) { + if (dev->board >= NE2K_RTL8019AS) switch(off) { case 0x1: /* 9346CR */ return(dev->_9346cr); @@ -1123,6 +1210,9 @@ page3_read(nic_t *dev, uint32_t off, unsigned int len) case 0x6: /* CONFIG3 */ return(dev->config3 & 0x46); + case 0x8: /* CSNSAV */ + return((dev->board == NE2K_RTL8019AS) ? dev->pnp_csnsav : 0x00); + case 0xe: /* 8029ASID0 */ return(0x29); @@ -1141,7 +1231,7 @@ page3_read(nic_t *dev, uint32_t off, unsigned int len) static void page3_write(nic_t *dev, uint32_t off, uint32_t val, unsigned len) { - if (dev->board == NE2K_RTL8029AS) { + if (dev->board >= NE2K_RTL8019AS) { nelog(3, "%s: Page2 write to register 0x%02x, len=%u, value=0x%04x\n", dev->name, off, len, val); @@ -1232,12 +1322,18 @@ write_cr(nic_t *dev, uint32_t val) nelog(3, "%s: loop mode %d not supported\n", dev->name, dev->TCR.loop_cntl); } else { - nic_rx(dev, - &dev->mem[dev->tx_page_start*256 - NE2K_MEMSTART], - dev->tx_bytes); + if (dev->board >= NE2K_NE2000) { + nic_rx(dev, + &dev->mem[dev->tx_page_start*256 - NE2K_MEMSTART], + dev->tx_bytes); + } else { + nic_rx(dev, + &dev->mem[dev->tx_page_start*256 - NE1K_MEMSTART], + dev->tx_bytes); + } } } else if (val & 0x04) { - if (dev->CR.stop || (!dev->CR.start && !dev->is_pci)) { + if (dev->CR.stop || (!dev->CR.start && (dev->board < NE2K_RTL8019AS))) { if (dev->tx_bytes == 0) /* njh@bandsman.co.uk */ { return; /* Solaris9 probe */ } @@ -1249,8 +1345,13 @@ write_cr(nic_t *dev, uint32_t val) /* Send the packet to the system driver */ dev->CR.tx_packet = 1; - network_tx(&dev->mem[dev->tx_page_start*256 - NE2K_MEMSTART], - dev->tx_bytes); + if (dev->board >= NE2K_NE2000) { + network_tx(&dev->mem[dev->tx_page_start*256 - NE2K_MEMSTART], + dev->tx_bytes); + } else { + network_tx(&dev->mem[dev->tx_page_start*256 - NE1K_MEMSTART], + dev->tx_bytes); + } /* some more debug */ if (dev->tx_timer_active) @@ -1404,6 +1505,334 @@ nic_writel(uint16_t addr, uint32_t val, void *priv) } +static void nic_iocheckset(nic_t *dev, uint16_t addr); +static void nic_iocheckremove(nic_t *dev, uint16_t addr); +static void nic_ioset(nic_t *dev, uint16_t addr); +static void nic_ioremove(nic_t *dev, uint16_t addr); + + +static uint8_t +nic_pnp_io_check_readb(uint16_t addr, void *priv) +{ + nic_t *dev = (nic_t *) priv; + + return((dev->pnp_io_check & 0x01) ? 0x55 : 0xAA); +} + + +static uint8_t +nic_pnp_readb(uint16_t addr, void *priv) +{ + nic_t *dev = (nic_t *) priv; + uint8_t bit, next_shift; + uint8_t ret = 0xFF; + + /* Plug and Play Registers */ + switch(dev->pnp_address) { + /* Card Control Registers */ + case 0x01: /* Serial Isolation */ + if (dev->pnp_phase != PNP_PHASE_ISOLATION) { + ret = 0x00; + break; + } + if (dev->pnp_serial_read_pair) { + dev->pnp_serial_read <<= 1; + /* TODO: Support for multiple PnP devices. + if (pnp_get_bus_data() != dev->pnp_serial_read) + dev->pnp_phase = PNP_PHASE_SLEEP; + } else { + */ + if (!dev->pnp_serial_read_pos) { + dev->pnp_res_pos = 0x1B; + dev->pnp_phase = PNP_PHASE_CONFIG; + nelog(1, "\nASSIGN CSN phase\n"); + } + } else { + if (dev->pnp_serial_read_pos < 64) { + bit = (dev->pnp_id >> dev->pnp_serial_read_pos) & 0x01; + next_shift = (!!(dev->pnp_id_checksum & 0x02) ^ !!(dev->pnp_id_checksum & 0x01) ^ bit) & 0x01; + dev->pnp_id_checksum >>= 1; + dev->pnp_id_checksum |= (next_shift << 7); + } else { + if (dev->pnp_serial_read_pos == 64) + dev->eeprom[0x1A] = dev->pnp_id_checksum; + bit = (dev->pnp_id_checksum >> (dev->pnp_serial_read_pos & 0x07)) & 0x01; + } + dev->pnp_serial_read = bit ? 0x55 : 0x00; + dev->pnp_serial_read_pos = (dev->pnp_serial_read_pos + 1) % 72; + } + dev->pnp_serial_read_pair ^= 1; + ret = dev->pnp_serial_read; + break; + case 0x04: /* Resource Data */ + ret = dev->eeprom[dev->pnp_res_pos]; + dev->pnp_res_pos++; + break; + case 0x05: /* Status */ + ret = 0x01; + break; + case 0x06: /* Card Select Number (CSN) */ + nelog(1, "Card Select Number (CSN)\n"); + ret = dev->pnp_csn; + break; + case 0x07: /* Logical Device Number */ + nelog(1, "Logical Device Number\n"); + ret = 0x00; + break; + case 0x30: /* Activate */ + nelog(1, "Activate\n"); + ret = dev->pnp_activate; + break; + case 0x31: /* I/O Range Check */ + nelog(1, "I/O Range Check\n"); + ret = dev->pnp_io_check; + break; + + /* Logical Device Configuration Registers */ + /* Memory Configuration Registers + We currently force them to stay 0x00 because we currently do not + support a RTL8019AS BIOS. */ + case 0x40: /* BROM base address bits[23:16] */ + case 0x41: /* BROM base address bits[15:0] */ + case 0x42: /* Memory Control */ + ret = 0x00; + break; + + /* I/O Configuration Registers */ + case 0x60: /* I/O base address bits[15:8] */ + ret = (dev->base_address >> 8); + break; + case 0x61: /* I/O base address bits[7:0] */ + ret = (dev->base_address & 0xFF); + break; + + /* Interrupt Configuration Registers */ + case 0x70: /* IRQ level */ + ret = dev->base_irq; + break; + case 0x71: /* IRQ type */ + ret = 0x02; /* high, edge */ + break; + + /* DMA Configuration Registers */ + case 0x74: /* DMA channel select 0 */ + case 0x75: /* DMA channel select 1 */ + ret = 0x04; /* indicating no DMA channel is needed */ + break; + + /* Vendor Defined Registers */ + case 0xF0: /* CONFIG0 */ + case 0xF1: /* CONFIG1 */ + ret = 0x00; + break; + case 0xF2: /* CONFIG2 */ + ret = (dev->config2 & 0xe0); + break; + case 0xF3: /* CONFIG3 */ + ret = (dev->config3 & 0x46); + break; + case 0xF5: /* CSNSAV */ + ret = (dev->pnp_csnsav); + break; + } + + nelog(1, "nic_pnp_readb(%04X) = %02X\n", addr, ret); + return(ret); +} + + +static void nic_pnp_io_set(nic_t *dev, uint16_t read_addr); +static void nic_pnp_io_remove(nic_t *dev); + + +static void +nic_pnp_writeb(uint16_t addr, uint8_t val, void *priv) +{ + nic_t *dev = (nic_t *) priv; + uint16_t new_addr = 0; + + nelog(1, "nic_pnp_writeb(%04X, %02X)\n", addr, val); + + /* Plug and Play Registers */ + switch(dev->pnp_address) { + /* Card Control Registers */ + case 0x00: /* Set RD_DATA port */ + new_addr = val; + new_addr <<= 2; + new_addr |= 3; + nic_pnp_io_remove(dev); + nic_pnp_io_set(dev, new_addr); + nelog(1, "PnP read data address now: %04X\n", new_addr); + break; + case 0x02: /* Config Control */ + if (val & 0x01) { + /* Reset command */ + nic_pnp_io_remove(dev); + memset(dev->pnp_regs, 0, 256); + nelog(1, "All logical devices reset\n"); + } + if (val & 0x02) { + /* Wait for Key command */ + dev->pnp_phase = PNP_PHASE_WAIT_FOR_KEY; + nelog(1, "WAIT FOR KEY phase\n"); + } + if (val & 0x04) { + /* PnP Reset CSN command */ + dev->pnp_csn = dev->pnp_csnsav = 0; + nelog(1, "CSN reset\n"); + } + break; + case 0x03: /* Wake[CSN] */ + nelog(1, "Wake[%02X]\n", val); + if (val == dev->pnp_csn) { + dev->pnp_res_pos = 0x12; + dev->pnp_id_checksum = 0x6A; + if (dev->pnp_phase == PNP_PHASE_SLEEP) { + dev->pnp_phase = val ? PNP_PHASE_CONFIG : PNP_PHASE_ISOLATION; + } + } else { + if ((dev->pnp_phase == PNP_PHASE_CONFIG) || (dev->pnp_phase == PNP_PHASE_ISOLATION)) + dev->pnp_phase = PNP_PHASE_SLEEP; + } + break; + case 0x06: /* Card Select Number (CSN) */ + dev->pnp_csn = dev->pnp_csnsav = val; + dev->pnp_phase = PNP_PHASE_CONFIG; + nelog(1, "CSN set to %02X\n", dev->pnp_csn); + break; + case 0x30: /* Activate */ + if ((dev->pnp_activate ^ val) & 0x01) { + nic_ioremove(dev, dev->base_address); + if (val & 0x01) + nic_ioset(dev, dev->base_address); + + nelog(1, "I/O range %sabled\n", val & 0x02 ? "en" : "dis"); + } + dev->pnp_activate = val; + break; + case 0x31: /* I/O Range Check */ + if ((dev->pnp_io_check ^ val) & 0x02) { + nic_iocheckremove(dev, dev->base_address); + if (val & 0x02) + nic_iocheckset(dev, dev->base_address); + + nelog(1, "I/O range check %sabled\n", val & 0x02 ? "en" : "dis"); + } + dev->pnp_io_check = val; + break; + + /* Logical Device Configuration Registers */ + /* Memory Configuration Registers + We currently force them to stay 0x00 because we currently do not + support a RTL8019AS BIOS. */ + + /* I/O Configuration Registers */ + case 0x60: /* I/O base address bits[15:8] */ + if ((dev->pnp_activate & 0x01) || (dev->pnp_io_check & 0x02)) + nic_ioremove(dev, dev->base_address); + dev->base_address &= 0x00ff; + dev->base_address |= (((uint16_t) val) << 8); + if ((dev->pnp_activate & 0x01) || (dev->pnp_io_check & 0x02)) + nic_ioset(dev, dev->base_address); + nelog(1, "Base address now: %04X\n", dev->base_address); + break; + case 0x61: /* I/O base address bits[7:0] */ + if ((dev->pnp_activate & 0x01) || (dev->pnp_io_check & 0x02)) + nic_ioremove(dev, dev->base_address); + dev->base_address &= 0xff00; + dev->base_address |= val; + if ((dev->pnp_activate & 0x01) || (dev->pnp_io_check & 0x02)) + nic_ioset(dev, dev->base_address); + nelog(1, "Base address now: %04X\n", dev->base_address); + break; + + /* Interrupt Configuration Registers */ + case 0x70: /* IRQ level */ + dev->base_irq = val; + nelog(1, "IRQ now: %02i\n", dev->base_irq); + break; + + /* Vendor Defined Registers */ + case 0xF6: /* Vendor Control */ + dev->pnp_csn = 0; + break; + } + return; +} + + +static void +nic_pnp_io_set(nic_t *dev, uint16_t read_addr) +{ + io_sethandler(0x0A79, 1, + NULL, NULL, NULL, + nic_pnp_writeb, NULL, NULL, dev); + if ((read_addr >= 0x0200) && (read_addr <= 0x03FF)) { + io_sethandler(read_addr, 1, + nic_pnp_readb, NULL, NULL, + NULL, NULL, NULL, dev); + } + dev->pnp_read = read_addr; +} + + +static void +nic_pnp_io_remove(nic_t *dev) +{ + io_removehandler(0x0A79, 1, + NULL, NULL, NULL, + nic_pnp_writeb, NULL, NULL, dev); + io_removehandler(dev->pnp_read, 1, + nic_pnp_readb, NULL, NULL, + NULL, NULL, NULL, dev); +} + + +static void +nic_pnp_address_writeb(uint16_t addr, uint8_t val, void *priv) +{ + nic_t *dev = (nic_t *) priv; + + /* nelog(1, "nic_pnp_address_writeb(%04X, %02X)\n", addr, val); */ + + switch(dev->pnp_phase) { + case PNP_PHASE_WAIT_FOR_KEY: + if (val == pnp_init_key[dev->pnp_magic_count]) { + dev->pnp_magic_count = (dev->pnp_magic_count + 1) & 0x1f; + if (!dev->pnp_magic_count) { + nic_pnp_io_remove(dev); + nic_pnp_io_set(dev, dev->pnp_read); + dev->pnp_phase = PNP_PHASE_SLEEP; + } + } else + dev->pnp_magic_count = 0; + break; + default: + dev->pnp_address = val; + break; + } + return; +} + + +static void +nic_iocheckset(nic_t *dev, uint16_t addr) +{ + io_sethandler(addr, 32, + nic_pnp_io_check_readb, NULL, NULL, + NULL, NULL, NULL, dev); +} + + +static void +nic_iocheckremove(nic_t *dev, uint16_t addr) +{ + io_removehandler(addr, 32, + nic_pnp_io_check_readb, NULL, NULL, + NULL, NULL, NULL, dev); +} + + static void nic_ioset(nic_t *dev, uint16_t addr) { @@ -1419,20 +1848,26 @@ nic_ioset(nic_t *dev, uint16_t addr) nic_writeb, nic_writew, nic_writel, dev); } else { io_sethandler(addr, 16, + nic_readb, NULL, NULL, + nic_writeb, NULL, NULL, dev); + if (dev->is_8bit) { + io_sethandler(addr+16, 16, nic_readb, NULL, NULL, nic_writeb, NULL, NULL, dev); - io_sethandler(addr+16, 16, + } else { + io_sethandler(addr+16, 16, nic_readb, nic_readw, NULL, nic_writeb, nic_writew, NULL, dev); + } io_sethandler(addr+0x1f, 1, - nic_readb, NULL, NULL, - nic_writeb, NULL, NULL, dev); + nic_readb, NULL, NULL, + nic_writeb, NULL, NULL, dev); } } static void -nic_ioremove(nic_t *dev, int16_t addr) +nic_ioremove(nic_t *dev, uint16_t addr) { if (dev->is_pci) { io_removehandler(addr, 16, @@ -1448,9 +1883,15 @@ nic_ioremove(nic_t *dev, int16_t addr) io_removehandler(addr, 16, nic_readb, NULL, NULL, nic_writeb, NULL, NULL, dev); - io_removehandler(addr+16, 16, - nic_readb, nic_readw, NULL, - nic_writeb, nic_writew, NULL, dev); + if (dev->is_8bit) { + io_removehandler(addr+16, 16, + nic_readb, NULL, NULL, + nic_writeb, NULL, NULL, dev); + } else { + io_removehandler(addr+16, 16, + nic_readb, nic_readw, NULL, + nic_writeb, nic_writew, NULL, dev); + } io_removehandler(addr+0x1f, 1, nic_readb, NULL, NULL, nic_writeb, NULL, NULL, dev); @@ -1858,7 +2299,10 @@ nic_rx(void *priv, uint8_t *buf, int io_len) dev->name, pkthdr[0], pkthdr[1], pkthdr[2], pkthdr[3]); /* Copy into buffer, update curpage, and signal interrupt if config'd */ - startptr = &dev->mem[(dev->curr_page * 256) - NE2K_MEMSTART]; + if (dev->board >= NE2K_NE2000) + startptr = &dev->mem[(dev->curr_page * 256) - NE2K_MEMSTART]; + else + startptr = &dev->mem[(dev->curr_page * 256) - NE1K_MEMSTART]; memcpy(startptr, pkthdr, sizeof(pkthdr)); if ((nextpage > dev->curr_page) || ((dev->curr_page + pages) == dev->page_stop)) { @@ -1866,7 +2310,10 @@ nic_rx(void *priv, uint8_t *buf, int io_len) } else { endbytes = (dev->page_stop - dev->curr_page) * 256; memcpy(startptr+sizeof(pkthdr), buf, endbytes-sizeof(pkthdr)); - startptr = &dev->mem[(dev->page_start * 256) - NE2K_MEMSTART]; + if (dev->board >= NE2K_NE2000) + startptr = &dev->mem[(dev->page_start * 256) - NE2K_MEMSTART]; + else + startptr = &dev->mem[(dev->page_start * 256) - NE1K_MEMSTART]; memcpy(startptr, buf+endbytes-sizeof(pkthdr), io_len-endbytes+8); } dev->curr_page = nextpage; @@ -1930,6 +2377,9 @@ nic_init(device_t *info) #ifdef ENABLE_NIC_LOG int i; #endif + int c; + char *ansi_id = "REALTEK PLUG & PLAY ETHERNET CARD"; + uint64_t *eeprom_pnp_id; /* Get the desired debug level. */ #ifdef ENABLE_NIC_LOG @@ -1943,112 +2393,57 @@ nic_init(device_t *info) dev->board = info->local; rom = NULL; switch(dev->board) { -#if defined(DEV_BRANCH) && defined(USE_NE1000) case NE2K_NE1000: - dev->maclocal[0] = 0x00; /* 00:00:D8 (NE1000 ISA OID) */ + case NE2K_NE2000: + dev->is_8bit = 1; + dev->maclocal[0] = 0x00; /* 00:00:D8 (Novell OID) */ dev->maclocal[1] = 0x00; dev->maclocal[2] = 0xD8; - rom = ROM_PATH_NE1000; - break; -#endif - - case NE2K_NE2000: - dev->maclocal[0] = 0x00; /* 00:A0:0C (NE2000 compatible OID) */ - dev->maclocal[1] = 0xA0; - dev->maclocal[2] = 0x0C; - rom = ROM_PATH_NE2000; + rom = (dev->board == NE2K_NE1000) ? NULL : ROM_PATH_NE2000; break; + case NE2K_RTL8019AS: case NE2K_RTL8029AS: - dev->is_pci = (PCI) ? 1 : 0; - dev->maclocal[0] = 0x00; /* 00:20:18 (RTL 8029AS PCI OID) */ - dev->maclocal[1] = 0x20; - dev->maclocal[2] = 0x18; - rom = ROM_PATH_RTL8029; + dev->is_pci = (dev->board == NE2K_RTL8029AS) ? 1 : 0; + dev->maclocal[0] = 0x00; /* 00:E0:4C (Realtek OID) */ + dev->maclocal[1] = 0xE0; + dev->maclocal[2] = 0x4C; + rom = (dev->board == NE2K_RTL8019AS) ? ROM_PATH_RTL8019 : ROM_PATH_RTL8029; break; } - if (dev->is_pci) { + if (dev->board >= NE2K_RTL8019AS) { dev->base_address = 0x340; - dev->base_irq = 10; - dev->bios_addr = 0xD0000; - dev->has_bios = device_get_config_int("bios"); + dev->base_irq = 12; + if (dev->board == NE2K_RTL8029AS) { + dev->bios_addr = 0xD0000; + dev->has_bios = device_get_config_int("bios"); + } else { + dev->bios_addr = 0x00000; + dev->has_bios = 0; + } } else { dev->base_address = device_get_config_hex16("base"); dev->base_irq = device_get_config_int("irq"); - dev->bios_addr = device_get_config_hex20("bios_addr"); - dev->has_bios = !!dev->bios_addr; + if (dev->board == NE2K_NE2000) { + dev->bios_addr = device_get_config_hex20("bios_addr"); + dev->has_bios = !!dev->bios_addr; + } else { + dev->bios_addr = 0x00000; + dev->has_bios = 0; + } } /* See if we have a local MAC address configured. */ mac = device_get_config_mac("mac", -1); /* Make this device known to the I/O system. */ - nic_ioset(dev, dev->base_address); + if (dev->board < NE2K_RTL8019AS) /* PnP and PCI devices start with address spaces inactive. */ + nic_ioset(dev, dev->base_address); /* Set up our BIOS ROM space, if any. */ nic_rom_init(dev, rom); - if (dev->is_pci) { - /* - * Configure the PCI space registers. - * - * We do this here, so the I/O routines are generic. - */ - memset(dev->pci_regs, 0, PCI_REGSIZE); - - dev->pci_regs[0x00] = (PCI_VENDID&0xff); - dev->pci_regs[0x01] = (PCI_VENDID>>8); - dev->pci_regs[0x02] = (PCI_DEVID&0xff); - dev->pci_regs[0x03] = (PCI_DEVID>>8); - - dev->pci_regs[0x04] = 0x03; /* IOEN */ - dev->pci_regs[0x05] = 0x00; - dev->pci_regs[0x07] = 0x02; /* DST0, medium devsel */ - - dev->pci_regs[0x09] = 0x00; /* PIFR */ - - dev->pci_regs[0x0B] = 0x02; /* BCR: Network Controller */ - dev->pci_regs[0x0A] = 0x00; /* SCR: Ethernet */ - - dev->pci_regs[0x2C] = (PCI_VENDID&0xff); - dev->pci_regs[0x2D] = (PCI_VENDID>>8); - dev->pci_regs[0x2E] = (PCI_DEVID&0xff); - dev->pci_regs[0x2F] = (PCI_DEVID>>8); - - dev->pci_regs[0x3D] = PCI_INTA; /* PCI_IPR */ - - /* Enable our address space in PCI. */ - dev->pci_bar[0].addr_regs[0] = 0x01; - - /* Enable our BIOS space in PCI, if needed. */ - if (dev->bios_addr > 0) { - dev->pci_bar[1].addr = 0xFFFF8000; - dev->pci_bar[1].addr_regs[1] = dev->bios_mask; - } else { - dev->pci_bar[1].addr = 0; - dev->bios_size = 0; - } - - mem_mapping_disable(&dev->bios_rom.mapping); - - /* Initialize the RTL8029 EEPROM. */ - memset(dev->eeprom, 0x00, sizeof(dev->eeprom)); - dev->eeprom[0x76] = - dev->eeprom[0x7A] = - dev->eeprom[0x7E] = (PCI_DEVID&0xff); - dev->eeprom[0x77] = - dev->eeprom[0x7B] = - dev->eeprom[0x7F] = (PCI_DEVID>>8); - dev->eeprom[0x78] = - dev->eeprom[0x7C] = (PCI_VENDID&0xff); - dev->eeprom[0x79] = - dev->eeprom[0x7D] = (PCI_VENDID>>8); - - /* Insert this device onto the PCI bus, keep its slot number. */ - dev->card = pci_add_card(PCI_ADD_NORMAL, nic_pci_read, nic_pci_write, dev); - } - /* Set up our BIA. */ if (mac & 0xff000000) { /* Generate new local MAC. */ @@ -2071,6 +2466,136 @@ nic_init(device_t *info) dev->physaddr[0], dev->physaddr[1], dev->physaddr[2], dev->physaddr[3], dev->physaddr[4], dev->physaddr[5]); + if (dev->board >= NE2K_RTL8019AS) { + if (dev->is_pci) { + /* + * Configure the PCI space registers. + * + * We do this here, so the I/O routines are generic. + */ + memset(dev->pci_regs, 0, PCI_REGSIZE); + + dev->pci_regs[0x00] = (PCI_VENDID&0xff); + dev->pci_regs[0x01] = (PCI_VENDID>>8); + dev->pci_regs[0x02] = (PCI_DEVID&0xff); + dev->pci_regs[0x03] = (PCI_DEVID>>8); + + dev->pci_regs[0x04] = 0x03; /* IOEN */ + dev->pci_regs[0x05] = 0x00; + dev->pci_regs[0x07] = 0x02; /* DST0, medium devsel */ + + dev->pci_regs[0x09] = 0x00; /* PIFR */ + + dev->pci_regs[0x0B] = 0x02; /* BCR: Network Controller */ + dev->pci_regs[0x0A] = 0x00; /* SCR: Ethernet */ + + dev->pci_regs[0x2C] = (PCI_VENDID&0xff); + dev->pci_regs[0x2D] = (PCI_VENDID>>8); + dev->pci_regs[0x2E] = (PCI_DEVID&0xff); + dev->pci_regs[0x2F] = (PCI_DEVID>>8); + + dev->pci_regs[0x3D] = PCI_INTA; /* PCI_IPR */ + + /* Enable our address space in PCI. */ + dev->pci_bar[0].addr_regs[0] = 0x01; + + /* Enable our BIOS space in PCI, if needed. */ + if (dev->bios_addr > 0) { + dev->pci_bar[1].addr = 0xFFFF8000; + dev->pci_bar[1].addr_regs[1] = dev->bios_mask; + } else { + dev->pci_bar[1].addr = 0; + dev->bios_size = 0; + } + + mem_mapping_disable(&dev->bios_rom.mapping); + + /* Insert this device onto the PCI bus, keep its slot number. */ + dev->card = pci_add_card(PCI_ADD_NORMAL, nic_pci_read, nic_pci_write, dev); + } else { + io_sethandler(0x0279, 1, + NULL, NULL, NULL, + nic_pnp_address_writeb, NULL, NULL, dev); + + dev->pnp_id = PNP_DEVID; + dev->pnp_id <<= 32LL; + dev->pnp_id |= PNP_VENDID; + dev->pnp_phase = PNP_PHASE_WAIT_FOR_KEY; + } + + /* Initialize the RTL8029 EEPROM. */ + memset(dev->eeprom, 0x00, sizeof(dev->eeprom)); + + if (dev->board == NE2K_RTL8029AS) { + memcpy(&dev->eeprom[0x02], dev->maclocal, 6); + + dev->eeprom[0x76] = + dev->eeprom[0x7A] = + dev->eeprom[0x7E] = (PCI_DEVID&0xff); + dev->eeprom[0x77] = + dev->eeprom[0x7B] = + dev->eeprom[0x7F] = (dev->board == NE2K_RTL8019AS) ? (PNP_DEVID>>8) : (PCI_DEVID>>8); + dev->eeprom[0x78] = + dev->eeprom[0x7C] = (PCI_VENDID&0xff); + dev->eeprom[0x79] = + dev->eeprom[0x7D] = (PCI_VENDID>>8); + } else { + eeprom_pnp_id = (uint64_t *) &dev->eeprom[0x12]; + *eeprom_pnp_id = dev->pnp_id; + + /* TAG: Plug and Play Version Number */ + dev->eeprom[0x1B] = 0x0A; /* Item byte */ + dev->eeprom[0x1C] = 0x10; /* PnP version */ + dev->eeprom[0x1D] = 0x10; /* Vendor version */ + + /* TAG: ANSI Identifier String */ + dev->eeprom[0x1E] = 0x82; /* Item byte */ + dev->eeprom[0x1F] = 0x22; /* Length bits 7-0 */ + dev->eeprom[0x20] = 0x00; /* Length bits 15-8 */ + memcpy(&dev->eeprom[0x21], ansi_id, 0x22); /* Identifier string */ + + /* TAG: Logical Device ID */ + dev->eeprom[0x43] = 0x16; /* Item byte */ + dev->eeprom[0x44] = 0x4A; /* Logical device ID0 */ + dev->eeprom[0x45] = 0x8C; /* Logical device ID1 */ + dev->eeprom[0x46] = 0x80; /* Logical device ID2 */ + dev->eeprom[0x47] = 0x19; /* Logical device ID3 */ + dev->eeprom[0x48] = 0x02; /* Flag 0 (02 = BROM is disabled) */ + dev->eeprom[0x49] = 0x00; /* Flag 1 */ + + /* TAG: Compatible Device ID (NE2000) */ + dev->eeprom[0x4A] = 0x1C; /* Item byte */ + dev->eeprom[0x4B] = 0x41; /* Compatible ID0 */ + dev->eeprom[0x4C] = 0xD0; /* Compatible ID1 */ + dev->eeprom[0x4D] = 0x80; /* Compatible ID2 */ + dev->eeprom[0x4E] = 0xD6; /* Compatible ID3 */ + + /* TAG: I/O Format */ + dev->eeprom[0x4F] = 0x47; /* Item byte */ + dev->eeprom[0x50] = 0x00; /* I/O information */ + dev->eeprom[0x51] = 0x20; /* Min. I/O base bits 7-0 */ + dev->eeprom[0x52] = 0x02; /* Min. I/O base bits 15-8 */ + dev->eeprom[0x53] = 0x80; /* Max. I/O base bits 7-0 */ + dev->eeprom[0x54] = 0x03; /* Max. I/O base bits 15-8 */ + dev->eeprom[0x55] = 0x20; /* Base alignment */ + dev->eeprom[0x56] = 0x20; /* Range length */ + + /* TAG: IRQ Format */ + dev->eeprom[0x57] = 0x23; /* Item byte */ + dev->eeprom[0x58] = 0x38; /* IRQ mask bits 7-0 */ + dev->eeprom[0x59] = 0x9E; /* IRQ mask bits 15-8 */ + dev->eeprom[0x5A] = 0x01; /* IRQ information */ + + /* TAG: END Tag */ + dev->eeprom[0x5B] = 0x79; /* Item byte */ + for (c = 0x1B; c < 0x5C; c++) /* Checksum (2's complement) */ + dev->eeprom[0x5C] += dev->eeprom[c]; + dev->eeprom[0x5C] = -dev->eeprom[0x5C]; + + nic_pnp_io_set(dev, dev->pnp_read); + } + } + /* Reset the board. */ nic_reset(dev); @@ -2100,7 +2625,6 @@ nic_close(void *priv) } -#if defined(DEV_BRANCH) && defined(USE_NE1000) static device_config_t ne1000_config[] = { { @@ -2149,31 +2673,10 @@ static device_config_t ne1000_config[] = { "mac", "MAC Address", CONFIG_MAC, "", -1 }, - { - "bios_addr", "BIOS address", CONFIG_HEX20, "", 0, - { - { - "Disabled", 0x00000 - }, - { - "D000", 0xD0000 - }, - { - "D800", 0xD8000 - }, - { - "C800", 0xC8000 - }, - { - "" - } - }, - }, { "", "", -1 } }; -#endif static device_config_t ne2000_config[] = { @@ -2254,6 +2757,16 @@ static device_config_t ne2000_config[] = } }; +static device_config_t rtl8019as_config[] = +{ + { + "mac", "MAC Address", CONFIG_MAC, "", -1 + }, + { + "", "", -1 + } +}; + static device_config_t rtl8029as_config[] = { { @@ -2268,26 +2781,33 @@ static device_config_t rtl8029as_config[] = }; -#if defined(DEV_BRANCH) && defined(USE_NE1000) device_t ne1000_device = { "Novell NE1000", - 0, + DEVICE_ISA, NE2K_NE1000, nic_init, nic_close, NULL, NULL, NULL, NULL, NULL, ne1000_config }; -#endif device_t ne2000_device = { "Novell NE2000", - DEVICE_AT, + DEVICE_ISA | DEVICE_AT, NE2K_NE2000, nic_init, nic_close, NULL, NULL, NULL, NULL, NULL, ne2000_config }; +device_t rtl8019as_device = { + "Realtek RTL8019AS", + DEVICE_ISA | DEVICE_AT, + NE2K_RTL8019AS, + nic_init, nic_close, NULL, + NULL, NULL, NULL, NULL, + rtl8019as_config +}; + device_t rtl8029as_device = { "Realtek RTL8029AS", DEVICE_PCI, diff --git a/src/network/net_ne2000.h b/src/network/net_ne2000.h index 44dcc3311..800e62863 100644 --- a/src/network/net_ne2000.h +++ b/src/network/net_ne2000.h @@ -8,7 +8,7 @@ * * Definitions for the NE2000 ethernet controller. * - * Version: @(#)net_ne2000.h 1.0.3 2017/05/17 + * Version: @(#)net_ne2000.h 1.0.4 2018/01/26 * * Author: Fred N. van Kempen, */ @@ -16,13 +16,18 @@ # define NET_NE2000_H -#define NE2K_NE1000 1 /* 8bit ISA NE1000 */ -#define NE2K_NE2000 2 /* 16bit ISA NE2000 */ -#define NE2K_RTL8029AS 3 /* 32bi PCI Realtek 8029AS */ +enum { + NE2K_NONE = 0, + NE2K_NE1000, /* 8bit ISA NE1000 */ + NE2K_NE2000, /* 16bit ISA NE2000 */ + NE2K_RTL8019AS, /* 16bit? ISA? PnP Realtek 8019AS */ + NE2K_RTL8029AS /* 32bit PCI Realtek 8029AS */ +}; extern device_t ne1000_device; extern device_t ne2000_device; +extern device_t rtl8019as_device; extern device_t rtl8029as_device; diff --git a/src/network/network.c b/src/network/network.c index c7d21b494..ec6e2755f 100644 --- a/src/network/network.c +++ b/src/network/network.c @@ -12,11 +12,11 @@ * it should be malloc'ed and then linked to the NETCARD def. * Will be done later. * - * Version: @(#)network.c 1.0.19 2017/11/04 + * Version: @(#)network.c 1.0.20 2018/01/26 * * Author: Fred N. van Kempen, * - * Copyright 2017 Fred N. van Kempen. + * Copyright 2017,2018 Fred N. van Kempen. */ #include #include @@ -34,13 +34,13 @@ static netcard_t net_cards[] = { { "None", "none", NULL, NULL, NULL }, -#if defined(DEV_BRANCH) && defined(USE_NE1000) - { "Novell NE1000", "ne1k", &ne1000_device, + { "[ISA] Novell NE1000", "ne1k", &ne1000_device, NULL, NULL }, -#endif - { "Novell NE2000", "ne2k", &ne2000_device, + { "[ISA] Novell NE2000", "ne2k", &ne2000_device, NULL, NULL }, - { "Realtek RTL8029AS", "ne2kpci", &rtl8029as_device, + { "[ISA] Realtek RTL8019AS", "ne2kpnp", &rtl8019as_device, + NULL, NULL }, + { "[PCI] Realtek RTL8029AS", "ne2kpci", &rtl8029as_device, NULL, NULL }, { "", "", NULL, NULL, NULL } diff --git a/src/network/network.h b/src/network/network.h index df14f20e0..3b25f9cff 100644 --- a/src/network/network.h +++ b/src/network/network.h @@ -8,7 +8,7 @@ * * Definitions for the network module. * - * Version: @(#)network.h 1.0.10 2017/11/01 + * Version: @(#)network.h 1.0.11 2018/01/26 * * Author: Fred N. van Kempen, */ @@ -23,9 +23,13 @@ #define NET_TYPE_SLIRP 2 /* use the SLiRP port forwarder */ /* Supported network cards. */ -#define NE1000 1 -#define NE2000 2 -#define RTL8029AS 3 +enum { + NONE = 0, + NE1000, + NE2000, + RTL8019AS, + RTL8029AS +}; typedef void (*NETRXCB)(void *, uint8_t *, int); diff --git a/src/pc.c b/src/pc.c index a8c494902..411a87c25 100644 --- a/src/pc.c +++ b/src/pc.c @@ -8,7 +8,7 @@ * * Main emulator module where most things are controlled. * - * Version: @(#)pc.c 1.0.54 2018/01/21 + * Version: @(#)pc.c 1.0.55 2018/01/28 * * Authors: Sarah Walker, * Miran Grca, @@ -823,7 +823,7 @@ pc_reset_hard_init(void) mouse_reset(); /* Reset the video card. */ - // video_reset(gfxcard); + video_reset(gfxcard); /* Reset the Hard Disk Controller module. */ hdc_reset(); @@ -881,8 +881,6 @@ pc_reset_hard_init(void) pic_reset(); cpu_cache_int_enabled = cpu_cache_ext_enabled = 0; - video_reset(gfxcard); - if (AT) setpitclock(machines[machine].cpu[cpu_manufacturer].cpus[cpu].rspeed); else diff --git a/src/video/vid_table.c b/src/video/vid_table.c index c73e2a005..49809ae0b 100644 --- a/src/video/vid_table.c +++ b/src/video/vid_table.c @@ -8,7 +8,7 @@ * * Define all known video cards. * - * Version: @(#)vid_table.c 1.0.12 2018/01/25 + * Version: @(#)vid_table.c 1.0.13 2018/01/27 * * Authors: Miran Grca, * Fred N. van Kempen, @@ -68,108 +68,106 @@ #include "vid_wy700.h" +enum { + VIDEO_ISA = 0, + VIDEO_BUS +}; + typedef struct { char name[64]; char internal_name[24]; device_t *device; int legacy_id; + struct { + int type; + int b, w, l; + } timing; } VIDEO_CARD; static VIDEO_CARD video_cards[] = { - { "None", "none", - NULL, GFX_NONE }, - { "Internal", "internal", - NULL, GFX_INTERNAL }, - {"[ISA] ATI Graphics Pro Turbo (Mach64 GX)", "mach64gx_isa", - &mach64gx_isa_device, GFX_MACH64GX_ISA }, - { "[ISA] ATI VGA Charger (ATI-28800-5)", "ati28800", - &ati28800_device, GFX_VGACHARGER }, - { "[ISA] ATI VGA Wonder XL24 (ATI-28800-6)", "ati28800w", - &ati28800_wonderxl24_device, GFX_VGAWONDERXL24 }, - { "[ISA] ATI VGA Edge-16 (ATI-18800)", "ati18800", - &ati18800_device, GFX_VGAEDGE16 }, - { "[ISA] CGA", "cga", - &cga_device, GFX_CGA }, - { "[ISA] Chips & Technologies SuperEGA", "superega", - &sega_device, GFX_SUPER_EGA }, + { "None", "none", NULL, GFX_NONE }, + { "Internal", "internal", NULL, GFX_INTERNAL, {VIDEO_ISA, 8, 16, 32}}, + {"[ISA] ATI Graphics Pro Turbo (Mach64 GX)", "mach64gx_isa", &mach64gx_isa_device, GFX_MACH64GX_ISA, {VIDEO_ISA, 3, 3, 6}}, + { "[ISA] ATI VGA Charger (ATI-28800-5)", "ati28800", &ati28800_device, GFX_VGACHARGER, {VIDEO_ISA, 3, 3, 6}}, + { "[ISA] ATI VGA Wonder XL24 (ATI-28800-6)", "ati28800w", &ati28800_wonderxl24_device, GFX_VGAWONDERXL24, {VIDEO_ISA, 3, 3, 6}}, + { "[ISA] ATI VGA Edge-16 (ATI-18800)", "ati18800", &ati18800_device, GFX_VGAEDGE16, {VIDEO_ISA, 3, 3, 6}}, + { "[ISA] CGA", "cga", &cga_device, GFX_CGA, {VIDEO_ISA, 8, 16, 32}}, + { "[ISA] Chips & Technologies SuperEGA", "superega", &sega_device, GFX_SUPER_EGA, {VIDEO_ISA, 8, 16, 32}}, #if defined(DEV_BRANCH) && defined(USE_CIRRUS) - { "[ISA] Cirrus Logic CL-GD5422", "cl_gd5422", - &gd5422_device, GFX_CL_GD5422 }, - { "[ISA] Cirrus Logic CL-GD5430", "cl_gd5430", - &gd5430_device, GFX_CL_GD5430 }, - { "[ISA] Cirrus Logic CL-GD5434", "cl_gd5434", &gd5434_device, GFX_CL_GD5434 }, - { "[ISA] Cirrus Logic CL-GD5436", "cl_gd5436", &gd5436_device, GFX_CL_GD5436 }, - { "[ISA] Cirrus Logic CL-GD5440", "cl_gd5440", &gd5440_device, GFX_CL_GD5440 }, + { "[ISA] Cirrus Logic CL-GD5422", "cl_gd5422", &gd5422_device, GFX_CL_GD5422, {VIDEO_ISA, 6, 8, 16}}, + { "[ISA] Cirrus Logic CL-GD5430", "cl_gd5430", &gd5430_device, GFX_CL_GD5430, {VIDEO_ISA, 3, 3, 6}}, + { "[ISA] Cirrus Logic CL-GD5434", "cl_gd5434", &gd5434_device, GFX_CL_GD5434, {VIDEO_ISA, 3, 3, 6}}, + { "[ISA] Cirrus Logic CL-GD5436", "cl_gd5436", &gd5436_device, GFX_CL_GD5436, {VIDEO_ISA, 3, 3, 6}}, + { "[ISA] Cirrus Logic CL-GD5440", "cl_gd5440", &gd5440_device, GFX_CL_GD5440, {VIDEO_ISA, 3, 3, 6}}, #endif - { "[ISA] Compaq ATI VGA Wonder XL (ATI-28800-5)","compaq_ati28800", &compaq_ati28800_device, GFX_VGAWONDERXL }, - { "[ISA] Compaq CGA", "compaq_cga", &compaq_cga_device, GFX_COMPAQ_CGA }, - { "[ISA] Compaq CGA 2", "compaq_cga_2", &compaq_cga_2_device, GFX_COMPAQ_CGA_2 }, - { "[ISA] Compaq EGA", "compaq_ega", &cpqega_device, GFX_COMPAQ_EGA }, - { "[ISA] EGA", "ega", &ega_device, GFX_EGA }, - { "[ISA] Hercules", "hercules", &hercules_device, GFX_HERCULES }, - { "[ISA] Hercules Plus", "hercules_plus", &herculesplus_device, GFX_HERCULESPLUS }, - { "[ISA] Hercules InColor", "incolor", &incolor_device, GFX_INCOLOR }, - { "[ISA] MDA", "mda", &mda_device, GFX_MDA }, - { "[ISA] MDSI Genius", "genius", &genius_device, GFX_GENIUS }, - { "[ISA] OAK OTI-067", "oti067", &oti067_device, GFX_OTI067 }, - { "[ISA] OAK OTI-077", "oti077", &oti077_device, GFX_OTI077 }, - { "[ISA] Paradise PVGA1A", "pvga1a", ¶dise_pvga1a_device, GFX_PVGA1A }, - { "[ISA] Paradise WD90C11-LR", "wd90c11", ¶dise_wd90c11_device, GFX_WD90C11 }, - { "[ISA] Paradise WD90C30-LR", "wd90c30", ¶dise_wd90c30_device, GFX_WD90C30 }, - { "[ISA] Plantronics ColorPlus", "plantronics", &colorplus_device, GFX_COLORPLUS }, + { "[ISA] Compaq ATI VGA Wonder XL (ATI-28800-5)","compaq_ati28800", &compaq_ati28800_device, GFX_VGAWONDERXL, {VIDEO_ISA, 3, 3, 6}}, + { "[ISA] Compaq CGA", "compaq_cga", &compaq_cga_device, GFX_COMPAQ_CGA, {VIDEO_ISA, 8, 16, 32}}, + { "[ISA] Compaq CGA 2", "compaq_cga_2", &compaq_cga_2_device, GFX_COMPAQ_CGA_2, {VIDEO_ISA, 8, 16, 32}}, + { "[ISA] Compaq EGA", "compaq_ega", &cpqega_device, GFX_COMPAQ_EGA, {VIDEO_ISA, 8, 16, 32}}, + { "[ISA] EGA", "ega", &ega_device, GFX_EGA, {VIDEO_ISA, 8, 16, 32}}, + { "[ISA] Hercules", "hercules", &hercules_device, GFX_HERCULES, {VIDEO_ISA, 8, 16, 32}}, + { "[ISA] Hercules Plus", "hercules_plus", &herculesplus_device, GFX_HERCULESPLUS, {VIDEO_ISA, 8, 16, 32}}, + { "[ISA] Hercules InColor", "incolor", &incolor_device, GFX_INCOLOR, {VIDEO_ISA, 8, 16, 32}}, + { "[ISA] MDA", "mda", &mda_device, GFX_MDA, {VIDEO_ISA, 8, 16, 32}}, + { "[ISA] MDSI Genius", "genius", &genius_device, GFX_GENIUS, {VIDEO_ISA, 8, 16, 32}}, + { "[ISA] OAK OTI-067", "oti067", &oti067_device, GFX_OTI067, {VIDEO_ISA, 6, 8, 16}}, + { "[ISA] OAK OTI-077", "oti077", &oti077_device, GFX_OTI077, {VIDEO_ISA, 6, 8, 16}}, + { "[ISA] Paradise PVGA1A", "pvga1a", ¶dise_pvga1a_device, GFX_PVGA1A, {VIDEO_ISA, 8, 16, 32}}, + { "[ISA] Paradise WD90C11-LR", "wd90c11", ¶dise_wd90c11_device, GFX_WD90C11, {VIDEO_ISA, 8, 16, 32}}, + { "[ISA] Paradise WD90C30-LR", "wd90c30", ¶dise_wd90c30_device, GFX_WD90C30, {VIDEO_ISA, 6, 8, 16}}, + { "[ISA] Plantronics ColorPlus", "plantronics", &colorplus_device, GFX_COLORPLUS, {VIDEO_ISA, 8, 16, 32}}, #if defined(DEV_BRANCH) && defined(USE_TI) - {"[ISA] TI CF62011 SVGA", "ti_cf62011", - &ti_cf62011_device, GFX_TICF62011 }, + {"[ISA] TI CF62011 SVGA", "ti_cf62011", &ti_cf62011_device, GFX_TICF62011, {VIDEO_ISA, 8, 16, 32}}, #endif - { "[ISA] Trident TVGA8900D", "tvga8900d", &tvga8900d_device, GFX_TVGA }, - { "[ISA] Tseng ET4000AX", "et4000ax", &et4000_device, GFX_ET4000 }, - {"[ISA] VGA", "vga", &vga_device, GFX_VGA }, - {"[ISA] Wyse 700", "wy700", &wy700_device, GFX_WY700 }, - {"[PCI] ATI Graphics Pro Turbo (Mach64 GX)", "mach64gx_pci", &mach64gx_pci_device, GFX_MACH64GX_PCI }, - {"[PCI] ATI Video Xpression (Mach64 VT2)", "mach64vt2", &mach64vt2_device, GFX_MACH64VT2 }, - {"[PCI] Cardex Tseng ET4000/w32p", "et4000w32p_pci", &et4000w32p_cardex_pci_device, GFX_ET4000W32_CARDEX_PCI }, + { "[ISA] Trident TVGA8900D", "tvga8900d", &tvga8900d_device, GFX_TVGA, {VIDEO_ISA, 3, 3, 6}}, + { "[ISA] Tseng ET4000AX", "et4000ax", &et4000_device, GFX_ET4000, {VIDEO_ISA, 3, 3, 6}}, + {"[ISA] VGA", "vga", &vga_device, GFX_VGA, {VIDEO_ISA, 8, 16, 32}}, + {"[ISA] Wyse 700", "wy700", &wy700_device, GFX_WY700, {VIDEO_ISA, 8, 16, 32}}, + {"[PCI] ATI Graphics Pro Turbo (Mach64 GX)", "mach64gx_pci", &mach64gx_pci_device, GFX_MACH64GX_PCI, {VIDEO_BUS, 4, 8, 16}}, + {"[PCI] ATI Video Xpression (Mach64 VT2)", "mach64vt2", &mach64vt2_device, GFX_MACH64VT2, {VIDEO_BUS, 3, 3, 4}}, + {"[PCI] Cardex Tseng ET4000/w32p", "et4000w32p_pci", &et4000w32p_cardex_pci_device, GFX_ET4000W32_CARDEX_PCI, {VIDEO_BUS, 4, 5, 10}}, #if defined(DEV_BRANCH) && defined(USE_STEALTH32) - {"[PCI] Diamond Stealth 32 (Tseng ET4000/w32p)","stealth32_pci", &et4000w32p_pci_device, GFX_ET4000W32_PCI }, + {"[PCI] Diamond Stealth 32 (Tseng ET4000/w32p)","stealth32_pci", &et4000w32p_pci_device, GFX_ET4000W32_PCI, {VIDEO_BUS, 4, 5, 10}}, #endif - {"[PCI] Diamond Stealth 3D 2000 (S3 ViRGE)", "stealth3d_2000_pci", &s3_virge_pci_device, GFX_VIRGE_PCI }, - {"[PCI] Diamond Stealth 3D 3000 (S3 ViRGE/VX)", "stealth3d_3000_pci", &s3_virge_988_pci_device, GFX_VIRGEVX_PCI }, - {"[PCI] Diamond Stealth 64 DRAM (S3 Trio64)", "stealth64d_pci", &s3_diamond_stealth64_pci_device, GFX_STEALTH64_PCI }, + {"[PCI] Diamond Stealth 3D 2000 (S3 ViRGE)", "stealth3d_2000_pci", &s3_virge_pci_device, GFX_VIRGE_PCI, {VIDEO_BUS, 3, 5, 10}}, + {"[PCI] Diamond Stealth 3D 3000 (S3 ViRGE/VX)", "stealth3d_3000_pci", &s3_virge_988_pci_device, GFX_VIRGEVX_PCI, {VIDEO_BUS, 3, 4, 7}}, + {"[PCI] Diamond Stealth 64 DRAM (S3 Trio64)", "stealth64d_pci", &s3_diamond_stealth64_pci_device, GFX_STEALTH64_PCI, {VIDEO_BUS, 3, 4, 7}}, #if defined(DEV_BRANCH) && defined(USE_RIVA) - {"[PCI] nVidia RIVA 128", "riva128", &riva128_device, GFX_RIVA128 }, - {"[PCI] nVidia RIVA TNT", "rivatnt", &rivatnt_device, GFX_RIVATNT }, - {"[PCI] nVidia RIVA TNT2", "rivatnt2", &rivatnt2_device, GFX_RIVATNT2 }, + {"[PCI] nVidia RIVA 128", "riva128", &riva128_device, GFX_RIVA128, {VIDEO_BUS, 2, 3, 4}}, + {"[PCI] nVidia RIVA TNT", "rivatnt", &rivatnt_device, GFX_RIVATNT, {VIDEO_BUS, 2, 3, 4}}, + {"[PCI] nVidia RIVA TNT2", "rivatnt2", &rivatnt2_device, GFX_RIVATNT2, {VIDEO_BUS, 2, 3, 4}}, #endif - {"[PCI] Number Nine 9FX (S3 Trio64)", "n9_9fx_pci", &s3_9fx_pci_device, GFX_N9_9FX_PCI }, - {"[PCI] Paradise Bahamas 64 (S3 Vision864)", "bahamas64_pci", &s3_bahamas64_pci_device, GFX_BAHAMAS64_PCI }, - {"[PCI] Phoenix S3 Vision864", "px_vision864_pci", &s3_phoenix_vision864_pci_device, GFX_PHOENIX_VISION864_PCI }, - {"[PCI] Phoenix S3 Trio32", "px_trio32_pci", &s3_phoenix_trio32_pci_device, GFX_PHOENIX_TRIO32_PCI }, - {"[PCI] Phoenix S3 Trio64", "px_trio64_pci", &s3_phoenix_trio64_pci_device, GFX_PHOENIX_TRIO64_PCI }, - {"[PCI] S3 ViRGE/DX", "virge375_pci", &s3_virge_375_pci_device, GFX_VIRGEDX_PCI }, - {"[PCI] S3 ViRGE/DX (VBE 2.0)", "virge375_vbe20_pci", &s3_virge_375_4_pci_device, GFX_VIRGEDX4_PCI }, - {"[PCI] Trident TGUI9440", "tgui9440_pci", &tgui9440_pci_device, GFX_TGUI9440_PCI }, - {"[VLB] ATI Graphics Pro Turbo (Mach64 GX)", "mach64gx_vlb", &mach64gx_vlb_device, GFX_MACH64GX_VLB }, - {"[VLB] Cardex Tseng ET4000/w32p", "et4000w32p_vlb", &et4000w32p_cardex_vlb_device, GFX_ET4000W32_CARDEX_VLB }, + {"[PCI] Number Nine 9FX (S3 Trio64)", "n9_9fx_pci", &s3_9fx_pci_device, GFX_N9_9FX_PCI, {VIDEO_BUS, 3, 5, 10}}, + {"[PCI] Paradise Bahamas 64 (S3 Vision864)", "bahamas64_pci", &s3_bahamas64_pci_device, GFX_BAHAMAS64_PCI, {VIDEO_BUS, 4, 5, 10}}, + {"[PCI] Phoenix S3 Vision864", "px_vision864_pci", &s3_phoenix_vision864_pci_device, GFX_PHOENIX_VISION864_PCI, {VIDEO_BUS, 3, 5, 10}}, + {"[PCI] Phoenix S3 Trio32", "px_trio32_pci", &s3_phoenix_trio32_pci_device, GFX_PHOENIX_TRIO32_PCI, {VIDEO_BUS, 4, 5, 10}}, + {"[PCI] Phoenix S3 Trio64", "px_trio64_pci", &s3_phoenix_trio64_pci_device, GFX_PHOENIX_TRIO64_PCI, {VIDEO_BUS, 3, 5, 10}}, + {"[PCI] S3 ViRGE/DX", "virge375_pci", &s3_virge_375_pci_device, GFX_VIRGEDX_PCI, {VIDEO_BUS, 2, 3, 4}}, + {"[PCI] S3 ViRGE/DX (VBE 2.0)", "virge375_vbe20_pci", &s3_virge_375_4_pci_device, GFX_VIRGEDX4_PCI, {VIDEO_BUS, 2, 3, 4}}, + {"[PCI] Trident TGUI9440", "tgui9440_pci", &tgui9440_pci_device, GFX_TGUI9440_PCI, {VIDEO_BUS, 4, 8, 16}}, + {"[VLB] ATI Graphics Pro Turbo (Mach64 GX)", "mach64gx_vlb", &mach64gx_vlb_device, GFX_MACH64GX_VLB, {VIDEO_BUS, 4, 8, 16}}, + {"[VLB] Cardex Tseng ET4000/w32p", "et4000w32p_vlb", &et4000w32p_cardex_vlb_device, GFX_ET4000W32_CARDEX_VLB, {VIDEO_BUS, 4, 5, 10}}, #if defined(DEV_BRANCH) && defined(USE_CIRRUS) - {"[VLB] Cirrus Logic CL-GD5429", "cl_gd5429", &gd5429_device, GFX_CL_GD5429 }, - {"[VLB] Cirrus Logic CL-GD5430", "cl_gd5430_vlb", &dia5430_device, GFX_CL_GD5430 }, - {"[VLB] Cirrus Logic CL-GD5446", "cl_gd5446", &gd5446_device, GFX_CL_GD5446 }, + {"[VLB] Cirrus Logic CL-GD5429", "cl_gd5429", &gd5429_device, GFX_CL_GD5429, {VIDEO_BUS, 4, 8, 16}}, + {"[VLB] Cirrus Logic CL-GD5430", "cl_gd5430_vlb", &dia5430_device, GFX_CL_GD5430, {VIDEO_BUS, 4, 8, 16}}, + {"[VLB] Cirrus Logic CL-GD5446", "cl_gd5446", &gd5446_device, GFX_CL_GD5446, {VIDEO_BUS, 4, 5, 10}}, #endif #if defined(DEV_BRANCH) && defined(USE_STEALTH32) - {"[VLB] Diamond Stealth 32 (Tseng ET4000/w32p)","stealth32_vlb", &et4000w32p_vlb_device, GFX_ET4000W32_VLB }, + {"[VLB] Diamond Stealth 32 (Tseng ET4000/w32p)","stealth32_vlb", &et4000w32p_vlb_device, GFX_ET4000W32_VLB, {VIDEO_BUS, 4, 5, 10}}, #endif - {"[VLB] Diamond Stealth 3D 2000 (S3 ViRGE)", "stealth3d_2000_vlb", &s3_virge_vlb_device, GFX_VIRGE_VLB }, - {"[VLB] Diamond Stealth 3D 3000 (S3 ViRGE/VX)", "stealth3d_3000_vlb", &s3_virge_988_vlb_device, GFX_VIRGEVX_VLB }, - {"[VLB] Diamond Stealth 64 DRAM (S3 Trio64)", "stealth64d_vlb", &s3_diamond_stealth64_vlb_device, GFX_STEALTH64_VLB }, - {"[VLB] Number Nine 9FX (S3 Trio64)", "n9_9fx_vlb", &s3_9fx_vlb_device, GFX_N9_9FX_VLB }, - {"[VLB] Paradise Bahamas 64 (S3 Vision864)", "bahamas64_vlb", &s3_bahamas64_vlb_device, GFX_BAHAMAS64_VLB }, - {"[VLB] Phoenix S3 Vision864", "px_vision864_vlb", &s3_phoenix_vision864_vlb_device, GFX_PHOENIX_VISION864_VLB }, - {"[VLB] Phoenix S3 Trio32", "px_trio32_vlb", &s3_phoenix_trio32_vlb_device, GFX_PHOENIX_TRIO32_VLB }, - {"[VLB] Phoenix S3 Trio64", "px_trio64_vlb", &s3_phoenix_trio64_vlb_device, GFX_PHOENIX_TRIO64_VLB }, - {"[VLB] S3 ViRGE/DX", "virge375_vlb", &s3_virge_375_vlb_device, GFX_VIRGEDX_VLB }, - {"[VLB] S3 ViRGE/DX (VBE 2.0)", "virge375_vbe20_vlb", &s3_virge_375_4_vlb_device, GFX_VIRGEDX4_VLB }, - {"[VLB] Trident TGUI9440", "tgui9440_vlb", &tgui9440_vlb_device, GFX_TGUI9440_VLB }, + {"[VLB] Diamond Stealth 3D 2000 (S3 ViRGE)", "stealth3d_2000_vlb", &s3_virge_vlb_device, GFX_VIRGE_VLB, {VIDEO_BUS, 3, 5, 10}}, + {"[VLB] Diamond Stealth 3D 3000 (S3 ViRGE/VX)", "stealth3d_3000_vlb", &s3_virge_988_vlb_device, GFX_VIRGEVX_VLB, {VIDEO_BUS, 3, 4, 7}}, + {"[VLB] Diamond Stealth 64 DRAM (S3 Trio64)", "stealth64d_vlb", &s3_diamond_stealth64_vlb_device, GFX_STEALTH64_VLB, {VIDEO_BUS, 3, 4, 7}}, + {"[VLB] Number Nine 9FX (S3 Trio64)", "n9_9fx_vlb", &s3_9fx_vlb_device, GFX_N9_9FX_VLB, {VIDEO_BUS, 3, 5, 10}}, + {"[VLB] Paradise Bahamas 64 (S3 Vision864)", "bahamas64_vlb", &s3_bahamas64_vlb_device, GFX_BAHAMAS64_VLB, {VIDEO_BUS, 4, 5, 10}}, + {"[VLB] Phoenix S3 Vision864", "px_vision864_vlb", &s3_phoenix_vision864_vlb_device, GFX_PHOENIX_VISION864_VLB, {VIDEO_BUS, 3, 5, 10}}, + {"[VLB] Phoenix S3 Trio32", "px_trio32_vlb", &s3_phoenix_trio32_vlb_device, GFX_PHOENIX_TRIO32_VLB, {VIDEO_BUS, 4, 5, 10}}, + {"[VLB] Phoenix S3 Trio64", "px_trio64_vlb", &s3_phoenix_trio64_vlb_device, GFX_PHOENIX_TRIO64_VLB, {VIDEO_BUS, 3, 5, 10}}, + {"[VLB] S3 ViRGE/DX", "virge375_vlb", &s3_virge_375_vlb_device, GFX_VIRGEDX_VLB, {VIDEO_BUS, 2, 3, 4}}, + {"[VLB] S3 ViRGE/DX (VBE 2.0)", "virge375_vbe20_vlb", &s3_virge_375_4_vlb_device, GFX_VIRGEDX4_VLB, {VIDEO_BUS, 2, 3, 4}}, + {"[VLB] Trident TGUI9440", "tgui9440_vlb", &tgui9440_vlb_device, GFX_TGUI9440_VLB, {VIDEO_BUS, 4, 8, 16}}, {"", "", NULL, -1 } }; @@ -231,6 +229,34 @@ video_card_has_config(int card) } +int +video_card_timing_gettype(int card) +{ + return(video_cards[card].timing.type); +} + + +int +video_card_timing_getb(int card) +{ + return(video_cards[card].timing.b); +} + + +int +video_card_timing_getw(int card) +{ + return(video_cards[card].timing.w); +} + + +int +video_card_timing_getl(int card) +{ + return(video_cards[card].timing.l); +} + + int video_card_getid(char *s) { diff --git a/src/video/video.c b/src/video/video.c index 3d13be7d7..fa874e830 100644 --- a/src/video/video.c +++ b/src/video/video.c @@ -40,13 +40,13 @@ * W = 3 bus clocks * L = 4 bus clocks * - * Version: @(#)video.c 1.0.12 2017/12/31 + * Version: @(#)video.c 1.0.13 2018/01/27 * * Authors: Sarah Walker, * Miran Grca, * - * Copyright 2008-2017 Sarah Walker. - * Copyright 2016,2017 Miran Grca. + * Copyright 2008-2018 Sarah Walker. + * Copyright 2016-2018 Miran Grca. */ #include #include @@ -341,14 +341,36 @@ cgapal_rebuild(void) void video_update_timing(void) { - if (video_timing[video_speed][0] == VIDEO_ISA) { - video_timing_b = (int)(isa_timing * video_timing[video_speed][1]); - video_timing_w = (int)(isa_timing * video_timing[video_speed][2]); - video_timing_l = (int)(isa_timing * video_timing[video_speed][3]); - } else { - video_timing_b = (int)(bus_timing * video_timing[video_speed][1]); - video_timing_w = (int)(bus_timing * video_timing[video_speed][2]); - video_timing_l = (int)(bus_timing * video_timing[video_speed][3]); + int new_gfxcard; + int type, b, w, l; + + if (video_speed == -1) { + new_gfxcard = video_old_to_new(gfxcard); + + type = video_card_timing_gettype(new_gfxcard); + b = video_card_timing_getb(new_gfxcard); + w = video_card_timing_getw(new_gfxcard); + l = video_card_timing_getl(new_gfxcard); + + if (type == VIDEO_ISA) { + video_timing_b = (int)(isa_timing * b); + video_timing_w = (int)(isa_timing * w); + video_timing_l = (int)(isa_timing * l); + } else { + video_timing_b = (int)(bus_timing * b); + video_timing_w = (int)(bus_timing * w); + video_timing_l = (int)(bus_timing * l); + } + } else { + if (video_timing[video_speed][0] == VIDEO_ISA) { + video_timing_b = (int)(isa_timing * video_timing[video_speed][1]); + video_timing_w = (int)(isa_timing * video_timing[video_speed][2]); + video_timing_l = (int)(isa_timing * video_timing[video_speed][3]); + } else { + video_timing_b = (int)(bus_timing * video_timing[video_speed][1]); + video_timing_w = (int)(bus_timing * video_timing[video_speed][2]); + video_timing_l = (int)(bus_timing * video_timing[video_speed][3]); + } } if (cpu_16bitbus) diff --git a/src/video/video.h b/src/video/video.h index 906964b9a..efdb776d6 100644 --- a/src/video/video.h +++ b/src/video/video.h @@ -8,7 +8,7 @@ * * Definitions for the video controller module. * - * Version: @(#)video.h 1.0.10 2018/01/25 + * Version: @(#)video.h 1.0.11 2018/01/27 * * Authors: Sarah Walker, * Miran Grca, @@ -203,6 +203,10 @@ extern char *video_card_getname(int card); extern device_t *video_card_getdevice(int card); #endif extern int video_card_has_config(int card); +extern int video_card_timing_gettype(int card); +extern int video_card_timing_getb(int card); +extern int video_card_timing_getw(int card); +extern int video_card_timing_getl(int card); extern int video_card_getid(char *s); extern int video_old_to_new(int card); extern int video_new_to_old(int card); diff --git a/src/win/86Box.rc b/src/win/86Box.rc index 703df8564..6aa842013 100644 --- a/src/win/86Box.rc +++ b/src/win/86Box.rc @@ -8,7 +8,7 @@ * * Application resource script for Windows. * - * Version: @(#)86Box.rc 1.0.26 2018/01/23 + * Version: @(#)86Box.rc 1.0.27 2018/01/27 * * Authors: Miran Grca, * Fred N. van Kempen, @@ -901,7 +901,7 @@ BEGIN IDS_2128 "Screen Filter" IDS_2129 "Render Threads" IDS_2130 "Recompiler" - IDS_2131 "System Default" + IDS_2131 "Default" IDS_2132 "%i Wait state(s)" IDS_2133 "8-bit" IDS_2134 "Slow 16-bit" diff --git a/src/win/win_settings.c b/src/win/win_settings.c index d21a82229..f71ce9a56 100644 --- a/src/win/win_settings.c +++ b/src/win/win_settings.c @@ -8,7 +8,7 @@ * * Windows 86Box Settings dialog handler. * - * Version: @(#)win_settings.c 1.0.35 2018/01/26 + * Version: @(#)win_settings.c 1.0.36 2018/01/27 * * Author: Miran Grca, * @@ -864,13 +864,14 @@ win_settings_video_proc(HWND hdlg, UINT message, WPARAM wParam, LPARAM lParam) recalc_vid_list(hdlg); h = GetDlgItem(hdlg, IDC_COMBO_VIDEO_SPEED); + SendMessage(h, CB_ADDSTRING, 0, (LPARAM)plat_get_string(IDS_2131)); SendMessage(h, CB_ADDSTRING, 0, (LPARAM)plat_get_string(IDS_2133)); SendMessage(h, CB_ADDSTRING, 0, (LPARAM)plat_get_string(IDS_2134)); SendMessage(h, CB_ADDSTRING, 0, (LPARAM)plat_get_string(IDS_2135)); SendMessage(h, CB_ADDSTRING, 0, (LPARAM)plat_get_string(IDS_2136)); SendMessage(h, CB_ADDSTRING, 0, (LPARAM)plat_get_string(IDS_2137)); SendMessage(h, CB_ADDSTRING, 0, (LPARAM)plat_get_string(IDS_2138)); - SendMessage(h, CB_SETCURSEL, temp_video_speed, 0); + SendMessage(h, CB_SETCURSEL, temp_video_speed + 1, 0); h=GetDlgItem(hdlg, IDC_CHECK_VOODOO); SendMessage(h, BM_SETCHECK, temp_voodoo, 0); @@ -959,7 +960,7 @@ win_settings_video_proc(HWND hdlg, UINT message, WPARAM wParam, LPARAM lParam) temp_gfxcard = video_new_to_old(video_card_getid(stransi)); h = GetDlgItem(hdlg, IDC_COMBO_VIDEO_SPEED); - temp_video_speed = SendMessage(h, CB_GETCURSEL, 0, 0); + temp_video_speed = SendMessage(h, CB_GETCURSEL, 0, 0) - 1; h = GetDlgItem(hdlg, IDC_CHECK_VOODOO); temp_voodoo = SendMessage(h, BM_GETCHECK, 0, 0); diff --git a/src/zip.c b/src/zip.c index c70302554..a10572d75 100644 --- a/src/zip.c +++ b/src/zip.c @@ -9,7 +9,7 @@ * Implementation of the Iomega ZIP drive with SCSI(-like) * commands, for both ATAPI and SCSI usage. * - * Version: @(#)zip.c 1.0.2 2018/01/27 + * Version: @(#)zip.c 1.0.3 2018/01/28 * * Author: Miran Grca, * @@ -1060,7 +1060,7 @@ static void zip_cmd_error(uint8_t id) zip[id].packet_status = 0x80; zip[id].callback = 50LL * ZIP_TIME; zip_set_callback(id); - pclog("ZIP %i: [%02X] ERROR: %02X/%02X/%02X\n", id, zip[id].current_cdb[0], zip_sense_key, zip_asc, zip_ascq); + zip_log("ZIP %i: [%02X] ERROR: %02X/%02X/%02X\n", id, zip[id].current_cdb[0], zip_sense_key, zip_asc, zip_ascq); } static void zip_unit_attention(uint8_t id) @@ -1157,7 +1157,7 @@ int zip_data(uint8_t id, uint32_t *len, int out) int i = 0; if (zip[id].sector_pos >= zip_drives[id].medium_size) { - pclog("ZIP %i: Trying to %s beyond the end of disk\n", id, out ? "write" : "read"); + zip_log("ZIP %i: Trying to %s beyond the end of disk\n", id, out ? "write" : "read"); zip_lba_out_of_range(id); return 0; } @@ -1443,12 +1443,12 @@ void zip_command(uint8_t id, uint8_t *cdb) memcpy(zip[id].current_cdb, cdb, zip[id].cdb_len); if (cdb[0] != 0) { - pclog("ZIP %i: Command 0x%02X, Sense Key %02X, Asc %02X, Ascq %02X, Unit attention: %i\n", id, cdb[0], zip_sense_key, zip_asc, zip_ascq, zip[id].unit_attention); - pclog("ZIP %i: Request length: %04X\n", id, zip[id].request_length); + zip_log("ZIP %i: Command 0x%02X, Sense Key %02X, Asc %02X, Ascq %02X, Unit attention: %i\n", id, cdb[0], zip_sense_key, zip_asc, zip_ascq, zip[id].unit_attention); + zip_log("ZIP %i: Request length: %04X\n", id, zip[id].request_length); #if 0 for (CdbLength = 1; CdbLength < zip[id].cdb_len; CdbLength++) - pclog("ZIP %i: CDB[%d] = %d\n", id, CdbLength, cdb[CdbLength]); + zip_log("ZIP %i: CDB[%d] = %d\n", id, CdbLength, cdb[CdbLength]); #endif } @@ -1563,7 +1563,7 @@ void zip_command(uint8_t id, uint8_t *cdb) case GPCMD_READ_6: zip[id].sector_len = cdb[4]; zip[id].sector_pos = ((((uint32_t) cdb[1]) & 0x1f) << 16) | (((uint32_t) cdb[2]) << 8) | ((uint32_t) cdb[3]); - pclog("ZIP %i: Length: %i, LBA: %i\n", id, zip[id].sector_len, zip[id].sector_pos); + zip_log("ZIP %i: Length: %i, LBA: %i\n", id, zip[id].sector_len, zip[id].sector_pos); break; case GPCMD_READ_10: zip[id].sector_len = (cdb[7] << 8) | cdb[8]; @@ -1783,7 +1783,7 @@ void zip_command(uint8_t id, uint8_t *cdb) } zip[id].current_page_code = cdb[2] & 0x3F; - pclog("Mode sense page: %02X\n", zip[id].current_page_code); + zip_log("Mode sense page: %02X\n", zip[id].current_page_code); if (!(zip_mode_sense_page_flags & (1LL << zip[id].current_page_code))) { zip_invalid_field(id); @@ -2552,7 +2552,7 @@ zip_global_reset(void) if (zip_drives[c].bus_type) SCSIReset(zip_drives[c].scsi_device_id, zip_drives[c].scsi_device_lun); -pclog("ZIP global_reset drive=%d host=%02x\n", c, zip_drives[c].host_drive); +zip_log("ZIP global_reset drive=%d host=%02x\n", c, zip_drives[c].host_drive); if (wcslen(zip_drives[c].image_path)) zip_load(c, zip_drives[c].image_path); }