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Merge branch 'temp' into temp

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This commit is contained in:
nerd73
2020-03-23 16:06:32 -06:00
committed by GitHub
parent 169bd9bdab d3b2d1b5e4
commit c007121062
19 changed files with 455 additions and 82 deletions
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201
src/chipset/intel_4x0.c
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@@ -45,8 +45,8 @@ enum
#if defined(DEV_BRANCH) && defined(USE_I686)
INTEL_440FX,
#endif
INTEL_440BX
INTEL_440BX,
INTEL_440ZX
};
typedef struct
@@ -126,6 +126,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case 0x04: /*Command register*/
switch (dev->type) {
case INTEL_420TX: case INTEL_420ZX: case INTEL_430LX: case INTEL_430NX:
case INTEL_440BX: case INTEL_440ZX:
default:
regs[0x04] = (regs[0x04] & ~0x42) | (val & 0x42);
break;
@@ -139,10 +140,11 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
break;
case 0x05:
switch (dev->type) {
case INTEL_420TX: case INTEL_420ZX: case INTEL_430LX: case INTEL_430NX: case INTEL_430HX: case INTEL_440BX:
case INTEL_420TX: case INTEL_420ZX: case INTEL_430LX: case INTEL_430NX: case INTEL_430HX:
#if defined(DEV_BRANCH) && defined(USE_I686)
case INTEL_440FX:
#endif
case INTEL_440BX: case INTEL_440ZX:
regs[0x05] = (regs[0x05] & ~0x01) | (val & 0x01);
break;
}
@@ -160,8 +162,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_440FX:
regs[0x07] &= ~(val & 0xf9);
break;
#endif
case INTEL_440BX:
case INTEL_440BX: case INTEL_440ZX
regs[0x07] &= ~(val & 0xf0);
break;
}
@@ -185,7 +187,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
break;
case 0x12:
switch (dev->type) {
case INTEL_440BX:
case INTEL_440BX: case INTEL_440ZX:
regs[0x12] = (val & 0xc0);
i4x0_mask_bar(regs);
break;
@@ -193,7 +195,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
break;
case 0x13:
switch (dev->type) {
case INTEL_440BX:
case INTEL_440BX: case INTEL_440ZX:
regs[0x13] = val;
i4x0_mask_bar(regs);
break;
@@ -201,7 +203,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
break;
case 0x2c: case 0x2d: case 0x2e: case 0x2f:
switch (dev->type) {
case INTEL_440BX:
case INTEL_440BX: case INTEL_440ZX:
if (!regs_l[addr]) {
regs[addr] = val;
regs_l[addr] = 1;
@@ -244,10 +246,14 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_440FX:
regs[0x50] = (val & 0xf4);
break;
#endif
#endif
case INTEL_440BX:
regs[0x50] = (regs[0x50] & 0x14) | (val & 0xeb);
break;
regs[0x50] = (regs[0x50] & 0x14) | (val & 0xeb);
break;
case INTEL_440ZX:
regs[0x50] = (regs[0x50] & 0x34) | (val & 0xcb);
break;
}
break;
case 0x51:
@@ -260,9 +266,9 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
regs[0x51] = (val & 0xc3);
break;
#endif
case INTEL_440BX:
regs[0x51] = (regs[0x50] & 0x70) | (val & 0x8f);
break;
case INTEL_440BX: case INTEL_440ZX:
regs[0x51] = (regs[0x50] & 0x70) | (val & 0x8f);
break;
}
break;
case 0x52: /* Cache Control Register */
@@ -280,7 +286,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
#endif
regs[0x52] = val;
break;
case INTEL_440BX:
case INTEL_440BX: case INTEL_440ZX:
regs[0x52] = val & 0x07;
break;
}
@@ -297,6 +303,10 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_430VX: case INTEL_430TX:
regs[0x53] = val & 0x3f;
break;
case INTEL_440BX:
/* Not applicable to 440ZX as that does not support ECC. */
regs[0x53] = val;
break;
}
break;
case 0x54:
@@ -368,10 +378,13 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_440FX:
regs[0x57] = val & 0x77;
break;
#endif
#endif
case INTEL_440BX:
regs[0x57] = val & 0x3f;
break;
regs[0x57] = val & 0x3f;
break;
case INTEL_440ZX:
regs[0x57] = val & 0x2f;
break;
}
break;
case 0x58:
@@ -381,7 +394,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
regs[0x58] = val & 0x01;
break;
case INTEL_430NX:
case INTEL_440BX:
case INTEL_440BX: case INTEL_440ZX:
regs[0x58] = val & 0x03;
break;
case INTEL_430FX: case INTEL_430FX_PB640:
@@ -458,10 +471,11 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
switch (dev->type) {
case INTEL_420TX: case INTEL_420ZX:
case INTEL_430LX: case INTEL_430NX:
case INTEL_430HX: case INTEL_440BX:
case INTEL_430HX:
#if defined(DEV_BRANCH) && defined(USE_I686)
case INTEL_440FX:
#endif
case INTEL_440BX: case INTEL_440ZX:
default:
regs[addr] = val;
break;
@@ -478,10 +492,11 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
switch (dev->type) {
case INTEL_420TX: case INTEL_420ZX:
case INTEL_430LX: case INTEL_430NX:
case INTEL_430HX: case INTEL_440BX:
case INTEL_430HX:
#if defined(DEV_BRANCH) && defined(USE_I686)
case INTEL_440FX:
#endif
case INTEL_440FX:
#endif
case INTEL_440BX: case INTEL_440ZX:
regs[addr] = val;
break;
case INTEL_430VX:
@@ -495,21 +510,21 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case 0x66:
switch (dev->type) {
case INTEL_430NX: case INTEL_430HX:
case INTEL_440BX:
#if defined(DEV_BRANCH) && defined(USE_I686)
case INTEL_440FX:
#endif
case INTEL_440BX: case INTEL_440ZX:
regs[addr] = val;
break;
}
break;
case 0x67:
switch (dev->type) {
case INTEL_430NX: case INTEL_430HX:
case INTEL_440BX:
case INTEL_430NX: case INTEL_430HX:
#if defined(DEV_BRANCH) && defined(USE_I686)
case INTEL_440FX:
#endif
case INTEL_440BX: case INTEL_440ZX:
regs[addr] = val;
break;
case INTEL_430VX:
@@ -533,10 +548,13 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_440FX:
regs[0x68] = val & 0xc0;
break;
#endif
#endif
case INTEL_440BX:
regs[0x68] = (regs[0x68] & 0x38) | (val & 0xc7);
break;
regs[0x68] = (regs[0x68] & 0x38) | (val & 0xc7);
break;
case INTEL_440ZX:
regs[0x68] = (regs[0x68] & 0x3f) | (val & 0xc0);
break;
}
break;
case 0x69:
@@ -548,6 +566,9 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_430VX:
regs[0x69] = val & 0x07;
break;
case INTEL_440ZX:
regs[0x69] = val & 0x3f;
break;
}
break;
case 0x6a: case 0x6b:
@@ -556,6 +577,14 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_440BX:
regs[addr] = val;
break;
#if defined(DEV_BRANCH) && defined(USE_I686)
case INTEL_440ZX:
if (addr == 0x6a)
regs[addr] = val & 0xfc;
else
regs[addr] = val & 0x33;
break;
#endif
}
break;
case 0x6c: case 0x6d: case 0x6e:
@@ -563,6 +592,12 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_440BX:
regs[addr] = val;
break;
case INTEL_440ZX:
if (addr == 0x6c)
regs[addr] = val & 0x03;
else if (addr == 0x6d)
regs[addr] = val & 0xcf;
break;
}
break;
case 0x70:
@@ -616,7 +651,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_430VX:
regs[0x73] = val & 0x03;
break;
case INTEL_440BX:
case INTEL_440BX: case INTEL_440ZX:
regs[0x73] = val;
break;
}
@@ -624,7 +659,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case 0x74:
switch (dev->type) {
case INTEL_430VX:
case INTEL_440BX:
case INTEL_440BX: case INTEL_440ZX:
regs[0x74] = val;
break;
}
@@ -632,13 +667,13 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case 0x75: case 0x76:
case 0x7b:
switch (dev->type) {
case INTEL_440BX:
case INTEL_440BX: case INTEL_440ZX:
regs[addr] = val;
}
break;
case 0x77:
switch (dev->type) {
case INTEL_440BX:
case INTEL_440BX: case INTEL_440ZX:
regs[0x77] = val & 0x03;
}
break;
@@ -647,7 +682,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_430VX:
regs[0x78] = val & 0xcf;
break;
case INTEL_440BX:
case INTEL_440BX: case INTEL_440ZX:
regs[0x78] = val & 0x0f;
break;
}
@@ -660,14 +695,14 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
if (val & 0x40)
io_sethandler(0x0022, 0x01, pm2_cntrl_read, NULL, NULL, pm2_cntrl_write, NULL, NULL, dev);
break;
case INTEL_440BX:
case INTEL_440BX: case INTEL_440ZX:
regs[0x79] = val;
break;
}
break;
case 0x7a:
switch (dev->type) {
case INTEL_440BX:
case INTEL_440BX: case INTEL_440ZX:
regs[0x7a] = (regs[0x7a] & 0x0a) | (val & 0xf5);
io_removehandler(0x0022, 0x01, pm2_cntrl_read, NULL, NULL, pm2_cntrl_write, NULL, NULL, dev);
if (val & 0x40)
@@ -681,7 +716,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_430LX: case INTEL_430NX:
regs[0x7c] = val & 0x8f;
break;
case INTEL_440BX:
case INTEL_440BX: case INTEL_440ZX:
regs[0x7c] = val & 0x1f;
break;
}
@@ -701,7 +736,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
}
case 0x80:
switch (dev->type) {
case INTEL_440BX:
case INTEL_440BX: case INTEL_440ZX:
regs[0x80] &= ~(val & 0x03);
break;
}
@@ -716,9 +751,9 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
regs[0x80] = val & 0x1b;
break;
#endif
case INTEL_440BX:
regs[0x7c] = val;
break;
case INTEL_440BX: case INTEL_440ZX:
regs[0x7c] = val;
break;
}
break;
case 0x91:
@@ -727,13 +762,14 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
#if defined(DEV_BRANCH) && defined(USE_I686)
case INTEL_440FX:
#endif
/* Not applicable on 82443ZX. */
regs[0x91] &= ~(val & 0x11);
break;
}
break;
case 0x92:
switch (dev->type) {
case INTEL_440BX:
case INTEL_440BX: case INTEL_440ZX:
regs[0x92] &= ~(val & 0x1f);
break;
}
@@ -750,28 +786,28 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
#endif
case 0xa8: case 0xa9:
switch (dev->type) {
case INTEL_440BX:
case INTEL_440BX: case INTEL_440ZX:
regs[addr] = (val & 0x03);
break;
}
break;
case 0xb0:
switch (dev->type) {
case INTEL_440BX:
case INTEL_440BX: case INTEL_440ZX:
regs[0xb0] = (val & 0x80);
break;
}
break;
case 0xb1:
switch (dev->type) {
case INTEL_440BX:
case INTEL_440BX: case INTEL_440ZX:
regs[0xb1] = (val & 0xa0);
break;
}
break;
case 0xb4:
switch (dev->type) {
case INTEL_440BX:
case INTEL_440BX: case INTEL_440ZX:
regs[0xb4] = (val & 0x3f);
i4x0_mask_bar(regs);
break;
@@ -779,17 +815,37 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
break;
case 0xb9:
switch (dev->type) {
case INTEL_440BX:
case INTEL_440BX: case INTEL_440ZX:
regs[0xb9] = (val & 0xf0);
break;
}
break;
case 0xba: case 0xbb: case 0xca: case 0xcb:
case 0xba: case 0xbb:
case 0xd0: case 0xd1: case 0xd2: case 0xd3: case 0xd4: case 0xd5: case 0xd6: case 0xd7:
switch (dev->type) {
case INTEL_440BX: case INTEL_440ZX:
regs[addr] = val;
break;
}
break;
case 0xca:
switch (dev->type) {
case INTEL_440BX:
regs[addr] = val;
break;
case INTEL_440ZX:
regs[addr] = val & 0xe7;
break;
}
break;
case 0xcb:
switch (dev->type) {
case INTEL_440BX:
regs[addr] = val;
break;
case INTEL_440ZX:
regs[addr] = val & 0xa7;
break;
}
break;
case 0xcc:
@@ -797,12 +853,15 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_440BX:
regs[0xcc] = (val & 0x7f);
break;
case INTEL_440ZX:
regs[0xcc] = (val & 0x58);
break;
}
break;
case 0xe0: case 0xe1: case 0xe2: case 0xe3: case 0xe4:
case 0xe8: case 0xe9: case 0xea: case 0xeb: case 0xec:
switch (dev->type) {
case INTEL_440BX:
case INTEL_440BX: case INTEL_440ZX:
if (!regs_l[addr])
regs[addr] = val;
break;
@@ -810,7 +869,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
break;
case 0xe5: case 0xed:
switch (dev->type) {
case INTEL_440BX:
case INTEL_440BX: case INTEL_440ZX:
if (!regs_l[addr])
regs[addr] = (val & 0x3f);
break;
@@ -818,7 +877,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
break;
case 0xe7:
switch (dev->type) {
case INTEL_440BX:
case INTEL_440BX: case INTEL_440ZX:
regs[0xe7] = 0x80;
for (i = 0; i < 16; i++)
regs_l[0xe0 + i] = !!(val & 0x80);
@@ -830,14 +889,14 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
break;
case 0xf0:
switch (dev->type) {
case INTEL_440BX:
case INTEL_440BX: case INTEL_440ZX:
regs[0xf0] = (val & 0xc0);
break;
}
break;
case 0xf1:
switch (dev->type) {
case INTEL_440BX:
case INTEL_440BX: case INTEL_440ZX:
regs[0xf1] = (val & 0x03);
break;
}
@@ -845,21 +904,21 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
} else if (func == 1) switch (addr) {
case 0x04:
switch (dev->type) {
case INTEL_440BX:
case INTEL_440BX: case INTEL_440ZX:
regs[0x04] = (val & 0x1f);
break;
}
break;
case 0x05:
switch (dev->type) {
case INTEL_440BX:
case INTEL_440BX: case INTEL_440ZX:
regs[0x05] = (val & 0x01);
break;
}
break;
case 0x0d: case 0x1b:
switch (dev->type) {
case INTEL_440BX:
case INTEL_440BX: case INTEL_440ZX:
regs[addr] = (val & 0xf8);
break;
}
@@ -868,7 +927,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case 0x21: case 0x23:
case 0x25: case 0x27:
switch (dev->type) {
case INTEL_440BX:
case INTEL_440BX: case INTEL_440ZX:
regs[addr] = val;
break;
}
@@ -877,21 +936,21 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case 0x20: case 0x22:
case 0x24: case 0x26:
switch (dev->type) {
case INTEL_440BX:
case INTEL_440BX: case INTEL_440ZX:
regs[addr] = (val & 0xf0);
break;
}
break;
case 0x1f:
switch (dev->type) {
case INTEL_440BX:
case INTEL_440BX: case INTEL_440ZX:
regs[0x1f] &= ~(val & 0xf0);
break;
}
break;
case 0x3e:
switch (dev->type) {
case INTEL_440BX:
case INTEL_440BX: case INTEL_440ZX:
regs[0x3e] = (val & 0xed);
break;
}
@@ -942,7 +1001,7 @@ i4x0_reset(void *priv)
else
i4x0_write(0, 0x72, 0x00, priv);
if (dev->type == INTEL_440BX) {
if ((dev->type == INTEL_440BX) || (dev->type == INTEL_440ZX)) {
for (i = 0; i <= dev->max_func; i++)
memset(dev->regs_locked[i], 0x00, 256 * sizeof(uint8_t));
}
@@ -1117,11 +1176,12 @@ static void
regs[0x72] = 0x02;
break;
#endif
case INTEL_440BX:
case INTEL_440BX: case INTEL_440ZX:
regs[0x7a] = (info->local >> 8) & 0xff;
dev->max_func = (regs[0x7a] & 0x02) ? 0 : 1;
regs[0x02] = (regs[0x7a] & 0x02) ? 0x92 : 0x90; regs[0x03] = 0x71; /* 82443BX */
regs[0x06] = (regs[0x7a] & 0x02) ? 0x00 : 0x10;
regs[0x08] = 0x02;
regs[0x10] = 0x08;
regs[0x34] = (regs[0x7a] & 0x02) ? 0x00 : 0xa0;
@@ -1164,7 +1224,7 @@ static void
smbase = 0xa0000;
if ((dev->type == INTEL_440BX) && (dev->max_func == 1)) {
if (((dev->type == INTEL_440BX) || (dev->type == INTEL_440ZX)) && (dev->max_func == 1)) {
regs = (uint8_t *) dev->regs[1];
regs[0x00] = 0x86; regs[0x01] = 0x80; /* Intel */
@@ -1350,3 +1410,18 @@ const device_t i440bx_device =
NULL,
NULL
};
const device_t i440zx_device =
{
"Intel 82443ZX",
DEVICE_PCI,
0x8000 | INTEL_440ZX,
i4x0_init,
i4x0_close,
i4x0_reset,
NULL,
NULL,
NULL,
NULL
};