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Merge branch 'temp' into temp

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This commit is contained in:
nerd73
2020-03-23 16:06:32 -06:00
committed by GitHub
parent 169bd9bdab d3b2d1b5e4
commit c007121062
19 changed files with 455 additions and 82 deletions
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1
src/86box.h
View File

@@ -99,6 +99,7 @@ extern int vid_cga_contrast, /* (C) video */
gfxcard; /* (C) graphics/video card */ gfxcard; /* (C) graphics/video card */
extern int serial_enabled[], /* (C) enable serial ports */ extern int serial_enabled[], /* (C) enable serial ports */
bugger_enabled, /* (C) enable ISAbugger */ bugger_enabled, /* (C) enable ISAbugger */
postcard_enabled, /* (C) enable POST card */
isamem_type[], /* (C) enable ISA mem cards */ isamem_type[], /* (C) enable ISA mem cards */
isartc_type; /* (C) enable ISA RTC card */ isartc_type; /* (C) enable ISA RTC card */
extern int sound_is_float, /* (C) sound uses FP values */ extern int sound_is_float, /* (C) sound uses FP values */

1
src/chipset/chipset.h
View File

@@ -45,6 +45,7 @@ extern const device_t i430tx_device;
extern const device_t i440fx_device; extern const device_t i440fx_device;
#endif #endif
extern const device_t i440bx_device; extern const device_t i440bx_device;
extern const device_t i440zx_device;
/* NEAT */ /* NEAT */
extern const device_t neat_device; extern const device_t neat_device;

201
src/chipset/intel_4x0.c
View File

@@ -45,8 +45,8 @@ enum
#if defined(DEV_BRANCH) && defined(USE_I686) #if defined(DEV_BRANCH) && defined(USE_I686)
INTEL_440FX, INTEL_440FX,
#endif #endif
INTEL_440BX INTEL_440BX,
INTEL_440ZX
}; };
typedef struct typedef struct
@@ -126,6 +126,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case 0x04: /*Command register*/ case 0x04: /*Command register*/
switch (dev->type) { switch (dev->type) {
case INTEL_420TX: case INTEL_420ZX: case INTEL_430LX: case INTEL_430NX: case INTEL_420TX: case INTEL_420ZX: case INTEL_430LX: case INTEL_430NX:
case INTEL_440BX: case INTEL_440ZX:
default: default:
regs[0x04] = (regs[0x04] & ~0x42) | (val & 0x42); regs[0x04] = (regs[0x04] & ~0x42) | (val & 0x42);
break; break;
@@ -139,10 +140,11 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
break; break;
case 0x05: case 0x05:
switch (dev->type) { switch (dev->type) {
case INTEL_420TX: case INTEL_420ZX: case INTEL_430LX: case INTEL_430NX: case INTEL_430HX: case INTEL_440BX: case INTEL_420TX: case INTEL_420ZX: case INTEL_430LX: case INTEL_430NX: case INTEL_430HX:
#if defined(DEV_BRANCH) && defined(USE_I686) #if defined(DEV_BRANCH) && defined(USE_I686)
case INTEL_440FX: case INTEL_440FX:
#endif #endif
case INTEL_440BX: case INTEL_440ZX:
regs[0x05] = (regs[0x05] & ~0x01) | (val & 0x01); regs[0x05] = (regs[0x05] & ~0x01) | (val & 0x01);
break; break;
} }
@@ -160,8 +162,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_440FX: case INTEL_440FX:
regs[0x07] &= ~(val & 0xf9); regs[0x07] &= ~(val & 0xf9);
break; break;
#endif
case INTEL_440BX: case INTEL_440BX: case INTEL_440ZX
regs[0x07] &= ~(val & 0xf0); regs[0x07] &= ~(val & 0xf0);
break; break;
} }
@@ -185,7 +187,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
break; break;
case 0x12: case 0x12:
switch (dev->type) { switch (dev->type) {
case INTEL_440BX: case INTEL_440BX: case INTEL_440ZX:
regs[0x12] = (val & 0xc0); regs[0x12] = (val & 0xc0);
i4x0_mask_bar(regs); i4x0_mask_bar(regs);
break; break;
@@ -193,7 +195,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
break; break;
case 0x13: case 0x13:
switch (dev->type) { switch (dev->type) {
case INTEL_440BX: case INTEL_440BX: case INTEL_440ZX:
regs[0x13] = val; regs[0x13] = val;
i4x0_mask_bar(regs); i4x0_mask_bar(regs);
break; break;
@@ -201,7 +203,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
break; break;
case 0x2c: case 0x2d: case 0x2e: case 0x2f: case 0x2c: case 0x2d: case 0x2e: case 0x2f:
switch (dev->type) { switch (dev->type) {
case INTEL_440BX: case INTEL_440BX: case INTEL_440ZX:
if (!regs_l[addr]) { if (!regs_l[addr]) {
regs[addr] = val; regs[addr] = val;
regs_l[addr] = 1; regs_l[addr] = 1;
@@ -244,10 +246,14 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_440FX: case INTEL_440FX:
regs[0x50] = (val & 0xf4); regs[0x50] = (val & 0xf4);
break; break;
#endif #endif
case INTEL_440BX: case INTEL_440BX:
regs[0x50] = (regs[0x50] & 0x14) | (val & 0xeb); regs[0x50] = (regs[0x50] & 0x14) | (val & 0xeb);
break; break;
case INTEL_440ZX:
regs[0x50] = (regs[0x50] & 0x34) | (val & 0xcb);
break;
} }
break; break;
case 0x51: case 0x51:
@@ -260,9 +266,9 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
regs[0x51] = (val & 0xc3); regs[0x51] = (val & 0xc3);
break; break;
#endif #endif
case INTEL_440BX: case INTEL_440BX: case INTEL_440ZX:
regs[0x51] = (regs[0x50] & 0x70) | (val & 0x8f); regs[0x51] = (regs[0x50] & 0x70) | (val & 0x8f);
break; break;
} }
break; break;
case 0x52: /* Cache Control Register */ case 0x52: /* Cache Control Register */
@@ -280,7 +286,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
#endif #endif
regs[0x52] = val; regs[0x52] = val;
break; break;
case INTEL_440BX: case INTEL_440BX: case INTEL_440ZX:
regs[0x52] = val & 0x07; regs[0x52] = val & 0x07;
break; break;
} }
@@ -297,6 +303,10 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_430VX: case INTEL_430TX: case INTEL_430VX: case INTEL_430TX:
regs[0x53] = val & 0x3f; regs[0x53] = val & 0x3f;
break; break;
case INTEL_440BX:
/* Not applicable to 440ZX as that does not support ECC. */
regs[0x53] = val;
break;
} }
break; break;
case 0x54: case 0x54:
@@ -368,10 +378,13 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_440FX: case INTEL_440FX:
regs[0x57] = val & 0x77; regs[0x57] = val & 0x77;
break; break;
#endif #endif
case INTEL_440BX: case INTEL_440BX:
regs[0x57] = val & 0x3f; regs[0x57] = val & 0x3f;
break; break;
case INTEL_440ZX:
regs[0x57] = val & 0x2f;
break;
} }
break; break;
case 0x58: case 0x58:
@@ -381,7 +394,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
regs[0x58] = val & 0x01; regs[0x58] = val & 0x01;
break; break;
case INTEL_430NX: case INTEL_430NX:
case INTEL_440BX: case INTEL_440BX: case INTEL_440ZX:
regs[0x58] = val & 0x03; regs[0x58] = val & 0x03;
break; break;
case INTEL_430FX: case INTEL_430FX_PB640: case INTEL_430FX: case INTEL_430FX_PB640:
@@ -458,10 +471,11 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
switch (dev->type) { switch (dev->type) {
case INTEL_420TX: case INTEL_420ZX: case INTEL_420TX: case INTEL_420ZX:
case INTEL_430LX: case INTEL_430NX: case INTEL_430LX: case INTEL_430NX:
case INTEL_430HX: case INTEL_440BX: case INTEL_430HX:
#if defined(DEV_BRANCH) && defined(USE_I686) #if defined(DEV_BRANCH) && defined(USE_I686)
case INTEL_440FX: case INTEL_440FX:
#endif #endif
case INTEL_440BX: case INTEL_440ZX:
default: default:
regs[addr] = val; regs[addr] = val;
break; break;
@@ -478,10 +492,11 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
switch (dev->type) { switch (dev->type) {
case INTEL_420TX: case INTEL_420ZX: case INTEL_420TX: case INTEL_420ZX:
case INTEL_430LX: case INTEL_430NX: case INTEL_430LX: case INTEL_430NX:
case INTEL_430HX: case INTEL_440BX: case INTEL_430HX:
#if defined(DEV_BRANCH) && defined(USE_I686) #if defined(DEV_BRANCH) && defined(USE_I686)
case INTEL_440FX: case INTEL_440FX:
#endif #endif
case INTEL_440BX: case INTEL_440ZX:
regs[addr] = val; regs[addr] = val;
break; break;
case INTEL_430VX: case INTEL_430VX:
@@ -495,21 +510,21 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case 0x66: case 0x66:
switch (dev->type) { switch (dev->type) {
case INTEL_430NX: case INTEL_430HX: case INTEL_430NX: case INTEL_430HX:
case INTEL_440BX:
#if defined(DEV_BRANCH) && defined(USE_I686) #if defined(DEV_BRANCH) && defined(USE_I686)
case INTEL_440FX: case INTEL_440FX:
#endif #endif
case INTEL_440BX: case INTEL_440ZX:
regs[addr] = val; regs[addr] = val;
break; break;
} }
break; break;
case 0x67: case 0x67:
switch (dev->type) { switch (dev->type) {
case INTEL_430NX: case INTEL_430HX: case INTEL_430NX: case INTEL_430HX:
case INTEL_440BX:
#if defined(DEV_BRANCH) && defined(USE_I686) #if defined(DEV_BRANCH) && defined(USE_I686)
case INTEL_440FX: case INTEL_440FX:
#endif #endif
case INTEL_440BX: case INTEL_440ZX:
regs[addr] = val; regs[addr] = val;
break; break;
case INTEL_430VX: case INTEL_430VX:
@@ -533,10 +548,13 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_440FX: case INTEL_440FX:
regs[0x68] = val & 0xc0; regs[0x68] = val & 0xc0;
break; break;
#endif #endif
case INTEL_440BX: case INTEL_440BX:
regs[0x68] = (regs[0x68] & 0x38) | (val & 0xc7); regs[0x68] = (regs[0x68] & 0x38) | (val & 0xc7);
break; break;
case INTEL_440ZX:
regs[0x68] = (regs[0x68] & 0x3f) | (val & 0xc0);
break;
} }
break; break;
case 0x69: case 0x69:
@@ -548,6 +566,9 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_430VX: case INTEL_430VX:
regs[0x69] = val & 0x07; regs[0x69] = val & 0x07;
break; break;
case INTEL_440ZX:
regs[0x69] = val & 0x3f;
break;
} }
break; break;
case 0x6a: case 0x6b: case 0x6a: case 0x6b:
@@ -556,6 +577,14 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_440BX: case INTEL_440BX:
regs[addr] = val; regs[addr] = val;
break; break;
#if defined(DEV_BRANCH) && defined(USE_I686)
case INTEL_440ZX:
if (addr == 0x6a)
regs[addr] = val & 0xfc;
else
regs[addr] = val & 0x33;
break;
#endif
} }
break; break;
case 0x6c: case 0x6d: case 0x6e: case 0x6c: case 0x6d: case 0x6e:
@@ -563,6 +592,12 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_440BX: case INTEL_440BX:
regs[addr] = val; regs[addr] = val;
break; break;
case INTEL_440ZX:
if (addr == 0x6c)
regs[addr] = val & 0x03;
else if (addr == 0x6d)
regs[addr] = val & 0xcf;
break;
} }
break; break;
case 0x70: case 0x70:
@@ -616,7 +651,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_430VX: case INTEL_430VX:
regs[0x73] = val & 0x03; regs[0x73] = val & 0x03;
break; break;
case INTEL_440BX: case INTEL_440BX: case INTEL_440ZX:
regs[0x73] = val; regs[0x73] = val;
break; break;
} }
@@ -624,7 +659,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case 0x74: case 0x74:
switch (dev->type) { switch (dev->type) {
case INTEL_430VX: case INTEL_430VX:
case INTEL_440BX: case INTEL_440BX: case INTEL_440ZX:
regs[0x74] = val; regs[0x74] = val;
break; break;
} }
@@ -632,13 +667,13 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case 0x75: case 0x76: case 0x75: case 0x76:
case 0x7b: case 0x7b:
switch (dev->type) { switch (dev->type) {
case INTEL_440BX: case INTEL_440BX: case INTEL_440ZX:
regs[addr] = val; regs[addr] = val;
} }
break; break;
case 0x77: case 0x77:
switch (dev->type) { switch (dev->type) {
case INTEL_440BX: case INTEL_440BX: case INTEL_440ZX:
regs[0x77] = val & 0x03; regs[0x77] = val & 0x03;
} }
break; break;
@@ -647,7 +682,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_430VX: case INTEL_430VX:
regs[0x78] = val & 0xcf; regs[0x78] = val & 0xcf;
break; break;
case INTEL_440BX: case INTEL_440BX: case INTEL_440ZX:
regs[0x78] = val & 0x0f; regs[0x78] = val & 0x0f;
break; break;
} }
@@ -660,14 +695,14 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
if (val & 0x40) if (val & 0x40)
io_sethandler(0x0022, 0x01, pm2_cntrl_read, NULL, NULL, pm2_cntrl_write, NULL, NULL, dev); io_sethandler(0x0022, 0x01, pm2_cntrl_read, NULL, NULL, pm2_cntrl_write, NULL, NULL, dev);
break; break;
case INTEL_440BX: case INTEL_440BX: case INTEL_440ZX:
regs[0x79] = val; regs[0x79] = val;
break; break;
} }
break; break;
case 0x7a: case 0x7a:
switch (dev->type) { switch (dev->type) {
case INTEL_440BX: case INTEL_440BX: case INTEL_440ZX:
regs[0x7a] = (regs[0x7a] & 0x0a) | (val & 0xf5); regs[0x7a] = (regs[0x7a] & 0x0a) | (val & 0xf5);
io_removehandler(0x0022, 0x01, pm2_cntrl_read, NULL, NULL, pm2_cntrl_write, NULL, NULL, dev); io_removehandler(0x0022, 0x01, pm2_cntrl_read, NULL, NULL, pm2_cntrl_write, NULL, NULL, dev);
if (val & 0x40) if (val & 0x40)
@@ -681,7 +716,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_430LX: case INTEL_430NX: case INTEL_430LX: case INTEL_430NX:
regs[0x7c] = val & 0x8f; regs[0x7c] = val & 0x8f;
break; break;
case INTEL_440BX: case INTEL_440BX: case INTEL_440ZX:
regs[0x7c] = val & 0x1f; regs[0x7c] = val & 0x1f;
break; break;
} }
@@ -701,7 +736,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
} }
case 0x80: case 0x80:
switch (dev->type) { switch (dev->type) {
case INTEL_440BX: case INTEL_440BX: case INTEL_440ZX:
regs[0x80] &= ~(val & 0x03); regs[0x80] &= ~(val & 0x03);
break; break;
} }
@@ -716,9 +751,9 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
regs[0x80] = val & 0x1b; regs[0x80] = val & 0x1b;
break; break;
#endif #endif
case INTEL_440BX: case INTEL_440BX: case INTEL_440ZX:
regs[0x7c] = val; regs[0x7c] = val;
break; break;
} }
break; break;
case 0x91: case 0x91:
@@ -727,13 +762,14 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
#if defined(DEV_BRANCH) && defined(USE_I686) #if defined(DEV_BRANCH) && defined(USE_I686)
case INTEL_440FX: case INTEL_440FX:
#endif #endif
/* Not applicable on 82443ZX. */
regs[0x91] &= ~(val & 0x11); regs[0x91] &= ~(val & 0x11);
break; break;
} }
break; break;
case 0x92: case 0x92:
switch (dev->type) { switch (dev->type) {
case INTEL_440BX: case INTEL_440BX: case INTEL_440ZX:
regs[0x92] &= ~(val & 0x1f); regs[0x92] &= ~(val & 0x1f);
break; break;
} }
@@ -750,28 +786,28 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
#endif #endif
case 0xa8: case 0xa9: case 0xa8: case 0xa9:
switch (dev->type) { switch (dev->type) {
case INTEL_440BX: case INTEL_440BX: case INTEL_440ZX:
regs[addr] = (val & 0x03); regs[addr] = (val & 0x03);
break; break;
} }
break; break;
case 0xb0: case 0xb0:
switch (dev->type) { switch (dev->type) {
case INTEL_440BX: case INTEL_440BX: case INTEL_440ZX:
regs[0xb0] = (val & 0x80); regs[0xb0] = (val & 0x80);
break; break;
} }
break; break;
case 0xb1: case 0xb1:
switch (dev->type) { switch (dev->type) {
case INTEL_440BX: case INTEL_440BX: case INTEL_440ZX:
regs[0xb1] = (val & 0xa0); regs[0xb1] = (val & 0xa0);
break; break;
} }
break; break;
case 0xb4: case 0xb4:
switch (dev->type) { switch (dev->type) {
case INTEL_440BX: case INTEL_440BX: case INTEL_440ZX:
regs[0xb4] = (val & 0x3f); regs[0xb4] = (val & 0x3f);
i4x0_mask_bar(regs); i4x0_mask_bar(regs);
break; break;
@@ -779,17 +815,37 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
break; break;
case 0xb9: case 0xb9:
switch (dev->type) { switch (dev->type) {
case INTEL_440BX: case INTEL_440BX: case INTEL_440ZX:
regs[0xb9] = (val & 0xf0); regs[0xb9] = (val & 0xf0);
break; break;
} }
break; break;
case 0xba: case 0xbb: case 0xca: case 0xcb: case 0xba: case 0xbb:
case 0xd0: case 0xd1: case 0xd2: case 0xd3: case 0xd4: case 0xd5: case 0xd6: case 0xd7: case 0xd0: case 0xd1: case 0xd2: case 0xd3: case 0xd4: case 0xd5: case 0xd6: case 0xd7:
switch (dev->type) {
case INTEL_440BX: case INTEL_440ZX:
regs[addr] = val;
break;
}
break;
case 0xca:
switch (dev->type) { switch (dev->type) {
case INTEL_440BX: case INTEL_440BX:
regs[addr] = val; regs[addr] = val;
break; break;
case INTEL_440ZX:
regs[addr] = val & 0xe7;
break;
}
break;
case 0xcb:
switch (dev->type) {
case INTEL_440BX:
regs[addr] = val;
break;
case INTEL_440ZX:
regs[addr] = val & 0xa7;
break;
} }
break; break;
case 0xcc: case 0xcc:
@@ -797,12 +853,15 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_440BX: case INTEL_440BX:
regs[0xcc] = (val & 0x7f); regs[0xcc] = (val & 0x7f);
break; break;
case INTEL_440ZX:
regs[0xcc] = (val & 0x58);
break;
} }
break; break;
case 0xe0: case 0xe1: case 0xe2: case 0xe3: case 0xe4: case 0xe0: case 0xe1: case 0xe2: case 0xe3: case 0xe4:
case 0xe8: case 0xe9: case 0xea: case 0xeb: case 0xec: case 0xe8: case 0xe9: case 0xea: case 0xeb: case 0xec:
switch (dev->type) { switch (dev->type) {
case INTEL_440BX: case INTEL_440BX: case INTEL_440ZX:
if (!regs_l[addr]) if (!regs_l[addr])
regs[addr] = val; regs[addr] = val;
break; break;
@@ -810,7 +869,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
break; break;
case 0xe5: case 0xed: case 0xe5: case 0xed:
switch (dev->type) { switch (dev->type) {
case INTEL_440BX: case INTEL_440BX: case INTEL_440ZX:
if (!regs_l[addr]) if (!regs_l[addr])
regs[addr] = (val & 0x3f); regs[addr] = (val & 0x3f);
break; break;
@@ -818,7 +877,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
break; break;
case 0xe7: case 0xe7:
switch (dev->type) { switch (dev->type) {
case INTEL_440BX: case INTEL_440BX: case INTEL_440ZX:
regs[0xe7] = 0x80; regs[0xe7] = 0x80;
for (i = 0; i < 16; i++) for (i = 0; i < 16; i++)
regs_l[0xe0 + i] = !!(val & 0x80); regs_l[0xe0 + i] = !!(val & 0x80);
@@ -830,14 +889,14 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
break; break;
case 0xf0: case 0xf0:
switch (dev->type) { switch (dev->type) {
case INTEL_440BX: case INTEL_440BX: case INTEL_440ZX:
regs[0xf0] = (val & 0xc0); regs[0xf0] = (val & 0xc0);
break; break;
} }
break; break;
case 0xf1: case 0xf1:
switch (dev->type) { switch (dev->type) {
case INTEL_440BX: case INTEL_440BX: case INTEL_440ZX:
regs[0xf1] = (val & 0x03); regs[0xf1] = (val & 0x03);
break; break;
} }
@@ -845,21 +904,21 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
} else if (func == 1) switch (addr) { } else if (func == 1) switch (addr) {
case 0x04: case 0x04:
switch (dev->type) { switch (dev->type) {
case INTEL_440BX: case INTEL_440BX: case INTEL_440ZX:
regs[0x04] = (val & 0x1f); regs[0x04] = (val & 0x1f);
break; break;
} }
break; break;
case 0x05: case 0x05:
switch (dev->type) { switch (dev->type) {
case INTEL_440BX: case INTEL_440BX: case INTEL_440ZX:
regs[0x05] = (val & 0x01); regs[0x05] = (val & 0x01);
break; break;
} }
break; break;
case 0x0d: case 0x1b: case 0x0d: case 0x1b:
switch (dev->type) { switch (dev->type) {
case INTEL_440BX: case INTEL_440BX: case INTEL_440ZX:
regs[addr] = (val & 0xf8); regs[addr] = (val & 0xf8);
break; break;
} }
@@ -868,7 +927,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case 0x21: case 0x23: case 0x21: case 0x23:
case 0x25: case 0x27: case 0x25: case 0x27:
switch (dev->type) { switch (dev->type) {
case INTEL_440BX: case INTEL_440BX: case INTEL_440ZX:
regs[addr] = val; regs[addr] = val;
break; break;
} }
@@ -877,21 +936,21 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case 0x20: case 0x22: case 0x20: case 0x22:
case 0x24: case 0x26: case 0x24: case 0x26:
switch (dev->type) { switch (dev->type) {
case INTEL_440BX: case INTEL_440BX: case INTEL_440ZX:
regs[addr] = (val & 0xf0); regs[addr] = (val & 0xf0);
break; break;
} }
break; break;
case 0x1f: case 0x1f:
switch (dev->type) { switch (dev->type) {
case INTEL_440BX: case INTEL_440BX: case INTEL_440ZX:
regs[0x1f] &= ~(val & 0xf0); regs[0x1f] &= ~(val & 0xf0);
break; break;
} }
break; break;
case 0x3e: case 0x3e:
switch (dev->type) { switch (dev->type) {
case INTEL_440BX: case INTEL_440BX: case INTEL_440ZX:
regs[0x3e] = (val & 0xed); regs[0x3e] = (val & 0xed);
break; break;
} }
@@ -942,7 +1001,7 @@ i4x0_reset(void *priv)
else else
i4x0_write(0, 0x72, 0x00, priv); i4x0_write(0, 0x72, 0x00, priv);
if (dev->type == INTEL_440BX) { if ((dev->type == INTEL_440BX) || (dev->type == INTEL_440ZX)) {
for (i = 0; i <= dev->max_func; i++) for (i = 0; i <= dev->max_func; i++)
memset(dev->regs_locked[i], 0x00, 256 * sizeof(uint8_t)); memset(dev->regs_locked[i], 0x00, 256 * sizeof(uint8_t));
} }
@@ -1117,11 +1176,12 @@ static void
regs[0x72] = 0x02; regs[0x72] = 0x02;
break; break;
#endif #endif
case INTEL_440BX: case INTEL_440BX: case INTEL_440ZX:
regs[0x7a] = (info->local >> 8) & 0xff; regs[0x7a] = (info->local >> 8) & 0xff;
dev->max_func = (regs[0x7a] & 0x02) ? 0 : 1; dev->max_func = (regs[0x7a] & 0x02) ? 0 : 1;
regs[0x02] = (regs[0x7a] & 0x02) ? 0x92 : 0x90; regs[0x03] = 0x71; /* 82443BX */ regs[0x02] = (regs[0x7a] & 0x02) ? 0x92 : 0x90; regs[0x03] = 0x71; /* 82443BX */
regs[0x06] = (regs[0x7a] & 0x02) ? 0x00 : 0x10;
regs[0x08] = 0x02; regs[0x08] = 0x02;
regs[0x10] = 0x08; regs[0x10] = 0x08;
regs[0x34] = (regs[0x7a] & 0x02) ? 0x00 : 0xa0; regs[0x34] = (regs[0x7a] & 0x02) ? 0x00 : 0xa0;
@@ -1164,7 +1224,7 @@ static void
smbase = 0xa0000; smbase = 0xa0000;
if ((dev->type == INTEL_440BX) && (dev->max_func == 1)) { if (((dev->type == INTEL_440BX) || (dev->type == INTEL_440ZX)) && (dev->max_func == 1)) {
regs = (uint8_t *) dev->regs[1]; regs = (uint8_t *) dev->regs[1];
regs[0x00] = 0x86; regs[0x01] = 0x80; /* Intel */ regs[0x00] = 0x86; regs[0x01] = 0x80; /* Intel */
@@ -1350,3 +1410,18 @@ const device_t i440bx_device =
NULL, NULL,
NULL NULL
}; };
const device_t i440zx_device =
{
"Intel 82443ZX",
DEVICE_PCI,
0x8000 | INTEL_440ZX,
i4x0_init,
i4x0_close,
i4x0_reset,
NULL,
NULL,
NULL,
NULL
};

6
src/config.c
View File

@@ -806,6 +806,7 @@ load_other_peripherals(void)
ide_qua_enabled = !!config_get_int(cat, "ide_qua", 0); ide_qua_enabled = !!config_get_int(cat, "ide_qua", 0);
bugger_enabled = !!config_get_int(cat, "bugger_enabled", 0); bugger_enabled = !!config_get_int(cat, "bugger_enabled", 0);
postcard_enabled = !!config_get_int(cat, "postcard_enabled", 0);
for (c = 0; c < ISAMEM_MAX; c++) { for (c = 0; c < ISAMEM_MAX; c++) {
sprintf(temp, "isamem%d_type", c); sprintf(temp, "isamem%d_type", c);
@@ -1686,6 +1687,11 @@ save_other_peripherals(void)
else else
config_set_int(cat, "bugger_enabled", bugger_enabled); config_set_int(cat, "bugger_enabled", bugger_enabled);
if (postcard_enabled == 0)
config_delete_var(cat, "postcard_enabled");
else
config_set_int(cat, "postcard_enabled", postcard_enabled);
for (c = 0; c < ISAMEM_MAX; c++) { for (c = 0; c < ISAMEM_MAX; c++) {
sprintf(temp, "isamem%d_type", c); sprintf(temp, "isamem%d_type", c);
if (isamem_type[c] == 0) if (isamem_type[c] == 0)

1
src/cpu_common/cpu.h
View File

@@ -157,6 +157,7 @@ extern CPU cpus_Cyrix3[];
#if defined(DEV_BRANCH) && defined(USE_I686) #if defined(DEV_BRANCH) && defined(USE_I686)
extern CPU cpus_PentiumPro[]; extern CPU cpus_PentiumPro[];
extern CPU cpus_PentiumII[]; extern CPU cpus_PentiumII[];
extern CPU cpus_PGA370[];
#endif #endif

52
src/cpu_common/cpu_table.c
View File

@@ -228,18 +228,18 @@ CPU cpus_486DLC[] = {
CPU cpus_i486S1[] = { CPU cpus_i486S1[] = {
/*i486*/ /*i486*/
{"i486SX/16", CPU_i486SX, 16000000, 1, 0x42a, 0, 0, CPU_SUPPORTS_DYNAREC, 3, 3,3,3, 2}, {"i486SX/16", CPU_i486SX, 16000000, 1, 0x420, 0, 0, CPU_SUPPORTS_DYNAREC, 3, 3,3,3, 2},
{"i486SX/20", CPU_i486SX, 20000000, 1, 0x42a, 0, 0, CPU_SUPPORTS_DYNAREC, 4, 4,3,3, 3}, {"i486SX/20", CPU_i486SX, 20000000, 1, 0x420, 0, 0, CPU_SUPPORTS_DYNAREC, 4, 4,3,3, 3},
{"i486SX/25", CPU_i486SX, 25000000, 1, 0x42a, 0, 0, CPU_SUPPORTS_DYNAREC, 4, 4,3,3, 3}, {"i486SX/25", CPU_i486SX, 25000000, 1, 0x422, 0, 0, CPU_SUPPORTS_DYNAREC, 4, 4,3,3, 3},
{"i486SX/33", CPU_i486SX, 33333333, 1, 0x42a, 0, 0, CPU_SUPPORTS_DYNAREC, 6, 6,3,3, 4}, {"i486SX/33", CPU_i486SX, 33333333, 1, 0x42a, 0, 0, CPU_SUPPORTS_DYNAREC, 6, 6,3,3, 4},
{"i486SX2/50", CPU_i486SX2, 50000000, 2, 0x45b, 0, 0, CPU_SUPPORTS_DYNAREC, 8, 8,6,6, 6}, {"i486SX2/50", CPU_i486SX, 50000000, 2, 0x45b, 0, 0, CPU_SUPPORTS_DYNAREC, 8, 8,6,6, 6},
{"i486SX2/66 (Q0569)", CPU_i486SX2, 66666666, 2, 0x45b, 0, 0, CPU_SUPPORTS_DYNAREC, 8, 8,6,6, 8}, {"i486SX2/66 (Q0569)", CPU_i486SX, 66666666, 2, 0x45b, 0, 0, CPU_SUPPORTS_DYNAREC, 8, 8,6,6, 8},
{"i486DX/25", CPU_i486DX, 25000000, 1, 0x404, 0, 0, CPU_SUPPORTS_DYNAREC, 4, 4,3,3, 3}, {"i486DX/25", CPU_i486DX, 25000000, 1, 0x404, 0, 0, CPU_SUPPORTS_DYNAREC, 4, 4,3,3, 3},
{"i486DX/33", CPU_i486DX, 33333333, 1, 0x404, 0, 0, CPU_SUPPORTS_DYNAREC, 6, 6,3,3, 4}, {"i486DX/33", CPU_i486DX, 33333333, 1, 0x414, 0, 0, CPU_SUPPORTS_DYNAREC, 6, 6,3,3, 4},
{"i486DX/50", CPU_i486DX, 50000000, 1, 0x404, 0, 0, CPU_SUPPORTS_DYNAREC, 8, 8,4,4, 6}, {"i486DX/50", CPU_i486DX, 50000000, 1, 0x411, 0, 0, CPU_SUPPORTS_DYNAREC, 8, 8,4,4, 6},
{"i486DX2/40", CPU_i486DX2, 40000000, 2, 0x430, 0x430, 0, CPU_SUPPORTS_DYNAREC, 7, 7,6,6, 5}, {"i486DX2/40", CPU_i486DX, 40000000, 2, 0x430, 0x430, 0, CPU_SUPPORTS_DYNAREC, 7, 7,6,6, 5},
{"i486DX2/50", CPU_i486DX2, 50000000, 2, 0x430, 0x430, 0, CPU_SUPPORTS_DYNAREC, 8, 8,6,6, 6}, {"i486DX2/50", CPU_i486DX, 50000000, 2, 0x433, 0x433, 0, CPU_SUPPORTS_DYNAREC, 8, 8,6,6, 6},
{"i486DX2/66", CPU_i486DX2, 66666666, 2, 0x430, 0x430, 0, CPU_SUPPORTS_DYNAREC, 12,12,6,6, 8}, {"i486DX2/66", CPU_i486DX, 66666666, 2, 0x435, 0x435, 0, CPU_SUPPORTS_DYNAREC, 12,12,6,6, 8},
{"iDX4 OverDrive 75", CPU_iDX4, 75000000, 3, 0x1480, 0x1480, 0, CPU_SUPPORTS_DYNAREC, 12,12,9,9, 9}, /*Only added the DX4 OverDrive as the others would be redundant*/ {"iDX4 OverDrive 75", CPU_iDX4, 75000000, 3, 0x1480, 0x1480, 0, CPU_SUPPORTS_DYNAREC, 12,12,9,9, 9}, /*Only added the DX4 OverDrive as the others would be redundant*/
{"iDX4 OverDrive 100", CPU_iDX4, 100000000, 3, 0x1480, 0x1480, 0, CPU_SUPPORTS_DYNAREC, 18,18,9,9, 12}, {"iDX4 OverDrive 100", CPU_iDX4, 100000000, 3, 0x1480, 0x1480, 0, CPU_SUPPORTS_DYNAREC, 18,18,9,9, 12},
{"", -1, 0, 0, 0, 0, 0, 0, 0, 0,0,0, 0} {"", -1, 0, 0, 0, 0, 0, 0, 0, 0,0,0, 0}
@@ -270,6 +270,28 @@ CPU cpus_Cx486S1[] = {
{"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} {"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
}; };
CPU cpus_i486[] = {
/*i486/P24T*/
{"i486SX/16", CPU_i486SX, 16000000, 1, 0x420, 0, 0, CPU_SUPPORTS_DYNAREC, 3, 3,3,3, 2},
{"i486SX/20", CPU_i486SX, 20000000, 1, 0x420, 0, 0, CPU_SUPPORTS_DYNAREC, 4, 4,3,3, 3},
{"i486SX/25", CPU_i486SX, 25000000, 1, 0x422, 0, 0, CPU_SUPPORTS_DYNAREC, 4, 4,3,3, 3},
{"i486SX/33", CPU_i486SX, 33333333, 1, 0x42a, 0, 0, CPU_SUPPORTS_DYNAREC, 6, 6,3,3, 4},
{"i486SX2/50", CPU_i486SX, 50000000, 2, 0x45b, 0, 0, CPU_SUPPORTS_DYNAREC, 8, 8,6,6, 6},
{"i486SX2/66 (Q0569)", CPU_i486SX, 66666666, 2, 0x45b, 0, 0, CPU_SUPPORTS_DYNAREC, 8, 8,6,6, 8},
{"i486DX/25", CPU_i486DX, 25000000, 1, 0x404, 0, 0, CPU_SUPPORTS_DYNAREC, 4, 4,3,3, 3},
{"i486DX/33", CPU_i486DX, 33333333, 1, 0x414, 0, 0, CPU_SUPPORTS_DYNAREC, 6, 6,3,3, 4},
{"i486DX/50", CPU_i486DX, 50000000, 1, 0x411, 0, 0, CPU_SUPPORTS_DYNAREC, 8, 8,4,4, 6},
{"i486DX2/40", CPU_i486DX, 40000000, 2, 0x430, 0x430, 0, CPU_SUPPORTS_DYNAREC, 7, 7,6,6, 5},
{"i486DX2/50", CPU_i486DX, 50000000, 2, 0x433, 0x433, 0, CPU_SUPPORTS_DYNAREC, 8, 8,6,6, 6},
{"i486DX2/66", CPU_i486DX, 66666666, 2, 0x435, 0x435, 0, CPU_SUPPORTS_DYNAREC, 12,12,6,6, 8},
{"iDX4/75", CPU_iDX4, 75000000, 3, 0x480, 0x480, 0, CPU_SUPPORTS_DYNAREC, 12,12,9,9, 9}, /*CPUID available on DX4, >= 75 MHz*/
{"iDX4/100", CPU_iDX4, 100000000, 3, 0x483, 0x483, 0, CPU_SUPPORTS_DYNAREC, 18,18,9,9, 12}, /*Is on some real Intel DX2s, limit here is pretty arbitary*/
{"iDX4 OverDrive 75", CPU_iDX4, 75000000, 3, 0x1480, 0x1480, 0, CPU_SUPPORTS_DYNAREC, 12,12,9,9, 9},
{"iDX4 OverDrive 100", CPU_iDX4, 100000000, 3, 0x1480, 0x1480, 0, CPU_SUPPORTS_DYNAREC, 18,18,9,9, 12},
{"Pentium OverDrive 63", CPU_PENTIUM, 62500000, 5/2, 0x1531, 0x1531, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10,7,7, 15/2},
{"Pentium OverDrive 83", CPU_PENTIUM, 83333333, 5/2, 0x1532, 0x1532, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,8,8, 10},
{"", -1, 0, 0, 0, 0, 0, 0, 0, 0,0,0, 0}
};
CPU cpus_i486[] = { CPU cpus_i486[] = {
/*i486/P24T*/ /*i486/P24T*/
{"i486SX/16", CPU_i486SX, 16000000, 1, 0x42a, 0, 0, CPU_SUPPORTS_DYNAREC, 3, 3,3,3, 2}, {"i486SX/16", CPU_i486SX, 16000000, 1, 0x42a, 0, 0, CPU_SUPPORTS_DYNAREC, 3, 3,3,3, 2},
@@ -716,6 +738,12 @@ CPU cpus_PentiumII[] = {
{"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} {"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
}; };
CPU cpus_PGA370[] = {
{"Celeron Mendocino 100", CPU_PENTIUM2D, 100000000, 3/2, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 12},
{"Celeron Mendocino 333", CPU_PENTIUM2D, 333333333, 5, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 40},
{"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
};
#endif #endif
#endif #endif
CPU cpus_Cyrix3[] = { CPU cpus_Cyrix3[] = {

2
src/intel_piix.c
View File

@@ -1186,14 +1186,12 @@ piix_reset_hard(piix_t *dev)
if (dev->type < 3) if (dev->type < 3)
pci_set_mirq_routing(PCI_MIRQ1, PCI_IRQ_DISABLED); pci_set_mirq_routing(PCI_MIRQ1, PCI_IRQ_DISABLED);
#ifdef WRONG_SPEC
if (dev->type == 4) { if (dev->type == 4) {
dev->power.gporeg[0] = 0xff; dev->power.gporeg[0] = 0xff;
dev->power.gporeg[1] = 0xbf; dev->power.gporeg[1] = 0xbf;
dev->power.gporeg[2] = 0xff; dev->power.gporeg[2] = 0xff;
dev->power.gporeg[3] = 0x7f; dev->power.gporeg[3] = 0x7f;
} }
#endif
} }

2
src/machine/m_at_socket7_s7.c
View File

@@ -540,7 +540,7 @@ machine_at_txp4_init(const machine_t *model)
pci_register_slot(0x0B, PCI_CARD_NORMAL, 2, 3, 4, 1); pci_register_slot(0x0B, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2); pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x09, PCI_CARD_NORMAL, 4, 1, 2, 3); pci_register_slot(0x09, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4); /* PIIX4 */ pci_register_slot(0x01, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4); /* PIIX4 */
pci_register_slot(0x0D, PCI_CARD_NORMAL, 1, 2, 3, 4); pci_register_slot(0x0D, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x08, PCI_CARD_NORMAL, 1, 2, 3, 4); pci_register_slot(0x08, PCI_CARD_NORMAL, 1, 2, 3, 4);
device_add(&i430tx_device); device_add(&i430tx_device);

65
src/machine/m_at_socket8.c
View File

@@ -198,4 +198,69 @@ machine_at_p2bls_init(const machine_t *model)
} }
int
machine_at_p6bxt_init(const machine_t *model)
{
int ret;
ret = bios_load_linear(L"roms/machines/p6bxt/bxt53s.BIN",
0x000c0000, 262144, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x09, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x0C, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 4, 3, 2, 1); // Slot 5: Probably the integrated sound chip
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4);
pci_register_slot(0x01, PCI_CARD_NORMAL, 1, 2, 3, 4);
device_add(&i440bx_device);
device_add(&piix4_device);
device_add(&w83977tf_device);
device_add(&keyboard_ps2_pci_device);
device_add(&intel_flash_bxt_device);
return ret;
}
int
machine_at_63a_init(const machine_t *model)
{
// 440ZX Board. 440ZX is basically an underpowered 440BX. There no
// difference between to chipsets other than the name.
int ret;
ret = bios_load_linear(L"roms/machines/63a/63a-q3.bin",
0x000c0000, 262144, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x08, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x09, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 2, 3, 4); // Integrated Sound?
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4);
pci_register_slot(0x01, PCI_CARD_NORMAL, 1, 2, 3, 4);
device_add(&i440zx_device);
device_add(&piix4_device);
device_add(&w83977tf_device);
device_add(&keyboard_ps2_pci_device);
device_add(&intel_flash_bxt_device);
return ret;
}
#endif #endif

2
src/machine/machine.h
View File

@@ -309,6 +309,8 @@ extern int machine_at_s1668_init(const machine_t *);
extern int machine_at_6abx3_init(const machine_t *); extern int machine_at_6abx3_init(const machine_t *);
#if defined(DEV_BRANCH) && defined(USE_I686) /*P2B-LS has no VIA C3 BIOS support, so further investigation may be needed*/ #if defined(DEV_BRANCH) && defined(USE_I686) /*P2B-LS has no VIA C3 BIOS support, so further investigation may be needed*/
extern int machine_at_p2bls_init(const machine_t *); extern int machine_at_p2bls_init(const machine_t *);
extern int machine_at_p6bxt_init(const machine_t *);
extern int machine_at_63a_init(const machine_t *);
#endif #endif
/* m_at_t3100e.c */ /* m_at_t3100e.c */

2
src/machine/machine_table.c
View File

@@ -242,6 +242,8 @@ const machine_t machines[] = {
#endif #endif
#if defined(DEV_BRANCH) && defined(USE_I686) #if defined(DEV_BRANCH) && defined(USE_I686)
{ "[Slot 1 BX] ASUS P2B-LS", "p2bls", {{"Intel", cpus_PentiumII}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 1024, 8, 255, machine_at_p2bls_init, NULL }, { "[Slot 1 BX] ASUS P2B-LS", "p2bls", {{"Intel", cpus_PentiumII}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 1024, 8, 255, machine_at_p2bls_init, NULL },
{ "[Socket 370 BX] ECS P6BXT-A+", "p6bxt", {{"Intel", cpus_PGA370}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 1024, 8, 255, machine_at_p6bxt_init, NULL },
{ "[Socket 370 ZX] Soltek SL-63A1", "63a", {{"Intel", cpus_PGA370}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 256, 8, 255, machine_at_63a_init, NULL },
#endif #endif
{ NULL, NULL, {{"", 0}, {"", 0}, {"", 0}, {"", 0}, {"", 0}}, 0, 0, 0, 0, 0, NULL, NULL } { NULL, NULL, {{"", 0}, {"", 0}, {"", 0}, {"", 0}, {"", 0}}, 0, 0, 0, 0, 0, NULL, NULL }
}; };

6
src/pc.c
View File

@@ -49,6 +49,7 @@
#include "nvr.h" #include "nvr.h"
#include "machine.h" #include "machine.h"
#include "bugger.h" #include "bugger.h"
#include "postcard.h"
#include "isamem.h" #include "isamem.h"
#include "isartc.h" #include "isartc.h"
#include "lpt.h" #include "lpt.h"
@@ -112,6 +113,7 @@ int vid_cga_contrast = 0, /* (C) video */
force_43 = 0; /* (C) video */ force_43 = 0; /* (C) video */
int serial_enabled[SERIAL_MAX] = {0,0}, /* (C) enable serial ports */ int serial_enabled[SERIAL_MAX] = {0,0}, /* (C) enable serial ports */
bugger_enabled = 0, /* (C) enable ISAbugger */ bugger_enabled = 0, /* (C) enable ISAbugger */
postcard_enabled = 0, /* (C) enable POST card */
isamem_type[ISAMEM_MAX] = { 0,0,0,0 }, /* (C) enable ISA mem cards */ isamem_type[ISAMEM_MAX] = { 0,0,0,0 }, /* (C) enable ISA mem cards */
isartc_type = 0; /* (C) enable ISA RTC card */ isartc_type = 0; /* (C) enable ISA RTC card */
int gfxcard = 0; /* (C) graphics/video card */ int gfxcard = 0; /* (C) graphics/video card */
@@ -779,7 +781,9 @@ pc_reset_hard_init(void)
/* Needs the status bar... */ /* Needs the status bar... */
if (bugger_enabled) if (bugger_enabled)
device_add(&bugger_device); device_add(&bugger_device);
if (postcard_enabled)
device_add(&postcard_device);
/* Reset the CPU module. */ /* Reset the CPU module. */
resetx86(); resetx86();

142
src/postcard.c Normal file
View File

@@ -0,0 +1,142 @@
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of a port 80h POST diagnostic card.
*
* Version: @(#)postcard.c 1.0.0 2020/03/23
*
* Author: RichardG, <richardg867@gmail.com>
* Copyright 2020 RichardG.
*/
#include <stdarg.h>
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include "86box.h"
#include "86box_io.h"
#include "device.h"
#include "machine.h"
#include "plat.h"
#include "ui.h"
#include "postcard.h"
static uint16_t postcard_port;
static uint8_t postcard_written;
static uint8_t postcard_code, postcard_prev_code;
#define UISTR_LEN 13
static char postcard_str[UISTR_LEN]; /* UI output string */
extern void ui_sb_bugui(char *__str);
#ifdef ENABLE_POSTCARD_LOG
int postcard_do_log = ENABLE_POSTCARD_LOG;
static void
postcard_log(const char *fmt, ...)
{
va_list ap;
if (postcard_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
int postcard_do_log = 0;
#define postcard_log(fmt, ...)
#endif
static void
postcard_setui(void)
{
if (!postcard_written)
sprintf(postcard_str, "POST: -- --");
else if (postcard_written == 1)
sprintf(postcard_str, "POST: %02X --", postcard_code);
else
sprintf(postcard_str, "POST: %02X %02X", postcard_code, postcard_prev_code);
ui_sb_bugui(postcard_str);
if (postcard_do_log) {
/* log same string sent to the UI */
int len = strlen(postcard_str);
postcard_str[len + 1] = '\0';
postcard_str[len] = '\n';
postcard_log(postcard_str);
}
}
static void
postcard_reset(void)
{
postcard_written = 0;
postcard_code = postcard_prev_code = 0x00;
postcard_setui();
}
static void
postcard_write(uint16_t port, uint8_t val, void *priv)
{
postcard_prev_code = postcard_code;
postcard_code = val;
if (postcard_written < 2)
postcard_written++;
postcard_setui();
}
static void *
postcard_init(const device_t *info)
{
postcard_reset();
if (machines[machine].flags & MACHINE_MCA)
postcard_port = 0x680; /* MCA machines */
else if (strstr(machines[machine].name, " PS/2 "))
postcard_port = 0x90; /* ISA PS/2 machines */
else
postcard_port = 0x80; /* AT and clone machines */
postcard_log("POST card initializing on port %04Xh\n", postcard_port);
if (postcard_port) io_sethandler(postcard_port, 1,
NULL, NULL, NULL, postcard_write, NULL, NULL, NULL);
return postcard_write;
}
static void
postcard_close(UNUSED(void *priv))
{
if (postcard_port) io_removehandler(postcard_port, 1,
NULL, NULL, NULL, postcard_write, NULL, NULL, NULL);
}
const device_t postcard_device = {
"POST Card",
DEVICE_ISA,
0,
postcard_init, postcard_close, NULL,
NULL, NULL, NULL,
NULL
};

35
src/postcard.h Normal file
View File

@@ -0,0 +1,35 @@
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of a port 80h POST diagnostic card.
*
* Version: @(#)postcard.c 1.0.0 2020/03/23
*
* Author: RichardG, <richardg867@gmail.com>
* Copyright 2020 RichardG.
*/
#ifndef POSTCARD_H
# define POSTCARD_H
#ifdef __cplusplus
extern "C" {
#endif
/* Global variables. */
extern const device_t postcard_device;
/* Functions. */
#ifdef __cplusplus
}
#endif
#endif /*BUGGER_H*/

3
src/win/86Box.rc
View File

@@ -474,6 +474,9 @@ BEGIN
CONTROL "ISABugger device",IDC_CHECK_BUGGER,"Button", CONTROL "ISABugger device",IDC_CHECK_BUGGER,"Button",
BS_AUTOCHECKBOX | WS_TABSTOP,7,80,94,10 BS_AUTOCHECKBOX | WS_TABSTOP,7,80,94,10
CONTROL "POST card",IDC_CHECK_POSTCARD,"Button",
BS_AUTOCHECKBOX | WS_TABSTOP,147,80,94,10
LTEXT "ISA RTC",IDT_1767,7,99,48,10 LTEXT "ISA RTC",IDT_1767,7,99,48,10
COMBOBOX IDC_COMBO_ISARTC,64,98,155,120, COMBOBOX IDC_COMBO_ISARTC,64,98,155,120,
CBS_DROPDOWNLIST | WS_VSCROLL | WS_TABSTOP CBS_DROPDOWNLIST | WS_VSCROLL | WS_TABSTOP

2
src/win/Makefile.mingw
View File

@@ -597,7 +597,7 @@ MCHOBJ := machine.o machine_table.o \
m_at_socket4_5.o m_at_socket7_s7.o \ m_at_socket4_5.o m_at_socket7_s7.o \
m_at_socket8.o m_at_socket8.o
DEVOBJ := bugger.o hwm.o hwm_w83781d.o ibm_5161.o isamem.o isartc.o lpt.o $(SERIAL) \ DEVOBJ := bugger.o hwm.o hwm_w83781d.o ibm_5161.o isamem.o isartc.o lpt.o postcard.o $(SERIAL) \
sio_acc3221.o \ sio_acc3221.o \
sio_fdc37c66x.o sio_fdc37c669.o \ sio_fdc37c66x.o sio_fdc37c669.o \
sio_fdc37c93x.o \ sio_fdc37c93x.o \

2
src/win/Makefile_ndr.mingw
View File

@@ -602,7 +602,7 @@ MCHOBJ := machine.o machine_table.o \
m_at_socket4_5.o m_at_socket7_s7.o \ m_at_socket4_5.o m_at_socket7_s7.o \
m_at_socket8.o m_at_socket8.o
DEVOBJ := bugger.o hwm.o hwm_w83781d.o ibm_5161.o isamem.o isartc.o lpt.o $(SERIAL) \ DEVOBJ := bugger.o hwm.o hwm_w83781d.o ibm_5161.o isamem.o isartc.o lpt.o postcard.o $(SERIAL) \
sio_acc3221.o \ sio_acc3221.o \
sio_fdc37c66x.o sio_fdc37c669.o \ sio_fdc37c66x.o sio_fdc37c669.o \
sio_fdc37c93x.o \ sio_fdc37c93x.o \

2
src/win/resource.h
View File

@@ -175,7 +175,7 @@
#define IDC_CHECK_IDE_QUA 1127 #define IDC_CHECK_IDE_QUA 1127
#define IDC_BUTTON_IDE_QUA 1128 #define IDC_BUTTON_IDE_QUA 1128
#define IDC_CHECK_BUGGER 1129 #define IDC_CHECK_BUGGER 1129
#define IDC_CONFIGURE_BUGGER 1130 #define IDC_CHECK_POSTCARD 1130
#define IDC_COMBO_ISARTC 1131 #define IDC_COMBO_ISARTC 1131
#define IDC_CONFIGURE_ISARTC 1132 #define IDC_CONFIGURE_ISARTC 1132
#define IDC_GROUP_ISAMEM 1140 #define IDC_GROUP_ISAMEM 1140

10
src/win/win_settings.c
View File

@@ -97,6 +97,7 @@ static int temp_serial[2], temp_lpt[3];
/* Other peripherals category */ /* Other peripherals category */
static int temp_hdc, temp_scsi_card, temp_ide_ter, temp_ide_qua; static int temp_hdc, temp_scsi_card, temp_ide_ter, temp_ide_qua;
static int temp_bugger; static int temp_bugger;
static int temp_postcard;
static int temp_isartc; static int temp_isartc;
static int temp_isamem[ISAMEM_MAX]; static int temp_isamem[ISAMEM_MAX];
@@ -248,6 +249,7 @@ win_settings_init(void)
temp_ide_ter = ide_ter_enabled; temp_ide_ter = ide_ter_enabled;
temp_ide_qua = ide_qua_enabled; temp_ide_qua = ide_qua_enabled;
temp_bugger = bugger_enabled; temp_bugger = bugger_enabled;
temp_postcard = postcard_enabled;
temp_isartc = isartc_type; temp_isartc = isartc_type;
/* ISA memory boards. */ /* ISA memory boards. */
@@ -356,6 +358,7 @@ win_settings_changed(void)
i = i || (temp_ide_ter != ide_ter_enabled); i = i || (temp_ide_ter != ide_ter_enabled);
i = i || (temp_ide_qua != ide_qua_enabled); i = i || (temp_ide_qua != ide_qua_enabled);
i = i || (temp_bugger != bugger_enabled); i = i || (temp_bugger != bugger_enabled);
i = i || (temp_postcard != postcard_enabled);
i = i || (temp_isartc != isartc_type); i = i || (temp_isartc != isartc_type);
/* ISA memory boards. */ /* ISA memory boards. */
@@ -460,6 +463,7 @@ win_settings_save(void)
ide_ter_enabled = temp_ide_ter; ide_ter_enabled = temp_ide_ter;
ide_qua_enabled = temp_ide_qua; ide_qua_enabled = temp_ide_qua;
bugger_enabled = temp_bugger; bugger_enabled = temp_bugger;
postcard_enabled = temp_postcard;
isartc_type = temp_isartc; isartc_type = temp_isartc;
/* ISA memory boards. */ /* ISA memory boards. */
@@ -1594,6 +1598,9 @@ win_settings_peripherals_proc(HWND hdlg, UINT message, WPARAM wParam, LPARAM lPa
h=GetDlgItem(hdlg, IDC_CHECK_BUGGER); h=GetDlgItem(hdlg, IDC_CHECK_BUGGER);
SendMessage(h, BM_SETCHECK, temp_bugger, 0); SendMessage(h, BM_SETCHECK, temp_bugger, 0);
h=GetDlgItem(hdlg, IDC_CHECK_POSTCARD);
SendMessage(h, BM_SETCHECK, temp_postcard, 0);
/* Populate the ISA RTC card dropdown. */ /* Populate the ISA RTC card dropdown. */
e = 0; e = 0;
h = GetDlgItem(hdlg, IDC_COMBO_ISARTC); h = GetDlgItem(hdlg, IDC_COMBO_ISARTC);
@@ -1797,6 +1804,9 @@ win_settings_peripherals_proc(HWND hdlg, UINT message, WPARAM wParam, LPARAM lPa
h = GetDlgItem(hdlg, IDC_CHECK_BUGGER); h = GetDlgItem(hdlg, IDC_CHECK_BUGGER);
temp_bugger = SendMessage(h, BM_GETCHECK, 0, 0); temp_bugger = SendMessage(h, BM_GETCHECK, 0, 0);
h = GetDlgItem(hdlg, IDC_CHECK_POSTCARD);
temp_postcard = SendMessage(h, BM_GETCHECK, 0, 0);
free(stransi); free(stransi);
free(lptsTemp); free(lptsTemp);