Rewrote the V86P's I/O chip and fixed its UART IRQ assignments, fixes serial mouse, closes #1678.
This commit is contained in:
OBattler
@@ -43,306 +43,318 @@
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#include <86box/nvr.h>
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#include <86box/sio.h>
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typedef struct upc_t
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{
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uint32_t local;
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int configuration_state; /* state of algorithm to enter configuration mode */
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int configuration_mode;
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uint16_t cri_addr; /* cri = configuration index register, addr is even */
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uint16_t cap_addr; /* cap = configuration access port, addr is odd and is cri_addr + 1 */
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uint8_t cri; /* currently indexed register */
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uint32_t local;
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int configuration_state; /* state of algorithm to enter configuration mode */
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int configuration_mode;
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uint16_t cri_addr; /* cri = configuration index register, addr is even */
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uint16_t cap_addr; /* cap = configuration access port, addr is odd and is cri_addr + 1 */
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uint8_t cri; /* currently indexed register */
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uint8_t last_write;
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/* these regs are not affected by reset */
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uint8_t regs[15]; /* there are 16 indexes, but there is no need to store the last one which is: R = cri_addr / 4, W = exit config mode */
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fdc_t *fdc;
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nvr_t *nvr;
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void *gameport;
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serial_t *uart[2];
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/* these regs are not affected by reset */
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uint8_t regs[15]; /* there are 16 indexes, but there is no need to store the last one which is: R = cri_addr / 4, W = exit config mode */
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fdc_t * fdc;
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nvr_t * nvr;
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void * gameport;
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serial_t * uart[2];
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} upc_t;
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static void
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f82c710_update_ports(upc_t *upc)
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f82c710_update_ports(upc_t *dev, int set)
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{
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uint16_t com_addr = 0;
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uint16_t lpt_addr = 0;
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serial_remove(upc->uart[0]);
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serial_remove(upc->uart[1]);
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lpt1_remove();
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lpt2_remove();
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fdc_remove(upc->fdc);
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ide_pri_disable();
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uint16_t com_addr = 0;
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uint16_t lpt_addr = 0;
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if (upc->regs[0] & 4) {
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com_addr = upc->regs[4] * 4;
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if (com_addr == SERIAL1_ADDR) {
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serial_setup(upc->uart[0], com_addr, 4);
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} else if (com_addr == SERIAL2_ADDR) {
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serial_setup(upc->uart[1], com_addr, 3);
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}
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}
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serial_remove(dev->uart[0]);
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serial_remove(dev->uart[1]);
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lpt1_remove();
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lpt2_remove();
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fdc_remove(dev->fdc);
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ide_pri_disable();
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if (upc->regs[0] & 8) {
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lpt_addr = upc->regs[6] * 4;
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lpt1_init(lpt_addr);
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if ((lpt_addr == 0x378) || (lpt_addr == 0x3bc)) {
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lpt1_irq(7);
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} else if (lpt_addr == 0x278) {
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lpt1_irq(5);
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}
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}
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if (!set)
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return;
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if (upc->regs[12] & 0x80) {
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ide_pri_enable();
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}
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if (dev->regs[0] & 4) {
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com_addr = dev->regs[4] * 4;
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if (com_addr == SERIAL1_ADDR)
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serial_setup(dev->uart[0], com_addr, 4);
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else if (com_addr == SERIAL2_ADDR)
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serial_setup(dev->uart[1], com_addr, 3);
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}
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if (upc->regs[12] & 0x20) {
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fdc_set_base(upc->fdc, 0x03f0);
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}
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if (dev->regs[0] & 8) {
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lpt_addr = dev->regs[6] * 4;
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lpt1_init(lpt_addr);
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if ((lpt_addr == 0x378) || (lpt_addr == 0x3bc))
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lpt1_irq(7);
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else if (lpt_addr == 0x278)
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lpt1_irq(5);
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}
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if (dev->regs[12] & 0x80)
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ide_pri_enable();
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if (dev->regs[12] & 0x20)
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fdc_set_base(dev->fdc, 0x03f0);
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}
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static void
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f82c606_update_ports(upc_t *upc)
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f82c606_update_ports(upc_t *dev, int set)
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{
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uint8_t uart1_int = 0xff;
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uint8_t uart2_int = 0xff;
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uint8_t lpt1_int = 0xff;
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int nvr_int = -1;
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uint8_t uart1_int = 0xff;
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uint8_t uart2_int = 0xff;
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uint8_t lpt1_int = 0xff;
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int nvr_int = -1;
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serial_remove(upc->uart[0]);
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serial_remove(upc->uart[1]);
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lpt1_remove();
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lpt2_remove();
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serial_remove(dev->uart[0]);
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serial_remove(dev->uart[1]);
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lpt1_remove();
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lpt2_remove();
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nvr_at_handler(0, upc->regs[3] * 4, upc->nvr);
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nvr_at_handler(0, 0x70, upc->nvr);
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nvr_at_handler(0, ((uint16_t) dev->regs[3]) << 2, dev->nvr);
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nvr_at_handler(0, 0x70, dev->nvr);
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switch (upc->regs[8] & 0xc0) {
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case 0x40: nvr_int = 4; break;
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case 0x80: uart1_int = 4; break;
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case 0xc0: uart2_int = 4; break;
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}
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gameport_remap(dev->gameport, 0);
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switch (upc->regs[8] & 0x30) {
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case 0x10: nvr_int = 3; break;
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case 0x20: uart1_int = 3; break;
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case 0x30: uart2_int = 3; break;
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}
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if (!set)
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return;
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switch (upc->regs[8] & 0x0c) {
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switch (dev->regs[8] & 0xc0) {
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case 0x40: nvr_int = 3; break;
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case 0x80: uart1_int = 3; break;
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case 0xc0: uart2_int = 3; break;
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}
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switch (dev->regs[8] & 0x30) {
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case 0x10: nvr_int = 4; break;
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case 0x20: uart1_int = 4; break;
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case 0x30: uart2_int = 4; break;
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}
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switch (dev->regs[8] & 0x0c) {
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case 0x04: nvr_int = 5; break;
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case 0x08: uart1_int = 5; break;
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case 0x0c: lpt1_int = 5; break;
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}
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}
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switch (upc->regs[8] & 0x03) {
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switch (dev->regs[8] & 0x03) {
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case 0x01: nvr_int = 7; break;
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case 0x02: uart2_int = 7; break;
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case 0x03: lpt1_int = 7; break;
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}
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}
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if (upc->regs[0] & 1)
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gameport_remap(upc->gameport, upc->regs[7] * 4);
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else
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gameport_remap(upc->gameport, 0);
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if (dev->regs[0] & 1) {
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gameport_remap(dev->gameport, ((uint16_t) dev->regs[7]) << 2);
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pclog("Game port at %04X\n", ((uint16_t) dev->regs[7]) << 2);
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}
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if (upc->regs[0] & 2)
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serial_setup(upc->uart[0], upc->regs[4] * 4, uart1_int);
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if (dev->regs[0] & 2) {
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serial_setup(dev->uart[0], ((uint16_t) dev->regs[4]) << 2, uart1_int);
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pclog("UART 1 at %04X, IRQ %i\n", ((uint16_t) dev->regs[4]) << 2, uart1_int);
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}
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if (upc->regs[0] & 4)
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serial_setup(upc->uart[1], upc->regs[5] * 4, uart2_int);
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if (dev->regs[0] & 4) {
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serial_setup(dev->uart[1], ((uint16_t) dev->regs[5]) << 2, uart2_int);
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pclog("UART 2 at %04X, IRQ %i\n", ((uint16_t) dev->regs[5]) << 2, uart2_int);
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}
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if (upc->regs[0] & 8) {
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lpt1_init(upc->regs[6] * 4);
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lpt1_irq(lpt1_int);
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}
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if (dev->regs[0] & 8) {
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lpt1_init(((uint16_t) dev->regs[6]) << 2);
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lpt1_irq(lpt1_int);
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pclog("LPT1 at %04X, IRQ %i\n", ((uint16_t) dev->regs[6]) << 2, lpt1_int);
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}
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nvr_at_handler(1, upc->regs[3] * 4, upc->nvr);
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nvr_irq_set(nvr_int, upc->nvr);
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nvr_at_handler(1, ((uint16_t) dev->regs[3]) << 2, dev->nvr);
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nvr_irq_set(nvr_int, dev->nvr);
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pclog("RTC at %04X, IRQ %i\n", ((uint16_t) dev->regs[3]) << 2, nvr_int);
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}
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static uint8_t
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f82c710_config_read(uint16_t port, void *priv)
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{
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upc_t *upc = (upc_t *)priv;
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uint8_t temp = 0xff;
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upc_t *dev = (upc_t *) priv;
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uint8_t temp = 0xff;
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if (upc->configuration_mode) {
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if (port == upc->cri_addr) {
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temp = upc->cri;
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} else if (port == upc->cap_addr) {
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if (upc->cri == 0xf)
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temp = upc->cri_addr / 4;
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else
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temp = upc->regs[upc->cri];
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}
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}
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if (dev->configuration_mode) {
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if (port == dev->cri_addr) {
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temp = dev->cri;
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} else if (port == dev->cap_addr) {
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if (dev->cri == 0xf)
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temp = dev->cri_addr / 4;
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else
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temp = dev->regs[dev->cri];
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}
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}
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return temp;
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return temp;
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}
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static void
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f82c710_config_write(uint16_t port, uint8_t val, void *priv)
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{
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upc_t *upc = (upc_t *)priv;
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int configuration_state_event = 0;
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upc_t *dev = (upc_t *) priv;
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int configuration_state_event = 0;
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switch(port) {
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case 0x2fa:
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if (upc->configuration_state == 0 && val == 0x55)
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configuration_state_event = 1;
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else if (upc->configuration_state == 4) {
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uint8_t addr_verify = upc->cri_addr / 4;
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addr_verify += val;
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if (addr_verify == 0xff) {
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upc->configuration_mode = 1;
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/* TODO: is the value of cri reset here or when exiting configuration mode? */
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io_sethandler(upc->cri_addr, 0x0002, f82c710_config_read, NULL, NULL, f82c710_config_write, NULL, NULL, upc);
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} else {
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upc->configuration_mode = 0;
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}
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}
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break;
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case 0x3fa:
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if (upc->configuration_state == 1 && val == 0xaa)
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configuration_state_event = 1;
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else if (upc->configuration_state == 2 && val == 0x36)
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configuration_state_event = 1;
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else if (upc->configuration_state == 3) {
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upc->cri_addr = val * 4;
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upc->cap_addr = upc->cri_addr + 1;
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configuration_state_event = 1;
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}
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break;
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default:
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break;
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}
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if (upc->configuration_mode) {
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if (port == upc->cri_addr) {
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upc->cri = val & 0xf;
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} else if (port == upc->cap_addr) {
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if (upc->cri == 0xf) {
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upc->configuration_mode = 0;
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io_removehandler(upc->cri_addr, 0x0002, f82c710_config_read, NULL, NULL, f82c710_config_write, NULL, NULL, upc);
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/* TODO: any benefit in updating at each register write instead of when exiting config mode? */
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if (upc->local == 710)
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f82c710_update_ports(upc);
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if (upc->local == 606)
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f82c606_update_ports(upc);
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} else {
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upc->regs[upc->cri] = val;
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}
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}
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}
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switch (port) {
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case 0x2fa:
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if ((dev->configuration_state == 0) && (val != 0x00) && (val != 0xff) && (dev->local == 606)) {
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configuration_state_event = 1;
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dev->last_write = val;
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} else if ((dev->configuration_state == 0) && (val == 0x55) && (dev->local == 710))
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configuration_state_event = 1;
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else if (dev->configuration_state == 4) {
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if ((val | dev->last_write) == 0xff) {
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dev->cri_addr = ((uint16_t) dev->last_write) << 2;
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dev->cap_addr = dev->cri_addr + 1;
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dev->configuration_mode = 1;
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if (dev->local == 606)
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f82c606_update_ports(dev, 0);
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else if (dev->local == 710)
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f82c710_update_ports(dev, 0);
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/* TODO: is the value of cri reset here or when exiting configuration mode? */
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io_sethandler(dev->cri_addr, 0x0002, f82c710_config_read, NULL, NULL, f82c710_config_write, NULL, NULL, dev);
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} else
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dev->configuration_mode = 0;
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}
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break;
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case 0x3fa:
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if ((dev->configuration_state == 1) && ((val | dev->last_write) == 0xff) && (dev->local == 606))
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configuration_state_event = 1;
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else if ((dev->configuration_state == 1) && (val == 0xaa) && (dev->local == 710))
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configuration_state_event = 1;
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else if ((dev->configuration_state == 2) && (val == 0x36))
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configuration_state_event = 1;
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else if (dev->configuration_state == 3) {
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dev->last_write = val;
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configuration_state_event = 1;
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}
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break;
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default:
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break;
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}
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/* TODO: is the state only reset when accessing 0x2fa and 0x3fa wrongly? */
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if ((port == 0x2fa || port == 0x3fa) && configuration_state_event)
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upc->configuration_state++;
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else
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upc->configuration_state = 0;
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if (dev->configuration_mode) {
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if (port == dev->cri_addr) {
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dev->cri = val & 0xf;
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} else if (port == dev->cap_addr) {
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if (dev->cri == 0xf) {
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dev->configuration_mode = 0;
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io_removehandler(dev->cri_addr, 0x0002, f82c710_config_read, NULL, NULL, f82c710_config_write, NULL, NULL, dev);
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/* TODO: any benefit in updating at each register write instead of when exiting config mode? */
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if (dev->local == 606)
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f82c606_update_ports(dev, 1);
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else if (dev->local == 710)
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f82c710_update_ports(dev, 1);
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} else
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dev->regs[dev->cri] = val;
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}
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}
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/* TODO: is the state only reset when accessing 0x2fa and 0x3fa wrongly? */
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if ((port == 0x2fa || port == 0x3fa) && configuration_state_event)
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dev->configuration_state++;
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else
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dev->configuration_state = 0;
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}
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static void
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f82c710_reset(upc_t *upc)
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f82c710_reset(void *priv)
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{
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serial_remove(upc->uart[0]);
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serial_setup(upc->uart[0], SERIAL1_ADDR, SERIAL1_IRQ);
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upc_t *dev = (upc_t *) priv;
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serial_remove(upc->uart[1]);
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serial_setup(upc->uart[1], SERIAL2_ADDR, SERIAL2_IRQ);
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lpt1_remove();
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lpt1_init(0x378);
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lpt1_irq(7);
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/* Set power-on defaults. */
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if (dev->local == 606) {
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dev->regs[0] = 0x00; /* Enable */
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dev->regs[1] = 0x00; /* Configuration Register */
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dev->regs[2] = 0x00; /* Ext Baud Rate Select */
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dev->regs[3] = 0xb0; /* RTC Base */
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dev->regs[4] = 0xfe; /* UART1 Base */
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dev->regs[5] = 0xbe; /* UART2 Base */
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dev->regs[6] = 0x9e; /* Parallel Base */
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dev->regs[7] = 0x80; /* Game Base */
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dev->regs[8] = 0xec; /* Interrupt Select */
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} else if (dev->local == 710) {
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dev->regs[0] = 0x0c;
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dev->regs[1] = 0x00;
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dev->regs[2] = 0x00;
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dev->regs[3] = 0x00;
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dev->regs[4] = 0xfe;
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dev->regs[5] = 0x00;
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dev->regs[6] = 0x9e;
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dev->regs[7] = 0x00;
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dev->regs[8] = 0x00;
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dev->regs[9] = 0xb0;
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dev->regs[10] = 0x00;
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dev->regs[11] = 0x00;
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dev->regs[12] = 0xa0;
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dev->regs[13] = 0x00;
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dev->regs[14] = 0x00;
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}
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if (upc->local == 710)
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fdc_reset(upc->fdc);
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if (dev->local == 606)
|
||||
f82c606_update_ports(dev, 1);
|
||||
else if (dev->local == 710)
|
||||
f82c710_update_ports(dev, 1);
|
||||
}
|
||||
|
||||
static void *
|
||||
f82c710_init(const device_t *info)
|
||||
{
|
||||
upc_t *upc = (upc_t *) malloc(sizeof(upc_t));
|
||||
memset(upc, 0, sizeof(upc_t));
|
||||
upc->local = info->local;
|
||||
|
||||
if (upc->local == 710) {
|
||||
upc->regs[0] = 0x0c;
|
||||
upc->regs[1] = 0x00;
|
||||
upc->regs[2] = 0x00;
|
||||
upc->regs[3] = 0x00;
|
||||
upc->regs[4] = 0xfe;
|
||||
upc->regs[5] = 0x00;
|
||||
upc->regs[6] = 0x9e;
|
||||
upc->regs[7] = 0x00;
|
||||
upc->regs[8] = 0x00;
|
||||
upc->regs[9] = 0xb0;
|
||||
upc->regs[10] = 0x00;
|
||||
upc->regs[11] = 0x00;
|
||||
upc->regs[12] = 0xa0;
|
||||
upc->regs[13] = 0x00;
|
||||
upc->regs[14] = 0x00;
|
||||
|
||||
upc->fdc = device_add(&fdc_at_device);
|
||||
}
|
||||
|
||||
if (upc->local == 606) {
|
||||
/* Set power-on defaults. */
|
||||
upc->regs[0] = 0x00; /* Enable */
|
||||
upc->regs[1] = 0x00; /* Configuration Register */
|
||||
upc->regs[2] = 0x00; /* Ext Baud Rate Select */
|
||||
upc->regs[3] = 0xb0; /* RTC Base */
|
||||
upc->regs[4] = 0xfe; /* UART1 Base */
|
||||
upc->regs[5] = 0xbe; /* UART2 Base */
|
||||
upc->regs[6] = 0x9e; /* Parallel Base */
|
||||
upc->regs[7] = 0x80; /* Game Base */
|
||||
upc->regs[8] = 0xec; /* Interrupt Select */
|
||||
|
||||
upc->nvr = device_add(&at_nvr_old_device);
|
||||
upc->gameport = gameport_add(&gameport_sio_device);
|
||||
}
|
||||
|
||||
upc->uart[0] = device_add_inst(&ns16450_device, 1);
|
||||
upc->uart[1] = device_add_inst(&ns16450_device, 2);
|
||||
|
||||
io_sethandler(0x02fa, 0x0001, NULL, NULL, NULL, f82c710_config_write, NULL, NULL, upc);
|
||||
io_sethandler(0x03fa, 0x0001, NULL, NULL, NULL, f82c710_config_write, NULL, NULL, upc);
|
||||
|
||||
f82c710_reset(upc);
|
||||
|
||||
if (upc->local == 710)
|
||||
f82c710_update_ports(upc);
|
||||
if (upc->local == 606)
|
||||
f82c606_update_ports(upc);
|
||||
|
||||
return upc;
|
||||
}
|
||||
|
||||
static void
|
||||
f82c710_close(void *priv)
|
||||
{
|
||||
upc_t *upc = (upc_t *)priv;
|
||||
upc_t *dev = (upc_t *) priv;
|
||||
|
||||
free(upc);
|
||||
free(dev);
|
||||
}
|
||||
|
||||
|
||||
static void *
|
||||
f82c710_init(const device_t *info)
|
||||
{
|
||||
upc_t *dev = (upc_t *) malloc(sizeof(upc_t));
|
||||
memset(dev, 0, sizeof(upc_t));
|
||||
dev->local = info->local;
|
||||
|
||||
if (dev->local == 606) {
|
||||
dev->nvr = device_add(&at_nvr_old_device);
|
||||
dev->gameport = gameport_add(&gameport_sio_device);
|
||||
} else if (dev->local == 710)
|
||||
dev->fdc = device_add(&fdc_at_device);
|
||||
|
||||
dev->uart[0] = device_add_inst(&ns16450_device, 1);
|
||||
dev->uart[1] = device_add_inst(&ns16450_device, 2);
|
||||
|
||||
io_sethandler(0x02fa, 0x0001, NULL, NULL, NULL, f82c710_config_write, NULL, NULL, dev);
|
||||
io_sethandler(0x03fa, 0x0001, NULL, NULL, NULL, f82c710_config_write, NULL, NULL, dev);
|
||||
|
||||
f82c710_reset(dev);
|
||||
|
||||
return dev;
|
||||
}
|
||||
|
||||
|
||||
const device_t f82c606_device = {
|
||||
"82C606 CHIPSpak Multifunction Controller",
|
||||
0,
|
||||
606,
|
||||
f82c710_init, f82c710_close, NULL,
|
||||
{ NULL }, NULL, NULL,
|
||||
NULL
|
||||
"82C606 CHIPSpak Multifunction Controller",
|
||||
0,
|
||||
606,
|
||||
f82c710_init, f82c710_close, f82c710_reset,
|
||||
{ NULL }, NULL, NULL,
|
||||
NULL
|
||||
};
|
||||
|
||||
const device_t f82c710_device = {
|
||||
"F82C710 UPC Super I/O",
|
||||
0,
|
||||
710,
|
||||
f82c710_init, f82c710_close, NULL,
|
||||
{ NULL }, NULL, NULL,
|
||||
NULL
|
||||
"F82C710 UPC Super I/O",
|
||||
0,
|
||||
710,
|
||||
f82c710_init, f82c710_close, f82c710_reset,
|
||||
{ NULL }, NULL, NULL,
|
||||
NULL
|
||||
};
|
||||
|
||||
Reference in New Issue
Block a user