diff --git a/src/cpu/386.c b/src/cpu/386.c
index fe05bb02e..940e01a76 100644
--- a/src/cpu/386.c
+++ b/src/cpu/386.c
@@ -281,11 +281,6 @@ exec386(int cycs)
 			}
 		}
 
-		ins_cycles -= cycles;
-		tsc += ins_cycles;
-
-		cycdiff = oldcyc - cycles;
-
 		if (smi_line)
 			enter_smm_check(0);
 		else if (trap) {
@@ -336,6 +331,11 @@ exec386(int cycs)
 
 		cpu_end_block_after_ins = 0;
 
+		ins_cycles -= cycles;
+		tsc += ins_cycles;
+
+		cycdiff = oldcyc - cycles;
+
 		if (timetolive) {
 			timetolive--;
 			if (!timetolive)
diff --git a/src/cpu/386_dynarec.c b/src/cpu/386_dynarec.c
index 663770bc3..552669434 100644
--- a/src/cpu/386_dynarec.c
+++ b/src/cpu/386_dynarec.c
@@ -756,19 +756,6 @@ exec386_dynarec(int cycs)
 			exec386_dynarec_dyn();
 		}
 
-		cycdiff = oldcyc - cycles;
-		delta = tsc - oldtsc;
-		if (delta > 0) {
-			/* TSC has changed, this means interim timer processing has happened,
-			   see how much we still need to add. */
-			cycdiff -= delta;
-			if (cycdiff > 0)
-				tsc += cycdiff;
-		} else {
-			/* TSC has not changed. */
-			tsc += cycdiff;
-		}
-
 		if (cpu_state.abrt) {
 			flags_rebuild();
 			tempi = cpu_state.abrt & ABRT_MASK;
@@ -819,6 +806,19 @@ exec386_dynarec(int cycs)
 			}
 		}
 
+		cycdiff = oldcyc - cycles;
+		delta = tsc - oldtsc;
+		if (delta > 0) {
+			/* TSC has changed, this means interim timer processing has happened,
+			   see how much we still need to add. */
+			cycdiff -= delta;
+			if (cycdiff > 0)
+				tsc += cycdiff;
+		} else {
+			/* TSC has not changed. */
+			tsc += cycdiff;
+		}
+
 		if (cycdiff > 0) {
 			if (TIMER_VAL_LESS_THAN_VAL(timer_target, (uint32_t) tsc))
 				timer_process_inline();