claunia/86Box
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

CPU and MMU cleanups and fixes, and non-Debug builds are now stripped again.

Browse Source
This commit is contained in:
OBattler
2021-04-10 07:18:47 +02:00
parent 99ca313565
commit c370ae7e18
22 changed files with 3488 additions and 4367 deletions
Download Patch File Download Diff File Expand all files Collapse all files

144
src/cpu/x86_ops_rep.h
View File

@@ -2,7 +2,8 @@
static int opREP_INSB_ ## size(uint32_t fetchdat) \
{ \
int reads = 0, writes = 0, total_cycles = 0; \
uint64_t addr64 = 0x0000000000000000ULL; \
\
addr64 = 0x00000000; \
\
if (CNT_REG > 0) \
{ \
@@ -11,6 +12,7 @@ static int opREP_INSB_ ## size(uint32_t fetchdat)
SEG_CHECK_WRITE(&cpu_state.seg_es); \
check_io_perm(DX); \
CHECK_WRITE(&cpu_state.seg_es, DEST_REG, DEST_REG); \
high_page = 0; \
do_mmut_wb(es, DEST_REG, &addr64); \
if (cpu_state.abrt) return 1; \
temp = inb(DX); \
@@ -34,7 +36,8 @@ static int opREP_INSB_ ## size(uint32_t fetchdat)
static int opREP_INSW_ ## size(uint32_t fetchdat) \
{ \
int reads = 0, writes = 0, total_cycles = 0; \
uint64_t addr64[2]; \
\
addr64a[0] = addr64a[1] = 0x00000000; \
\
if (CNT_REG > 0) \
{ \
@@ -43,11 +46,12 @@ static int opREP_INSW_ ## size(uint32_t fetchdat)
SEG_CHECK_WRITE(&cpu_state.seg_es); \
check_io_perm(DX); \
check_io_perm(DX+1); \
CHECK_WRITE(&cpu_state.seg_es, DEST_REG, DEST_REG + 1); \
do_mmut_ww(es, DEST_REG, addr64); \
CHECK_WRITE(&cpu_state.seg_es, DEST_REG, DEST_REG + 1UL); \
high_page = 0; \
do_mmut_ww(es, DEST_REG, addr64a); \
if (cpu_state.abrt) return 1; \
temp = inw(DX); \
writememw_n(es, DEST_REG, addr64, temp); if (cpu_state.abrt) return 1; \
writememw_n(es, DEST_REG, addr64a, temp); if (cpu_state.abrt) return 1; \
\
if (cpu_state.flags & D_FLAG) DEST_REG -= 2; \
else DEST_REG += 2; \
@@ -67,7 +71,8 @@ static int opREP_INSW_ ## size(uint32_t fetchdat)
static int opREP_INSL_ ## size(uint32_t fetchdat) \
{ \
int reads = 0, writes = 0, total_cycles = 0; \
uint64_t addr64[4]; \
\
addr64a[0] = addr64a[1] = addr64a[2] = addr64a[3] = 0x00000000; \
\
if (CNT_REG > 0) \
{ \
@@ -78,11 +83,12 @@ static int opREP_INSL_ ## size(uint32_t fetchdat)
check_io_perm(DX+1); \
check_io_perm(DX+2); \
check_io_perm(DX+3); \
CHECK_WRITE(&cpu_state.seg_es, DEST_REG, DEST_REG + 3); \
do_mmut_wl(es, DEST_REG, addr64); \
CHECK_WRITE(&cpu_state.seg_es, DEST_REG, DEST_REG + 3UL); \
high_page = 0; \
do_mmut_wl(es, DEST_REG, addr64a); \
if (cpu_state.abrt) return 1; \
temp = inl(DX); \
writememl_n(es, DEST_REG, addr64, temp); if (cpu_state.abrt) return 1; \
writememl_n(es, DEST_REG, addr64a, temp); if (cpu_state.abrt) return 1; \
\
if (cpu_state.flags & D_FLAG) DEST_REG -= 4; \
else DEST_REG += 4; \
@@ -135,7 +141,7 @@ static int opREP_OUTSW_ ## size(uint32_t fetchdat)
{ \
uint16_t temp; \
SEG_CHECK_READ(cpu_state.ea_seg); \
CHECK_READ(cpu_state.ea_seg, SRC_REG, SRC_REG + 1); \
CHECK_READ(cpu_state.ea_seg, SRC_REG, SRC_REG + 1UL); \
temp = readmemw(cpu_state.ea_seg->base, SRC_REG); if (cpu_state.abrt) return 1; \
check_io_perm(DX); \
check_io_perm(DX+1); \
@@ -163,7 +169,7 @@ static int opREP_OUTSL_ ## size(uint32_t fetchdat)
{ \
uint32_t temp; \
SEG_CHECK_READ(cpu_state.ea_seg); \
CHECK_READ(cpu_state.ea_seg, SRC_REG, SRC_REG + 3); \
CHECK_READ(cpu_state.ea_seg, SRC_REG, SRC_REG + 3UL); \
temp = readmeml(cpu_state.ea_seg->base, SRC_REG); if (cpu_state.abrt) return 1; \
check_io_perm(DX); \
check_io_perm(DX+1); \
@@ -190,27 +196,27 @@ static int opREP_MOVSB_ ## size(uint32_t fetchdat)
{ \
int reads = 0, writes = 0, total_cycles = 0; \
int cycles_end = cycles - ((is386 && cpu_use_dynarec) ? 1000 : 100); \
uint64_t addr64r = 0x0000000000000000ULL; \
uint64_t addr64w = 0x0000000000000000ULL; \
addr64 = addr64_2 = 0x00000000; \
if (trap) \
cycles_end = cycles+1; /*Force the instruction to end after only one iteration when trap flag set*/ \
if (CNT_REG > 0) \
{ \
SEG_CHECK_READ(cpu_state.ea_seg); \
SEG_CHECK_WRITE(&cpu_state.seg_es); \
} \
} \
while (CNT_REG > 0) \
{ \
uint8_t temp; \
\
CHECK_READ_REP(cpu_state.ea_seg, SRC_REG, SRC_REG); \
do_mmut_rb(cpu_state.ea_seg->base, SRC_REG, &addr64r); \
high_page = 0; \
do_mmut_rb(cpu_state.ea_seg->base, SRC_REG, &addr64) ; \
if (cpu_state.abrt) break; \
CHECK_WRITE_REP(&cpu_state.seg_es, DEST_REG, DEST_REG); \
do_mmut_wb(es, DEST_REG, &addr64w); \
do_mmut_wb(es, DEST_REG, &addr64_2); \
if (cpu_state.abrt) break; \
temp = readmemb_n(cpu_state.ea_seg->base, SRC_REG, addr64r); if (cpu_state.abrt) return 1; \
writememb_n(es, DEST_REG, addr64w, temp); if (cpu_state.abrt) return 1; \
temp = readmemb_n(cpu_state.ea_seg->base, SRC_REG, addr64); if (cpu_state.abrt) return 1; \
writememb_n(es, DEST_REG, addr64_2, temp); if (cpu_state.abrt) return 1; \
\
if (cpu_state.flags & D_FLAG) { DEST_REG--; SRC_REG--; } \
else { DEST_REG++; SRC_REG++; } \
@@ -233,27 +239,28 @@ static int opREP_MOVSW_ ## size(uint32_t fetchdat)
{ \
int reads = 0, writes = 0, total_cycles = 0; \
int cycles_end = cycles - ((is386 && cpu_use_dynarec) ? 1000 : 100); \
uint64_t addr64r[2]; \
uint64_t addr64w[2]; \
addr64a[0] = addr64a[1] = 0x00000000; \
addr64a_2[0] = addr64a_2[1] = 0x00000000; \
if (trap) \
cycles_end = cycles+1; /*Force the instruction to end after only one iteration when trap flag set*/ \
if (CNT_REG > 0) \
{ \
SEG_CHECK_READ(cpu_state.ea_seg); \
SEG_CHECK_WRITE(&cpu_state.seg_es); \
} \
} \
while (CNT_REG > 0) \
{ \
uint16_t temp; \
\
CHECK_READ_REP(cpu_state.ea_seg, SRC_REG, SRC_REG + 1); \
do_mmut_rw(cpu_state.ea_seg->base, SRC_REG, addr64r); \
CHECK_READ_REP(cpu_state.ea_seg, SRC_REG, SRC_REG + 1UL); \
high_page = 0; \
do_mmut_rw(cpu_state.ea_seg->base, SRC_REG, addr64a); \
if (cpu_state.abrt) break; \
CHECK_WRITE_REP(&cpu_state.seg_es, DEST_REG, DEST_REG + 1); \
do_mmut_ww(es, DEST_REG, addr64w); \
CHECK_WRITE_REP(&cpu_state.seg_es, DEST_REG, DEST_REG + 1UL); \
do_mmut_ww(es, DEST_REG, addr64a_2); \
if (cpu_state.abrt) break; \
temp = readmemw_n(cpu_state.ea_seg->base, SRC_REG, addr64r); if (cpu_state.abrt) return 1; \
writememw_n(es, DEST_REG, addr64w, temp); if (cpu_state.abrt) return 1; \
temp = readmemw_n(cpu_state.ea_seg->base, SRC_REG, addr64a); if (cpu_state.abrt) return 1; \
writememw_n(es, DEST_REG, addr64a_2, temp); if (cpu_state.abrt) return 1; \
\
if (cpu_state.flags & D_FLAG) { DEST_REG -= 2; SRC_REG -= 2; } \
else { DEST_REG += 2; SRC_REG += 2; } \
@@ -276,27 +283,28 @@ static int opREP_MOVSL_ ## size(uint32_t fetchdat)
{ \
int reads = 0, writes = 0, total_cycles = 0; \
int cycles_end = cycles - ((is386 && cpu_use_dynarec) ? 1000 : 100); \
uint64_t addr64r[4]; \
uint64_t addr64w[4]; \
addr64a[0] = addr64a[1] = addr64a[2] = addr64a[3] = 0x00000000; \
addr64a_2[0] = addr64a_2[1] = addr64a_2[2] = addr64a_2[3] = 0x00000000; \
if (trap) \
cycles_end = cycles+1; /*Force the instruction to end after only one iteration when trap flag set*/ \
if (CNT_REG > 0) \
{ \
SEG_CHECK_READ(cpu_state.ea_seg); \
SEG_CHECK_WRITE(&cpu_state.seg_es); \
} \
} \
while (CNT_REG > 0) \
{ \
uint32_t temp; \
\
CHECK_READ_REP(cpu_state.ea_seg, SRC_REG, SRC_REG + 3); \
do_mmut_rl(cpu_state.ea_seg->base, SRC_REG, addr64r); \
CHECK_READ_REP(cpu_state.ea_seg, SRC_REG, SRC_REG + 3UL); \
high_page = 0; \
do_mmut_rl(cpu_state.ea_seg->base, SRC_REG, addr64a); \
if (cpu_state.abrt) break; \
CHECK_WRITE_REP(&cpu_state.seg_es, DEST_REG, DEST_REG + 3); \
do_mmut_wl(es, DEST_REG, addr64w); \
CHECK_WRITE_REP(&cpu_state.seg_es, DEST_REG, DEST_REG + 3UL); \
do_mmut_wl(es, DEST_REG, addr64a_2); \
if (cpu_state.abrt) break; \
temp = readmeml_n(cpu_state.ea_seg->base, SRC_REG, addr64r); if (cpu_state.abrt) return 1; \
writememl_n(es, DEST_REG, addr64w, temp); if (cpu_state.abrt) return 1; \
temp = readmeml_n(cpu_state.ea_seg->base, SRC_REG, addr64a); if (cpu_state.abrt) return 1; \
writememl_n(es, DEST_REG, addr64a_2, temp); if (cpu_state.abrt) return 1; \
\
if (cpu_state.flags & D_FLAG) { DEST_REG -= 4; SRC_REG -= 4; } \
else { DEST_REG += 4; SRC_REG += 4; } \
@@ -356,7 +364,7 @@ static int opREP_STOSW_ ## size(uint32_t fetchdat)
SEG_CHECK_WRITE(&cpu_state.seg_es); \
while (CNT_REG > 0) \
{ \
CHECK_WRITE_REP(&cpu_state.seg_es, DEST_REG, DEST_REG + 1); \
CHECK_WRITE_REP(&cpu_state.seg_es, DEST_REG, DEST_REG + 1UL); \
writememw(es, DEST_REG, AX); if (cpu_state.abrt) return 1; \
if (cpu_state.flags & D_FLAG) DEST_REG -= 2; \
else DEST_REG += 2; \
@@ -385,7 +393,7 @@ static int opREP_STOSL_ ## size(uint32_t fetchdat)
SEG_CHECK_WRITE(&cpu_state.seg_es); \
while (CNT_REG > 0) \
{ \
CHECK_WRITE_REP(&cpu_state.seg_es, DEST_REG, DEST_REG + 3); \
CHECK_WRITE_REP(&cpu_state.seg_es, DEST_REG, DEST_REG + 3UL); \
writememl(es, DEST_REG, EAX); if (cpu_state.abrt) return 1; \
if (cpu_state.flags & D_FLAG) DEST_REG -= 4; \
else DEST_REG += 4; \
@@ -444,7 +452,7 @@ static int opREP_LODSW_ ## size(uint32_t fetchdat)
SEG_CHECK_READ(cpu_state.ea_seg); \
while (CNT_REG > 0) \
{ \
CHECK_READ_REP(cpu_state.ea_seg, SRC_REG, SRC_REG + 1); \
CHECK_READ_REP(cpu_state.ea_seg, SRC_REG, SRC_REG + 1UL); \
AX = readmemw(cpu_state.ea_seg->base, SRC_REG); if (cpu_state.abrt) return 1; \
if (cpu_state.flags & D_FLAG) SRC_REG -= 2; \
else SRC_REG += 2; \
@@ -473,7 +481,7 @@ static int opREP_LODSL_ ## size(uint32_t fetchdat)
SEG_CHECK_READ(cpu_state.ea_seg); \
while (CNT_REG > 0) \
{ \
CHECK_READ_REP(cpu_state.ea_seg, SRC_REG, SRC_REG + 3); \
CHECK_READ_REP(cpu_state.ea_seg, SRC_REG, SRC_REG + 3UL); \
EAX = readmeml(cpu_state.ea_seg->base, SRC_REG); if (cpu_state.abrt) return 1; \
if (cpu_state.flags & D_FLAG) SRC_REG -= 4; \
else SRC_REG += 4; \
@@ -501,8 +509,8 @@ static int opREP_LODSL_ ## size(uint32_t fetchdat)
static int opREP_CMPSB_ ## size(uint32_t fetchdat) \
{ \
int reads = 0, total_cycles = 0, tempz; \
uint64_t addr64 = 0x0000000000000000ULL; \
uint64_t addr642 = 0x0000000000000000ULL; \
\
addr64 = addr64_2 = 0x00000000; \
\
tempz = FV; \
if ((CNT_REG > 0) && (FV == tempz)) \
@@ -511,12 +519,14 @@ static int opREP_CMPSB_ ## size(uint32_t fetchdat)
SEG_CHECK_READ(cpu_state.ea_seg); \
SEG_CHECK_READ(&cpu_state.seg_es); \
CHECK_READ(cpu_state.ea_seg, SRC_REG, SRC_REG); \
high_page = 0; \
do_mmut_rb(cpu_state.ea_seg->base, SRC_REG, &addr64); \
CHECK_READ(&cpu_state.seg_es, DEST_REG, DEST_REG); \
do_mmut_rb(es, DEST_REG, &addr642); \
if (cpu_state.abrt) return 1; \
temp = readmemb_n(cpu_state.ea_seg->base, SRC_REG, addr64); \
temp2 = readmemb_n(es, DEST_REG, addr642); if (cpu_state.abrt) return 1; \
CHECK_READ(&cpu_state.seg_es, DEST_REG, DEST_REG); \
do_mmut_rb(es, DEST_REG, &addr64_2); \
if (cpu_state.abrt) return 1; \
temp = readmemb_n(cpu_state.ea_seg->base, SRC_REG, addr64); if (cpu_state.abrt) return 1; \
temp2 = readmemb_n(es, DEST_REG, addr64_2); if (cpu_state.abrt) return 1; \
\
if (cpu_state.flags & D_FLAG) { DEST_REG--; SRC_REG--; } \
else { DEST_REG++; SRC_REG++; } \
@@ -538,8 +548,9 @@ static int opREP_CMPSB_ ## size(uint32_t fetchdat)
static int opREP_CMPSW_ ## size(uint32_t fetchdat) \
{ \
int reads = 0, total_cycles = 0, tempz; \
uint64_t addr64[2]; \
uint64_t addr642[2]; \
\
addr64a[0] = addr64a[1] = 0x00000000; \
addr64a_2[0] = addr64a_2[1] = 0x00000000; \
\
tempz = FV; \
if ((CNT_REG > 0) && (FV == tempz)) \
@@ -547,13 +558,15 @@ static int opREP_CMPSW_ ## size(uint32_t fetchdat)
uint16_t temp, temp2; \
SEG_CHECK_READ(cpu_state.ea_seg); \
SEG_CHECK_READ(&cpu_state.seg_es); \
CHECK_READ(cpu_state.ea_seg, SRC_REG, SRC_REG + 1); \
do_mmut_rw(cpu_state.ea_seg->base, SRC_REG, addr64); \
CHECK_READ(&cpu_state.seg_es, DEST_REG, DEST_REG + 1); \
do_mmut_rw(es, DEST_REG, addr642); \
CHECK_READ(cpu_state.ea_seg, SRC_REG, SRC_REG + 1UL); \
high_page = 0; \
do_mmut_rw(cpu_state.ea_seg->base, SRC_REG, addr64a); \
if (cpu_state.abrt) return 1; \
temp = readmemw_n(cpu_state.ea_seg->base, SRC_REG, addr64); \
temp2 = readmemw_n(es, DEST_REG, addr642); if (cpu_state.abrt) return 1; \
CHECK_READ(&cpu_state.seg_es, DEST_REG, DEST_REG + 1UL); \
do_mmut_rw(es, DEST_REG, addr64a_2); \
if (cpu_state.abrt) return 1; \
temp = readmemw_n(cpu_state.ea_seg->base, SRC_REG, addr64a); if (cpu_state.abrt) return 1; \
temp2 = readmemw_n(es, DEST_REG, addr64a_2); if (cpu_state.abrt) return 1; \
\
if (cpu_state.flags & D_FLAG) { DEST_REG -= 2; SRC_REG -= 2; } \
else { DEST_REG += 2; SRC_REG += 2; } \
@@ -575,8 +588,9 @@ static int opREP_CMPSW_ ## size(uint32_t fetchdat)
static int opREP_CMPSL_ ## size(uint32_t fetchdat) \
{ \
int reads = 0, total_cycles = 0, tempz; \
uint64_t addr64[4]; \
uint64_t addr642[4]; \
\
addr64a[0] = addr64a[1] = addr64a[2] = addr64a[3] = 0x00000000; \
addr64a_2[0] = addr64a_2[1] = addr64a_2[2] = addr64a_2[3] = 0x00000000; \
\
tempz = FV; \
if ((CNT_REG > 0) && (FV == tempz)) \
@@ -584,13 +598,15 @@ static int opREP_CMPSL_ ## size(uint32_t fetchdat)
uint32_t temp, temp2; \
SEG_CHECK_READ(cpu_state.ea_seg); \
SEG_CHECK_READ(&cpu_state.seg_es); \
CHECK_READ(cpu_state.ea_seg, SRC_REG, SRC_REG + 3); \
do_mmut_rl(cpu_state.ea_seg->base, SRC_REG, addr64); \
CHECK_READ(&cpu_state.seg_es, DEST_REG, DEST_REG + 3); \
do_mmut_rl(es, DEST_REG, addr642); \
CHECK_READ(cpu_state.ea_seg, SRC_REG, SRC_REG + 3UL); \
high_page = 0; \
do_mmut_rl(cpu_state.ea_seg->base, SRC_REG, addr64a); \
if (cpu_state.abrt) return 1; \
temp = readmeml_n(cpu_state.ea_seg->base, SRC_REG, addr64); \
temp2 = readmeml_n(es, DEST_REG, addr642); if (cpu_state.abrt) return 1; \
CHECK_READ(&cpu_state.seg_es, DEST_REG, DEST_REG + 3UL); \
do_mmut_rl(es, DEST_REG, addr64a_2); \
if (cpu_state.abrt) return 1; \
temp = readmeml_n(cpu_state.ea_seg->base, SRC_REG, addr64a); if (cpu_state.abrt) return 1; \
temp2 = readmeml_n(es, DEST_REG, addr64a_2); if (cpu_state.abrt) return 1; \
\
if (cpu_state.flags & D_FLAG) { DEST_REG -= 4; SRC_REG -= 4; } \
else { DEST_REG += 4; SRC_REG += 4; } \
@@ -653,7 +669,7 @@ static int opREP_SCASW_ ## size(uint32_t fetchdat)
SEG_CHECK_READ(&cpu_state.seg_es); \
while ((CNT_REG > 0) && (FV == tempz)) \
{ \
CHECK_READ_REP(&cpu_state.seg_es, DEST_REG, DEST_REG + 1); \
CHECK_READ_REP(&cpu_state.seg_es, DEST_REG, DEST_REG + 1UL); \
uint16_t temp = readmemw(es, DEST_REG); if (cpu_state.abrt) break;\
setsub16(AX, temp); \
tempz = (ZF_SET()) ? 1 : 0; \
@@ -685,7 +701,7 @@ static int opREP_SCASL_ ## size(uint32_t fetchdat)
SEG_CHECK_READ(&cpu_state.seg_es); \
while ((CNT_REG > 0) && (FV == tempz)) \
{ \
CHECK_READ_REP(&cpu_state.seg_es, DEST_REG, DEST_REG + 3); \
CHECK_READ_REP(&cpu_state.seg_es, DEST_REG, DEST_REG + 3UL); \
uint32_t temp = readmeml(es, DEST_REG); if (cpu_state.abrt) break;\
setsub32(EAX, temp); \
tempz = (ZF_SET()) ? 1 : 0; \