Implement the RZ-1000 PCI IDE controller needed by some Intel machines.
This commit is contained in:
OBattler
@@ -31,6 +31,7 @@ add_library(hdd OBJECT
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hdc_ide_opti611.c
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hdc_ide_cmd640.c
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hdc_ide_cmd646.c
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hdc_ide_rz1000.c
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hdc_ide_sff8038i.c
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hdc_ide_um8673f.c
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hdc_ide_w83769f.c
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322
src/disk/hdc_ide_rz1000.c
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322
src/disk/hdc_ide_rz1000.c
Normal file
@@ -0,0 +1,322 @@
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/*
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* 86Box A hypervisor and IBM PC system emulator that specializes in
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* running old operating systems and software designed for IBM
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* PC systems and compatibles from 1981 through fairly recent
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* system designs based on the PCI bus.
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*
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* This file is part of the 86Box distribution.
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*
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* Implementation of the PC Technology RZ-1000 controller.
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*
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* Authors: Miran Grca, <mgrca8@gmail.com>
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*
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* Copyright 2025 Miran Grca.
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*/
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#include <stdarg.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <wchar.h>
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#define HAVE_STDARG_H
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#include <86box/86box.h>
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#include <86box/cdrom.h>
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#include <86box/scsi_device.h>
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#include <86box/scsi_cdrom.h>
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#include <86box/dma.h>
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#include <86box/io.h>
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#include <86box/device.h>
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#include <86box/keyboard.h>
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#include <86box/mem.h>
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#include <86box/pci.h>
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#include <86box/pic.h>
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#include <86box/timer.h>
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#include <86box/hdc.h>
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#include <86box/hdc_ide.h>
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#include <86box/hdc_ide_sff8038i.h>
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#include <86box/zip.h>
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#include <86box/mo.h>
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typedef struct rz1000_t {
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uint8_t vlb_idx;
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uint8_t id;
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uint8_t in_cfg;
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uint8_t channels;
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uint8_t pci;
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uint8_t irq_state;
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uint8_t pci_slot;
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uint8_t pad0;
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uint8_t regs[256];
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uint32_t local;
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int irq_mode[2];
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int irq_pin;
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int irq_line;
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} rz1000_t;
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static int next_id = 0;
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#define ENABLE_RZ1000_LOG 1
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#ifdef ENABLE_RZ1000_LOG
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int rz1000_do_log = ENABLE_RZ1000_LOG;
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static void
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rz1000_log(const char *fmt, ...)
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{
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va_list ap;
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if (rz1000_do_log) {
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va_start(ap, fmt);
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pclog_ex(fmt, ap);
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va_end(ap);
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}
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}
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#else
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# define rz1000_log(fmt, ...)
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#endif
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static void
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rz1000_ide_handlers(rz1000_t *dev)
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{
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uint16_t main;
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uint16_t side;
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if (dev->channels & 0x01) {
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ide_pri_disable();
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main = 0x1f0;
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side = 0x3f6;
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ide_set_base(0, main);
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ide_set_side(0, side);
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if (dev->regs[0x04] & 0x01)
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ide_pri_enable();
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}
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if (dev->channels & 0x02) {
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ide_sec_disable();
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main = 0x170;
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side = 0x376;
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ide_set_base(1, main);
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ide_set_side(1, side);
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if (dev->regs[0x04] & 0x01)
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ide_sec_enable();
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}
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}
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static void
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rz1000_pci_write(int func, int addr, uint8_t val, void *priv)
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{
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rz1000_t *dev = (rz1000_t *) priv;
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rz1000_log("rz1000_pci_write(%i, %02X, %02X)\n", func, addr, val);
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if (func == 0x00)
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switch (addr) {
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case 0x04:
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dev->regs[addr] = (val & 0x41);
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rz1000_ide_handlers(dev);
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break;
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case 0x07:
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dev->regs[addr] &= ~(val & 0x80);
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break;
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case 0x09:
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if ((dev->regs[addr] & 0x0a) == 0x0a) {
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dev->regs[addr] = (dev->regs[addr] & 0x0a) | (val & 0x05);
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dev->irq_mode[0] = !!(val & 0x01);
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dev->irq_mode[1] = !!(val & 0x04);
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rz1000_ide_handlers(dev);
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}
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break;
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case 0x10:
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dev->regs[0x10] = (val & 0xf8) | 1;
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rz1000_ide_handlers(dev);
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break;
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case 0x11:
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dev->regs[0x11] = val;
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rz1000_ide_handlers(dev);
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break;
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case 0x14:
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dev->regs[0x14] = (val & 0xfc) | 1;
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rz1000_ide_handlers(dev);
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break;
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case 0x15:
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dev->regs[0x15] = val;
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rz1000_ide_handlers(dev);
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break;
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case 0x18:
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dev->regs[0x18] = (val & 0xf8) | 1;
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rz1000_ide_handlers(dev);
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break;
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case 0x19:
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dev->regs[0x19] = val;
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rz1000_ide_handlers(dev);
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break;
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case 0x1c:
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dev->regs[0x1c] = (val & 0xfc) | 1;
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rz1000_ide_handlers(dev);
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break;
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case 0x1d:
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dev->regs[0x1d] = val;
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rz1000_ide_handlers(dev);
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break;
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case 0x40 ... 0x4f:
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dev->regs[addr] = val;
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break;
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}
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}
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static uint8_t
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rz1000_pci_read(int func, int addr, void *priv)
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{
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rz1000_t *dev = (rz1000_t *) priv;
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uint8_t ret = 0xff;
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if (func == 0x00)
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ret = dev->regs[addr];
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rz1000_log("rz1000_pci_read(%i, %02X, %02X)\n", func, addr, ret);
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return ret;
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}
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static void
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rz1000_reset(void *priv)
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{
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rz1000_t *dev = (rz1000_t *) priv;
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int i = 0;
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int min_channel;
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int max_channel;
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switch (dev->channels) {
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default:
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case 0x00:
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min_channel = max_channel = 0;
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break;
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case 0x01:
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min_channel = 0;
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max_channel = 1;
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break;
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case 0x02:
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min_channel = 2;
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max_channel = 3;
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break;
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case 0x03:
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min_channel = 0;
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max_channel = 3;
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break;
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}
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for (i = 0; i < CDROM_NUM; i++) {
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if ((cdrom[i].bus_type == CDROM_BUS_ATAPI) && (cdrom[i].ide_channel >= min_channel) &&
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(cdrom[i].ide_channel <= max_channel) && cdrom[i].priv)
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scsi_cdrom_reset((scsi_common_t *) cdrom[i].priv);
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}
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for (i = 0; i < ZIP_NUM; i++) {
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if ((zip_drives[i].bus_type == ZIP_BUS_ATAPI) && (zip_drives[i].ide_channel >= min_channel) &&
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(zip_drives[i].ide_channel <= max_channel) && zip_drives[i].priv)
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zip_reset((scsi_common_t *) zip_drives[i].priv);
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}
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for (i = 0; i < MO_NUM; i++) {
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if ((mo_drives[i].bus_type == MO_BUS_ATAPI) && (mo_drives[i].ide_channel >= min_channel) &&
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(mo_drives[i].ide_channel <= max_channel) && mo_drives[i].priv)
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mo_reset((scsi_common_t *) mo_drives[i].priv);
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}
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memset(dev->regs, 0x00, sizeof(dev->regs));
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rz1000_log("dev->local = %08X\n", dev->local);
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dev->regs[0x00] = 0x42; /* PC Technology */
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dev->regs[0x01] = 0x10;
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dev->regs[0x02] = 0x00; /* RZ-1000 */
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dev->regs[0x03] = 0x10;
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dev->regs[0x04] = 0x01;
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dev->regs[0x07] = 0x02; /* DEVSEL timing: 01 medium */
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dev->regs[0x08] = 0x02; /* Revision 02 */
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dev->regs[0x09] = dev->local; /* Programming interface */
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dev->regs[0x0a] = 0x01; /* IDE controller */
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dev->regs[0x0b] = 0x01; /* Mass storage controller */
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dev->regs[0x3c] = 0x14; /* IRQ 14 */
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dev->regs[0x3d] = 0x01; /* INTA */
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dev->irq_mode[0] = dev->irq_mode[1] = 0;
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dev->irq_pin = PCI_INTA;
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dev->irq_line = 14;
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rz1000_ide_handlers(dev);
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}
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static void
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rz1000_close(void *priv)
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{
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rz1000_t *dev = (rz1000_t *) priv;
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free(dev);
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next_id = 0;
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}
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static void *
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rz1000_init(const device_t *info)
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{
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rz1000_t *dev = (rz1000_t *) calloc(1, sizeof(rz1000_t));
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dev->id = next_id | 0x60;
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dev->pci = !!(info->flags & DEVICE_PCI);
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dev->local = info->local;
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dev->channels = ((info->local & 0x60000) >> 17) & 0x03;
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device_add(&ide_pci_2ch_device);
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if (info->local & 0x80000)
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pci_add_card(PCI_ADD_NORMAL, rz1000_pci_read, rz1000_pci_write, dev, &dev->pci_slot);
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else
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pci_add_card(PCI_ADD_IDE, rz1000_pci_read, rz1000_pci_write, dev, &dev->pci_slot);
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if (dev->channels & 0x01)
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ide_board_set_force_ata3(0, 1);
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if (dev->channels & 0x02)
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ide_board_set_force_ata3(1, 1);
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next_id++;
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rz1000_reset(dev);
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return dev;
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}
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const device_t ide_rz1000_pci_device = {
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.name = "PC Technology RZ-1000 PCI",
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.internal_name = "ide_rz1000_pci",
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.flags = DEVICE_PCI,
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.local = 0x6000a,
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.init = rz1000_init,
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.close = rz1000_close,
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.reset = rz1000_reset,
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.available = NULL,
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.speed_changed = NULL,
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.force_redraw = NULL,
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.config = NULL
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};
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const device_t ide_rz1000_pci_single_channel_device = {
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.name = "PC Technology RZ-1000 PCI",
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.internal_name = "ide_rz1000_pci_single_channel",
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.flags = DEVICE_PCI,
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.local = 0x2000a,
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.init = rz1000_init,
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.close = rz1000_close,
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.reset = rz1000_reset,
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.available = NULL,
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.speed_changed = NULL,
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.force_redraw = NULL,
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.config = NULL
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};
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@@ -60,6 +60,8 @@ extern const device_t ide_pci_device; /* pci_ide */
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extern const device_t ide_pci_sec_device; /* pci_ide sec */
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extern const device_t ide_pci_2ch_device; /* pci_ide_2ch */
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extern const device_t ide_pci_ter_qua_2ch_device; /* pci_ide_ter_qua_2ch */
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extern const device_t ide_ali1489_device; /* ALi M1489 */
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extern const device_t ide_ali5213_device; /* ALi M5213 */
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@@ -76,10 +78,14 @@ extern const device_t ide_cmd640_pci_single_channel_sec_device; /* CMD PCI-640B
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extern const device_t ide_cmd646_device; /* CMD PCI-646 */
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extern const device_t ide_cmd646_legacy_only_device; /* CMD PCI-646 (Legacy Mode Only) */
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extern const device_t ide_cmd646_single_channel_device; /* CMD PCI-646 (Only primary channel) */
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extern const device_t ide_cmd646_ter_qua_device; /* CMD PCI-646 (Tertiary and quaternary channels) */
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extern const device_t ide_opti611_vlb_device; /* OPTi 82c611/611A VLB */
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extern const device_t ide_opti611_vlb_sec_device; /* OPTi 82c611/611A VLB (Secondary channel) */
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extern const device_t ide_rz1000_pci_device; /* PC Technology RZ-1000 PCI */
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extern const device_t ide_rz1000_pci_single_channel_device; /* PC Technology RZ-1000 PCI (Only primary channel) */
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extern const device_t ide_um8673f_device; /* UMC UM8673F */
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extern const device_t ide_um8886af_device; /* UMC UM8886AF */
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@@ -58,7 +58,8 @@ machine_at_premiere_common_init(const machine_t *model, int pci_switch)
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pci_register_slot(0x02, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
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device_add(&keyboard_ps2_phoenix_device);
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device_add(&sio_zb_device);
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device_add(&fdc37c665_device);
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device_add(&ide_rz1000_pci_single_channel_device);
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device_add(&fdc37c665_ide_sec_device);
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device_add(&intel_flash_bxt_ami_device);
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}
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@@ -169,8 +169,8 @@ machine_at_tek932_init(const machine_t *model)
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device_add(&keyboard_ps2_intel_ami_pci_device);
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device_add(&i430nx_device);
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device_add(&sio_zb_device);
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device_add(&fdc37c665_ide_device);
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device_add(&ide_vlb_device);
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device_add(&fdc37c665_ide_pri_device);
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device_add(&intel_flash_bxt_ami_device);
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return ret;
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