Merge pull request #1676 from 86Box/master
Bring the branch up to par with master.
This commit is contained in:
Miran Grča
GitHub
352
src/chipset/82c100.c
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352
src/chipset/82c100.c
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/*
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* 86Box A hypervisor and IBM PC system emulator that specializes in
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* running old operating systems and software designed for IBM
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* PC systems and compatibles from 1981 through fairly recent
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* system designs based on the PCI bus.
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*
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* This file is part of the 86Box distribution.
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*
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* Implementation of Chips&Technology's 82C100 chipset.
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*
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*
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*
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* Authors: Miran Grca, <mgrca8@gmail.com>
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*
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* Copyright 2021 Miran Grca.
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*/
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#include <stdint.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <wchar.h>
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#include <86box/86box.h>
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#include <86box/device.h>
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#include "cpu.h"
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#include "x86.h"
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#include <86box/io.h>
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#include <86box/mem.h>
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#include <86box/nmi.h>
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#include <86box/port_92.h>
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#include <86box/rom.h>
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#include <86box/chipset.h>
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typedef struct
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{
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int enabled;
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uint32_t virt, phys;
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} ems_page_t;
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typedef struct
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{
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uint8_t index, access;
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uint16_t ems_io_base;
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uint32_t ems_window_base;
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uint8_t ems_page_regs[4],
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regs[256];
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ems_page_t ems_pages[4];
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mem_mapping_t ems_mappings[4];
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} ct_82c100_t;
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static void
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ct_82c100_ems_pages_recalc(ct_82c100_t *dev)
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{
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int i;
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uint32_t page_base;
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for (i = 0; i < 4; i++) {
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page_base = dev->ems_window_base + (i << 14);
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if (dev->ems_page_regs[i] & 0x80) {
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dev->ems_pages[i].virt = page_base;
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dev->ems_pages[i].phys = 0xa0000 + (((uint32_t) (dev->ems_page_regs[i] & 0x7f)) << 14);
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mem_mapping_set_addr(&(dev->ems_mappings[i]), dev->ems_pages[i].virt, 0x4000);
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mem_mapping_set_exec(&(dev->ems_mappings[i]), &(ram[dev->ems_pages[i].phys]));
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mem_set_mem_state_both(page_base, 0x00004000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
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} else {
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mem_mapping_disable(&(dev->ems_mappings[i]));
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mem_set_mem_state_both(page_base, 0x00004000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
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}
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}
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}
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static void
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ct_82c100_ems_out(uint16_t port, uint8_t val, void *priv)
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{
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ct_82c100_t *dev = (ct_82c100_t *) priv;
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dev->ems_page_regs[port >> 14] = val;
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ct_82c100_ems_pages_recalc(dev);
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}
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static uint8_t
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ct_82c100_ems_in(uint16_t port, void *priv)
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{
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ct_82c100_t *dev = (ct_82c100_t *) priv;
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uint8_t ret = 0xff;
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ret = dev->ems_page_regs[port >> 14];
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return ret;
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}
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static void
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ct_82c100_ems_update(ct_82c100_t *dev)
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{
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int i;
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for (i = 0; i < 4; i++) {
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io_handler(0, dev->ems_io_base + (i << 14), 1,
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ct_82c100_ems_in, NULL, NULL, ct_82c100_ems_out, NULL, NULL, dev);
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}
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dev->ems_io_base = 0x0208 + (dev->regs[0x4c] & 0xf0);
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for (i = 0; i < 4; i++) {
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io_handler(1, dev->ems_io_base + (i << 14), 1,
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ct_82c100_ems_in, NULL, NULL, ct_82c100_ems_out, NULL, NULL, dev);
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}
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dev->ems_window_base = 0xc0000 + (((uint32_t) (dev->regs[0x4c] & 0x0f)) << 14);
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ct_82c100_ems_pages_recalc(dev);
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}
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static void
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ct_82c100_reset(void *priv)
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{
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ct_82c100_t *dev = (ct_82c100_t *) priv;
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memset(dev->regs, 0x00, sizeof(dev->regs));
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memset(dev->ems_page_regs, 0x00, sizeof(dev->ems_page_regs));
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dev->index = dev->access = 0x00;
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/* INTERNAL CONFIGURATION/CONTROL REGISTERS */
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dev->regs[0x40] = 0x01; /* Defaults to 8086/V30 mode. */
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dev->regs[0x43] = 0x30;
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dev->regs[0x48] = 0x01;
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use_custom_nmi_vector = 0;
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ct_82c100_ems_update(dev);
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/* ADDITIONAL I/O REGISTERS */
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}
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static void
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ct_82c100_out(uint16_t port, uint8_t val, void *priv)
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{
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ct_82c100_t *dev = (ct_82c100_t *) priv;
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if (port == 0x0022) {
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dev->index = val;
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dev->access = 1;
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} else if (port == 0x0023) {
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if (dev->access) {
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switch (dev->index) {
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/* INTERNAL CONFIGURATION/CONTROL REGISTERS */
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case 0x40:
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dev->regs[0x40] = val & 0xc7;
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/* TODO: Clock stuff - needs CPU speed change functionality that's
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going to be implemented in 86box v4.0.
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Bit 0 is 0 for 8088/V20 and 1 for 8086/V30. */
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break;
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case 0x41:
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dev->regs[0x41] = val & 0xed;
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/* TODO: Where is the Software Reset Function that's enabled by
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setting bit 6 to 1? */
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break;
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case 0x42:
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dev->regs[0x42] = val & 0x01;
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break;
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case 0x43:
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dev->regs[0x43] = val;
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break;
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case 0x44:
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dev->regs[0x44] = val;
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custom_nmi_vector = (custom_nmi_vector & 0xffffff00) | ((uint32_t) val);
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break;
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case 0x45:
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dev->regs[0x45] = val;
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custom_nmi_vector = (custom_nmi_vector & 0xffff00ff) | (((uint32_t) val) << 8);
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break;
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case 0x46:
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dev->regs[0x46] = val;
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custom_nmi_vector = (custom_nmi_vector & 0xff00ffff) | (((uint32_t) val) << 16);
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break;
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case 0x47:
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dev->regs[0x47] = val;
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custom_nmi_vector = (custom_nmi_vector & 0x00ffffff) | (((uint32_t) val) << 24);
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break;
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case 0x48: case 0x49:
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dev->regs[dev->index] = val;
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break;
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case 0x4b:
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dev->regs[0x4b] = val;
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use_custom_nmi_vector = !!(val & 0x40);
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break;
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case 0x4c:
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dev->regs[0x4c] = val;
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ct_82c100_ems_update(dev);
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break;
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}
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dev->access = 0;
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}
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} else if (port == 0x72)
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dev->regs[0x72] = val & 0x7e;
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else if (port == 0x7e)
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dev->regs[0x7e] = val;
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else if (port == 0x7f) {
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/* Bit 3 is Software Controlled Reset, asserted if set. Will be
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done in the feature/machine_and_kb branch using hardresetx86(). */
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dev->regs[0x7f] = val;
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if ((dev->regs[0x41] & 0x40) && (val & 0x08)) {
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softresetx86();
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cpu_set_edx();
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ct_82c100_reset(dev);
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}
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}
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}
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static uint8_t
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ct_82c100_in(uint16_t port, void *priv)
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{
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ct_82c100_t *dev = (ct_82c100_t *) priv;
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uint8_t ret = 0xff;
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if (port == 0x0022)
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ret = dev->index;
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else if (port == 0x0023) {
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if (dev->access) {
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switch (dev->index) {
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/* INTERNAL CONFIGURATION/CONTROL REGISTERS */
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case 0x40 ... 0x49:
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case 0x4b: case 0x4c:
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ret = dev->regs[dev->index];
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break;
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}
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dev->access = 0;
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}
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} else if (port == 0x72)
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ret = dev->regs[0x72];
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else if (port == 0x7e)
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ret = dev->regs[0x7e];
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else if (port == 0x7f)
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ret = dev->regs[0x7f];
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return ret;
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}
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static uint8_t
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mem_read_emsb(uint32_t addr, void *priv)
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{
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ems_page_t *page = (ems_page_t *)priv;
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uint8_t val = 0xff;
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addr = addr - page->virt + page->phys;
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if (addr < ((uint32_t)mem_size << 10))
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val = ram[addr];
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return val;
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}
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static uint16_t
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mem_read_emsw(uint32_t addr, void *priv)
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{
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ems_page_t *page = (ems_page_t *)priv;
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uint16_t val = 0xffff;
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addr = addr - page->virt + page->phys;
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if (addr < ((uint32_t)mem_size << 10))
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val = *(uint16_t *)&ram[addr];
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return val;
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}
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static void
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mem_write_emsb(uint32_t addr, uint8_t val, void *priv)
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{
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ems_page_t *page = (ems_page_t *)priv;
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addr = addr - page->virt + page->phys;
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if (addr < ((uint32_t)mem_size << 10))
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ram[addr] = val;
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}
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static void
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mem_write_emsw(uint32_t addr, uint16_t val, void *priv)
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{
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ems_page_t *page = (ems_page_t *)priv;
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addr = addr - page->virt + page->phys;
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if (addr < ((uint32_t)mem_size << 10))
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*(uint16_t *)&ram[addr] = val;
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}
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static void
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ct_82c100_close(void *priv)
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{
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ct_82c100_t *dev = (ct_82c100_t *) priv;
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free(dev);
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}
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static void *
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ct_82c100_init(const device_t *info)
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{
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ct_82c100_t *dev;
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uint32_t i;
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dev = (ct_82c100_t *)malloc(sizeof(ct_82c100_t));
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memset(dev, 0x00, sizeof(ct_82c100_t));
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ct_82c100_reset(dev);
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io_sethandler(0x0022, 2,
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ct_82c100_in, NULL, NULL, ct_82c100_out, NULL, NULL, dev);
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io_sethandler(0x0072, 1,
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ct_82c100_in, NULL, NULL, ct_82c100_out, NULL, NULL, dev);
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io_sethandler(0x007e, 2,
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ct_82c100_in, NULL, NULL, ct_82c100_out, NULL, NULL, dev);
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for (i = 0; i < 4; i++) {
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mem_mapping_add(&(dev->ems_mappings[i]), (i + 28) << 14, 0x04000,
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mem_read_emsb, mem_read_emsw, NULL,
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mem_write_emsb, mem_write_emsw, NULL,
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ram + 0xa0000 + (i << 14), MEM_MAPPING_INTERNAL, &dev->ems_pages[i]);
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mem_mapping_disable(&(dev->ems_mappings[i]));
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}
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mem_mapping_disable(&ram_mid_mapping);
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device_add(&port_92_device);
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return(dev);
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}
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const device_t ct_82c100_device = {
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"C&T 82C100",
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0,
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0,
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ct_82c100_init, ct_82c100_close, ct_82c100_reset,
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{ NULL }, NULL, NULL,
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NULL
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};
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