Merge pull request #1676 from 86Box/master
Bring the branch up to par with master.
This commit is contained in:
@@ -6,13 +6,23 @@
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*
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* This file is part of the 86Box distribution.
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*
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* Implementation of the Chips & Technologies F82C710 Universal Peripheral Controller (UPC).
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* Implementation of the Chips & Technologies F82C710 Universal Peripheral
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* Controller (UPC) and 82C606 CHIPSpak Multifunction Controller.
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*
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* Relevant literature:
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*
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* [1] Chips and Technologies, Inc.,
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* 82C605/82C606 CHIPSpak/CHIPSport MULTIFUNCTION CONTROLLERS,
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* PRELIMINARY Data Sheet, Revision 1, May 1987.
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* <https://archive.org/download/82C606/82C606.pdf>
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*
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* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
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* Eluan Costa Miranda <eluancm@gmail.com>
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* Lubomir Rintel <lkundrak@v3.sk>
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*
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* Copyright 2020 Sarah Walker.
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* Copyright 2020 Eluan Costa Miranda.
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* Copyright 2021 Lubomir Rintel.
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*/
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#include <stdio.h>
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#include <stdint.h>
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@@ -25,14 +35,17 @@
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#include <86box/device.h>
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#include <86box/lpt.h>
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#include <86box/serial.h>
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#include <86box/gameport.h>
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#include <86box/hdc.h>
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#include <86box/hdc_ide.h>
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#include <86box/fdd.h>
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#include <86box/fdc.h>
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#include <86box/nvr.h>
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#include <86box/sio.h>
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typedef struct upc_t
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{
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uint32_t local;
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int configuration_state; /* state of algorithm to enter configuration mode */
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int configuration_mode;
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uint16_t cri_addr; /* cri = configuration index register, addr is even */
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@@ -42,6 +55,8 @@ typedef struct upc_t
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/* these regs are not affected by reset */
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uint8_t regs[15]; /* there are 16 indexes, but there is no need to store the last one which is: R = cri_addr / 4, W = exit config mode */
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fdc_t *fdc;
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nvr_t *nvr;
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void *gameport;
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serial_t *uart[2];
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} upc_t;
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@@ -87,6 +102,66 @@ f82c710_update_ports(upc_t *upc)
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}
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}
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static void
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f82c606_update_ports(upc_t *upc)
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{
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uint8_t uart1_int = 0xff;
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uint8_t uart2_int = 0xff;
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uint8_t lpt1_int = 0xff;
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int nvr_int = -1;
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serial_remove(upc->uart[0]);
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serial_remove(upc->uart[1]);
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lpt1_remove();
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lpt2_remove();
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nvr_at_handler(0, upc->regs[3] * 4, upc->nvr);
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nvr_at_handler(0, 0x70, upc->nvr);
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switch (upc->regs[8] & 0xc0) {
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case 0x40: nvr_int = 4; break;
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case 0x80: uart1_int = 4; break;
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case 0xc0: uart2_int = 4; break;
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}
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switch (upc->regs[8] & 0x30) {
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case 0x10: nvr_int = 3; break;
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case 0x20: uart1_int = 3; break;
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case 0x30: uart2_int = 3; break;
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}
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switch (upc->regs[8] & 0x0c) {
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case 0x04: nvr_int = 5; break;
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case 0x08: uart1_int = 5; break;
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case 0x0c: lpt1_int = 5; break;
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}
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switch (upc->regs[8] & 0x03) {
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case 0x01: nvr_int = 7; break;
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case 0x02: uart2_int = 7; break;
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case 0x03: lpt1_int = 7; break;
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}
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if (upc->regs[0] & 1)
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gameport_remap(upc->gameport, upc->regs[7] * 4);
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else
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gameport_remap(upc->gameport, 0);
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if (upc->regs[0] & 2)
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serial_setup(upc->uart[0], upc->regs[4] * 4, uart1_int);
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if (upc->regs[0] & 4)
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serial_setup(upc->uart[1], upc->regs[5] * 4, uart2_int);
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if (upc->regs[0] & 8) {
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lpt1_init(upc->regs[6] * 4);
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lpt1_irq(lpt1_int);
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}
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nvr_at_handler(1, upc->regs[3] * 4, upc->nvr);
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nvr_irq_set(nvr_int, upc->nvr);
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}
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static uint8_t
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f82c710_config_read(uint16_t port, void *priv)
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{
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@@ -151,7 +226,11 @@ f82c710_config_write(uint16_t port, uint8_t val, void *priv)
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if (upc->cri == 0xf) {
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upc->configuration_mode = 0;
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io_removehandler(upc->cri_addr, 0x0002, f82c710_config_read, NULL, NULL, f82c710_config_write, NULL, NULL, upc);
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f82c710_update_ports(upc); /* TODO: any benefit in updating at each register write instead of when exiting config mode? */
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/* TODO: any benefit in updating at each register write instead of when exiting config mode? */
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if (upc->local == 710)
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f82c710_update_ports(upc);
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if (upc->local == 606)
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f82c606_update_ports(upc);
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} else {
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upc->regs[upc->cri] = val;
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}
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@@ -179,7 +258,8 @@ f82c710_reset(upc_t *upc)
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lpt1_init(0x378);
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lpt1_irq(7);
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fdc_reset(upc->fdc);
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if (upc->local == 710)
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fdc_reset(upc->fdc);
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}
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static void *
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@@ -187,8 +267,43 @@ f82c710_init(const device_t *info)
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{
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upc_t *upc = (upc_t *) malloc(sizeof(upc_t));
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memset(upc, 0, sizeof(upc_t));
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upc->local = info->local;
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upc->fdc = device_add(&fdc_at_device);
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if (upc->local == 710) {
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upc->regs[0] = 0x0c;
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upc->regs[1] = 0x00;
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upc->regs[2] = 0x00;
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upc->regs[3] = 0x00;
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upc->regs[4] = 0xfe;
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upc->regs[5] = 0x00;
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upc->regs[6] = 0x9e;
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upc->regs[7] = 0x00;
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upc->regs[8] = 0x00;
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upc->regs[9] = 0xb0;
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upc->regs[10] = 0x00;
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upc->regs[11] = 0x00;
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upc->regs[12] = 0xa0;
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upc->regs[13] = 0x00;
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upc->regs[14] = 0x00;
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upc->fdc = device_add(&fdc_at_device);
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}
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if (upc->local == 606) {
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/* Set power-on defaults. */
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upc->regs[0] = 0x00; /* Enable */
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upc->regs[1] = 0x00; /* Configuration Register */
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upc->regs[2] = 0x00; /* Ext Baud Rate Select */
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upc->regs[3] = 0xb0; /* RTC Base */
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upc->regs[4] = 0xfe; /* UART1 Base */
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upc->regs[5] = 0xbe; /* UART2 Base */
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upc->regs[6] = 0x9e; /* Parallel Base */
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upc->regs[7] = 0x80; /* Game Base */
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upc->regs[8] = 0xec; /* Interrupt Select */
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upc->nvr = device_add(&at_nvr_old_device);
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upc->gameport = gameport_add(&gameport_sio_device);
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}
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upc->uart[0] = device_add_inst(&ns16450_device, 1);
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upc->uart[1] = device_add_inst(&ns16450_device, 2);
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@@ -196,25 +311,12 @@ f82c710_init(const device_t *info)
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io_sethandler(0x02fa, 0x0001, NULL, NULL, NULL, f82c710_config_write, NULL, NULL, upc);
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io_sethandler(0x03fa, 0x0001, NULL, NULL, NULL, f82c710_config_write, NULL, NULL, upc);
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upc->regs[0] = 0x0c;
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upc->regs[1] = 0x00;
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upc->regs[2] = 0x00;
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upc->regs[3] = 0x00;
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upc->regs[4] = 0xfe;
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upc->regs[5] = 0x00;
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upc->regs[6] = 0x9e;
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upc->regs[7] = 0x00;
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upc->regs[8] = 0x00;
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upc->regs[9] = 0xb0;
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upc->regs[10] = 0x00;
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upc->regs[11] = 0x00;
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upc->regs[12] = 0xa0;
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upc->regs[13] = 0x00;
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upc->regs[14] = 0x00;
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f82c710_reset(upc);
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f82c710_update_ports(upc);
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if (upc->local == 710)
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f82c710_update_ports(upc);
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if (upc->local == 606)
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f82c606_update_ports(upc);
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return upc;
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}
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@@ -227,10 +329,19 @@ f82c710_close(void *priv)
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free(upc);
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}
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const device_t f82c710_device = {
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"F82C710 UPC Super I/O",
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0,
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const device_t f82c606_device = {
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"82C606 CHIPSpak Multifunction Controller",
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0,
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606,
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f82c710_init, f82c710_close, NULL,
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{ NULL }, NULL, NULL,
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NULL
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};
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const device_t f82c710_device = {
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"F82C710 UPC Super I/O",
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0,
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710,
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f82c710_init, f82c710_close, NULL,
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{ NULL }, NULL, NULL,
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NULL
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