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Replaced the codegen_ops_NULL table references with NULL pointers, as it has the same effect without requiring an extra table of opcodes, also made the new recompiler clear codegen_flags_changed after every interpreted instruction to prevent conditional jumps from occasionally taking the wrong turn (fixes CL-GD 54x6 driver glitches in 24bpp mode on Windows 98 SE), and added instruction length heuristics on fetching the instruction, fixes Jane's US Navy Fighters.

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This commit is contained in:
OBattler
2023-06-09 14:55:13 +02:00
parent 022a036a83
commit c76e8ff06c
11 changed files with 111 additions and 127 deletions
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16
src/codegen/codegen_x86-64.c
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@@ -883,7 +883,7 @@ codegen_generate_call(uint8_t opcode, OpFn op, uint32_t fetchdat, uint32_t new_p
case 0xd8:
op_table = (op_32 & 0x200) ? x86_dynarec_opcodes_d8_a32 : x86_dynarec_opcodes_d8_a16;
recomp_op_table = fpu_softfloat ? recomp_opcodes_NULL : recomp_opcodes_d8;
recomp_op_table = fpu_softfloat ? NULL : recomp_opcodes_d8;
opcode_shift = 3;
opcode_mask = 0x1f;
over = 1;
@@ -893,7 +893,7 @@ codegen_generate_call(uint8_t opcode, OpFn op, uint32_t fetchdat, uint32_t new_p
break;
case 0xd9:
op_table = (op_32 & 0x200) ? x86_dynarec_opcodes_d9_a32 : x86_dynarec_opcodes_d9_a16;
recomp_op_table = fpu_softfloat ? recomp_opcodes_NULL : recomp_opcodes_d9;
recomp_op_table = fpu_softfloat ? NULL : recomp_opcodes_d9;
opcode_mask = 0xff;
over = 1;
pc_off = -1;
@@ -902,7 +902,7 @@ codegen_generate_call(uint8_t opcode, OpFn op, uint32_t fetchdat, uint32_t new_p
break;
case 0xda:
op_table = (op_32 & 0x200) ? x86_dynarec_opcodes_da_a32 : x86_dynarec_opcodes_da_a16;
recomp_op_table = fpu_softfloat ? recomp_opcodes_NULL : recomp_opcodes_da;
recomp_op_table = fpu_softfloat ? NULL : recomp_opcodes_da;
opcode_mask = 0xff;
over = 1;
pc_off = -1;
@@ -911,7 +911,7 @@ codegen_generate_call(uint8_t opcode, OpFn op, uint32_t fetchdat, uint32_t new_p
break;
case 0xdb:
op_table = (op_32 & 0x200) ? x86_dynarec_opcodes_db_a32 : x86_dynarec_opcodes_db_a16;
recomp_op_table = fpu_softfloat ? recomp_opcodes_NULL : recomp_opcodes_db;
recomp_op_table = fpu_softfloat ? NULL : recomp_opcodes_db;
opcode_mask = 0xff;
over = 1;
pc_off = -1;
@@ -920,7 +920,7 @@ codegen_generate_call(uint8_t opcode, OpFn op, uint32_t fetchdat, uint32_t new_p
break;
case 0xdc:
op_table = (op_32 & 0x200) ? x86_dynarec_opcodes_dc_a32 : x86_dynarec_opcodes_dc_a16;
recomp_op_table = fpu_softfloat ? recomp_opcodes_NULL : recomp_opcodes_dc;
recomp_op_table = fpu_softfloat ? NULL : recomp_opcodes_dc;
opcode_shift = 3;
opcode_mask = 0x1f;
over = 1;
@@ -930,7 +930,7 @@ codegen_generate_call(uint8_t opcode, OpFn op, uint32_t fetchdat, uint32_t new_p
break;
case 0xdd:
op_table = (op_32 & 0x200) ? x86_dynarec_opcodes_dd_a32 : x86_dynarec_opcodes_dd_a16;
recomp_op_table = fpu_softfloat ? recomp_opcodes_NULL : recomp_opcodes_dd;
recomp_op_table = fpu_softfloat ? NULL : recomp_opcodes_dd;
opcode_mask = 0xff;
over = 1;
pc_off = -1;
@@ -939,7 +939,7 @@ codegen_generate_call(uint8_t opcode, OpFn op, uint32_t fetchdat, uint32_t new_p
break;
case 0xde:
op_table = (op_32 & 0x200) ? x86_dynarec_opcodes_de_a32 : x86_dynarec_opcodes_de_a16;
recomp_op_table = fpu_softfloat ? recomp_opcodes_NULL : recomp_opcodes_de;
recomp_op_table = fpu_softfloat ? NULL : recomp_opcodes_de;
opcode_mask = 0xff;
over = 1;
pc_off = -1;
@@ -948,7 +948,7 @@ codegen_generate_call(uint8_t opcode, OpFn op, uint32_t fetchdat, uint32_t new_p
break;
case 0xdf:
op_table = (op_32 & 0x200) ? x86_dynarec_opcodes_df_a32 : x86_dynarec_opcodes_df_a16;
recomp_op_table = fpu_softfloat ? recomp_opcodes_NULL : recomp_opcodes_df;
recomp_op_table = fpu_softfloat ? NULL : recomp_opcodes_df;
opcode_mask = 0xff;
over = 1;
pc_off = -1;