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Replaced the codegen_ops_NULL table references with NULL pointers, as it has the same effect without requiring an extra table of opcodes, also made the new recompiler clear codegen_flags_changed after every interpreted instruction to prevent conditional jumps from occasionally taking the wrong turn (fixes CL-GD 54x6 driver glitches in 24bpp mode on Windows 98 SE), and added instruction length heuristics on fetching the instruction, fixes Jane's US Navy Fighters.

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This commit is contained in:
OBattler
2023-06-09 14:55:13 +02:00
parent 022a036a83
commit c76e8ff06c
11 changed files with 111 additions and 127 deletions
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17
src/codegen_new/codegen.c
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@@ -440,7 +440,7 @@ codegen_generate_call(uint8_t opcode, OpFn op, uint32_t fetchdat, uint32_t new_p
last_prefix = 0xd8;
#endif
op_table = (op_32 & 0x200) ? x86_dynarec_opcodes_d8_a32 : x86_dynarec_opcodes_d8_a16;
recomp_op_table = fpu_softfloat ? recomp_opcodes_NULL : recomp_opcodes_d8;
recomp_op_table = fpu_softfloat ? NULL : recomp_opcodes_d8;
opcode_shift = 3;
opcode_mask = 0x1f;
over = 1;
@@ -453,7 +453,7 @@ codegen_generate_call(uint8_t opcode, OpFn op, uint32_t fetchdat, uint32_t new_p
last_prefix = 0xd9;
#endif
op_table = (op_32 & 0x200) ? x86_dynarec_opcodes_d9_a32 : x86_dynarec_opcodes_d9_a16;
recomp_op_table = fpu_softfloat ? recomp_opcodes_NULL : recomp_opcodes_d9;
recomp_op_table = fpu_softfloat ? NULL : recomp_opcodes_d9;
opcode_mask = 0xff;
over = 1;
pc_off = -1;
@@ -465,7 +465,7 @@ codegen_generate_call(uint8_t opcode, OpFn op, uint32_t fetchdat, uint32_t new_p
last_prefix = 0xda;
#endif
op_table = (op_32 & 0x200) ? x86_dynarec_opcodes_da_a32 : x86_dynarec_opcodes_da_a16;
recomp_op_table = fpu_softfloat ? recomp_opcodes_NULL : recomp_opcodes_da;
recomp_op_table = fpu_softfloat ? NULL : recomp_opcodes_da;
opcode_mask = 0xff;
over = 1;
pc_off = -1;
@@ -477,7 +477,7 @@ codegen_generate_call(uint8_t opcode, OpFn op, uint32_t fetchdat, uint32_t new_p
last_prefix = 0xdb;
#endif
op_table = (op_32 & 0x200) ? x86_dynarec_opcodes_db_a32 : x86_dynarec_opcodes_db_a16;
recomp_op_table = fpu_softfloat ? recomp_opcodes_NULL : recomp_opcodes_db;
recomp_op_table = fpu_softfloat ? NULL : recomp_opcodes_db;
opcode_mask = 0xff;
over = 1;
pc_off = -1;
@@ -489,7 +489,7 @@ codegen_generate_call(uint8_t opcode, OpFn op, uint32_t fetchdat, uint32_t new_p
last_prefix = 0xdc;
#endif
op_table = (op_32 & 0x200) ? x86_dynarec_opcodes_dc_a32 : x86_dynarec_opcodes_dc_a16;
recomp_op_table = fpu_softfloat ? recomp_opcodes_NULL : recomp_opcodes_dc;
recomp_op_table = fpu_softfloat ? NULL : recomp_opcodes_dc;
opcode_shift = 3;
opcode_mask = 0x1f;
over = 1;
@@ -502,7 +502,7 @@ codegen_generate_call(uint8_t opcode, OpFn op, uint32_t fetchdat, uint32_t new_p
last_prefix = 0xdd;
#endif
op_table = (op_32 & 0x200) ? x86_dynarec_opcodes_dd_a32 : x86_dynarec_opcodes_dd_a16;
recomp_op_table = fpu_softfloat ? recomp_opcodes_NULL : recomp_opcodes_dd;
recomp_op_table = fpu_softfloat ? NULL : recomp_opcodes_dd;
opcode_mask = 0xff;
over = 1;
pc_off = -1;
@@ -514,7 +514,7 @@ codegen_generate_call(uint8_t opcode, OpFn op, uint32_t fetchdat, uint32_t new_p
last_prefix = 0xde;
#endif
op_table = (op_32 & 0x200) ? x86_dynarec_opcodes_de_a32 : x86_dynarec_opcodes_de_a16;
recomp_op_table = fpu_softfloat ? recomp_opcodes_NULL : recomp_opcodes_de;
recomp_op_table = fpu_softfloat ? NULL : recomp_opcodes_de;
opcode_mask = 0xff;
over = 1;
pc_off = -1;
@@ -526,7 +526,7 @@ codegen_generate_call(uint8_t opcode, OpFn op, uint32_t fetchdat, uint32_t new_p
last_prefix = 0xdf;
#endif
op_table = (op_32 & 0x200) ? x86_dynarec_opcodes_df_a32 : x86_dynarec_opcodes_df_a16;
recomp_op_table = fpu_softfloat ? recomp_opcodes_NULL : recomp_opcodes_df;
recomp_op_table = fpu_softfloat ? NULL : recomp_opcodes_df;
opcode_mask = 0xff;
over = 1;
pc_off = -1;
@@ -713,6 +713,7 @@ generate_call:
uop_MOV_IMM(ir, IREG_ssegs, op_ssegs);
uop_LOAD_FUNC_ARG_IMM(ir, 0, fetchdat);
uop_CALL_INSTRUCTION_FUNC(ir, op);
codegen_flags_changed = 0;
codegen_mark_code_present(block, cs + cpu_state.pc, 8);
last_op_32 = op_32;