From c9ee3864bf61ff9dd96fc5ab7047d585e71b0ea1 Mon Sep 17 00:00:00 2001
From: Panagiotis <58827426+tiseno100@users.noreply.github.com>
Date: Fri, 23 Oct 2020 13:47:40 +0300
Subject: [PATCH] Tiny fix on the VIA PIPC suspension. Fixes dozens of boards.

For some reason. SCI suspension was programmed while it's read-only.
---
 src/chipset/via_pipc.c | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/src/chipset/via_pipc.c b/src/chipset/via_pipc.c
index 4c4917002..232f0ec89 100644
--- a/src/chipset/via_pipc.c
+++ b/src/chipset/via_pipc.c
@@ -53,7 +53,7 @@
 #include <86box/chipset.h>
 #include <86box/sio.h>
 #include <86box/hwm.h>
-
+#define ENABLE_PIPC_LOG 1
 
 /* Most revision numbers (PCI-ISA bridge or otherwise) were lifted from PCI device
    listings on forums, as VIA's datasheets are not very helpful regarding those. */
@@ -268,8 +268,9 @@ pipc_reset_hard(void *priv)
 			dev->power_regs[0x08] = 0x40;
 			break;
 	}
-	if (dev->local >= VIA_PIPC_686A)
-		dev->power_regs[0x42] = 0x40; /* external suspend-related pin, must be set */
+	dev->power_regs[0x40] = 0x20;
+
+	dev->power_regs[0x42] = 0xd0;
 	dev->power_regs[0x48] = 0x01;
 
 	if (dev->local >= VIA_PIPC_686A)
@@ -754,7 +755,7 @@ pipc_write(int func, int addr, uint8_t val, void *priv)
 			break;
 
 		case 0x42:
-			dev->power_regs[addr] = val & 0x0f;
+			dev->power_regs[addr] = (dev->power_regs[0x42] & ~0x0f) | (val & 0x0f);
 			break;
 
 		case 0x61: case 0x62: case 0x63: