claunia/86Box
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Removed the file pointer from the hdd_t struct;

Browse Source 
Partially split off the Logitech Serial Mouse emulation from Microsoft Serial Mouse;
Slightly reworked serial port emulation (the two UART's are now device_t's, non-FIFO mode implemented and is now default, FIFO mode reimplemented from scratch so it's now actually correct);
Added the emulation of the SiS 85c497 chip to the SiS 85c496/497 chipset;
Bugfixes to the emulated Super I/O chips and made them all device_t's now.
This commit is contained in:
OBattler
2018-11-08 19:21:55 +01:00
parent 7b1a40164e
commit d386240fcb
34 changed files with 3590 additions and 2952 deletions
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61
src/machine/m_at_4x0.c
View File

@@ -8,7 +8,7 @@
*
* Implementation of the Intel PCISet chips from 430LX to 440FX.
*
* Version: @(#)m_at_430lx_nx.c 1.0.3 2018/09/19
* Version: @(#)m_at_430lx_nx.c 1.0.4 2018/11/05
*
* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
@@ -505,9 +505,8 @@ machine_at_premiere_common_init(const machine_t *model)
pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 3, 2, 4);
pci_register_slot(0x02, PCI_CARD_SPECIAL, 0, 0, 0, 0);
device_add(&sio_device);
fdc37c665_init();
intel_batman_init();
device_add(&fdc37c665_device);
device_add(&intel_batman_device);
device_add(&intel_flash_bxt_ami_device);
}
@@ -546,8 +545,7 @@ machine_at_p54tp4xe_init(const machine_t *model)
pci_register_slot(0x07, PCI_CARD_SPECIAL, 0, 0, 0, 0);
device_add(&i430fx_device);
device_add(&piix_device);
fdc37c665_init();
device_add(&fdc37c665_device);
device_add(&intel_flash_bxt_device);
}
@@ -569,8 +567,7 @@ machine_at_endeavor_init(const machine_t *model)
pci_register_slot(0x07, PCI_CARD_SPECIAL, 0, 0, 0, 0);
device_add(&i430fx_device);
device_add(&piix_device);
pc87306_init();
device_add(&pc87306_device);
device_add(&intel_flash_bxt_ami_device);
if (gfxcard == VID_INTERNAL)
@@ -600,8 +597,7 @@ machine_at_zappa_init(const machine_t *model)
pci_register_slot(0x07, PCI_CARD_SPECIAL, 0, 0, 0, 0);
device_add(&i430fx_device);
device_add(&piix_device);
pc87306_init();
device_add(&pc87306_device);
device_add(&intel_flash_bxt_ami_device);
}
@@ -621,8 +617,7 @@ machine_at_mb500n_init(const machine_t *model)
pci_register_slot(0x07, PCI_CARD_SPECIAL, 0, 0, 0, 0);
device_add(&i430fx_device);
device_add(&piix_device);
fdc37c665_init();
device_add(&fdc37c665_device);
device_add(&intel_flash_bxt_device);
}
@@ -643,8 +638,7 @@ machine_at_president_init(const machine_t *model)
pci_register_slot(0x07, PCI_CARD_SPECIAL, 0, 0, 0, 0);
device_add(&i430fx_device);
device_add(&piix_device);
w83877f_init(4);
device_add(&w83877f_president_device);
device_add(&intel_flash_bxt_device);
}
@@ -666,9 +660,8 @@ machine_at_thor_init(const machine_t *model)
pci_register_slot(0x07, PCI_CARD_SPECIAL, 0, 0, 0, 0);
device_add(&i430fx_device);
device_add(&piix_device);
pc87306_init();
device_add(&intel_flash_bxt_ami_device);
device_add(&pc87306_device);
device_add(&intel_flash_bxt_ami_device);
}
@@ -689,8 +682,7 @@ machine_at_pb640_init(const machine_t *model)
device_add(&i430fx_pb640_device);
device_add(&piix_pb640_device);
ide_enable_pio_override();
pc87306_init();
device_add(&pc87306_device);
device_add(&intel_flash_bxt_ami_device);
if (gfxcard == VID_INTERNAL)
@@ -722,7 +714,7 @@ machine_at_acerm3a_init(const machine_t *model)
pci_register_slot(0x10, PCI_CARD_ONBOARD, 4, 0, 0, 0);
device_add(&i430hx_device);
device_add(&piix3_device);
fdc37c932fr_init();
device_add(&fdc37c932fr_device);
device_add(&acerm3a_device);
device_add(&intel_flash_bxb_device);
@@ -746,7 +738,7 @@ machine_at_acerv35n_init(const machine_t *model)
pci_register_slot(0x0D, PCI_CARD_NORMAL, 1, 2, 3, 4);
device_add(&i430hx_device);
device_add(&piix3_device);
fdc37c932fr_init();
device_add(&fdc37c932fr_device);
device_add(&acerm3a_device);
device_add(&intel_flash_bxb_device);
@@ -771,8 +763,7 @@ machine_at_ap53_init(const machine_t *model)
pci_register_slot(0x06, PCI_CARD_ONBOARD, 1, 2, 3, 4);
device_add(&i430hx_device);
device_add(&piix3_device);
fdc37c669_init();
device_add(&fdc37c669_device);
device_add(&intel_flash_bxt_device);
}
@@ -793,8 +784,7 @@ machine_at_p55t2p4_init(const machine_t *model)
pci_register_slot(0x07, PCI_CARD_SPECIAL, 0, 0, 0, 0);
device_add(&i430hx_device);
device_add(&piix3_device);
w83877f_init(5);
device_add(&w83877f_device);
device_add(&intel_flash_bxt_device);
}
@@ -816,8 +806,7 @@ machine_at_p55t2s_init(const machine_t *model)
pci_register_slot(0x07, PCI_CARD_SPECIAL, 0, 0, 0, 0);
device_add(&i430hx_device);
device_add(&piix3_device);
pc87306_init();
device_add(&pc87306_device);
device_add(&intel_flash_bxt_device);
}
@@ -838,8 +827,7 @@ machine_at_p55tvp4_init(const machine_t *model)
pci_register_slot(0x07, PCI_CARD_SPECIAL, 0, 0, 0, 0);
device_add(&i430vx_device);
device_add(&piix3_device);
w83877f_init(5);
device_add(&w83877f_device);
device_add(&intel_flash_bxt_device);
}
@@ -860,8 +848,7 @@ machine_at_i430vx_init(const machine_t *model)
pci_register_slot(0x07, PCI_CARD_SPECIAL, 0, 0, 0, 0);
device_add(&i430vx_device);
device_add(&piix3_device);
um8669f_init();
device_add(&um8669f_device);
device_add(&intel_flash_bxt_device);
}
@@ -881,8 +868,7 @@ machine_at_p55va_init(const machine_t *model)
pci_register_slot(0x07, PCI_CARD_SPECIAL, 0, 0, 0, 0);
device_add(&i430vx_device);
device_add(&piix3_device);
fdc37c932fr_init();
device_add(&fdc37c932fr_device);
device_add(&intel_flash_bxt_device);
}
@@ -901,8 +887,7 @@ machine_at_j656vxd_init(const machine_t *model)
pci_register_slot(0x07, PCI_CARD_SPECIAL, 0, 0, 0, 0);
device_add(&i430vx_device);
device_add(&piix3_device);
fdc37c669_init();
device_add(&fdc37c669_device);
device_add(&intel_flash_bxt_device);
}
@@ -925,8 +910,7 @@ machine_at_i440fx_init(const machine_t *model)
pci_register_slot(0x07, PCI_CARD_SPECIAL, 0, 0, 0, 0);
device_add(&i440fx_device);
device_add(&piix3_device);
fdc37c665_init();
device_add(&fdc37c665_device);
device_add(&intel_flash_bxt_device);
}
@@ -948,8 +932,7 @@ machine_at_s1668_init(const machine_t *model)
pci_register_slot(0x0A, PCI_CARD_NORMAL, 1, 2, 3, 4);
device_add(&i440fx_device);
device_add(&piix3_device);
fdc37c665_init();
device_add(&fdc37c665_device);
device_add(&intel_flash_bxt_device);
}
#endif

8
src/machine/m_at_commodore.c
View File

@@ -8,7 +8,7 @@
*
* Implementation of the Commodore PC3 system.
*
* Version: @(#)m_at_commodore.c 1.0.0 2018/09/02
* Version: @(#)m_at_commodore.c 1.0.1 2018/11/06
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
* Miran Grca, <mgrca8@gmail.com>
@@ -53,6 +53,8 @@
static void cbm_io_write(uint16_t port, uint8_t val, void *p)
{
serial_t *uart = machine_get_serial(0);
lpt1_remove();
lpt2_remove();
switch (val & 3)
@@ -70,10 +72,10 @@ static void cbm_io_write(uint16_t port, uint8_t val, void *p)
switch (val & 0xc)
{
case 0x4:
serial_setup(1, 0x2f8, 3);
serial_setup(uart, 0x2f8, 3);
break;
case 0x8:
serial_setup(1, 0x3f8, 4);
serial_setup(uart, 0x3f8, 4);
break;
}
}

374
src/machine/m_at_sis_85c471.c
View File

@@ -9,7 +9,7 @@
* SiS sis85c471 Super I/O Chip
* Used by DTK PKM-0038S E-2
*
* Version: @(#)m_at_sis85c471.c 1.0.10 2018/03/18
* Version: @(#)m_at_sis85c471.c 1.0.11 2018/11/06
*
* Author: Miran Grca, <mgrca8@gmail.com>
*
@@ -17,6 +17,7 @@
*/
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#include "../86box.h"
@@ -32,220 +33,201 @@
#include "machine.h"
static int sis_85c471_curreg;
static uint8_t sis_85c471_regs[39];
typedef struct {
uint8_t cur_reg,
regs[39];
} sis_85c471_t;
static void sis_85c471_write(uint16_t port, uint8_t val, void *priv)
static void
sis_85c471_write(uint16_t port, uint8_t val, void *priv)
{
uint8_t index = (port & 1) ? 0 : 1;
uint8_t x;
sis_85c471_t *dev = (sis_85c471_t *) priv;
uint8_t index = (port & 1) ? 0 : 1;
uint8_t valxor;
serial_t *uart[2];
if (index)
{
if ((val >= 0x50) && (val <= 0x76)) sis_85c471_curreg = val;
return;
}
else
{
if ((sis_85c471_curreg < 0x50) || (sis_85c471_curreg > 0x76)) return;
x = val ^ sis_85c471_regs[sis_85c471_curreg - 0x50];
/* Writes to 0x52 are blocked as otherwise, large hard disks don't read correctly. */
if (sis_85c471_curreg != 0x52) sis_85c471_regs[sis_85c471_curreg - 0x50] = val;
goto process_value;
}
if (index) {
if ((val >= 0x50) && (val <= 0x76))
dev->cur_reg = val;
return;
} else {
if ((dev->cur_reg < 0x50) || (dev->cur_reg > 0x76))
return;
valxor = val ^ dev->regs[dev->cur_reg - 0x50];
/* Writes to 0x52 are blocked as otherwise, large hard disks don't read correctly. */
if (dev->cur_reg != 0x52)
dev->regs[dev->cur_reg - 0x50] = val;
}
process_value:
switch(sis_85c471_curreg)
{
case 0x73:
#if 0
if (x & 0x40)
{
if (val & 0x40)
ide_pri_enable();
else
ide_pri_disable();
}
#endif
if (x & 0x20)
{
if (val & 0x20)
{
serial_setup(1, SERIAL1_ADDR, SERIAL1_IRQ);
serial_setup(2, SERIAL2_ADDR, SERIAL2_IRQ);
}
else
{
serial_remove(1);
serial_remove(2);
}
}
if (x & 0x10)
{
if (val & 0x10)
lpt1_init(0x378);
else
lpt1_remove();
}
break;
}
sis_85c471_curreg = 0;
}
static uint8_t sis_85c471_read(uint16_t port, void *priv)
{
uint8_t index = (port & 1) ? 0 : 1;
uint8_t temp;
if (index)
return sis_85c471_curreg;
else
if ((sis_85c471_curreg >= 0x50) && (sis_85c471_curreg <= 0x76))
{
temp = sis_85c471_regs[sis_85c471_curreg - 0x50];
sis_85c471_curreg = 0;
return temp;
switch(dev->cur_reg) {
case 0x73:
if (valxor & 0x40) {
ide_pri_disable();
if (val & 0x40)
ide_pri_enable();
}
else
return 0xFF;
if (valxor & 0x20) {
uart[0] = machine_get_serial(0);
uart[1] = machine_get_serial(1);
serial_remove(uart[0]);
serial_remove(uart[1]);
if (val & 0x20) {
serial_setup(uart[0], SERIAL1_ADDR, SERIAL1_IRQ);
serial_setup(uart[0], SERIAL2_ADDR, SERIAL2_IRQ);
}
}
if (valxor & 0x10) {
lpt1_remove();
if (val & 0x10)
lpt1_init(0x378);
}
break;
}
dev->cur_reg = 0;
}
static void sis_85c471_init(void)
static uint8_t
sis_85c471_read(uint16_t port, void *priv)
{
int i = 0;
sis_85c471_t *dev = (sis_85c471_t *) priv;
uint8_t index = (port & 1) ? 0 : 1;
uint8_t ret = 0xff;;
lpt2_remove();
sis_85c471_curreg = 0;
for (i = 0; i < 0x27; i++)
{
sis_85c471_regs[i] = 0;
}
sis_85c471_regs[9] = 0x40;
switch (mem_size)
{
case 0:
case 1:
sis_85c471_regs[9] |= 0;
break;
case 2:
case 3:
sis_85c471_regs[9] |= 1;
break;
case 4:
sis_85c471_regs[9] |= 2;
break;
case 5:
sis_85c471_regs[9] |= 0x20;
break;
case 6:
case 7:
sis_85c471_regs[9] |= 9;
break;
case 8:
case 9:
sis_85c471_regs[9] |= 4;
break;
case 10:
case 11:
sis_85c471_regs[9] |= 5;
break;
case 12:
case 13:
case 14:
case 15:
sis_85c471_regs[9] |= 0xB;
break;
case 16:
sis_85c471_regs[9] |= 0x13;
break;
case 17:
sis_85c471_regs[9] |= 0x21;
break;
case 18:
case 19:
sis_85c471_regs[9] |= 6;
break;
case 20:
case 21:
case 22:
case 23:
sis_85c471_regs[9] |= 0xD;
break;
case 24:
case 25:
case 26:
case 27:
case 28:
case 29:
case 30:
case 31:
sis_85c471_regs[9] |= 0xE;
break;
case 32:
case 33:
case 34:
case 35:
sis_85c471_regs[9] |= 0x1B;
break;
case 36:
case 37:
case 38:
case 39:
sis_85c471_regs[9] |= 0xF;
break;
case 40:
case 41:
case 42:
case 43:
case 44:
case 45:
case 46:
case 47:
sis_85c471_regs[9] |= 0x17;
break;
case 48:
sis_85c471_regs[9] |= 0x1E;
break;
default:
if (mem_size < 64)
{
sis_85c471_regs[9] |= 0x1E;
}
else if ((mem_size >= 65) && (mem_size < 68))
{
sis_85c471_regs[9] |= 0x22;
}
else
{
sis_85c471_regs[9] |= 0x24;
}
break;
if (index)
ret = dev->cur_reg;
else {
if ((dev->cur_reg >= 0x50) && (dev->cur_reg <= 0x76)) {
ret = dev->regs[dev->cur_reg - 0x50];
dev->cur_reg = 0;
}
}
sis_85c471_regs[0x11] = 9;
sis_85c471_regs[0x12] = 0xFF;
sis_85c471_regs[0x23] = 0xF0;
sis_85c471_regs[0x26] = 1;
io_sethandler(0x0022, 0x0002, sis_85c471_read, NULL, NULL, sis_85c471_write, NULL, NULL, NULL);
return ret;
}
static void
sis_85c471_close(void *priv)
{
sis_85c471_t *dev = (sis_85c471_t *) priv;
free(dev);
}
static void *
sis_85c471_init(const device_t *info)
{
int mem_size_mb, i = 0;
sis_85c471_t *dev = (sis_85c471_t *) malloc(sizeof(sis_85c471_t));
memset(dev, 0, sizeof(sis_85c471_t));
lpt2_remove();
dev->cur_reg = 0;
for (i = 0; i < 0x27; i++)
dev->regs[i] = 0x00;
dev->regs[9] = 0x40;
mem_size_mb = mem_size >> 10;
switch (mem_size_mb) {
case 0: case 1:
dev->regs[9] |= 0;
break;
case 2: case 3:
dev->regs[9] |= 1;
break;
case 4:
dev->regs[9] |= 2;
break;
case 5:
dev->regs[9] |= 0x20;
break;
case 6: case 7:
dev->regs[9] |= 9;
break;
case 8: case 9:
dev->regs[9] |= 4;
break;
case 10: case 11:
dev->regs[9] |= 5;
break;
case 12: case 13: case 14: case 15:
dev->regs[9] |= 0xB;
break;
case 16:
dev->regs[9] |= 0x13;
break;
case 17:
dev->regs[9] |= 0x21;
break;
case 18: case 19:
dev->regs[9] |= 6;
break;
case 20: case 21: case 22: case 23:
dev->regs[9] |= 0xD;
break;
case 24: case 25: case 26: case 27:
case 28: case 29: case 30: case 31:
dev->regs[9] |= 0xE;
break;
case 32: case 33: case 34: case 35:
dev->regs[9] |= 0x1B;
break;
case 36: case 37: case 38: case 39:
dev->regs[9] |= 0xF;
break;
case 40: case 41: case 42: case 43:
case 44: case 45: case 46: case 47:
dev->regs[9] |= 0x17;
break;
case 48:
dev->regs[9] |= 0x1E;
break;
default:
if (mem_size_mb < 64)
dev->regs[9] |= 0x1E;
else if ((mem_size_mb >= 65) && (mem_size_mb < 68))
dev->regs[9] |= 0x22;
else
dev->regs[9] |= 0x24;
break;
}
dev->regs[0x11] = 9;
dev->regs[0x12] = 0xFF;
dev->regs[0x23] = 0xF0;
dev->regs[0x26] = 1;
io_sethandler(0x0022, 0x0002,
sis_85c471_read, NULL, NULL, sis_85c471_write, NULL, NULL, dev);
return dev;
}
const device_t sis_85c471_device = {
"SiS 85c471",
0,
0,
sis_85c471_init, sis_85c471_close, NULL,
NULL, NULL, NULL,
NULL
};
void
machine_at_dtk486_init(const machine_t *model)
{
machine_at_ide_init(model);
device_add(&fdc_at_device);
machine_at_ide_init(model);
device_add(&fdc_at_device);
memregs_init();
sis_85c471_init();
secondary_ide_check();
memregs_init();
device_add(&sis_85c471_device);
secondary_ide_check();
}

190
src/machine/m_at_sis_85c496.c
View File

@@ -8,7 +8,7 @@
*
* Implementation of the SiS 85c496/85c497 chip.
*
* Version: @(#)m_at_sis_85c496.c 1.0.2 2018/10/02
* Version: @(#)m_at_sis_85c496.c 1.0.3 2018/11/05
*
* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
@@ -35,10 +35,54 @@
typedef struct sis_85c496_t
{
uint8_t pci_conf[256];
uint8_t cur_reg,
regs[39],
pci_conf[256];
} sis_85c496_t;
static void
sis_85c497_write(uint16_t port, uint8_t val, void *priv)
{
sis_85c496_t *dev = (sis_85c496_t *) priv;
uint8_t index = (port & 1) ? 0 : 1;
if (index) {
if ((val >= 0x50) && (val <= 0x76))
dev->cur_reg = val;
return;
} else {
if ((dev->cur_reg < 0x50) || (dev->cur_reg > 0x76))
return;
/* Writes to 0x52 are blocked as otherwise, large hard disks don't read correctly. */
if (dev->cur_reg != 0x52)
dev->regs[dev->cur_reg - 0x50] = val;
}
dev->cur_reg = 0;
}
static uint8_t
sis_85c497_read(uint16_t port, void *priv)
{
sis_85c496_t *dev = (sis_85c496_t *) priv;
uint8_t index = (port & 1) ? 0 : 1;
uint8_t ret = 0xff;
if (index)
ret = dev->cur_reg;
else {
if ((dev->cur_reg >= 0x50) && (dev->cur_reg <= 0x76)) {
ret = dev->regs[dev->cur_reg - 0x50];
dev->cur_reg = 0;
}
}
return ret;
}
static void
sis_85c496_recalcmapping(sis_85c496_t *dev)
{
@@ -72,9 +116,9 @@ sis_85c496_recalcmapping(sis_85c496_t *dev)
static void
sis_85c496_write(int func, int addr, uint8_t val, void *p)
sis_85c496_write(int func, int addr, uint8_t val, void *priv)
{
sis_85c496_t *dev = (sis_85c496_t *) p;
sis_85c496_t *dev = (sis_85c496_t *) priv;
switch (addr) {
case 0x44: /*Shadow configure*/
@@ -90,6 +134,10 @@ sis_85c496_write(int func, int addr, uint8_t val, void *p)
}
break;
case 0x82:
sis_85c497_write(0x22, val, priv);
break;
case 0xc0:
if (val & 0x80)
pci_set_irq_routing(PCI_INTA, val & 0xf);
@@ -122,14 +170,104 @@ sis_85c496_write(int func, int addr, uint8_t val, void *p)
static uint8_t
sis_85c496_read(int func, int addr, void *p)
sis_85c496_read(int func, int addr, void *priv)
{
sis_85c496_t *dev = (sis_85c496_t *) p;
sis_85c496_t *dev = (sis_85c496_t *) priv;
return dev->pci_conf[addr];
}
static void
sis_85c497_reset(sis_85c496_t *dev)
{
int mem_size_mb, i = 0;
memset(dev->regs, 0, sizeof(dev->regs));
dev->cur_reg = 0;
for (i = 0; i < 0x27; i++)
dev->regs[i] = 0x00;
dev->regs[9] = 0x40;
mem_size_mb = mem_size >> 10;
switch (mem_size_mb) {
case 0: case 1:
dev->regs[9] |= 0;
break;
case 2: case 3:
dev->regs[9] |= 1;
break;
case 4:
dev->regs[9] |= 2;
break;
case 5:
dev->regs[9] |= 0x20;
break;
case 6: case 7:
dev->regs[9] |= 9;
break;
case 8: case 9:
dev->regs[9] |= 4;
break;
case 10: case 11:
dev->regs[9] |= 5;
break;
case 12: case 13: case 14: case 15:
dev->regs[9] |= 0xB;
break;
case 16:
dev->regs[9] |= 0x13;
break;
case 17:
dev->regs[9] |= 0x21;
break;
case 18: case 19:
dev->regs[9] |= 6;
break;
case 20: case 21: case 22: case 23:
dev->regs[9] |= 0xD;
break;
case 24: case 25: case 26: case 27:
case 28: case 29: case 30: case 31:
dev->regs[9] |= 0xE;
break;
case 32: case 33: case 34: case 35:
dev->regs[9] |= 0x1B;
break;
case 36: case 37: case 38: case 39:
dev->regs[9] |= 0xF;
break;
case 40: case 41: case 42: case 43:
case 44: case 45: case 46: case 47:
dev->regs[9] |= 0x17;
break;
case 48:
dev->regs[9] |= 0x1E;
break;
default:
if (mem_size_mb < 64)
dev->regs[9] |= 0x1E;
else if ((mem_size_mb >= 65) && (mem_size_mb < 68))
dev->regs[9] |= 0x22;
else
dev->regs[9] |= 0x24;
break;
}
dev->regs[0x11] = 9;
dev->regs[0x12] = 0xFF;
dev->regs[0x23] = 0xF0;
dev->regs[0x26] = 1;
io_removehandler(0x0022, 0x0002,
sis_85c497_read, NULL, NULL, sis_85c497_write, NULL, NULL, dev);
io_sethandler(0x0022, 0x0002,
sis_85c497_read, NULL, NULL, sis_85c497_write, NULL, NULL, dev);
}
static void
sis_85c496_reset(void *priv)
{
@@ -137,6 +275,8 @@ sis_85c496_reset(void *priv)
val = sis_85c496_read(0, 0x44, priv); /* Read current value of 0x44. */
sis_85c496_write(0, 0x44, val & 0xf, priv); /* Turn off shadow BIOS but keep the lower 4 bits. */
sis_85c497_reset((sis_85c496_t *) priv);
}
@@ -152,31 +292,33 @@ sis_85c496_close(void *p)
static void
*sis_85c496_init(const device_t *info)
{
sis_85c496_t *sis496 = malloc(sizeof(sis_85c496_t));
memset(sis496, 0, sizeof(sis_85c496_t));
sis_85c496_t *dev = malloc(sizeof(sis_85c496_t));
memset(dev, 0, sizeof(sis_85c496_t));
sis496->pci_conf[0x00] = 0x39; /*SiS*/
sis496->pci_conf[0x01] = 0x10;
sis496->pci_conf[0x02] = 0x96; /*496/497*/
sis496->pci_conf[0x03] = 0x04;
dev->pci_conf[0x00] = 0x39; /*SiS*/
dev->pci_conf[0x01] = 0x10;
dev->pci_conf[0x02] = 0x96; /*496/497*/
dev->pci_conf[0x03] = 0x04;
sis496->pci_conf[0x04] = 7;
sis496->pci_conf[0x05] = 0;
dev->pci_conf[0x04] = 7;
dev->pci_conf[0x05] = 0;
sis496->pci_conf[0x06] = 0x80;
sis496->pci_conf[0x07] = 0x02;
dev->pci_conf[0x06] = 0x80;
dev->pci_conf[0x07] = 0x02;
sis496->pci_conf[0x08] = 2; /*Device revision*/
dev->pci_conf[0x08] = 2; /*Device revision*/
sis496->pci_conf[0x09] = 0x00; /*Device class (PCI bridge)*/
sis496->pci_conf[0x0a] = 0x00;
sis496->pci_conf[0x0b] = 0x06;
dev->pci_conf[0x09] = 0x00; /*Device class (PCI bridge)*/
dev->pci_conf[0x0a] = 0x00;
dev->pci_conf[0x0b] = 0x06;
sis496->pci_conf[0x0e] = 0x00; /*Single function device*/
dev->pci_conf[0x0e] = 0x00; /*Single function device*/
pci_add_card(5, sis_85c496_read, sis_85c496_write, sis496);
pci_add_card(5, sis_85c496_read, sis_85c496_write, dev);
return sis496;
sis_85c497_reset(dev);
return dev;
}
@@ -225,5 +367,5 @@ machine_at_r418_init(const machine_t *model)
{
machine_at_sis_85c496_common_init(model);
fdc37c665_init();
device_add(&fdc37c665_device);
}

29
src/machine/m_at_wd76c10.c
View File

@@ -50,6 +50,11 @@ wd76c10_read(uint16_t port, void *priv)
static void
wd76c10_write(uint16_t port, uint16_t val, void *priv)
{
serial_t *uart[2];
uart[0] = machine_get_serial(0);
uart[1] = machine_get_serial(1);
switch (port)
{
case 0x0092:
@@ -62,28 +67,28 @@ wd76c10_write(uint16_t port, uint16_t val, void *priv)
case 0x2072:
wd76c10_2072 = val;
serial_remove(1);
serial_remove(uart[0]);
if (!(val & 0x10))
{
switch ((val >> 5) & 7)
{
case 1: serial_setup(1, 0x3f8, 4); break;
case 2: serial_setup(1, 0x2f8, 4); break;
case 3: serial_setup(1, 0x3e8, 4); break;
case 4: serial_setup(1, 0x2e8, 4); break;
default: serial_remove(1); break;
case 1: serial_setup(uart[0], 0x3f8, 4); break;
case 2: serial_setup(uart[0], 0x2f8, 4); break;
case 3: serial_setup(uart[0], 0x3e8, 4); break;
case 4: serial_setup(uart[0], 0x2e8, 4); break;
default: break;
}
}
serial_remove(2);
serial_remove(uart[1]);
if (!(val & 0x01))
{
switch ((val >> 1) & 7)
{
case 1: serial_setup(2, 0x3f8, 3); break;
case 2: serial_setup(2, 0x2f8, 3); break;
case 3: serial_setup(2, 0x3e8, 3); break;
case 4: serial_setup(2, 0x2e8, 3); break;
default: serial_remove(1); break;
case 1: serial_setup(uart[1], 0x3f8, 3); break;
case 2: serial_setup(uart[1], 0x2f8, 3); break;
case 3: serial_setup(uart[1], 0x3e8, 3); break;
case 4: serial_setup(uart[1], 0x2e8, 3); break;
default: break;
}
}
break;

4
src/machine/m_pcjr.c
View File

@@ -8,7 +8,7 @@
*
* Emulation of the IBM PCjr.
*
* Version: @(#)m_pcjr.c 1.0.10 2018/11/02
* Version: @(#)m_pcjr.c 1.0.11 2018/11/06
*
* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
@@ -757,7 +757,7 @@ machine_pcjr_init(const machine_t *model)
setrtcconst(14318184.0);
if (serial_enabled[0])
serial_setup(1, 0x2f8, 3);
serial_setup(machine_get_serial(0), 0x2f8, 3);
/* Initialize the video controller. */
mem_mapping_add(&pcjr->mapping, 0xb8000, 0x08000,

12
src/machine/m_ps1.c
View File

@@ -28,7 +28,7 @@
* boot. Sometimes, they do, and then it shows an "Incorrect
* DOS" error message?? --FvK
*
* Version: @(#)m_ps1.c 1.0.12 2018/09/19
* Version: @(#)m_ps1.c 1.0.13 2018/11/06
*
* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
@@ -292,6 +292,7 @@ static void
ps1_write(uint16_t port, uint8_t val, void *priv)
{
ps1_t *ps = (ps1_t *)priv;
serial_t *uart;
switch (port) {
case 0x0092:
@@ -327,10 +328,11 @@ ps1_write(uint16_t port, uint8_t val, void *priv)
case 0x0102:
lpt1_remove();
uart = machine_get_serial(0);
if (val & 0x04)
serial_setup(1, SERIAL1_ADDR, SERIAL1_IRQ);
serial_setup(uart, SERIAL1_ADDR, SERIAL1_IRQ);
else
serial_remove(1);
serial_remove(uart);
if (val & 0x10) {
switch ((val >> 5) & 3) {
case 0:
@@ -457,8 +459,8 @@ ps1_setup(int model)
lpt2_remove();
serial_remove(1);
serial_remove(2);
serial_remove(machine_get_serial(0));
serial_remove(machine_get_serial(1));
/* Enable the PS/1 VGA controller. */
if (model == 2011)

6
src/machine/m_ps2_isa.c
View File

@@ -70,6 +70,8 @@ static uint8_t ps2_read(uint16_t port, void *p)
static void ps2_write(uint16_t port, uint8_t val, void *p)
{
serial_t *uart = machine_get_serial(0);
switch (port)
{
case 0x94:
@@ -78,9 +80,9 @@ static void ps2_write(uint16_t port, uint8_t val, void *p)
case 0x102:
lpt1_remove();
if (val & 0x04)
serial_setup(1, SERIAL1_ADDR, SERIAL1_IRQ);
serial_setup(uart, SERIAL1_ADDR, SERIAL1_IRQ);
else
serial_remove(1);
serial_remove(uart);
if (val & 0x10)
{
switch ((val >> 5) & 3)

42
src/machine/m_ps2_mca.c
View File

@@ -8,7 +8,7 @@
*
* Implementation of MCA-based PS/2 machines.
*
* Version: @(#)m_ps2_mca.c 1.0.3 2018/10/22
* Version: @(#)m_ps2_mca.c 1.0.4 2018/11/06
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
* Miran Grca, <mgrca8@gmail.com>
@@ -372,6 +372,8 @@ static uint8_t model_80_read(uint16_t port)
static void model_50_write(uint16_t port, uint8_t val)
{
serial_t *uart = machine_get_serial(0);
switch (port)
{
case 0x100:
@@ -381,16 +383,14 @@ static void model_50_write(uint16_t port, uint8_t val)
break;
case 0x102:
lpt1_remove();
serial_remove(1);
serial_remove(uart);
if (val & 0x04)
{
if (val & 0x08)
serial_setup(1, SERIAL1_ADDR, SERIAL1_IRQ);
serial_setup(uart, SERIAL1_ADDR, SERIAL1_IRQ);
else
serial_setup(1, SERIAL2_ADDR, SERIAL2_IRQ);
serial_setup(uart, SERIAL2_ADDR, SERIAL2_IRQ);
}
else
serial_remove(1);
if (val & 0x10)
{
switch ((val >> 5) & 3)
@@ -428,6 +428,8 @@ static void model_50_write(uint16_t port, uint8_t val)
static void model_55sx_write(uint16_t port, uint8_t val)
{
serial_t *uart = machine_get_serial(0);
switch (port)
{
case 0x100:
@@ -437,16 +439,14 @@ static void model_55sx_write(uint16_t port, uint8_t val)
break;
case 0x102:
lpt1_remove();
serial_remove(1);
serial_remove(uart);
if (val & 0x04)
{
if (val & 0x08)
serial_setup(1, SERIAL1_ADDR, SERIAL1_IRQ);
serial_setup(uart, SERIAL1_ADDR, SERIAL1_IRQ);
else
serial_setup(1, SERIAL2_ADDR, SERIAL2_IRQ);
serial_setup(uart, SERIAL2_ADDR, SERIAL2_IRQ);
}
else
serial_remove(1);
if (val & 0x10)
{
switch ((val >> 5) & 3)
@@ -505,6 +505,8 @@ static void model_55sx_write(uint16_t port, uint8_t val)
static void model_70_type3_write(uint16_t port, uint8_t val)
{
serial_t *uart = machine_get_serial(0);
switch (port)
{
case 0x100:
@@ -513,16 +515,14 @@ static void model_70_type3_write(uint16_t port, uint8_t val)
break;
case 0x102:
lpt1_remove();
serial_remove(1);
serial_remove(uart);
if (val & 0x04)
{
if (val & 0x08)
serial_setup(1, SERIAL1_ADDR, SERIAL1_IRQ);
serial_setup(uart, SERIAL1_ADDR, SERIAL1_IRQ);
else
serial_setup(1, SERIAL2_ADDR, SERIAL2_IRQ);
serial_setup(uart, SERIAL2_ADDR, SERIAL2_IRQ);
}
else
serial_remove(1);
if (val & 0x10)
{
switch ((val >> 5) & 3)
@@ -555,6 +555,8 @@ static void model_70_type3_write(uint16_t port, uint8_t val)
static void model_80_write(uint16_t port, uint8_t val)
{
serial_t *uart = machine_get_serial(0);
switch (port)
{
case 0x100:
@@ -563,16 +565,14 @@ static void model_80_write(uint16_t port, uint8_t val)
break;
case 0x102:
lpt1_remove();
serial_remove(1);
serial_remove(uart);
if (val & 0x04)
{
if (val & 0x08)
serial_setup(1, SERIAL1_ADDR, SERIAL1_IRQ);
serial_setup(uart, SERIAL1_ADDR, SERIAL1_IRQ);
else
serial_setup(1, SERIAL2_ADDR, SERIAL2_IRQ);
serial_setup(uart, SERIAL2_ADDR, SERIAL2_IRQ);
}
else
serial_remove(1);
if (val & 0x10)
{
switch ((val >> 5) & 3)

23
src/machine/machine.c
View File

@@ -8,7 +8,7 @@
*
* Handling of the emulated machines.
*
* Version: @(#)machine.c 1.0.35 2018/10/22
* Version: @(#)machine.c 1.0.36 2018/11/05
*
* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
@@ -42,6 +42,8 @@ int machine;
int AT, PCI;
int romset;
static serial_t *uart[2];
#ifdef ENABLE_MACHINE_LOG
int machine_do_log = ENABLE_MACHINE_LOG;
@@ -90,6 +92,12 @@ machine_init(void)
/* All good, boot the machine! */
machines[machine].init(&machines[machine]);
/* For non-PCI machines, add two regular 8250 UART's. */
if (!PCI) {
uart[0] = device_add_inst(&i8250_device, 1);
uart[1] = device_add_inst(&i8250_device, 2);
}
/* If it's a PCI or MCA machine, reset the video card
after initializing the machine, so the slots work correctly. */
if (PCI || MCA)
@@ -97,6 +105,13 @@ machine_init(void)
}
serial_t *
machine_get_serial(int port)
{
return uart[port];
}
void
machine_common_init(const machine_t *model)
{
@@ -113,10 +128,4 @@ machine_common_init(const machine_t *model)
if (lpt_enabled)
lpt_init();
if (serial_enabled[0])
serial_setup(1, SERIAL1_ADDR, SERIAL1_IRQ);
if (serial_enabled[1])
serial_setup(2, SERIAL2_ADDR, SERIAL2_IRQ);
}

3
src/machine/machine.h
View File

@@ -82,6 +82,9 @@ extern int machine_getmachine(int romset);
extern char *machine_getname(void);
extern char *machine_get_internal_name(void);
extern int machine_get_machine_from_internal_name(char *s);
#ifdef EMU_SERIAL_H
extern serial_t *machine_get_serial(int port);
#endif
extern void machine_init(void);
#ifdef EMU_DEVICE_H
extern const device_t *machine_getdevice(int machine);

4
src/machine/machine_table.c
View File

@@ -11,7 +11,7 @@
* NOTES: OpenAT wip for 286-class machine with open BIOS.
* PS2_M80-486 wip, pending receipt of TRM's for machine.
*
* Version: @(#)machine_table.c 1.0.43 2018/11/02
* Version: @(#)machine_table.c 1.0.44 2018/11/03
*
* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
@@ -85,7 +85,7 @@ const machine_t machines[] = {
{ "[286 MCA] IBM PS/2 model 50", ROM_IBMPS2_M50, "ibmps2_m50", {{"", cpus_ps2_m30_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MACHINE_MCA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC_PS2 | MACHINE_VIDEO, 1, 10, 1, 63, machine_ps2_model_50_init, NULL },
{ "[386SX ISA] AMA-932J", ROM_AMA932J, "ama932j", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT | MACHINE_HDC | MACHINE_VIDEO, 512, 8192, 128, 127, machine_at_ama932j_init, at_ama932j_get_device },
{ "[386DX ISA] AMI 386SX clone", ROM_AMI386SX_OPTI495, "ami386sx", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 16, 1, 127, machine_at_opti495_ami_init, NULL },
{ "[386DX ISA] AMI 386SX clone", ROM_AMI386SX_OPTI495, "ami386sx", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 16, 1, 127, machine_at_opti495_ami_init, NULL },
{ "[386SX ISA] AMI Unknown 386SX", ROM_AMI386SX, "ami386", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT | MACHINE_HDC, 512,16384, 128, 127, machine_at_headland_init, NULL },
{ "[386SX ISA] Amstrad MegaPC", ROM_MEGAPC, "megapc", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_VIDEO | MACHINE_HDC, 1, 16, 1, 127, machine_at_wd76c10_init, NULL },
{ "[386SX ISA] Award 386SX clone", ROM_AWARD386SX_OPTI495, "award386sx", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, 0, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 16, 1, 127, machine_at_opti495_init, NULL },