Removed the file pointer from the hdd_t struct;
Partially split off the Logitech Serial Mouse emulation from Microsoft Serial Mouse; Slightly reworked serial port emulation (the two UART's are now device_t's, non-FIFO mode implemented and is now default, FIFO mode reimplemented from scratch so it's now actually correct); Added the emulation of the SiS 85c497 chip to the SiS 85c496/497 chipset; Bugfixes to the emulated Super I/O chips and made them all device_t's now.
This commit is contained in:
OBattler
676
src/serial.c
676
src/serial.c
@@ -1,11 +1,12 @@
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#include <stdarg.h>
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#include <stdio.h>
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#include <stdint.h>
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#include <string.h>
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#include <stdlib.h>
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#include <string.h>
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#include <wchar.h>
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#define HAVE_STDARG_H
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#include "86box.h"
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#include "device.h"
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#include "machine/machine.h"
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#include "io.h"
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#include "pic.h"
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@@ -18,14 +19,15 @@
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enum
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{
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SERIAL_INT_LSR = 1,
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SERIAL_INT_RECEIVE = 2,
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SERIAL_INT_TRANSMIT = 4,
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SERIAL_INT_MSR = 8
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SERIAL_INT_LSR = 1,
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SERIAL_INT_RECEIVE = 2,
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SERIAL_INT_TRANSMIT = 4,
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SERIAL_INT_MSR = 8
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};
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SERIAL serial1, serial2;
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int serial_do_log = 0;
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static int next_inst = 0;
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static serial_device_t serial_devices[SERIAL_MAX];
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#ifdef ENABLE_SERIAL_LOG
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@@ -48,339 +50,405 @@ serial_log(const char *fmt, ...)
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#endif
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void serial_reset()
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void
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serial_reset_port(serial_t *dev)
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{
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serial1.iir = serial1.ier = serial1.lcr = 0;
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serial2.iir = serial2.ier = serial2.lcr = 0;
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serial1.fifo_read = serial1.fifo_write = 0;
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serial2.fifo_read = serial2.fifo_write = 0;
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dev->iir = dev->ier = dev->lcr = dev->fcr = 0;
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dev->fifo_enabled = 0;
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dev->xmit_fifo_pos = dev->rcvr_fifo_pos = 0;
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memset(dev->xmit_fifo, 0, 14);
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memset(dev->rcvr_fifo, 0, 14);
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}
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void serial_update_ints(SERIAL *serial)
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void
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serial_update_ints(serial_t *dev)
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{
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int stat = 0;
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serial->iir = 1;
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int stat = 0;
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if ((serial->ier & 4) && (serial->int_status & SERIAL_INT_LSR)) /*Line status interrupt*/
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{
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stat = 1;
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serial->iir = 6;
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}
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else if ((serial->ier & 1) && (serial->int_status & SERIAL_INT_RECEIVE)) /*Recieved data available*/
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{
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stat = 1;
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serial->iir = 4;
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}
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else if ((serial->ier & 2) && (serial->int_status & SERIAL_INT_TRANSMIT)) /*Transmit data empty*/
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{
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stat = 1;
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serial->iir = 2;
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}
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else if ((serial->ier & 8) && (serial->int_status & SERIAL_INT_MSR)) /*Modem status interrupt*/
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{
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stat = 1;
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serial->iir = 0;
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}
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dev->iir = 1;
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if (stat && ((serial->mctrl & 8) || PCJR)) {
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picintlevel(1 << serial->irq);
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} else
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picintc(1 << serial->irq);
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if ((dev->ier & 4) && (dev->int_status & SERIAL_INT_LSR)) {
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/* Line status interrupt */
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stat = 1;
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dev->iir = 6;
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} else if ((dev->ier & 1) && (dev->int_status & SERIAL_INT_RECEIVE)) {
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/* Recieved data available */
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stat = 1;
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dev->iir = 4;
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} else if ((dev->ier & 2) && (dev->int_status & SERIAL_INT_TRANSMIT)) {
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/* Transmit data empty */
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stat = 1;
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dev->iir = 2;
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} else if ((dev->ier & 8) && (dev->int_status & SERIAL_INT_MSR)) {
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/* Modem status interrupt */
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stat = 1;
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dev->iir = 0;
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}
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if (stat && ((dev->mctrl & 8) || PCJR)) {
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if (dev->type >= SERIAL_NS16540)
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picintlevel(1 << dev->irq);
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else
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picint(1 << dev->irq);
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} else
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picintc(1 << dev->irq);
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}
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void serial_clear_fifo(SERIAL *serial)
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void
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serial_write_fifo(serial_t *dev, uint8_t dat)
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{
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memset(serial->fifo, 0, 256);
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serial->fifo_read = serial->fifo_write = 0;
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uint8_t old_lsr;
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serial_log("serial_write_fifo(%08X, %02X, %i)\n", dev, dat, (dev->type >= SERIAL_NS16550) && dev->fifo_enabled);
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if ((dev->type >= SERIAL_NS16550) && dev->fifo_enabled) {
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/* FIFO mode. */
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dev->rcvr_fifo[dev->rcvr_fifo_pos++] = dat;
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dev->rcvr_fifo_pos %= dev->fifo_len;
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old_lsr = dev->lsr;
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dev->lsr &= 0xfe;
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dev->lsr |= (!dev->rcvr_fifo_pos);
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dev->int_status &= SERIAL_INT_RECEIVE;
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if (!dev->rcvr_fifo_pos)
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dev->int_status |= SERIAL_INT_RECEIVE;
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if ((old_lsr ^ dev->lsr) & 0x01)
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serial_update_ints(dev);
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} else {
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/* Non-FIFO mode. */
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dev->dat = dat;
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dev->lsr |= 1;
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dev->int_status |= SERIAL_INT_RECEIVE;
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serial_update_ints(dev);
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}
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}
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void serial_write_fifo(SERIAL *serial, uint8_t dat)
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void
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serial_dev_write(serial_t *dev, uint8_t val)
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{
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serial->fifo[serial->fifo_write] = dat;
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serial->fifo_write = (serial->fifo_write + 1) & 0xFF;
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if (!(serial->lsr & 1))
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{
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serial->lsr |= 1;
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serial->int_status |= SERIAL_INT_RECEIVE;
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serial_update_ints(serial);
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}
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if (dev->mctrl & 0x10)
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serial_write_fifo(dev, val);
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else if (dev->sd->dev_write)
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dev->sd->dev_write(dev, dev->sd->priv, val);
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}
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uint8_t serial_read_fifo(SERIAL *serial)
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{
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if (serial->fifo_read != serial->fifo_write)
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{
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serial->dat = serial->fifo[serial->fifo_read];
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serial->fifo_read = (serial->fifo_read + 1) & 0xFF;
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}
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return serial->dat;
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}
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void serial_write(uint16_t addr, uint8_t val, void *p)
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void
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serial_write(uint16_t addr, uint8_t val, void *p)
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{
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SERIAL *serial = (SERIAL *)p;
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switch (addr&7)
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{
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case 0:
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if (serial->lcr & 0x80)
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{
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serial->dlab1 = val;
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return;
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}
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serial->thr = val;
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serial->lsr |= 0x20;
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serial->int_status |= SERIAL_INT_TRANSMIT;
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serial_update_ints(serial);
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if (serial->mctrl & 0x10)
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{
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serial_write_fifo(serial, val);
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}
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break;
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case 1:
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if (serial->lcr & 0x80)
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{
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serial->dlab2 = val;
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return;
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}
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serial->ier = val & 0xf;
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serial_update_ints(serial);
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break;
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case 2:
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serial->fcr = val;
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break;
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case 3:
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serial->lcr = val;
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break;
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case 4:
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if ((val & 2) && !(serial->mctrl & 2))
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{
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if (serial->rcr_callback)
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serial->rcr_callback((struct SERIAL *)serial, serial->rcr_callback_p);
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}
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serial->mctrl = val;
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if (val & 0x10)
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{
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uint8_t new_msr;
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new_msr = (val & 0x0c) << 4;
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new_msr |= (val & 0x02) ? 0x10: 0;
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new_msr |= (val & 0x01) ? 0x20: 0;
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if ((serial->msr ^ new_msr) & 0x10)
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new_msr |= 0x01;
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if ((serial->msr ^ new_msr) & 0x20)
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new_msr |= 0x02;
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if ((serial->msr ^ new_msr) & 0x80)
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new_msr |= 0x08;
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if ((serial->msr & 0x40) && !(new_msr & 0x40))
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new_msr |= 0x04;
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serial->msr = new_msr;
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}
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break;
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case 5:
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serial->lsr = val;
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if (serial->lsr & 0x01)
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serial->int_status |= SERIAL_INT_RECEIVE;
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if (serial->lsr & 0x1e)
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serial->int_status |= SERIAL_INT_LSR;
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if (serial->lsr & 0x20)
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serial->int_status |= SERIAL_INT_TRANSMIT;
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serial_update_ints(serial);
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break;
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case 6:
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serial->msr = val;
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if (serial->msr & 0x0f)
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serial->int_status |= SERIAL_INT_MSR;
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serial_update_ints(serial);
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break;
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case 7:
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serial->scratch = val;
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break;
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}
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}
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serial_t *dev = (serial_t *)p;
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uint8_t new_msr, old_lsr, i;
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uint8_t serial_read(uint16_t addr, void *p)
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{
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SERIAL *serial = (SERIAL *)p;
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uint8_t temp = 0;
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switch (addr&7)
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{
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case 0:
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if (serial->lcr & 0x80)
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{
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temp = serial->dlab1;
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break;
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serial_log("UART: Write %02X to port %02X\n", val, addr);
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switch (addr & 7) {
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case 0:
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if (dev->lcr & 0x80) {
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dev->dlab1 = val;
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return;
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}
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serial->lsr &= ~1;
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serial->int_status &= ~SERIAL_INT_RECEIVE;
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serial_update_ints(serial);
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temp = serial_read_fifo(serial);
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if (serial->fifo_read != serial->fifo_write) {
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serial->recieve_delay = 1000LL * TIMER_USEC;
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if ((dev->type >= SERIAL_NS16550) && dev->fifo_enabled) {
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/* FIFO mode. */
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dev->xmit_fifo[dev->xmit_fifo_pos++] = val;
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dev->xmit_fifo_pos %= dev->fifo_len;
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old_lsr = dev->lsr;
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dev->lsr &= 0xdf;
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if (!dev->xmit_fifo_pos) {
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for (i = 0; i < dev->fifo_len; i++)
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serial_dev_write(dev, dev->xmit_fifo[i]);
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dev->lsr |= 0x20;
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dev->int_status |= SERIAL_INT_TRANSMIT;
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}
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if ((old_lsr ^ dev->lsr) & 0x20)
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serial_update_ints(dev);
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} else {
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/* Non-FIFO mode. */
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dev->thr = val;
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dev->lsr |= 0x20;
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dev->int_status |= SERIAL_INT_TRANSMIT;
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serial_dev_write(dev, val);
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serial_update_ints(dev);
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}
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break;
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case 1:
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if (serial->lcr & 0x80)
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temp = serial->dlab2;
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else
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temp = serial->ier;
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break;
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case 2:
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temp = serial->iir;
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if ((temp & 0xe) == 2)
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{
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serial->int_status &= ~SERIAL_INT_TRANSMIT;
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serial_update_ints(serial);
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}
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if (serial->fcr & 1)
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temp |= 0xc0;
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break;
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case 3:
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temp = serial->lcr;
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break;
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case 4:
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temp = serial->mctrl;
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break;
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case 5:
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if (serial->lsr & 0x20)
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serial->lsr |= 0x40;
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serial->lsr |= 0x20;
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temp = serial->lsr;
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if (serial->lsr & 0x1f)
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serial->lsr &= ~0x1e;
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serial->int_status &= ~SERIAL_INT_LSR;
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serial_update_ints(serial);
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break;
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case 6:
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temp = serial->msr;
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serial->msr &= ~0x0f;
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serial->int_status &= ~SERIAL_INT_MSR;
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serial_update_ints(serial);
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break;
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case 7:
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temp = serial->scratch;
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break;
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}
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return temp;
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break;
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case 1:
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if (dev->lcr & 0x80) {
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dev->dlab2 = val;
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return;
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}
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dev->ier = val & 0xf;
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serial_update_ints(dev);
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break;
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case 2:
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if (dev->type >= SERIAL_NS16550) {
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dev->fcr = val & 0xf9;
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dev->fifo_enabled = val & 0x01;
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if (val & 0x02) {
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memset(dev->rcvr_fifo, 0, 14);
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dev->rcvr_fifo_pos = 0;
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}
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if (val & 0x04) {
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memset(dev->xmit_fifo, 0, 14);
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dev->xmit_fifo_pos = 0;
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}
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switch ((val >> 6) & 0x03) {
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case 0:
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dev->fifo_len = 1;
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break;
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case 1:
|
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dev->fifo_len = 4;
|
||||
break;
|
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case 2:
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dev->fifo_len = 8;
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break;
|
||||
case 3:
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dev->fifo_len = 14;
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||||
break;
|
||||
}
|
||||
}
|
||||
break;
|
||||
case 3:
|
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dev->lcr = val;
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break;
|
||||
case 4:
|
||||
if ((val & 2) && !(dev->mctrl & 2)) {
|
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if (dev->sd->rcr_callback)
|
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dev->sd->rcr_callback(dev, dev->sd->priv);
|
||||
}
|
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dev->mctrl = val;
|
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if (val & 0x10) {
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||||
new_msr = (val & 0x0c) << 4;
|
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new_msr |= (val & 0x02) ? 0x10: 0;
|
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new_msr |= (val & 0x01) ? 0x20: 0;
|
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|
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if ((dev->msr ^ new_msr) & 0x10)
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new_msr |= 0x01;
|
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if ((dev->msr ^ new_msr) & 0x20)
|
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new_msr |= 0x02;
|
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if ((dev->msr ^ new_msr) & 0x80)
|
||||
new_msr |= 0x08;
|
||||
if ((dev->msr & 0x40) && !(new_msr & 0x40))
|
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new_msr |= 0x04;
|
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|
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dev->msr = new_msr;
|
||||
}
|
||||
break;
|
||||
case 5:
|
||||
dev->lsr = val;
|
||||
if (dev->lsr & 0x01)
|
||||
dev->int_status |= SERIAL_INT_RECEIVE;
|
||||
if (dev->lsr & 0x1e)
|
||||
dev->int_status |= SERIAL_INT_LSR;
|
||||
if (dev->lsr & 0x20)
|
||||
dev->int_status |= SERIAL_INT_TRANSMIT;
|
||||
serial_update_ints(dev);
|
||||
break;
|
||||
case 6:
|
||||
dev->msr = val;
|
||||
if (dev->msr & 0x0f)
|
||||
dev->int_status |= SERIAL_INT_MSR;
|
||||
serial_update_ints(dev);
|
||||
break;
|
||||
case 7:
|
||||
dev->scratch = val;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void serial_recieve_callback(void *p)
|
||||
|
||||
uint8_t
|
||||
serial_read(uint16_t addr, void *p)
|
||||
{
|
||||
SERIAL *serial = (SERIAL *)p;
|
||||
|
||||
serial->recieve_delay = 0;
|
||||
|
||||
if (serial->fifo_read != serial->fifo_write)
|
||||
{
|
||||
serial->lsr |= 1;
|
||||
serial->int_status |= SERIAL_INT_RECEIVE;
|
||||
serial_update_ints(serial);
|
||||
}
|
||||
serial_t *dev = (serial_t *)p;
|
||||
uint8_t old_lsr, ret = 0;
|
||||
|
||||
switch (addr & 7) {
|
||||
case 0:
|
||||
if (dev->lcr & 0x80) {
|
||||
ret = dev->dlab1;
|
||||
break;
|
||||
}
|
||||
|
||||
if ((dev->type >= SERIAL_NS16550) && dev->fifo_enabled) {
|
||||
/* FIFO mode. */
|
||||
ret = dev->rcvr_fifo[dev->rcvr_fifo_pos++];
|
||||
dev->rcvr_fifo_pos %= dev->fifo_len;
|
||||
old_lsr = dev->lsr;
|
||||
if (!dev->rcvr_fifo_pos) {
|
||||
dev->lsr &= 0xfe;
|
||||
dev->int_status &= ~SERIAL_INT_RECEIVE;
|
||||
if ((old_lsr ^ dev->lsr) & 0x01)
|
||||
serial_update_ints(dev);
|
||||
}
|
||||
} else {
|
||||
ret = dev->dat;
|
||||
dev->lsr &= 0xfe;
|
||||
dev->int_status &= ~SERIAL_INT_RECEIVE;
|
||||
serial_update_ints(dev);
|
||||
}
|
||||
break;
|
||||
case 1:
|
||||
if (dev->lcr & 0x80)
|
||||
ret = dev->dlab2;
|
||||
else
|
||||
ret = dev->ier;
|
||||
break;
|
||||
case 2:
|
||||
ret = dev->iir;
|
||||
if ((ret & 0xe) == 2) {
|
||||
dev->int_status &= ~SERIAL_INT_TRANSMIT;
|
||||
serial_update_ints(dev);
|
||||
}
|
||||
if (dev->fcr & 1)
|
||||
ret |= 0xc0;
|
||||
break;
|
||||
case 3:
|
||||
ret = dev->lcr;
|
||||
break;
|
||||
case 4:
|
||||
ret = dev->mctrl;
|
||||
break;
|
||||
case 5:
|
||||
if (dev->lsr & 0x20)
|
||||
dev->lsr |= 0x40;
|
||||
dev->lsr |= 0x20;
|
||||
ret = dev->lsr;
|
||||
if (dev->lsr & 0x1f)
|
||||
dev->lsr &= ~0x1e;
|
||||
dev->int_status &= ~SERIAL_INT_LSR;
|
||||
serial_update_ints(dev);
|
||||
break;
|
||||
case 6:
|
||||
ret = dev->msr;
|
||||
dev->msr &= ~0x0f;
|
||||
dev->int_status &= ~SERIAL_INT_MSR;
|
||||
serial_update_ints(dev);
|
||||
break;
|
||||
case 7:
|
||||
ret = dev->scratch;
|
||||
break;
|
||||
}
|
||||
|
||||
serial_log("UART: Read %02X from port %02X\n", ret, addr);
|
||||
return ret;
|
||||
}
|
||||
|
||||
uint16_t base_address[2] = { 0x0000, 0x0000 };
|
||||
|
||||
void serial_remove(int port)
|
||||
void
|
||||
serial_remove(serial_t *dev)
|
||||
{
|
||||
if ((port < 1) || (port > 2))
|
||||
{
|
||||
fatal("serial_remove(): Invalid serial port: %i\n", port);
|
||||
exit(-1);
|
||||
}
|
||||
if (!serial_enabled[dev->inst])
|
||||
return;
|
||||
|
||||
if (!serial_enabled[port - 1])
|
||||
{
|
||||
return;
|
||||
}
|
||||
if (!dev->base_address)
|
||||
return;
|
||||
|
||||
if (!base_address[port - 1])
|
||||
{
|
||||
return;
|
||||
}
|
||||
serial_log("Removing serial port %i at %04X...\n", dev->inst, dev->base_address);
|
||||
|
||||
serial_log("Removing serial port %i at %04X...\n", port, base_address[port - 1]);
|
||||
|
||||
switch(port)
|
||||
{
|
||||
case 1:
|
||||
io_removehandler(base_address[0], 0x0008, serial_read, NULL, NULL, serial_write, NULL, NULL, &serial1);
|
||||
base_address[0] = 0x0000;
|
||||
break;
|
||||
case 2:
|
||||
io_removehandler(base_address[1], 0x0008, serial_read, NULL, NULL, serial_write, NULL, NULL, &serial2);
|
||||
base_address[1] = 0x0000;
|
||||
break;
|
||||
}
|
||||
io_removehandler(dev->base_address, 0x0008,
|
||||
serial_read, NULL, NULL, serial_write, NULL, NULL, dev);
|
||||
dev->base_address = 0x0000;
|
||||
}
|
||||
|
||||
void serial_setup(int port, uint16_t addr, int irq)
|
||||
|
||||
void
|
||||
serial_setup(serial_t *dev, uint16_t addr, int irq)
|
||||
{
|
||||
serial_log("Adding serial port %i at %04X...\n", port, addr);
|
||||
serial_log("Adding serial port %i at %04X...\n", dev->inst, addr);
|
||||
|
||||
switch(port)
|
||||
{
|
||||
case 1:
|
||||
if (!serial_enabled[0])
|
||||
{
|
||||
return;
|
||||
}
|
||||
if (base_address[0] != 0x0000)
|
||||
{
|
||||
serial_remove(port);
|
||||
}
|
||||
if (addr != 0x0000)
|
||||
{
|
||||
base_address[0] = addr;
|
||||
io_sethandler(addr, 0x0008, serial_read, NULL, NULL, serial_write, NULL, NULL, &serial1);
|
||||
}
|
||||
serial1.irq = irq;
|
||||
break;
|
||||
case 2:
|
||||
if (!serial_enabled[1])
|
||||
{
|
||||
return;
|
||||
}
|
||||
if (base_address[1] != 0x0000)
|
||||
{
|
||||
serial_remove(port);
|
||||
}
|
||||
if (addr != 0x0000)
|
||||
{
|
||||
base_address[1] = addr;
|
||||
io_sethandler(addr, 0x0008, serial_read, NULL, NULL, serial_write, NULL, NULL, &serial2);
|
||||
}
|
||||
serial2.irq = irq;
|
||||
break;
|
||||
default:
|
||||
fatal("serial_setup(): Invalid serial port: %i\n", port);
|
||||
break;
|
||||
}
|
||||
if (!serial_enabled[dev->inst])
|
||||
return;
|
||||
if (dev->base_address != 0x0000)
|
||||
serial_remove(dev);
|
||||
dev->base_address = addr;
|
||||
if (addr != 0x0000)
|
||||
io_sethandler(addr, 0x0008, serial_read, NULL, NULL, serial_write, NULL, NULL, dev);
|
||||
dev->irq = irq;
|
||||
}
|
||||
|
||||
void serial_init(void)
|
||||
|
||||
serial_t *
|
||||
serial_attach(int port,
|
||||
void (*rcr_callback)(struct serial_s *serial, void *p),
|
||||
void (*dev_write)(struct serial_s *serial, void *p, uint8_t data),
|
||||
void *priv)
|
||||
{
|
||||
base_address[0] = 0x03f8;
|
||||
base_address[1] = 0x02f8;
|
||||
serial_device_t *sd = &serial_devices[port];
|
||||
|
||||
if (serial_enabled[0])
|
||||
{
|
||||
serial_log("Adding serial port 1...\n");
|
||||
memset(&serial1, 0, sizeof(serial1));
|
||||
io_sethandler(0x3f8, 0x0008, serial_read, NULL, NULL, serial_write, NULL, NULL, &serial1);
|
||||
serial1.irq = 4;
|
||||
serial1.rcr_callback = NULL;
|
||||
timer_add(serial_recieve_callback, &serial1.recieve_delay, &serial1.recieve_delay, &serial1);
|
||||
}
|
||||
if (serial_enabled[1])
|
||||
{
|
||||
serial_log("Adding serial port 2...\n");
|
||||
memset(&serial2, 0, sizeof(serial2));
|
||||
io_sethandler(0x2f8, 0x0008, serial_read, NULL, NULL, serial_write, NULL, NULL, &serial2);
|
||||
serial2.irq = 3;
|
||||
serial2.rcr_callback = NULL;
|
||||
timer_add(serial_recieve_callback, &serial2.recieve_delay, &serial2.recieve_delay, &serial2);
|
||||
}
|
||||
sd->rcr_callback = rcr_callback;
|
||||
sd->dev_write = dev_write;
|
||||
sd->priv = priv;
|
||||
|
||||
return sd->serial;
|
||||
}
|
||||
|
||||
|
||||
static void
|
||||
serial_close(void *priv)
|
||||
{
|
||||
serial_t *dev = (serial_t *) priv;
|
||||
|
||||
next_inst--;
|
||||
|
||||
free(dev);
|
||||
}
|
||||
|
||||
|
||||
static void *
|
||||
serial_init(const device_t *info)
|
||||
{
|
||||
serial_t *dev = (serial_t *) malloc(sizeof(serial_t));
|
||||
memset(dev, 0, sizeof(serial_t));
|
||||
|
||||
dev->base_address = next_inst ? 0x03f8 : 0x02f8;
|
||||
|
||||
if (serial_enabled[next_inst]) {
|
||||
serial_log("Adding serial port %i...\n", next_inst);
|
||||
io_sethandler(dev->base_address, 0x0008,
|
||||
serial_read, NULL, NULL, serial_write, NULL, NULL, dev);
|
||||
dev->irq = next_inst ? 4 : 3;
|
||||
dev->type = info->local;
|
||||
dev->inst = next_inst;
|
||||
memset(&(serial_devices[next_inst]), 0, sizeof(serial_device_t));
|
||||
dev->sd = &(serial_devices[next_inst]);
|
||||
dev->sd->serial = dev;
|
||||
serial_reset_port(dev);
|
||||
if (next_inst)
|
||||
serial_setup(dev, SERIAL2_ADDR, SERIAL2_IRQ);
|
||||
else
|
||||
serial_setup(dev, SERIAL1_ADDR, SERIAL1_IRQ);
|
||||
}
|
||||
|
||||
next_inst++;
|
||||
|
||||
return dev;
|
||||
}
|
||||
|
||||
|
||||
const device_t i8250_device = {
|
||||
"Intel 8250(-compatible) UART",
|
||||
0,
|
||||
SERIAL_8250,
|
||||
serial_init, serial_close, NULL,
|
||||
NULL, NULL, NULL,
|
||||
NULL
|
||||
};
|
||||
|
||||
const device_t ns16540_device = {
|
||||
"National Semiconductor NS16540(-compatible) UART",
|
||||
0,
|
||||
SERIAL_NS16540,
|
||||
serial_init, serial_close, NULL,
|
||||
NULL, NULL, NULL,
|
||||
NULL
|
||||
};
|
||||
|
||||
const device_t ns16550_device = {
|
||||
"National Semiconductor NS16550(-compatible) UART",
|
||||
0,
|
||||
SERIAL_NS16550,
|
||||
serial_init, serial_close, NULL,
|
||||
NULL, NULL, NULL,
|
||||
NULL
|
||||
};
|
||||
|
||||
Reference in New Issue
Block a user