From e6c75a7f1abd4859c495d44e46e332f94c5f9777 Mon Sep 17 00:00:00 2001 From: TC1995 Date: Sun, 19 Jan 2020 01:19:40 +0100 Subject: [PATCH 01/33] Fixed some fatal's that turned out to be missing parts of the blt and the width bpp. --- src/video/vid_mga.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/src/video/vid_mga.c b/src/video/vid_mga.c index 5da087e12..966e7f7ee 100644 --- a/src/video/vid_mga.c +++ b/src/video/vid_mga.c @@ -234,6 +234,7 @@ #define DWGCTRL_OPCODE_MASK (0xf << 0) #define DWGCTRL_OPCODE_LINE_OPEN (0x0 << 0) #define DWGCTRL_OPCODE_AUTOLINE_OPEN (0x1 << 0) +#define DWGCTRL_OPCODE_LINE_CLOSE (0x2 << 0) #define DWGCTRL_OPCODE_AUTOLINE_CLOSE (0x3 << 0) #define DWGCTRL_OPCODE_TRAP (0x4 << 0) #define DWGCTRL_OPCODE_TEXTURE_TRAP (0x6 << 0) @@ -4111,6 +4112,15 @@ blit_bitblt(mystique_t *mystique) svga->changedvram[(((mystique->dwgreg.ydst_lin + x) * 3) & mystique->vram_mask) >> 12] = changeframecount; break; + case MACCESS_PWIDTH_32: + dst = ((uint32_t *)svga->vram)[(mystique->dwgreg.ydst_lin + x) & mystique->vram_mask_l]; + + dst = bitop(src, dst, mystique->dwgreg.dwgctrl_running); + + ((uint32_t *)svga->vram)[(mystique->dwgreg.ydst_lin + x) & mystique->vram_mask_l] = dst; + svga->changedvram[((mystique->dwgreg.ydst_lin + x) & mystique->vram_mask_l) >> 10] = changeframecount; + break; + default: fatal("BITBLT RPL BMONOLEF PWIDTH %x %08x\n", mystique->maccess_running & MACCESS_PWIDTH_MASK, mystique->dwgreg.dwgctrl_running); } @@ -4436,6 +4446,10 @@ mystique_start_blit(mystique_t *mystique) case DWGCTRL_OPCODE_AUTOLINE_OPEN: blit_autoline(mystique, 0); break; + + case DWGCTRL_OPCODE_LINE_CLOSE: + blit_line(mystique, 1); + break; case DWGCTRL_OPCODE_AUTOLINE_CLOSE: blit_autoline(mystique, 1); @@ -4478,7 +4492,8 @@ mystique_start_blit(mystique_t *mystique) break; default: - fatal("mystique_start_blit: unknown blit %08x\n", mystique->dwgreg.dwgctrl_running); + fatal("mystique_start_blit: unknown blit %08x\n", mystique->dwgreg.dwgctrl_running & DWGCTRL_OPCODE_MASK); + break; } end_time = plat_timer_read(); From 8e8492baed11b52ffacaaa05c798a2cf1b834df1 Mon Sep 17 00:00:00 2001 From: GH Cao Date: Tue, 4 Feb 2020 22:08:05 +0800 Subject: [PATCH 02/33] win: fix declaration of SetCurrentProcessExplicitAppUserModelID --- src/win/Makefile.mingw | 2 +- src/win/Makefile_ndr.mingw | 2 +- src/win/win.c | 2 ++ 3 files changed, 4 insertions(+), 2 deletions(-) diff --git a/src/win/Makefile.mingw b/src/win/Makefile.mingw index 0e2287be5..1bccbeaa8 100644 --- a/src/win/Makefile.mingw +++ b/src/win/Makefile.mingw @@ -729,7 +729,7 @@ endif ifneq ($(WX), n) LIBS += $(WX_LIBS) -lm endif -LIBS += -lpng -lz -lwsock32 -liphlpapi -ldinput8 -lSDL2 -limm32 -lhid -lsetupapi -loleaut32 -lversion -lwinmm -static -lstdc++ +LIBS += -lpng -lz -lwsock32 -lshell32 -liphlpapi -ldinput8 -lSDL2 -limm32 -lhid -lsetupapi -loleaut32 -lversion -lwinmm -static -lstdc++ ifneq ($(X64), y) LIBS += -Wl,--large-address-aware endif diff --git a/src/win/Makefile_ndr.mingw b/src/win/Makefile_ndr.mingw index 62713f351..94faccebd 100644 --- a/src/win/Makefile_ndr.mingw +++ b/src/win/Makefile_ndr.mingw @@ -735,7 +735,7 @@ endif ifneq ($(WX), n) LIBS += $(WX_LIBS) -lm endif -LIBS += -lpng -lz -lwsock32 -liphlpapi -ldinput8 -lSDL2 -limm32 -lhid -lsetupapi -loleaut32 -lversion -lwinmm -static -lstdc++ +LIBS += -lpng -lz -lwsock32 -lshell32 -liphlpapi -ldinput8 -lSDL2 -limm32 -lhid -lsetupapi -loleaut32 -lversion -lwinmm -static -lstdc++ ifneq ($(X64), y) LIBS += -Wl,--large-address-aware endif diff --git a/src/win/win.c b/src/win/win.c index cfbdab264..1e04d4bb6 100644 --- a/src/win/win.c +++ b/src/win/win.c @@ -19,8 +19,10 @@ * Copyright 2017-2019 Fred N. van Kempen. */ #define UNICODE +#define NTDDI_VERSION 0x06010000 #include #include +#include #include #include #include From 382c606483f599f04088d10ec684b87d5e7c7877 Mon Sep 17 00:00:00 2001 From: GH Cao Date: Tue, 4 Feb 2020 22:11:14 +0800 Subject: [PATCH 03/33] win_settings: fix progress bar in new disk image dialog --- src/win/win_settings.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/win/win_settings.c b/src/win/win_settings.c index 69f054acd..264b5338f 100644 --- a/src/win/win_settings.c +++ b/src/win/win_settings.c @@ -2789,7 +2789,7 @@ win_settings_hard_disks_add_proc(HWND hdlg, UINT message, WPARAM wParam, LPARAM if (r) { for (i = 0; i < r; i++) { fwrite(big_buf, 1, 1048576, f); - SendMessage(h, PBM_SETPOS, (WPARAM) (size + 1), (LPARAM) 0); + SendMessage(h, PBM_SETPOS, (WPARAM) (i + 1), (LPARAM) 0); while (PeekMessage(&msg, 0, 0, 0, PM_REMOVE | PM_NOYIELD)) { TranslateMessage(&msg); From d66608f77b5e59f5297738884755f012e1873590 Mon Sep 17 00:00:00 2001 From: GH Cao Date: Tue, 4 Feb 2020 22:29:01 +0800 Subject: [PATCH 04/33] win rawinput: move all GetRawInputData into one --- src/win/win.h | 8 +++--- src/win/win_joystick.cpp | 1 + ...stick_xinput.cpp => win_joystick_xinput.c} | 3 +- src/win/win_keyboard.c | 25 ++--------------- src/win/win_mouse.c | 28 ++----------------- src/win/win_ui.c | 28 +++++++++++++++---- 6 files changed, 34 insertions(+), 59 deletions(-) rename src/win/{win_joystick_xinput.cpp => win_joystick_xinput.c} (99%) diff --git a/src/win/win.h b/src/win/win.h index 6c8444a33..5bbb6ec95 100644 --- a/src/win/win.h +++ b/src/win/win.h @@ -114,13 +114,13 @@ extern int get_vidpause(void); extern void show_cursor(int); extern void keyboard_getkeymap(void); -extern void keyboard_handle(LPARAM lParam, int infocus); +extern void keyboard_handle(PRAWINPUT raw); extern void win_mouse_init(void); extern void win_mouse_close(void); -#ifndef USE_DINPUT -extern void win_mouse_handle(LPARAM lParam, int infocus); -#endif +extern void win_mouse_handle(PRAWINPUT raw); + +extern void win_joystick_handle(PRAWINPUT raw); extern void win_notify_dlg_open(void); extern void win_notify_dlg_closed(void); diff --git a/src/win/win_joystick.cpp b/src/win/win_joystick.cpp index 499f19903..dea7c70a6 100644 --- a/src/win/win_joystick.cpp +++ b/src/win/win_joystick.cpp @@ -336,3 +336,4 @@ void joystick_process(void) } } +void win_joystick_handle(PRAWINPUT raw) {} diff --git a/src/win/win_joystick_xinput.cpp b/src/win/win_joystick_xinput.c similarity index 99% rename from src/win/win_joystick_xinput.cpp rename to src/win/win_joystick_xinput.c index 237cab23c..cd0b1cea3 100644 --- a/src/win/win_joystick_xinput.cpp +++ b/src/win/win_joystick_xinput.c @@ -18,7 +18,7 @@ * Copyright 2016-2018 Miran Grca. * Copyright 2019 GH Cao. */ -#include +#include #include #include #include @@ -260,3 +260,4 @@ void joystick_process(void) } } +void win_joystick_handle(PRAWINPUT raw) {} diff --git a/src/win/win_keyboard.c b/src/win/win_keyboard.c index eaf4ddac4..b1700b79d 100644 --- a/src/win/win_keyboard.c +++ b/src/win/win_keyboard.c @@ -108,30 +108,12 @@ keyboard_getkeymap(void) void -keyboard_handle(LPARAM lParam, int infocus) +keyboard_handle(PRAWINPUT raw) { - uint32_t ri_size = 0; - UINT size; - RAWINPUT *raw; USHORT scancode; static int recv_lalt = 0, recv_ralt = 0, recv_tab = 0; - if (! infocus) return; - - GetRawInputData((HRAWINPUT)lParam, RID_INPUT, NULL, - &size, sizeof(RAWINPUTHEADER)); - - raw = malloc(size); - if (raw == NULL) return; - - /* Here we read the raw input data for the keyboard */ - ri_size = GetRawInputData((HRAWINPUT)(lParam), RID_INPUT, - raw, &size, sizeof(RAWINPUTHEADER)); - if (ri_size != size) return; - - /* If the input is keyboard, we process it */ - if (raw->header.dwType == RIM_TYPEKEYBOARD) { - RAWKEYBOARD rawKB = raw->data.keyboard; + RAWKEYBOARD rawKB = raw->data.keyboard; scancode = rawKB.MakeCode; /* If it's not a scan code that starts with 0xE1 */ @@ -217,7 +199,4 @@ keyboard_handle(LPARAM lParam, int infocus) if (scancode != 0xFFFF) keyboard_input(!(rawKB.Flags & RI_KEY_BREAK), scancode); } - } - - free(raw); } diff --git a/src/win/win_mouse.c b/src/win/win_mouse.c index 2ca004e9f..b2cf2eeba 100644 --- a/src/win/win_mouse.c +++ b/src/win/win_mouse.c @@ -58,32 +58,11 @@ win_mouse_init(void) } void -win_mouse_handle(LPARAM lParam, int infocus) +win_mouse_handle(PRAWINPUT raw) { - uint32_t ri_size = 0; - UINT size; - RAWINPUT *raw; - RAWMOUSE state; + RAWMOUSE state = raw->data.mouse; static int x, y; - if (! infocus) return; - - GetRawInputData((HRAWINPUT)lParam, RID_INPUT, NULL, - &size, sizeof(RAWINPUTHEADER)); - - raw = (RAWINPUT*)malloc(size); - if (raw == NULL) return; - - /* Here we read the raw input data for the mouse */ - ri_size = GetRawInputData((HRAWINPUT)(lParam), RID_INPUT, - raw, &size, sizeof(RAWINPUTHEADER)); - if (ri_size != size) goto err; - - /* If the input is not a mouse, we ignore it */ - if (raw->header.dwType != RIM_TYPEMOUSE) goto err; - - state = raw->data.mouse; - /* read mouse buttons and wheel */ if (state.usButtonFlags & RI_MOUSE_LEFT_BUTTON_DOWN) mousestate.buttons |= 1; @@ -120,9 +99,6 @@ win_mouse_handle(LPARAM lParam, int infocus) mousestate.dx += state.lLastX; mousestate.dy += state.lLastY; } - - err: - free(raw); } void diff --git a/src/win/win_ui.c b/src/win/win_ui.c index 812e4c2cb..608ccb775 100644 --- a/src/win/win_ui.c +++ b/src/win/win_ui.c @@ -1238,12 +1238,30 @@ input_proc(HWND hwnd, UINT message, WPARAM wParam, LPARAM lParam) { switch (message) { case WM_INPUT: - keyboard_handle(lParam, infocus); -#ifndef USE_DINPUT - win_mouse_handle(lParam, infocus); -#endif - break; + if (infocus) { + UINT size = 0; + PRAWINPUT raw = NULL; + /* Here we read the raw input data */ + GetRawInputData((HRAWINPUT)lParam, RID_INPUT, NULL, &size, sizeof(RAWINPUTHEADER)); + raw = (PRAWINPUT)malloc(size); + if (GetRawInputData((HRAWINPUT)lParam, RID_INPUT, raw, &size, sizeof(RAWINPUTHEADER)) == size) { + switch(raw->header.dwType) + { + case RIM_TYPEKEYBOARD: + keyboard_handle(raw); + break; + case RIM_TYPEMOUSE: + win_mouse_handle(raw); + break; + case RIM_TYPEHID: + win_joystick_handle(raw); + break; + } + } + free(raw); + } + break; case WM_SETFOCUS: infocus = 1; if (! hook_enabled) { From dfbb56af41332441a6da691fb84a8cb575909408 Mon Sep 17 00:00:00 2001 From: GH Cao Date: Tue, 4 Feb 2020 22:49:19 +0800 Subject: [PATCH 05/33] win: RawInput Joystick interface --- src/win/win_joystick_rawinput.c | 472 ++++++++++++++++++++++++++++++++ 1 file changed, 472 insertions(+) create mode 100644 src/win/win_joystick_rawinput.c diff --git a/src/win/win_joystick_rawinput.c b/src/win/win_joystick_rawinput.c new file mode 100644 index 000000000..91ef6989f --- /dev/null +++ b/src/win/win_joystick_rawinput.c @@ -0,0 +1,472 @@ +/* + * 86Box A hypervisor and IBM PC system emulator that specializes in + * running old operating systems and software designed for IBM + * PC systems and compatibles from 1981 through fairly recent + * system designs based on the PCI bus. + * + * This file is part of the 86Box distribution. + * + * RawInput joystick interface. + * + * Version: @(#)win_joystick_rawinput.c 1.0.0 2020/1/19 + * + * Authors: Sarah Walker, + * Miran Grca, + * GH Cao, + * + * Copyright 2008-2018 Sarah Walker. + * Copyright 2016-2018 Miran Grca. + * Copyright 2020 GH Cao. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#define HAVE_STDARG_H +#include "../86box.h" +#include "../device.h" +#include "../plat.h" +#include "../game/gameport.h" +#include "win.h" + +#ifdef ENABLE_JOYSTICK_LOG +int joystick_do_log = ENABLE_JOYSTICK_LOG; + + +static void +joystick_log(const char *fmt, ...) +{ + va_list ap; + + if (joystick_do_log) { + va_start(ap, fmt); + pclog_ex(fmt, ap); + va_end(ap); + } +} +#else +#define joystick_log(fmt, ...) +#endif + +typedef struct { + HANDLE hdevice; + PHIDP_PREPARSED_DATA data; + + USAGE usage_button[128]; + + struct raw_axis_t { + USAGE usage; + USHORT link; + USHORT bitsize; + LONG max; + LONG min; + } axis[8]; + + struct raw_pov_t { + USAGE usage; + USHORT link; + LONG max; + LONG min; + } pov[4]; +} raw_joystick_t; + +plat_joystick_t plat_joystick_state[MAX_PLAT_JOYSTICKS]; +joystick_t joystick_state[MAX_JOYSTICKS]; +int joysticks_present = 0; + +raw_joystick_t raw_joystick_state[MAX_PLAT_JOYSTICKS]; + +/* We only use the first 32 buttons reported, from Usage ID 1-128 */ +void joystick_add_button(raw_joystick_t* rawjoy, plat_joystick_t* joy, USAGE usage) { + if (joy->nr_buttons >= 32) return; + if (usage < 1 || usage > 128) return; + + rawjoy->usage_button[usage] = joy->nr_buttons; + sprintf(joy->button[joy->nr_buttons].name, "Button %d", usage); + joy->nr_buttons++; +} + +void joystick_add_axis(raw_joystick_t* rawjoy, plat_joystick_t* joy, PHIDP_VALUE_CAPS prop) { + if (joy->nr_axes >= 8) return; + + switch (prop->Range.UsageMin) { + case HID_USAGE_GENERIC_X: + sprintf(joy->axis[joy->nr_axes].name, "X"); + break; + case HID_USAGE_GENERIC_Y: + sprintf(joy->axis[joy->nr_axes].name, "Y"); + break; + case HID_USAGE_GENERIC_Z: + sprintf(joy->axis[joy->nr_axes].name, "Z"); + break; + case HID_USAGE_GENERIC_RX: + sprintf(joy->axis[joy->nr_axes].name, "RX"); + break; + case HID_USAGE_GENERIC_RY: + sprintf(joy->axis[joy->nr_axes].name, "RY"); + break; + case HID_USAGE_GENERIC_RZ: + sprintf(joy->axis[joy->nr_axes].name, "RZ"); + break; + default: + return; + } + + joy->axis[joy->nr_axes].id = joy->nr_axes; + rawjoy->axis[joy->nr_axes].usage = prop->Range.UsageMin; + rawjoy->axis[joy->nr_axes].link = prop->LinkCollection; + rawjoy->axis[joy->nr_axes].bitsize = prop->BitSize; + + /* Assume unsigned when min >= 0 */ + if (prop->LogicalMin < 0) { + rawjoy->axis[joy->nr_axes].max = prop->LogicalMax; + } else { + /* + * Some joysticks will send -1 in LogicalMax, like Xbox Controllers + * so we need to mask that to appropriate value (instead of 0xFFFFFFFF) + */ + rawjoy->axis[joy->nr_axes].max = prop->LogicalMax & ((1 << prop->BitSize) - 1); + } + rawjoy->axis[joy->nr_axes].min = prop->LogicalMin; + + joy->nr_axes++; +} + +void joystick_add_pov(raw_joystick_t* rawjoy, plat_joystick_t* joy, PHIDP_VALUE_CAPS prop) { + if (joy->nr_povs >= 4) return; + + sprintf(joy->pov[joy->nr_povs].name, "POV %d", joy->nr_povs+1); + rawjoy->pov[joy->nr_povs].usage = prop->Range.UsageMin; + rawjoy->pov[joy->nr_povs].link = prop->LinkCollection; + rawjoy->pov[joy->nr_povs].min = prop->LogicalMin; + rawjoy->pov[joy->nr_povs].max = prop->LogicalMax; + + joy->nr_povs++; +} + +void joystick_get_capabilities(raw_joystick_t* rawjoy, plat_joystick_t* joy) { + UINT size = 0; + PHIDP_BUTTON_CAPS btn_caps = NULL; + PHIDP_VALUE_CAPS val_caps = NULL; + + /* Get preparsed data (HID data format) */ + GetRawInputDeviceInfoW(rawjoy->hdevice, RIDI_PREPARSEDDATA, NULL, &size); + rawjoy->data = malloc(size); + if (GetRawInputDeviceInfoW(rawjoy->hdevice, RIDI_PREPARSEDDATA, rawjoy->data, &size) <= 0) + fatal("joystick_get_capabilities: Failed to get preparsed data.\n"); + + HIDP_CAPS caps; + HidP_GetCaps(rawjoy->data, &caps); + + /* Buttons */ + if (caps.NumberInputButtonCaps > 0) { + btn_caps = calloc(caps.NumberInputButtonCaps, sizeof(HIDP_BUTTON_CAPS)); + if (HidP_GetButtonCaps(HidP_Input, btn_caps, &caps.NumberInputButtonCaps, rawjoy->data) != HIDP_STATUS_SUCCESS) { + joystick_log("joystick_get_capabilities: Failed to query input buttons.\n"); + goto end; + } + /* We only detect generic stuff */ + for (int c=0; c 0) { + val_caps = calloc(caps.NumberInputValueCaps, sizeof(HIDP_VALUE_CAPS)); + if (HidP_GetValueCaps(HidP_Input, val_caps, &caps.NumberInputValueCaps, rawjoy->data) != HIDP_STATUS_SUCCESS) { + joystick_log("joystick_get_capabilities: Failed to query axes and povs.\n"); + goto end; + } + /* We only detect generic stuff */ + for (int c=0; chdevice, RIDI_DEVICENAME, device_name, &size); + device_name = calloc(size, sizeof(char)); + if (GetRawInputDeviceInfoA(rawjoy->hdevice, RIDI_DEVICENAME, device_name, &size) <= 0) + fatal("joystick_get_capabilities: Failed to get device name.\n"); + + HANDLE hDevObj = CreateFile(device_name, GENERIC_READ | GENERIC_WRITE, + FILE_SHARE_READ | FILE_SHARE_WRITE, NULL, OPEN_EXISTING, 0, NULL); + if (hDevObj) { + HidD_GetProductString(hDevObj, device_desc_wide, sizeof(WCHAR) * 200); + CloseHandle(hDevObj); + } + free(device_name); + + int result = WideCharToMultiByte(CP_ACP, 0, device_desc_wide, 200, joy->name, 260, NULL, NULL); + if (result == 0 || strlen(joy->name) == 0) + sprintf(joy->name, + "RawInput %s, VID:%04lX PID:%04lX", + info->hid.usUsage == HID_USAGE_GENERIC_JOYSTICK ? "Joystick" : "Gamepad", + info->hid.dwProductId, + info->hid.dwVendorId); +} + +void joystick_init() +{ + UINT size = 0; + atexit(joystick_close); + + joysticks_present = 0; + memset(raw_joystick_state, 0, sizeof(raw_joystick_t) * MAX_PLAT_JOYSTICKS); + + /* Get a list of raw input devices from Windows */ + UINT raw_devices = 0; + GetRawInputDeviceList(NULL, &raw_devices, sizeof(RAWINPUTDEVICELIST)); + PRAWINPUTDEVICELIST deviceList = calloc(raw_devices, sizeof(RAWINPUTDEVICELIST)); + GetRawInputDeviceList(deviceList, &raw_devices, sizeof(RAWINPUTDEVICELIST)); + + for (int i=0; i= MAX_PLAT_JOYSTICKS) break; + if (deviceList[i].dwType != RIM_TYPEHID) continue; + + /* Get device info: hardware IDs and usage IDs */ + GetRawInputDeviceInfoA(deviceList[i].hDevice, RIDI_DEVICEINFO, NULL, &size); + info = malloc(size); + info->cbSize = sizeof(RID_DEVICE_INFO); + if (GetRawInputDeviceInfoA(deviceList[i].hDevice, RIDI_DEVICEINFO, info, &size) <= 0) + goto end_loop; + + /* If this is not a joystick/gamepad, skip */ + if (info->hid.usUsagePage != HID_USAGE_PAGE_GENERIC) goto end_loop; + if (info->hid.usUsage != HID_USAGE_GENERIC_JOYSTICK && + info->hid.usUsage != HID_USAGE_GENERIC_GAMEPAD) goto end_loop; + + plat_joystick_t *joy = &plat_joystick_state[joysticks_present]; + raw_joystick_t *rawjoy = &raw_joystick_state[joysticks_present]; + rawjoy->hdevice = deviceList[i].hDevice; + + joystick_get_capabilities(rawjoy, joy); + joystick_get_device_name(rawjoy, joy, info); + + joystick_log("joystick_init: %s - %d buttons, %d axes, %d POVs\n", + joy->name, joy->nr_buttons, joy->nr_axes, joy->nr_povs); + + joysticks_present++; + + end_loop: + free(info); + } + + joystick_log("joystick_init: joysticks_present=%i\n", joysticks_present); + + /* Initialize the RawInput (joystick and gamepad) module. */ + RAWINPUTDEVICE ridev[2]; + ridev[0].dwFlags = 0; + ridev[0].hwndTarget = NULL; + ridev[0].usUsagePage = HID_USAGE_PAGE_GENERIC; + ridev[0].usUsage = HID_USAGE_GENERIC_JOYSTICK; + + ridev[1].dwFlags = 0; + ridev[1].hwndTarget = NULL; + ridev[1].usUsagePage = HID_USAGE_PAGE_GENERIC; + ridev[1].usUsage = HID_USAGE_GENERIC_GAMEPAD; + + if (!RegisterRawInputDevices(ridev, 2, sizeof(RAWINPUTDEVICE))) + fatal("plat_joystick_init: RegisterRawInputDevices failed\n"); +} + +void joystick_close() +{ + RAWINPUTDEVICE ridev[2]; + ridev[0].dwFlags = RIDEV_REMOVE; + ridev[0].hwndTarget = NULL; + ridev[0].usUsagePage = HID_USAGE_PAGE_GENERIC; + ridev[0].usUsage = HID_USAGE_GENERIC_JOYSTICK; + + ridev[1].dwFlags = RIDEV_REMOVE; + ridev[1].hwndTarget = NULL; + ridev[1].usUsagePage = HID_USAGE_PAGE_GENERIC; + ridev[1].usUsage = HID_USAGE_GENERIC_GAMEPAD; + + RegisterRawInputDevices(ridev, 2, sizeof(RAWINPUTDEVICE)); +} + + +void win_joystick_handle(PRAWINPUT raw) +{ + HRESULT r; + int j = -1; /* current joystick index, -1 when not found */ + + /* If the input is not from a known device, we ignore it */ + for (int i=0; iheader.hDevice) { + j = i; + break; + } + } + if (j == -1) return; + + /* Read buttons */ + USAGE usage_list[128] = {0}; + ULONG usage_length = plat_joystick_state[j].nr_buttons; + memset(plat_joystick_state[j].b, 0, 32 * sizeof(int)); + + r = HidP_GetUsages(HidP_Input, HID_USAGE_PAGE_BUTTON, 0, usage_list, &usage_length, + raw_joystick_state[j].data, (PCHAR)raw->data.hid.bRawData, raw->data.hid.dwSizeHid); + + if (r == HIDP_STATUS_SUCCESS) { + for (int i=0; imax - axis->min + 1) / 2; + + r = HidP_GetUsageValue(HidP_Input, HID_USAGE_PAGE_GENERIC, axis->link, axis->usage, &uvalue, + raw_joystick_state[j].data, (PCHAR)raw->data.hid.bRawData, raw->data.hid.dwSizeHid); + + if (r == HIDP_STATUS_SUCCESS) { + if (axis->min < 0) { + /* extend signed uvalue to LONG */ + if (uvalue & (1 << (axis->bitsize-1))) { + ULONG mask = (1 << axis->bitsize) - 1; + value = -1U ^ mask; + value |= uvalue; + } else { + value = uvalue; + } + } else { + /* Assume unsigned when min >= 0, convert to a signed value */ + value = (LONG)uvalue - center; + } + if (abs(value) == 1) value = 0; + value = value * 32768 / center; + } + + plat_joystick_state[j].a[a] = value; + //joystick_log("%s %-06d ", plat_joystick_state[j].axis[a].name, plat_joystick_state[j].a[a]); + } + + /* read povs */ + for (int p=0; plink, pov->usage, &uvalue, + raw_joystick_state[j].data, (PCHAR)raw->data.hid.bRawData, raw->data.hid.dwSizeHid); + + if (r == HIDP_STATUS_SUCCESS && (uvalue >= pov->min && uvalue <= pov->max)) { + value = (uvalue - pov->min) * 36000; + value /= (pov->max - pov->min + 1); + value %= 36000; + } + + plat_joystick_state[j].p[p] = value; + + //joystick_log("%s %-3d ", plat_joystick_state[j].pov[p].name, plat_joystick_state[j].p[p]); + + } + //joystick_log("\n"); +} + + +static int joystick_get_axis(int joystick_nr, int mapping) +{ + if (mapping & POV_X) + { + int pov = plat_joystick_state[joystick_nr].p[mapping & 3]; + if (LOWORD(pov) == 0xFFFF) + return 0; + else + return sin((2*M_PI * (double)pov) / 36000.0) * 32767; + } + else if (mapping & POV_Y) + { + int pov = plat_joystick_state[joystick_nr].p[mapping & 3]; + + if (LOWORD(pov) == 0xFFFF) + return 0; + else + return -cos((2*M_PI * (double)pov) / 36000.0) * 32767; + } + else + return plat_joystick_state[joystick_nr].a[plat_joystick_state[joystick_nr].axis[mapping].id]; + +} + + +void joystick_process(void) +{ + int c, d; + + if (joystick_type == 7) return; + + for (c = 0; c < joystick_get_max_joysticks(joystick_type); c++) + { + if (joystick_state[c].plat_joystick_nr) + { + int joystick_nr = joystick_state[c].plat_joystick_nr - 1; + + for (d = 0; d < joystick_get_axis_count(joystick_type); d++) + joystick_state[c].axis[d] = joystick_get_axis(joystick_nr, joystick_state[c].axis_mapping[d]); + for (d = 0; d < joystick_get_button_count(joystick_type); d++) + joystick_state[c].button[d] = plat_joystick_state[joystick_nr].b[joystick_state[c].button_mapping[d]]; + + for (d = 0; d < joystick_get_pov_count(joystick_type); d++) + { + int x, y; + double angle, magnitude; + + x = joystick_get_axis(joystick_nr, joystick_state[c].pov_mapping[d][0]); + y = joystick_get_axis(joystick_nr, joystick_state[c].pov_mapping[d][1]); + + angle = (atan2((double)y, (double)x) * 360.0) / (2*M_PI); + magnitude = sqrt((double)x*(double)x + (double)y*(double)y); + + if (magnitude < 16384) + joystick_state[c].pov[d] = -1; + else + joystick_state[c].pov[d] = ((int)angle + 90 + 360) % 360; + } + } + else + { + for (d = 0; d < joystick_get_axis_count(joystick_type); d++) + joystick_state[c].axis[d] = 0; + for (d = 0; d < joystick_get_button_count(joystick_type); d++) + joystick_state[c].button[d] = 0; + for (d = 0; d < joystick_get_pov_count(joystick_type); d++) + joystick_state[c].pov[d] = -1; + } + } +} + From bc2acaa8d41c74921e4bdabf7ffae89bd32cb80d Mon Sep 17 00:00:00 2001 From: GH Cao Date: Wed, 5 Feb 2020 07:05:28 +0800 Subject: [PATCH 06/33] makefile: do not specify .exe when calling pkg-config --- src/win/Makefile.mingw | 2 +- src/win/Makefile_ndr.mingw | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/win/Makefile.mingw b/src/win/Makefile.mingw index 1bccbeaa8..13ef9fefa 100644 --- a/src/win/Makefile.mingw +++ b/src/win/Makefile.mingw @@ -543,7 +543,7 @@ CFLAGS := $(WX_FLAGS) $(OPTS) $(DFLAGS) $(COPTIM) $(AOPTIM) \ -fno-strict-aliasing # Add freetyp2 references through pkgconfig -CFLAGS := $(CFLAGS) `pkg-config.exe --cflags freetype2` +CFLAGS := $(CFLAGS) `pkg-config --cflags freetype2` CXXFLAGS := $(CFLAGS) diff --git a/src/win/Makefile_ndr.mingw b/src/win/Makefile_ndr.mingw index 94faccebd..06c035f9e 100644 --- a/src/win/Makefile_ndr.mingw +++ b/src/win/Makefile_ndr.mingw @@ -549,7 +549,7 @@ CFLAGS := $(WX_FLAGS) $(OPTS) $(DFLAGS) $(COPTIM) $(AOPTIM) \ -fno-strict-aliasing # Add freetyp2 references through pkgconfig -CFLAGS := $(CFLAGS) `pkg-config.exe --cflags freetype2` +CFLAGS := $(CFLAGS) `pkg-config --cflags freetype2` CXXFLAGS := $(CFLAGS) From 8d400e140e9e1074fe4b5118475200364e4c0c7e Mon Sep 17 00:00:00 2001 From: GH Cao Date: Wed, 5 Feb 2020 07:17:31 +0800 Subject: [PATCH 07/33] makefile: honor LDFLAGS --- src/win/Makefile.mingw | 4 ++-- src/win/Makefile_ndr.mingw | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/win/Makefile.mingw b/src/win/Makefile.mingw index 13ef9fefa..a7ad0b8eb 100644 --- a/src/win/Makefile.mingw +++ b/src/win/Makefile.mingw @@ -788,7 +788,7 @@ all: $(PROG).exe pcap_if.exe $(PROG).exe: $(OBJ) 86Box.res @echo Linking $(PROG).exe .. - @$(CC) -o $(PROG).exe $(OBJ) 86Box.res $(LIBS) + @$(CC) $(LDFLAGS) -o $(PROG).exe $(OBJ) 86Box.res $(LIBS) ifneq ($(DEBUG), y) @$(STRIP) $(PROG).exe endif @@ -799,7 +799,7 @@ pcap_if.res: pcap_if.rc pcap_if.exe: pcap_if.o win_dynld.o pcap_if.res @echo Linking pcap_if.exe .. - @$(CC) -o pcap_if.exe pcap_if.o win_dynld.o pcap_if.res + @$(CC) $(LDFLAGS) -o pcap_if.exe pcap_if.o win_dynld.o pcap_if.res ifneq ($(DEBUG), y) @$(STRIP) pcap_if.exe endif diff --git a/src/win/Makefile_ndr.mingw b/src/win/Makefile_ndr.mingw index 06c035f9e..58a79edac 100644 --- a/src/win/Makefile_ndr.mingw +++ b/src/win/Makefile_ndr.mingw @@ -794,7 +794,7 @@ all: $(PROG).exe pcap_if.exe $(PROG).exe: $(OBJ) 86Box.res @echo Linking $(PROG).exe .. - @$(CC) -o $(PROG).exe $(OBJ) 86Box.res $(LIBS) + @$(CC) $(LDFLAGS) -o $(PROG).exe $(OBJ) 86Box.res $(LIBS) ifneq ($(DEBUG), y) @$(STRIP) $(PROG).exe endif @@ -805,7 +805,7 @@ pcap_if.res: pcap_if.rc pcap_if.exe: pcap_if.o win_dynld.o pcap_if.res @echo Linking pcap_if.exe .. - @$(CC) -o pcap_if.exe pcap_if.o win_dynld.o pcap_if.res + @$(CC) $(LDFLAGS) -o pcap_if.exe pcap_if.o win_dynld.o pcap_if.res ifneq ($(DEBUG), y) @$(STRIP) pcap_if.exe endif From 4da7d7492a814c874f03005598c329bd7be751b0 Mon Sep 17 00:00:00 2001 From: GH Cao Date: Wed, 5 Feb 2020 08:07:09 +0800 Subject: [PATCH 08/33] makefile: add rawinput joystick --- src/win/Makefile.mingw | 20 +++++++++++--------- src/win/Makefile_ndr.mingw | 20 +++++++++++--------- 2 files changed, 22 insertions(+), 18 deletions(-) diff --git a/src/win/Makefile.mingw b/src/win/Makefile.mingw index a7ad0b8eb..8fce7321b 100644 --- a/src/win/Makefile.mingw +++ b/src/win/Makefile.mingw @@ -196,7 +196,7 @@ ifndef RDP RDP := n endif ifndef DINPUT - DINPUT := n + DINPUT := y endif ifndef OPENAL OPENAL := y @@ -437,10 +437,6 @@ RDPLIB += -lrdp RDPOBJ := rdp.o endif -ifeq ($(DINPUT), y) -OPTS += -DUSE_DINPUT -endif - ifeq ($(DISCORD), y) OPTS += -DUSE_DISCORD RFLAGS += -DUSE_DISCORD @@ -703,7 +699,13 @@ PLATOBJ := win.o \ win_dynld.o win_thread.o \ win_cdrom.o win_keyboard.o \ win_midi.o \ - win_mouse.o win_joystick.o + win_mouse.o + +ifeq ($(DINPUT), y) + PLATOBJ += win_joystick.o +else + PLATOBJ += win_joystick_rawinput.o +endif OBJ := $(MAINOBJ) $(INTELOBJ) $(CPUOBJ) $(CHIPSETOBJ) $(MCHOBJ) \ $(DEVOBJ) $(FDDOBJ) $(CDROMOBJ) $(ZIPOBJ) $(HDDOBJ) \ @@ -729,12 +731,12 @@ endif ifneq ($(WX), n) LIBS += $(WX_LIBS) -lm endif -LIBS += -lpng -lz -lwsock32 -lshell32 -liphlpapi -ldinput8 -lSDL2 -limm32 -lhid -lsetupapi -loleaut32 -lversion -lwinmm -static -lstdc++ +LIBS += -lpng -lz -lwsock32 -lshell32 -liphlpapi -lSDL2 -limm32 -lhid -lsetupapi -loleaut32 -lversion -lwinmm -static -lstdc++ ifneq ($(X64), y) LIBS += -Wl,--large-address-aware endif -ifneq ($(DINPUT), y) - LIBS += -lxinput +ifeq ($(DINPUT), y) + LIBS += -ldinput8 endif LIBS += -static diff --git a/src/win/Makefile_ndr.mingw b/src/win/Makefile_ndr.mingw index 58a79edac..767329dcb 100644 --- a/src/win/Makefile_ndr.mingw +++ b/src/win/Makefile_ndr.mingw @@ -196,7 +196,7 @@ ifndef RDP RDP := n endif ifndef DINPUT - DINPUT := n + DINPUT := y endif ifndef OPENAL OPENAL := y @@ -443,10 +443,6 @@ RDPLIB += -lrdp RDPOBJ := rdp.o endif -ifeq ($(DINPUT), y) -OPTS += -DUSE_DINPUT -endif - ifeq ($(DISCORD), y) OPTS += -DUSE_DISCORD RFLAGS += -DUSE_DISCORD @@ -709,7 +705,13 @@ PLATOBJ := win.o \ win_dynld.o win_thread.o \ win_cdrom.o win_keyboard.o \ win_midi.o \ - win_mouse.o win_joystick.o + win_mouse.o + +ifeq ($(DINPUT), y) + PLATOBJ += win_joystick.o +else + PLATOBJ += win_joystick_rawinput.o +endif OBJ := $(MAINOBJ) $(INTELOBJ) $(CPUOBJ) $(CHIPSETOBJ) $(MCHOBJ) \ $(DEVOBJ) $(FDDOBJ) $(CDROMOBJ) $(ZIPOBJ) $(HDDOBJ) \ @@ -735,12 +737,12 @@ endif ifneq ($(WX), n) LIBS += $(WX_LIBS) -lm endif -LIBS += -lpng -lz -lwsock32 -lshell32 -liphlpapi -ldinput8 -lSDL2 -limm32 -lhid -lsetupapi -loleaut32 -lversion -lwinmm -static -lstdc++ +LIBS += -lpng -lz -lwsock32 -lshell32 -liphlpapi -lSDL2 -limm32 -lhid -lsetupapi -loleaut32 -lversion -lwinmm -static -lstdc++ ifneq ($(X64), y) LIBS += -Wl,--large-address-aware endif -ifneq ($(DINPUT), y) - LIBS += -lxinput +ifeq ($(DINPUT), y) + LIBS += -ldinput8 endif LIBS += -static From b35f5628be0dcf8faef962854978a9a77e13192a Mon Sep 17 00:00:00 2001 From: driver1998 Date: Thu, 27 Feb 2020 01:43:25 +0800 Subject: [PATCH 09/33] prt_escp: fix return value of read_ctrl --- src/printer/prt_escp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/printer/prt_escp.c b/src/printer/prt_escp.c index c74449ba6..2aa922b87 100644 --- a/src/printer/prt_escp.c +++ b/src/printer/prt_escp.c @@ -2006,7 +2006,7 @@ read_ctrl(void *priv) { escp_t *dev = (escp_t *)priv; - return 0xe0 | dev->autofeed ? 0x02 : 0x00 | (dev->ctrl & 0xfd); + return 0xe0 | (dev->autofeed ? 0x02 : 0x00) | (dev->ctrl & 0xfd); } From bf8ff98fd4d5f84cc146c91bd88ed800f1ff85d9 Mon Sep 17 00:00:00 2001 From: driver1998 Date: Thu, 27 Feb 2020 02:00:58 +0800 Subject: [PATCH 10/33] rawinput: fix VID and PID display in device name --- src/win/win_joystick_rawinput.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/win/win_joystick_rawinput.c b/src/win/win_joystick_rawinput.c index 91ef6989f..85e8f31df 100644 --- a/src/win/win_joystick_rawinput.c +++ b/src/win/win_joystick_rawinput.c @@ -227,8 +227,8 @@ void joystick_get_device_name(raw_joystick_t* rawjoy, plat_joystick_t* joy, PRID sprintf(joy->name, "RawInput %s, VID:%04lX PID:%04lX", info->hid.usUsage == HID_USAGE_GENERIC_JOYSTICK ? "Joystick" : "Gamepad", - info->hid.dwProductId, - info->hid.dwVendorId); + info->hid.dwVendorId, + info->hid.dwProductId); } void joystick_init() From 42a3032b931336e42ceae5680e58c90997174482 Mon Sep 17 00:00:00 2001 From: TC1995 Date: Tue, 24 Mar 2020 23:34:36 +0100 Subject: [PATCH 11/33] Apparently the wd80x3 and the rest of PIO-based DP8390 nics don't like to have a common way of receiving/transmitting packets. --- src/network/net_dp8390.c | 22 +++++++++++++++++----- 1 file changed, 17 insertions(+), 5 deletions(-) diff --git a/src/network/net_dp8390.c b/src/network/net_dp8390.c index 4b1fa3edd..1fcee0e87 100644 --- a/src/network/net_dp8390.c +++ b/src/network/net_dp8390.c @@ -204,8 +204,11 @@ dp8390_write_cr(dp8390_t *dev, uint32_t val) /* Check for start-tx */ if ((val & 0x04) && dev->TCR.loop_cntl) { if (dev->TCR.loop_cntl) { - dp8390_rx(dev, dev->mem, - dev->tx_bytes); + if ((dev->flags & DP8390_FLAG_CHECK_CR) || (dev->flags & DP8390_FLAG_EVEN_MAC)) + dp8390_rx(dev, &dev->mem[(dev->tx_page_start * 256) - dev->mem_start], + dev->tx_bytes); + else + dp8390_rx(dev, dev->mem, dev->tx_bytes); } } else if (val & 0x04) { if (dev->CR.stop || (!dev->CR.start && (dev->flags & DP8390_FLAG_CHECK_CR))) { @@ -224,7 +227,10 @@ dp8390_write_cr(dp8390_t *dev, uint32_t val) /* Send the packet to the system driver */ dev->CR.tx_packet = 1; - network_tx(dev->mem, dev->tx_bytes); + if ((dev->flags & DP8390_FLAG_CHECK_CR) || (dev->flags & DP8390_FLAG_EVEN_MAC)) + network_tx(&dev->mem[(dev->tx_page_start * 256) - dev->mem_start], dev->tx_bytes); + else + network_tx(dev->mem, dev->tx_bytes); /* some more debug */ #ifdef ENABLE_DP8390_LOG @@ -388,7 +394,10 @@ dp8390_rx(void *priv, uint8_t *buf, int io_len) pkthdr[0], pkthdr[1], pkthdr[2], pkthdr[3]); /* Copy into buffer, update curpage, and signal interrupt if config'd */ - startptr = dev->mem + ((dev->curr_page * 256) - dev->mem_start); + if ((dev->flags & DP8390_FLAG_CHECK_CR) || (dev->flags & DP8390_FLAG_EVEN_MAC)) + startptr = &dev->mem[(dev->curr_page * 256) - dev->mem_start]; + else + startptr = dev->mem + ((dev->curr_page * 256) - dev->mem_start); memcpy(startptr, pkthdr, sizeof(pkthdr)); if ((nextpage > dev->curr_page) || ((dev->curr_page + pages) == dev->page_stop)) { @@ -396,7 +405,10 @@ dp8390_rx(void *priv, uint8_t *buf, int io_len) } else { endbytes = (dev->page_stop - dev->curr_page) * 256; memcpy(startptr+sizeof(pkthdr), buf, endbytes-sizeof(pkthdr)); - startptr = dev->mem + ((dev->page_start * 256) - dev->mem_start); + if ((dev->flags & DP8390_FLAG_CHECK_CR) || (dev->flags & DP8390_FLAG_EVEN_MAC)) + startptr = &dev->mem[(dev->page_start * 256) - dev->mem_start]; + else + startptr = dev->mem + ((dev->page_start * 256) - dev->mem_start); memcpy(startptr, buf+endbytes-sizeof(pkthdr), io_len-endbytes+8); } dev->curr_page = nextpage; From 4e0a0a1dfd94d32b85c61fd4fd57e8750bda31f3 Mon Sep 17 00:00:00 2001 From: TC1995 Date: Tue, 24 Mar 2020 23:40:20 +0100 Subject: [PATCH 12/33] Fixed proper detection of the 8-bit ISA-based NE1000, as it was previously using NE2000 resources. --- src/network/net_ne2000.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/src/network/net_ne2000.c b/src/network/net_ne2000.c index 8feb13c5c..8701d9344 100644 --- a/src/network/net_ne2000.c +++ b/src/network/net_ne2000.c @@ -1274,16 +1274,20 @@ nic_init(const device_t *info) switch(dev->board) { case NE2K_NE1000: + dev->maclocal[0] = 0x00; /* 00:00:D8 (Novell OID) */ + dev->maclocal[1] = 0x00; + dev->maclocal[2] = 0xD8; dev->is_8bit = 1; + rom = NULL; dp8390_set_defaults(dev->dp8390, DP8390_FLAG_CHECK_CR | DP8390_FLAG_CLEAR_IRQ); dp8390_mem_alloc(dev->dp8390, 0x2000, 0x2000); - /*FALLTHROUGH*/ + break; case NE2K_NE2000: dev->maclocal[0] = 0x00; /* 00:00:D8 (Novell OID) */ dev->maclocal[1] = 0x00; dev->maclocal[2] = 0xD8; - rom = (dev->board == NE2K_NE1000) ? NULL : ROM_PATH_NE2000; + rom = ROM_PATH_NE2000; dp8390_set_defaults(dev->dp8390, DP8390_FLAG_EVEN_MAC | DP8390_FLAG_CHECK_CR | DP8390_FLAG_CLEAR_IRQ); dp8390_mem_alloc(dev->dp8390, 0x4000, 0x4000); From c3eab668444d9d8cfbd6079c7789e64960345b3d Mon Sep 17 00:00:00 2001 From: TC1995 Date: Tue, 24 Mar 2020 23:43:30 +0100 Subject: [PATCH 13/33] Fixed hard reset crashes in the PCnet code. --- src/network/net_pcnet.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/network/net_pcnet.c b/src/network/net_pcnet.c index d2e20acd3..3499df54a 100644 --- a/src/network/net_pcnet.c +++ b/src/network/net_pcnet.c @@ -2835,6 +2835,9 @@ pcnet_close(void *priv) pcnetlog(1, "%s: closed\n", dev->name); + /* Make sure the platform layer is shut down. */ + network_close(); + if (dev) { timer_disable(&dev->poll_timer); From 0c509fd55182b35f266cf01c0d168b30d92255cc Mon Sep 17 00:00:00 2001 From: Daniel Gurney Date: Wed, 25 Mar 2020 00:46:02 +0200 Subject: [PATCH 14/33] Remove version tree-wide --- src/86box.h | 2 +- src/86box_io.h | 2 +- src/apm.c | 2 +- src/apm.h | 2 +- src/apm_new.c | 2 +- src/bugger.c | 2 +- src/bugger.h | 2 +- src/cdrom/cdrom.c | 2 +- src/cdrom/cdrom.h | 2 +- src/cdrom/cdrom_image.c | 2 +- src/cdrom/cdrom_image_backend.c | 2 +- src/cdrom/cdrom_image_backend.h | 2 +- src/chipset/acc2168.c | 2 +- src/chipset/acer_m3a.c | 2 +- src/chipset/ali1429.c | 2 +- src/chipset/chipset.h | 2 +- src/chipset/headland.c | 2 +- src/chipset/intel_4x0.c | 2 +- src/chipset/neat.c | 2 +- src/chipset/scamp.c | 2 +- src/chipset/scat.c | 2 +- src/chipset/sis_85c471.c | 2 +- src/chipset/sis_85c496.c | 2 +- src/chipset/sis_85c50x.c | 2 +- src/chipset/via_mvp3.c | 2 +- src/chipset/wd76c10.c | 2 +- src/config.c | 2 +- src/config.h | 2 +- src/cpu/codegen.h | 2 +- src/cpu/codegen_x86.c | 2 +- src/cpu/x86seg.c | 2 +- src/cpu_common/386_common.h | 2 +- src/cpu_common/386_ops.h | 2 +- src/cpu_common/808x.c | 2 +- src/cpu_common/codegen_public.h | 2 +- src/cpu_common/cpu.c | 2 +- src/cpu_common/cpu.h | 2 +- src/cpu_common/cpu_table - Cópia.c | 2 +- src/cpu_common/cpu_table.c | 2 +- src/cpu_common/x86_ops.h | 2 +- src/cpu_common/x86_ops_amd.h | 2 +- src/cpu_common/x86_ops_i686.h | 2 +- src/cpu_common/x86seg.h | 2 +- src/cpu_common/x87_ops.h | 2 +- src/cpu_common/x87_ops_loadstore.h | 2 +- src/cpu_new/x86seg.c | 2 +- src/device.c | 2 +- src/device.h | 2 +- src/disk/hdc.c | 2 +- src/disk/hdc.h | 2 +- src/disk/hdc_esdi_at.c | 2 +- src/disk/hdc_esdi_mca.c | 2 +- src/disk/hdc_ide.c | 2 +- src/disk/hdc_ide.h | 2 +- src/disk/hdc_ide_sff8038i.c | 2 +- src/disk/hdc_ide_sff8038i.h | 2 +- src/disk/hdc_st506_at.c | 2 +- src/disk/hdc_st506_xt.c | 2 +- src/disk/hdc_xta.c | 2 +- src/disk/hdc_xtide.c | 2 +- src/disk/hdd.c | 2 +- src/disk/hdd.h | 2 +- src/disk/hdd_image.c | 2 +- src/disk/hdd_table.c | 2 +- src/disk/zip.c | 2 +- src/disk/zip.h | 2 +- src/dma.c | 2 +- src/dma.h | 2 +- src/floppy/fdc.c | 2 +- src/floppy/fdc.h | 2 +- src/floppy/fdd.c | 2 +- src/floppy/fdd.h | 2 +- src/floppy/fdd_86f.c | 2 +- src/floppy/fdd_86f.h | 2 +- src/floppy/fdd_common.c | 2 +- src/floppy/fdd_common.h | 2 +- src/floppy/fdd_fdi.c | 2 +- src/floppy/fdd_fdi.h | 2 +- src/floppy/fdd_imd.c | 2 +- src/floppy/fdd_imd.h | 2 +- src/floppy/fdd_img.c | 2 +- src/floppy/fdd_img.h | 2 +- src/floppy/fdd_json.c | 2 +- src/floppy/fdd_json.h | 2 +- src/floppy/fdd_mfm.c | 2 +- src/floppy/fdd_mfm.h | 2 +- src/floppy/fdd_td0.c | 2 +- src/floppy/fdd_td0.h | 2 +- src/floppy/fdi2raw.c | 2 +- src/floppy/fdi2raw.h | 2 +- src/game/gameport.c | 2 +- src/game/gameport.h | 2 +- src/game/joystick_ch_flightstick_pro.c | 2 +- src/game/joystick_ch_flightstick_pro.h | 2 +- src/game/joystick_standard.c | 2 +- src/game/joystick_standard.h | 2 +- src/game/joystick_sw_pad.c | 2 +- src/game/joystick_sw_pad.h | 2 +- src/game/joystick_tm_fcs.c | 2 +- src/game/joystick_tm_fcs.h | 2 +- src/hwm.c | 2 +- src/hwm.h | 2 +- src/hwm_w83781d.c | 2 +- src/ibm_5161.c | 2 +- src/ibm_5161.h | 2 +- src/intel_flash.c | 2 +- src/intel_flash.h | 2 +- src/intel_piix.c | 2 +- src/intel_sio.c | 2 +- src/intel_sio.h | 2 +- src/io.c | 2 +- src/isamem.c | 2 +- src/isamem.h | 2 +- src/isartc.c | 2 +- src/isartc.h | 2 +- src/keyboard.c | 2 +- src/keyboard.h | 2 +- src/keyboard_at.c | 2 +- src/keyboard_xt.c | 2 +- src/lang/language.h | 2 +- src/machine/m_amstrad.c | 2 +- src/machine/m_amstrad.h | 2 +- src/machine/m_at.c | 2 +- src/machine/m_at_286_386sx.c | 2 +- src/machine/m_at_386dx_486.c | 2 +- src/machine/m_at_commodore.c | 2 +- src/machine/m_at_compaq.c | 2 +- src/machine/m_at_socket4_5.c | 2 +- src/machine/m_at_socket7_s7.c | 2 +- src/machine/m_at_socket8.c | 2 +- src/machine/m_at_t3100e.c | 2 +- src/machine/m_at_t3100e.h | 2 +- src/machine/m_at_t3100e_vid.c | 2 +- src/machine/m_europc.c | 2 +- src/machine/m_olivetti_m24.c | 2 +- src/machine/m_pcjr.c | 2 +- src/machine/m_ps1.c | 2 +- src/machine/m_ps1_hdc.c | 2 +- src/machine/m_ps2_mca.c | 2 +- src/machine/m_tandy.c | 2 +- src/machine/m_xt_compaq.c | 2 +- src/machine/m_xt_t1000.c | 2 +- src/machine/m_xt_t1000.h | 2 +- src/machine/m_xt_t1000_vid.c | 2 +- src/machine/m_xt_zenith.c | 2 +- src/machine/machine.c | 2 +- src/machine/machine.h | 2 +- src/machine/machine_table.c | 2 +- src/mem.c | 2 +- src/mem.h | 2 +- src/mouse.c | 2 +- src/mouse.h | 2 +- src/mouse_bus.c | 2 +- src/mouse_ps2.c | 2 +- src/mouse_serial.c | 2 +- src/network/bswap.h | 2 +- src/network/net_3c503.c | 2 +- src/network/net_dp8390.c | 2 +- src/network/net_dp8390.h | 2 +- src/network/net_ne2000.c | 2 +- src/network/net_ne2000.h | 2 +- src/network/net_pcap.c | 2 +- src/network/net_pcnet.c | 2 +- src/network/net_pcnet.h | 2 +- src/network/net_slirp.c | 2 +- src/network/net_wd8003.c | 2 +- src/network/net_wd8003.h | 2 +- src/network/network.c | 2 +- src/network/network.h | 2 +- src/network/pcap_if.c | 2 +- src/nvr.c | 2 +- src/nvr.h | 2 +- src/nvr_at.c | 2 +- src/nvr_ps2.c | 2 +- src/nvr_ps2.h | 2 +- src/pc.c | 2 +- src/pci.c | 2 +- src/pci.h | 2 +- src/pic.c | 2 +- src/piix.h | 2 +- src/pit.c | 2 +- src/pit.h | 2 +- src/plat.h | 2 +- src/plat_dynld.h | 2 +- src/port_92.c | 2 +- src/port_92.h | 2 +- src/postcard.c | 2 +- src/postcard.h | 2 +- src/printer/png.c | 2 +- src/printer/png_struct.h | 2 +- src/printer/printer.h | 2 +- src/printer/prt_cpmap.c | 2 +- src/printer/prt_escp.c | 2 +- src/printer/prt_ps.c | 2 +- src/printer/prt_text.c | 2 +- src/random.c | 2 +- src/random.h | 2 +- src/rom.c | 2 +- src/rom.h | 2 +- src/scsi/scsi.c | 2 +- src/scsi/scsi.h | 2 +- src/scsi/scsi_aha154x.c | 2 +- src/scsi/scsi_buslogic.c | 2 +- src/scsi/scsi_buslogic.h | 2 +- src/scsi/scsi_cdrom.c | 2 +- src/scsi/scsi_cdrom.h | 2 +- src/scsi/scsi_device.c | 2 +- src/scsi/scsi_device.h | 2 +- src/scsi/scsi_disk.c | 2 +- src/scsi/scsi_disk.h | 2 +- src/scsi/scsi_ncr5380.c | 2 +- src/scsi/scsi_ncr5380.h | 2 +- src/scsi/scsi_ncr53c8xx.c | 2 +- src/scsi/scsi_ncr53c8xx.h | 2 +- src/scsi/scsi_spock.c | 2 +- src/scsi/scsi_spock.h | 2 +- src/scsi/scsi_x54x.c | 2 +- src/scsi/scsi_x54x.h | 2 +- src/serial.c | 2 +- src/serial.h | 2 +- src/sio.h | 2 +- src/sio_acc3221.c | 2 +- src/sio_detect.c | 2 +- src/sio_fdc37c669.c | 2 +- src/sio_fdc37c66x.c | 2 +- src/sio_fdc37c67x.c | 2 +- src/sio_fdc37c93x.c | 2 +- src/sio_pc87306.c | 2 +- src/sio_w83787f.c | 2 +- src/sio_w83877f.c | 2 +- src/sio_w83977f.c | 2 +- src/smbus.c | 2 +- src/smbus.h | 2 +- src/sound/midi.c | 2 +- src/sound/openal.c | 2 +- src/sound/snd_mpu401.c | 2 +- src/sound/snd_mpu401.h | 2 +- src/sound/snd_sb.c | 2 +- src/sound/snd_speaker.c | 2 +- src/sound/snd_speaker.h | 2 +- src/sound/snd_wss.c | 2 +- src/sound/sound.c | 2 +- src/sound/sound.h | 2 +- src/sst_flash.c | 2 +- src/sst_flash.h | 2 +- src/ui.h | 2 +- src/via_vt82c586b.c | 2 +- src/via_vt82c586b.h | 2 +- src/video/vid_ati18800.c | 2 +- src/video/vid_ati28800.c | 2 +- src/video/vid_ati68860_ramdac.c | 2 +- src/video/vid_ati_eeprom.c | 2 +- src/video/vid_ati_mach64.c | 2 +- src/video/vid_att20c49x_ramdac.c | 2 +- src/video/vid_av9194.c | 2 +- src/video/vid_bt48x_ramdac.c | 2 +- src/video/vid_cga.c | 2 +- src/video/vid_cga.h | 2 +- src/video/vid_cga_comp.c | 2 +- src/video/vid_cga_comp.h | 2 +- src/video/vid_cl54xx.c | 2 +- src/video/vid_colorplus.c | 2 +- src/video/vid_compaq_cga.c | 2 +- src/video/vid_ega.c | 2 +- src/video/vid_ega.h | 2 +- src/video/vid_ega_render.c | 2 +- src/video/vid_et4000.c | 2 +- src/video/vid_et4000w32.c | 2 +- src/video/vid_genius.c | 2 +- src/video/vid_hercules.c | 2 +- src/video/vid_herculesplus.c | 2 +- src/video/vid_ht216.c | 2 +- src/video/vid_icd2061.c | 2 +- src/video/vid_ics2595.c | 2 +- src/video/vid_im1024.c | 2 +- src/video/vid_incolor.c | 2 +- src/video/vid_mda.c | 2 +- src/video/vid_mga.c | 2 +- src/video/vid_oak_oti.c | 2 +- src/video/vid_paradise.c | 2 +- src/video/vid_pgc.c | 2 +- src/video/vid_pgc.h | 2 +- src/video/vid_pgc_palette.h | 2 +- src/video/vid_s3.c | 2 +- src/video/vid_s3_virge.c | 2 +- src/video/vid_sc1502x_ramdac.c | 2 +- src/video/vid_sdac_ramdac.c | 2 +- src/video/vid_sigma.c | 2 +- src/video/vid_stg_ramdac.c | 2 +- src/video/vid_svga.c | 2 +- src/video/vid_svga.h | 2 +- src/video/vid_svga_render.c | 2 +- src/video/vid_svga_render.h | 2 +- src/video/vid_table.c | 2 +- src/video/vid_tgui9440.c | 2 +- src/video/vid_ti_cf62011.c | 2 +- src/video/vid_tkd8001_ramdac.c | 2 +- src/video/vid_tvga.c | 2 +- src/video/vid_vga.c | 2 +- src/video/vid_voodoo.c | 2 +- src/video/vid_wy700.c | 2 +- src/video/video.c | 2 +- src/video/video.h | 2 +- src/vnc.c | 2 +- src/vnc.h | 2 +- src/vnc_keymap.c | 2 +- src/win/86Box.rc | 2 +- src/win/plat_dir.h | 2 +- src/win/resource.h | 2 +- src/win/win.c | 2 +- src/win/win.h | 2 +- src/win/win_about.c | 2 +- src/win/win_cdrom.c | 2 +- src/win/win_crashdump.c | 2 +- src/win/win_d2d.c | 2 +- src/win/win_d2d.h | 2 +- src/win/win_devconf.c | 2 +- src/win/win_dialog.c | 2 +- src/win/win_discord.c | 2 +- src/win/win_discord.h | 2 +- src/win/win_dynld.c | 2 +- src/win/win_joystick.cpp | 2 +- src/win/win_joystick_xinput.cpp | 2 +- src/win/win_keyboard.c | 2 +- src/win/win_new_floppy.c | 2 +- src/win/win_opendir.c | 2 +- src/win/win_sdl.c | 2 +- src/win/win_sdl.h | 2 +- src/win/win_settings.c | 2 +- src/win/win_snd_gain.c | 2 +- src/win/win_stbar.c | 2 +- src/win/win_thread.c | 2 +- src/win/win_ui.c | 2 +- src/x87_bak/x87_ops.h | 2 +- src/x87_bak/x87_ops_loadstore.h | 2 +- 335 files changed, 335 insertions(+), 335 deletions(-) diff --git a/src/86box.h b/src/86box.h index 30a5088e1..fb351eeb0 100644 --- a/src/86box.h +++ b/src/86box.h @@ -8,7 +8,7 @@ * * Main include file for the application. * - * Version: @(#)86box.h 1.0.37 2020/01/19 + * * * Authors: Miran Grca, *f Fred N. van Kempen, diff --git a/src/86box_io.h b/src/86box_io.h index 93bb3be03..7ec808abf 100644 --- a/src/86box_io.h +++ b/src/86box_io.h @@ -8,7 +8,7 @@ * * Definitions for the I/O handler. * - * Version: @(#)io.h 1.0.1 2017/12/16 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/apm.c b/src/apm.c index 27c33474e..82a6661f0 100644 --- a/src/apm.c +++ b/src/apm.c @@ -8,7 +8,7 @@ * * Advanced Power Management emulation. * - * Version: @(#)apm.c 1.0.0 2019/05/12 + * * * Authors: Miran Grca, * diff --git a/src/apm.h b/src/apm.h index 3f0e34780..5caae9468 100644 --- a/src/apm.h +++ b/src/apm.h @@ -15,7 +15,7 @@ * * Definitions for the Advanced Power Management emulation. * - * Version: @(#)apm.h 1.0.0 2019/05/12 + * * * Authors: Miran Grca, * diff --git a/src/apm_new.c b/src/apm_new.c index 2ae56d82e..3f8385cc3 100644 --- a/src/apm_new.c +++ b/src/apm_new.c @@ -8,7 +8,7 @@ * * Advanced Power Management emulation. * - * Version: @(#)apm.c 1.0.0 2019/05/12 + * * * Authors: Miran Grca, * diff --git a/src/bugger.c b/src/bugger.c index 7205ea25d..f18f0d1a4 100644 --- a/src/bugger.c +++ b/src/bugger.c @@ -44,7 +44,7 @@ * configuration register (CTRL_SPCFG bit set) but have to * remember that stuff first... * - * Version: @(#)bugger.c 1.0.13 2018/10/17 + * * * Author: Fred N. van Kempen, * Copyright 1989-2018 Fred N. van Kempen. diff --git a/src/bugger.h b/src/bugger.h index d3a1ac775..985f13d2f 100644 --- a/src/bugger.h +++ b/src/bugger.h @@ -15,7 +15,7 @@ * * Definitions for the BUGGER card. * - * Version: @(#)bugger.h 1.0.6 2018/03/18 + * * * Author: Fred N. van Kempen, * diff --git a/src/cdrom/cdrom.c b/src/cdrom/cdrom.c index 2b68ff09f..e9655e44d 100644 --- a/src/cdrom/cdrom.c +++ b/src/cdrom/cdrom.c @@ -8,7 +8,7 @@ * * Generic CD-ROM drive core. * - * Version: @(#)cdrom.c 1.0.10 2020/03/23 + * * * Author: Miran Grca, * diff --git a/src/cdrom/cdrom.h b/src/cdrom/cdrom.h index e5b3a948f..0df5d9c77 100644 --- a/src/cdrom/cdrom.h +++ b/src/cdrom/cdrom.h @@ -8,7 +8,7 @@ * * Generic CD-ROM drive core header. * - * Version: @(#)cdrom.h 1.0.18 2019/09/26 + * * * Author: Miran Grca, * diff --git a/src/cdrom/cdrom_image.c b/src/cdrom/cdrom_image.c index 2a4c7b30c..8990ef257 100644 --- a/src/cdrom/cdrom_image.c +++ b/src/cdrom/cdrom_image.c @@ -8,7 +8,7 @@ * * CD-ROM image support. * - * Version: @(#)cdrom_image.c 1.0.11 2019/03/06 + * * * Author: RichardG867, * Miran Grca, diff --git a/src/cdrom/cdrom_image_backend.c b/src/cdrom/cdrom_image_backend.c index c85739b6c..42a8bfe2c 100644 --- a/src/cdrom/cdrom_image_backend.c +++ b/src/cdrom/cdrom_image_backend.c @@ -9,7 +9,7 @@ * CD-ROM image file handling module, translated to C from * cdrom_dosbox.cpp. * - * Version: @(#)cdrom_image_backend.c 1.0.5 2020/01/17 + * * * Authors: Miran Grca, * Fred N. van Kempen, diff --git a/src/cdrom/cdrom_image_backend.h b/src/cdrom/cdrom_image_backend.h index 69a59031c..837a7459d 100644 --- a/src/cdrom/cdrom_image_backend.h +++ b/src/cdrom/cdrom_image_backend.h @@ -9,7 +9,7 @@ * CD-ROM image file handling module header , translated to C * from cdrom_dosbox.h. * - * Version: @(#)cdrom_image_backend.h 1.0.2 2020/01/17 + * * * Authors: Miran Grca, * Fred N. van Kempen, diff --git a/src/chipset/acc2168.c b/src/chipset/acc2168.c index 686301c24..809eafc41 100644 --- a/src/chipset/acc2168.c +++ b/src/chipset/acc2168.c @@ -9,7 +9,7 @@ * Implementation of the ACC 2168 chipset * used by the Packard Bell Legend 760 Supreme (PB410A or PB430). * - * Version: @(#)acc2168.c 1.0.1 2019/10/19 + * * * Authors: Sarah Walker, * diff --git a/src/chipset/acer_m3a.c b/src/chipset/acer_m3a.c index 43c19d6f1..409618076 100644 --- a/src/chipset/acer_m3a.c +++ b/src/chipset/acer_m3a.c @@ -8,7 +8,7 @@ * * Implementation of the Acer M3A and V35N ports EAh and EBh. * - * Version: @(#)acer_m3a.c 1.0.0 2019/05/13 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/chipset/ali1429.c b/src/chipset/ali1429.c index 2f6b8cad1..82a1e1a24 100644 --- a/src/chipset/ali1429.c +++ b/src/chipset/ali1429.c @@ -8,7 +8,7 @@ * * Implementation of the ALi M-1429/1431 chipset. * - * Version: @(#)ali1429.c 1.0.9 2019/10/09 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/chipset/chipset.h b/src/chipset/chipset.h index 9c9b96a2c..61ea87401 100644 --- a/src/chipset/chipset.h +++ b/src/chipset/chipset.h @@ -8,7 +8,7 @@ * * Handling of the emulated chipsets. * - * Version: @(#)machine.h 1.0.2 2020/01/24 + * * * Authors: Miran Grca, * diff --git a/src/chipset/headland.c b/src/chipset/headland.c index d3f1f4081..75eb066bb 100644 --- a/src/chipset/headland.c +++ b/src/chipset/headland.c @@ -8,7 +8,7 @@ * * Implementation of the HEADLAND AT286 chipset. * - * Version: @(#)headland.c 1.0.1 2019/10/19 + * * * Authors: Sarah Walker, * Fred N. van Kempen, diff --git a/src/chipset/intel_4x0.c b/src/chipset/intel_4x0.c index 3a711ba3d..9bccbf235 100644 --- a/src/chipset/intel_4x0.c +++ b/src/chipset/intel_4x0.c @@ -8,7 +8,7 @@ * * Implementation of the Intel PCISet chips from 420TX to 440FX. * - * Version: @(#)intel_4x0.c 1.0.3 2020/01/24 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/chipset/neat.c b/src/chipset/neat.c index dc2798813..0bbb02990 100644 --- a/src/chipset/neat.c +++ b/src/chipset/neat.c @@ -13,7 +13,7 @@ * 8MB of DRAM chips', because it works fine with bus-based * memory expansion. * - * Version: @(#)m_at_neat.c 1.0.5 2018/10/22 + * * * Author: Fred N. van Kempen, * diff --git a/src/chipset/scamp.c b/src/chipset/scamp.c index c6f3619c3..f22b4c607 100644 --- a/src/chipset/scamp.c +++ b/src/chipset/scamp.c @@ -13,7 +13,7 @@ * 8MB of DRAM chips', because it works fine with bus-based * memory expansion. * - * Version: @(#)scamp.c 1.0.1 2020/01/22 + * * * Authors: Sarah Walker, * diff --git a/src/chipset/scat.c b/src/chipset/scat.c index a9b668141..d5a29ed89 100644 --- a/src/chipset/scat.c +++ b/src/chipset/scat.c @@ -10,7 +10,7 @@ * * Re-worked version based on the 82C235 datasheet and errata. * - * Version: @(#)scat.c 1.0.1 2019/10/19 + * * * Authors: Original by GreatPsycho for PCem. * Fred N. van Kempen, diff --git a/src/chipset/sis_85c471.c b/src/chipset/sis_85c471.c index d28d824c1..0212a4854 100644 --- a/src/chipset/sis_85c471.c +++ b/src/chipset/sis_85c471.c @@ -11,7 +11,7 @@ * SiS sis85c471 Super I/O Chip * Used by DTK PKM-0038S E-2 * - * Version: @(#)sis_85c471.c 1.0.2 2019/10/21 + * * * Authors: Miran Grca, * diff --git a/src/chipset/sis_85c496.c b/src/chipset/sis_85c496.c index 607178fb9..a43925cbc 100644 --- a/src/chipset/sis_85c496.c +++ b/src/chipset/sis_85c496.c @@ -8,7 +8,7 @@ * * Implementation of the SiS 85c496/85c497 chip. * - * Version: @(#)sis_85c496.c 1.0.2 2019/10/21 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/chipset/sis_85c50x.c b/src/chipset/sis_85c50x.c index 605799e17..7b2b13e48 100644 --- a/src/chipset/sis_85c50x.c +++ b/src/chipset/sis_85c50x.c @@ -8,7 +8,7 @@ * * Implementation of the SiS 85c501/85c503 chip. * - * Version: @(#)sis_85c50x.c 1.0.1 2019/10/19 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/chipset/via_mvp3.c b/src/chipset/via_mvp3.c index cdbcc17d1..084889c33 100644 --- a/src/chipset/via_mvp3.c +++ b/src/chipset/via_mvp3.c @@ -8,7 +8,7 @@ * * Implementation of the VIA MVP3 chip. * - * Version: @(#)via_mvp3.c 1.0.1 2019/10/19 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/chipset/wd76c10.c b/src/chipset/wd76c10.c index f01290e65..6264105f2 100644 --- a/src/chipset/wd76c10.c +++ b/src/chipset/wd76c10.c @@ -8,7 +8,7 @@ * * Implementation of the WD76C10 System Controller chip. * - * Version: @(#)wd76c10.c 1.0.1 2019/10/19 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/config.c b/src/config.c index 6daa573aa..450727344 100644 --- a/src/config.c +++ b/src/config.c @@ -8,7 +8,7 @@ * * Configuration file handler. * - * Version: @(#)config.c 1.0.66 2019/12/21 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/config.h b/src/config.h index a3abf7f74..969bc2489 100644 --- a/src/config.h +++ b/src/config.h @@ -8,7 +8,7 @@ * * Configuration file handler header. * - * Version: @(#)config.h 1.0.6 2017/12/03 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/cpu/codegen.h b/src/cpu/codegen.h index f7c41f849..559149316 100644 --- a/src/cpu/codegen.h +++ b/src/cpu/codegen.h @@ -8,7 +8,7 @@ * * Definitions for the code generator. * - * Version: @(#)codegen.h 1.0.2 2018/03/14 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/cpu/codegen_x86.c b/src/cpu/codegen_x86.c index b6fd2a49b..9e240b690 100644 --- a/src/cpu/codegen_x86.c +++ b/src/cpu/codegen_x86.c @@ -8,7 +8,7 @@ * * Dynamic Recompiler for Intel 32-bit systems. * - * Version: @(#)codegen_x86.c 1.0.3 2018/05/05 + * * * Authors: Fred N. van Kempen, * Sarah Walker, diff --git a/src/cpu/x86seg.c b/src/cpu/x86seg.c index ced052ea0..01a846118 100644 --- a/src/cpu/x86seg.c +++ b/src/cpu/x86seg.c @@ -8,7 +8,7 @@ * * x86 CPU segment emulation. * - * Version: @(#)x86seg.c 1.0.9 2018/11/14 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/cpu_common/386_common.h b/src/cpu_common/386_common.h index 2ab8157a2..c57241e2d 100644 --- a/src/cpu_common/386_common.h +++ b/src/cpu_common/386_common.h @@ -8,7 +8,7 @@ * * Common 386 CPU code. * - * Version: @(#)386_common.h 1.0.1 2019/02/19 + * * * Author: Sarah Walker, * Miran Grca, diff --git a/src/cpu_common/386_ops.h b/src/cpu_common/386_ops.h index 8459607ff..41435393b 100644 --- a/src/cpu_common/386_ops.h +++ b/src/cpu_common/386_ops.h @@ -8,7 +8,7 @@ * * 286/386+ instruction handlers list. * - * Version: @(#)386_ops.h 1.0.5 2018/10/17 + * * * Authors: Fred N. van Kempen, * Sarah Walker, diff --git a/src/cpu_common/808x.c b/src/cpu_common/808x.c index ede1412cd..abee70e26 100644 --- a/src/cpu_common/808x.c +++ b/src/cpu_common/808x.c @@ -9,7 +9,7 @@ * 808x CPU emulation, mostly ported from reenigne's XTCE, which * is cycle-accurate. * - * Version: @(#)808x.c 1.0.11 2019/10/21 + * * * Authors: Andrew Jenner, * Miran Grca, diff --git a/src/cpu_common/codegen_public.h b/src/cpu_common/codegen_public.h index e5ca4b33e..868bc41ab 100644 --- a/src/cpu_common/codegen_public.h +++ b/src/cpu_common/codegen_public.h @@ -8,7 +8,7 @@ * * Definitions for the code generator. * - * Version: @(#)codegen_public.h 1.0.0 2020/01/27 + * * * Authors: Miran Grca, * diff --git a/src/cpu_common/cpu.c b/src/cpu_common/cpu.c index 43e8a7adb..1cd856236 100644 --- a/src/cpu_common/cpu.c +++ b/src/cpu_common/cpu.c @@ -8,7 +8,7 @@ * * CPU type handler. * - * Version: @(#)cpu.c 1.0.6 2018/05/05 + * * * Authors: Fred N. van Kempen, * Sarah Walker, diff --git a/src/cpu_common/cpu.h b/src/cpu_common/cpu.h index 3672486f5..4f164f748 100644 --- a/src/cpu_common/cpu.h +++ b/src/cpu_common/cpu.h @@ -8,7 +8,7 @@ * * CPU type handler. * - * Version: @(#)cpu.h 1.0.13 2018/11/14 + * * * Authors: Sarah Walker, * leilei, diff --git a/src/cpu_common/cpu_table - Cópia.c b/src/cpu_common/cpu_table - Cópia.c index 2c5676023..16121561a 100644 --- a/src/cpu_common/cpu_table - Cópia.c +++ b/src/cpu_common/cpu_table - Cópia.c @@ -29,7 +29,7 @@ * 16 = 180 MHz * 17 = 200 MHz * - * Version: @(#)cpu_table.c 1.0.7 2019/10/21 + * * * Authors: Sarah Walker, * leilei, diff --git a/src/cpu_common/cpu_table.c b/src/cpu_common/cpu_table.c index f8422126b..3903317dc 100644 --- a/src/cpu_common/cpu_table.c +++ b/src/cpu_common/cpu_table.c @@ -29,7 +29,7 @@ * 16 = 180 MHz * 17 = 200 MHz * - * Version: @(#)cpu_table.c 1.0.7 2019/10/21 + * * * Authors: Sarah Walker, * leilei, diff --git a/src/cpu_common/x86_ops.h b/src/cpu_common/x86_ops.h index 34d1bcb24..cf192f79e 100644 --- a/src/cpu_common/x86_ops.h +++ b/src/cpu_common/x86_ops.h @@ -8,7 +8,7 @@ * * Miscellaneous x86 CPU Instructions. * - * Version: @(#)x86_ops.h 1.0.2 2018/05/05 + * * * Authors: Fred N. van Kempen, * Sarah Walker, diff --git a/src/cpu_common/x86_ops_amd.h b/src/cpu_common/x86_ops_amd.h index 8f003e1fb..aa42c3d8e 100644 --- a/src/cpu_common/x86_ops_amd.h +++ b/src/cpu_common/x86_ops_amd.h @@ -8,7 +8,7 @@ * * AMD SYSCALL and SYSRET CPU Instructions. * - * Version: @(#)x86_ops_amd.h 1.0.4 2018/10/17 + * * * Author: Miran Grca, * Copyright 2016-2018 Miran Grca. diff --git a/src/cpu_common/x86_ops_i686.h b/src/cpu_common/x86_ops_i686.h index 2b34e0822..ad0fb946e 100644 --- a/src/cpu_common/x86_ops_i686.h +++ b/src/cpu_common/x86_ops_i686.h @@ -8,7 +8,7 @@ * * x86 i686 (Pentium Pro/Pentium II) CPU Instructions. * - * Version: @(#)x86_ops_i686.h 1.0.6 2020/01/27 + * * * Author: Miran Grca, * Copyright 2016-2020 Miran Grca. diff --git a/src/cpu_common/x86seg.h b/src/cpu_common/x86seg.h index 4f12a8d65..d740f9cea 100644 --- a/src/cpu_common/x86seg.h +++ b/src/cpu_common/x86seg.h @@ -8,7 +8,7 @@ * * x86 CPU segment emulation. * - * Version: @(#)x86seg.h 1.0.1 2017/10/12 + * * * Author: Miran Grca, * diff --git a/src/cpu_common/x87_ops.h b/src/cpu_common/x87_ops.h index 239b449f2..1cb50a9fc 100644 --- a/src/cpu_common/x87_ops.h +++ b/src/cpu_common/x87_ops.h @@ -8,7 +8,7 @@ * * x87 FPU instructions core. * - * Version: @(#)x87_ops.h 1.0.8 2019/06/11 + * * * Authors: Fred N. van Kempen, * Sarah Walker, diff --git a/src/cpu_common/x87_ops_loadstore.h b/src/cpu_common/x87_ops_loadstore.h index b5ad491f9..925fe87bd 100644 --- a/src/cpu_common/x87_ops_loadstore.h +++ b/src/cpu_common/x87_ops_loadstore.h @@ -8,7 +8,7 @@ * * x87 FPU instructions core. * - * Version: @(#)x87_ops_loadstore.h 1.0.2 2019/06/11 + * * * Author: Sarah Walker, * Miran Grca, diff --git a/src/cpu_new/x86seg.c b/src/cpu_new/x86seg.c index 12ad3753b..86eaafd00 100644 --- a/src/cpu_new/x86seg.c +++ b/src/cpu_new/x86seg.c @@ -8,7 +8,7 @@ * * x86 CPU segment emulation. * - * Version: @(#)x86seg.c 1.0.9 2018/11/14 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/device.c b/src/device.c index dddf24551..fa4f0cd8d 100644 --- a/src/device.c +++ b/src/device.c @@ -9,7 +9,7 @@ * Implementation of the generic device interface to handle * all devices attached to the emulator. * - * Version: @(#)device.c 1.0.24 2019/03/014 + * * * Authors: Fred N. van Kempen, * Miran Grca, diff --git a/src/device.h b/src/device.h index dbf9976a2..ecfb5bc59 100644 --- a/src/device.h +++ b/src/device.h @@ -8,7 +8,7 @@ * * Definitions for the device handler. * - * Version: @(#)device.h 1.0.12 2019/03/14 + * * * Authors: Fred N. van Kempen, * Miran Grca, diff --git a/src/disk/hdc.c b/src/disk/hdc.c index f6ed1ae35..ba3678670 100644 --- a/src/disk/hdc.c +++ b/src/disk/hdc.c @@ -8,7 +8,7 @@ * * Common code to handle all sorts of disk controllers. * - * Version: @(#)hdc.c 1.0.17 2018/11/18 + * * * Authors: Miran Grca, * Fred N. van Kempen, diff --git a/src/disk/hdc.h b/src/disk/hdc.h index c5e8d624c..10bf2885a 100644 --- a/src/disk/hdc.h +++ b/src/disk/hdc.h @@ -8,7 +8,7 @@ * * Definitions for the common disk controller handler. * - * Version: @(#)hdc.h 1.0.11 2019/03/03 + * * * Authors: Miran Grca, * Fred N. van Kempen, diff --git a/src/disk/hdc_esdi_at.c b/src/disk/hdc_esdi_at.c index 91f1071a4..ba549104c 100644 --- a/src/disk/hdc_esdi_at.c +++ b/src/disk/hdc_esdi_at.c @@ -8,7 +8,7 @@ * * Driver for the ESDI controller (WD1007-vse1) for PC/AT. * - * Version: @(#)hdc_esdi_at.c 1.0.15 2018/10/31 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/disk/hdc_esdi_mca.c b/src/disk/hdc_esdi_mca.c index c3438e8dd..b1f04c0f6 100644 --- a/src/disk/hdc_esdi_mca.c +++ b/src/disk/hdc_esdi_mca.c @@ -52,7 +52,7 @@ * however, are auto-configured by the system software as * shown above. * - * Version: @(#)hdc_esdi_mca.c 1.0.14 2018/10/17 + * * * Authors: Sarah Walker, * Fred N. van Kempen, diff --git a/src/disk/hdc_ide.c b/src/disk/hdc_ide.c index 3e6c4a6f1..a91f7a221 100644 --- a/src/disk/hdc_ide.c +++ b/src/disk/hdc_ide.c @@ -9,7 +9,7 @@ * Implementation of the IDE emulation for hard disks and ATAPI * CD-ROM devices. * - * Version: @(#)hdc_ide.c 1.0.66 2020/01/14 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/disk/hdc_ide.h b/src/disk/hdc_ide.h index b1e172748..954d11971 100644 --- a/src/disk/hdc_ide.h +++ b/src/disk/hdc_ide.h @@ -9,7 +9,7 @@ * Implementation of the IDE emulation for hard disks and ATAPI * CD-ROM devices. * - * Version: @(#)hdd_ide.h 1.0.16 2019/11/19 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/disk/hdc_ide_sff8038i.c b/src/disk/hdc_ide_sff8038i.c index 5e2b19e8d..9d7841e40 100644 --- a/src/disk/hdc_ide_sff8038i.c +++ b/src/disk/hdc_ide_sff8038i.c @@ -10,7 +10,7 @@ * word 0 - base address * word 1 - bits 1-15 = byte count, bit 31 = end of transfer * - * Version: @(#)hdc_ide_sff8038i.c 1.0.1 2020/01/14 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/disk/hdc_ide_sff8038i.h b/src/disk/hdc_ide_sff8038i.h index bad14a7c6..72a68a6ba 100644 --- a/src/disk/hdc_ide_sff8038i.h +++ b/src/disk/hdc_ide_sff8038i.h @@ -8,7 +8,7 @@ * * Emulation core dispatcher. * - * Version: @(#)hdc_ide_sff8038i.h 1.0.2 2020/01/26 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/disk/hdc_st506_at.c b/src/disk/hdc_st506_at.c index 8f29d4fa4..7b2ac579c 100644 --- a/src/disk/hdc_st506_at.c +++ b/src/disk/hdc_st506_at.c @@ -12,7 +12,7 @@ * based design. Most cards were WD1003-WA2 or -WAH, where the * -WA2 cards had a floppy controller as well (to save space.) * - * Version: @(#)hdc_st506_at.c 1.0.21 2019/11/01 + * * * Authors: Sarah Walker, * Fred N. van Kempen, diff --git a/src/disk/hdc_st506_xt.c b/src/disk/hdc_st506_xt.c index f096879c6..0f56ed35c 100644 --- a/src/disk/hdc_st506_xt.c +++ b/src/disk/hdc_st506_xt.c @@ -41,7 +41,7 @@ * Since all controllers (including the ones made by DTC) use * (mostly) the same API, we keep them all in this module. * - * Version: @(#)hdc_st506_xt.c 1.0.17 2019/10/20 + * * * Authors: Fred N. van Kempen, * Sarah Walker, diff --git a/src/disk/hdc_xta.c b/src/disk/hdc_xta.c index 9a3d57186..20e47e434 100644 --- a/src/disk/hdc_xta.c +++ b/src/disk/hdc_xta.c @@ -46,7 +46,7 @@ * * NOTE: The XTA interface is 0-based for sector numbers !! * - * Version: @(#)hdc_ide_xta.c 1.0.9 2018/10/17 + * * * Author: Fred N. van Kempen, * diff --git a/src/disk/hdc_xtide.c b/src/disk/hdc_xtide.c index 26ef50cb8..d46bd65b0 100644 --- a/src/disk/hdc_xtide.c +++ b/src/disk/hdc_xtide.c @@ -21,7 +21,7 @@ * already on their way out, the newer IDE standard based on the * PC/AT controller and 16b design became the IDE we now know. * - * Version: @(#)hdc_xtide.c 1.0.13 2018/04/26 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/disk/hdd.c b/src/disk/hdd.c index 6163e8e06..353d43672 100644 --- a/src/disk/hdd.c +++ b/src/disk/hdd.c @@ -8,7 +8,7 @@ * * Common code to handle all sorts of hard disk images. * - * Version: @(#)hdd.c 1.0.10 2019/09/26 + * * * Authors: Miran Grca, * Fred N. van Kempen, diff --git a/src/disk/hdd.h b/src/disk/hdd.h index 0ff451f42..08f3a4c77 100644 --- a/src/disk/hdd.h +++ b/src/disk/hdd.h @@ -8,7 +8,7 @@ * * Definitions for the hard disk image handler. * - * Version: @(#)hdd.h 1.0.8 2018/10/28 + * * * Authors: Miran Grca, * Fred N. van Kempen, diff --git a/src/disk/hdd_image.c b/src/disk/hdd_image.c index 7002c0634..fdb1a14a2 100644 --- a/src/disk/hdd_image.c +++ b/src/disk/hdd_image.c @@ -8,7 +8,7 @@ * * Handling of hard disk image files. * - * Version: @(#)hdd_image.c 1.0.20 2018/10/28 + * * * Authors: Miran Grca, * Fred N. van Kempen, diff --git a/src/disk/hdd_table.c b/src/disk/hdd_table.c index 7a68fdb99..b9152ce9d 100644 --- a/src/disk/hdd_table.c +++ b/src/disk/hdd_table.c @@ -9,7 +9,7 @@ * Implementation of the IDE emulation for hard disks and ATAPI * CD-ROM devices. * - * Version: @(#)hdd_table.c 1.0.5 2018/04/08 + * * * Authors: Miran Grca, * Fred N. van Kempen, diff --git a/src/disk/zip.c b/src/disk/zip.c index 429c68dab..52985b07d 100644 --- a/src/disk/zip.c +++ b/src/disk/zip.c @@ -9,7 +9,7 @@ * Implementation of the Iomega ZIP drive with SCSI(-like) * commands, for both ATAPI and SCSI usage. * - * Version: @(#)zip.c 1.0.38 2019/11/19 + * * * Author: Miran Grca, * diff --git a/src/disk/zip.h b/src/disk/zip.h index 02c355472..e0f577762 100644 --- a/src/disk/zip.h +++ b/src/disk/zip.h @@ -9,7 +9,7 @@ * Implementation of the Iomega ZIP drive with SCSI(-like) * commands, for both ATAPI and SCSI usage. * - * Version: @(#)zip.h 1.0.10 2019/11/19 + * * * Author: Miran Grca, * diff --git a/src/dma.c b/src/dma.c index 802c0e836..33ddaf10a 100644 --- a/src/dma.c +++ b/src/dma.c @@ -8,7 +8,7 @@ * * Implementation of the Intel DMA controllers. * - * Version: @(#)dma.c 1.0.9 2020/01/26 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/dma.h b/src/dma.h index 7761107f1..fb08912d2 100644 --- a/src/dma.h +++ b/src/dma.h @@ -8,7 +8,7 @@ * * Definitions for the Intel DMA controller. * - * Version: @(#)dma.h 1.0.4 2020/01/26 + * * * Authors: Fred N. van Kempen, * Miran Grca, diff --git a/src/floppy/fdc.c b/src/floppy/fdc.c index d4eebc796..2dab22dcb 100644 --- a/src/floppy/fdc.c +++ b/src/floppy/fdc.c @@ -9,7 +9,7 @@ * Implementation of the NEC uPD-765 and compatible floppy disk * controller. * - * Version: @(#)fdc.c 1.0.22 2020/01/24 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/floppy/fdc.h b/src/floppy/fdc.h index 4fae14c62..cae83896a 100644 --- a/src/floppy/fdc.h +++ b/src/floppy/fdc.h @@ -9,7 +9,7 @@ * Implementation of the NEC uPD-765 and compatible floppy disk * controller. * - * Version: @(#)fdc.h 1.0.9 2020/01/24 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/floppy/fdd.c b/src/floppy/fdd.c index 37f100002..af6c72bfd 100644 --- a/src/floppy/fdd.c +++ b/src/floppy/fdd.c @@ -8,7 +8,7 @@ * * Implementation of the floppy drive emulation. * - * Version: @(#)fdd.c 1.0.15 2019/10/20 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/floppy/fdd.h b/src/floppy/fdd.h index 149d06378..b486b617d 100644 --- a/src/floppy/fdd.h +++ b/src/floppy/fdd.h @@ -8,7 +8,7 @@ * * Definitions for the floppy drive emulation. * - * Version: @(#)fdd.h 1.0.7 2019/12/05 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/floppy/fdd_86f.c b/src/floppy/fdd_86f.c index 8eb4d0f42..c74c1fe61 100644 --- a/src/floppy/fdd_86f.c +++ b/src/floppy/fdd_86f.c @@ -10,7 +10,7 @@ * data in the form of FM/MFM-encoded transitions) which also * forms the core of the emulator's floppy disk emulation. * - * Version: @(#)fdd_86f.c 1.0.20 2019/12/06 + * * * Authors: Miran Grca, * Fred N. van Kempen, diff --git a/src/floppy/fdd_86f.h b/src/floppy/fdd_86f.h index ced699711..0b8e5c76c 100644 --- a/src/floppy/fdd_86f.h +++ b/src/floppy/fdd_86f.h @@ -8,7 +8,7 @@ * * Definitions for the 86F floppy image format. * - * Version: @(#)floppy_86f.h 1.0.6 2019/12/05 + * * * Authors: Miran Grca, * Fred N. van Kempen, diff --git a/src/floppy/fdd_common.c b/src/floppy/fdd_common.c index 3ad3db4aa..64e64f349 100644 --- a/src/floppy/fdd_common.c +++ b/src/floppy/fdd_common.c @@ -8,7 +8,7 @@ * * Shared code for all the floppy modules. * - * Version: @(#)fdd_common.c 1.0.2 2018/03/16 + * * * Author: Fred N. van Kempen, * diff --git a/src/floppy/fdd_common.h b/src/floppy/fdd_common.h index 509fdfa7d..e904aaaa6 100644 --- a/src/floppy/fdd_common.h +++ b/src/floppy/fdd_common.h @@ -8,7 +8,7 @@ * * Shared code for all the floppy modules. * - * Version: @(#)fdd_common.h 1.0.2 2018/03/16 + * * * Author: Fred N. van Kempen, * diff --git a/src/floppy/fdd_fdi.c b/src/floppy/fdd_fdi.c index 04315377a..dc9c85d85 100644 --- a/src/floppy/fdd_fdi.c +++ b/src/floppy/fdd_fdi.c @@ -9,7 +9,7 @@ * Implementation of the FDI floppy stream image format * interface to the FDI2RAW module. * - * Version: @(#)fdd_fdi.c 1.0.4 2018/10/18 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/floppy/fdd_fdi.h b/src/floppy/fdd_fdi.h index 9e3f258a4..80c5be202 100644 --- a/src/floppy/fdd_fdi.h +++ b/src/floppy/fdd_fdi.h @@ -9,7 +9,7 @@ * Implementation of the FDI floppy stream image format * interface to the FDI2RAW module. * - * Version: @(#)floppy_fdi.h 1.0.2 2018/03/17 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/floppy/fdd_imd.c b/src/floppy/fdd_imd.c index 14078ee01..20d343a77 100644 --- a/src/floppy/fdd_imd.c +++ b/src/floppy/fdd_imd.c @@ -8,7 +8,7 @@ * * Implementation of the IMD floppy image format. * - * Version: @(#)fdd_imd.c 1.0.9 2019/12/05 + * * * Authors: Fred N. van Kempen, * Miran Grca, diff --git a/src/floppy/fdd_imd.h b/src/floppy/fdd_imd.h index 02363a64a..23c346d9d 100644 --- a/src/floppy/fdd_imd.h +++ b/src/floppy/fdd_imd.h @@ -8,7 +8,7 @@ * * Definitions for the IMD floppy image format. * - * Version: @(#)floppy_imd.h 1.0.2 2018/03/17 + * * * Authors: Miran Grca, * Fred N. van Kempen, diff --git a/src/floppy/fdd_img.c b/src/floppy/fdd_img.c index 54039a320..25e008c04 100644 --- a/src/floppy/fdd_img.c +++ b/src/floppy/fdd_img.c @@ -13,7 +13,7 @@ * re-merged with the other files. Much of it is generic to * all formats. * - * Version: @(#)fdd_img.c 1.0.10 2018/12/05 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/floppy/fdd_img.h b/src/floppy/fdd_img.h index dde817dab..cbfff4d3a 100644 --- a/src/floppy/fdd_img.h +++ b/src/floppy/fdd_img.h @@ -9,7 +9,7 @@ * Implementation of the raw sector-based floppy image format, * as well as the Japanese FDI, CopyQM, and FDF formats. * - * Version: @(#)floppy_img.h 1.0.2 2018/03/17 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/floppy/fdd_json.c b/src/floppy/fdd_json.c index 9b96f0c3b..dc17448db 100644 --- a/src/floppy/fdd_json.c +++ b/src/floppy/fdd_json.c @@ -8,7 +8,7 @@ * * Implementation of the PCjs JSON floppy image format. * - * Version: @(#)fdd_json.c 1.0.7 2019/12/05 + * * * Author: Fred N. van Kempen, * diff --git a/src/floppy/fdd_json.h b/src/floppy/fdd_json.h index 0df9dab7d..8ae1c7094 100644 --- a/src/floppy/fdd_json.h +++ b/src/floppy/fdd_json.h @@ -8,7 +8,7 @@ * * Definitions for the PCjs JSON floppy image format. * - * Version: @(#)floppy_json.h 1.0.2 2018/03/17 + * * * Author: Fred N. van Kempen, * diff --git a/src/floppy/fdd_mfm.c b/src/floppy/fdd_mfm.c index 13d9e88a0..19e9232de 100644 --- a/src/floppy/fdd_mfm.c +++ b/src/floppy/fdd_mfm.c @@ -8,7 +8,7 @@ * * Implementation of the HxC MFM image format. * - * Version: @(#)fdd_mfm.c 1.0.2 2019/12/05 + * * * Authors: Miran Grca, * diff --git a/src/floppy/fdd_mfm.h b/src/floppy/fdd_mfm.h index 2aba3fb47..9ed2a333e 100644 --- a/src/floppy/fdd_mfm.h +++ b/src/floppy/fdd_mfm.h @@ -8,7 +8,7 @@ * * Implementation of the HxC MFM image format. * - * Version: @(#)fdd_mfm.h 1.0.0 2018/11/12 + * * * Authors: Miran Grca, * diff --git a/src/floppy/fdd_td0.c b/src/floppy/fdd_td0.c index b7517f437..0d5d8567c 100644 --- a/src/floppy/fdd_td0.c +++ b/src/floppy/fdd_td0.c @@ -8,7 +8,7 @@ * * Implementation of the Teledisk floppy image format. * - * Version: @(#)fdd_td0.c 1.0.10 2019/12/06 + * * * Authors: Milodrag Milanovic, * Haruhiko OKUMURA, diff --git a/src/floppy/fdd_td0.h b/src/floppy/fdd_td0.h index e5a3525b9..305968517 100644 --- a/src/floppy/fdd_td0.h +++ b/src/floppy/fdd_td0.h @@ -8,7 +8,7 @@ * * Definitions for the Teledisk floppy image format. * - * Version: @(#)floppy_td0.h 1.0.2 2018/03/17 + * * * Authors: Miran Grca, * Fred N. van Kempen, diff --git a/src/floppy/fdi2raw.c b/src/floppy/fdi2raw.c index bf54babfb..52bcb3d82 100644 --- a/src/floppy/fdi2raw.c +++ b/src/floppy/fdi2raw.c @@ -12,7 +12,7 @@ * addition of get_last_head and C++ callability by Thomas * Harte. * - * Version: @(#)fdi2raw.c 1.0.4 2018/10/18 + * * * Authors: Toni Wilen, * and Vincent Joguin, diff --git a/src/floppy/fdi2raw.h b/src/floppy/fdi2raw.h index b00dfd5de..8f71679a8 100644 --- a/src/floppy/fdi2raw.h +++ b/src/floppy/fdi2raw.h @@ -8,7 +8,7 @@ * * Definitions for the FDI floppy file format. * - * Version: @(#)fdi2raw.h 1.0.1 2018/02/14 + * * * Authors: Toni Wilen, * and Vincent Joguin, diff --git a/src/game/gameport.c b/src/game/gameport.c index f2c545a26..ecdf5e0d7 100644 --- a/src/game/gameport.c +++ b/src/game/gameport.c @@ -8,7 +8,7 @@ * * Implementation of a generic Game Port. * - * Version: @(#)gameport.c 1.0.6 2018/04/29 + * * * Authors: Miran Grca, * Sarah Walker, diff --git a/src/game/gameport.h b/src/game/gameport.h index 0ef53921d..a91a26232 100644 --- a/src/game/gameport.h +++ b/src/game/gameport.h @@ -10,7 +10,7 @@ * * NOTE: This module needs a good cleanup someday. * - * Version: @(#)gameport.h 1.0.4 2018/11/11 + * * * Authors: Miran Grca, * Sarah Walker, diff --git a/src/game/joystick_ch_flightstick_pro.c b/src/game/joystick_ch_flightstick_pro.c index 5b7b99da8..9a2754c73 100644 --- a/src/game/joystick_ch_flightstick_pro.c +++ b/src/game/joystick_ch_flightstick_pro.c @@ -8,7 +8,7 @@ * * Implementation of the Flight Stick Pro. * - * Version: @(#)flightstick_pro.c 1.0.4 2018/03/15 + * * * Authors: Miran Grca, * Sarah Walker, diff --git a/src/game/joystick_ch_flightstick_pro.h b/src/game/joystick_ch_flightstick_pro.h index 7cbb71767..1358f9d69 100644 --- a/src/game/joystick_ch_flightstick_pro.h +++ b/src/game/joystick_ch_flightstick_pro.h @@ -8,7 +8,7 @@ * * Definitions for the Flight Stick Pro driver. * - * Version: @(#)joystick_ch_flightstickpro.h 1.0.2 2018/03/15 + * * * Authors: Miran Grca, * Sarah Walker, diff --git a/src/game/joystick_standard.c b/src/game/joystick_standard.c index 29b31f590..570f614a9 100644 --- a/src/game/joystick_standard.c +++ b/src/game/joystick_standard.c @@ -8,7 +8,7 @@ * * Implementation of a standard joystick. * - * Version: @(#)joystick_standard.c 1.0.4 2018/03/15 + * * * Authors: Miran Grca, * Sarah Walker, diff --git a/src/game/joystick_standard.h b/src/game/joystick_standard.h index 4aa593f0d..eb35c384b 100644 --- a/src/game/joystick_standard.h +++ b/src/game/joystick_standard.h @@ -8,7 +8,7 @@ * * Definitions for the joystick driver. * - * Version: @(#)joystick_standard.h 1.0.2 2018/03/15 + * * * Authors: Miran Grca, * Sarah Walker, diff --git a/src/game/joystick_sw_pad.c b/src/game/joystick_sw_pad.c index 5a8c0d284..7d98f547a 100644 --- a/src/game/joystick_sw_pad.c +++ b/src/game/joystick_sw_pad.c @@ -29,7 +29,7 @@ * - Some DOS stuff will write to 0x201 while a packet is * being transferred. This seems to be ignored. * - * Version: @(#)sw_pad.c 1.0.5 2018/03/15 + * * * Authors: Miran Grca, * Sarah Walker, diff --git a/src/game/joystick_sw_pad.h b/src/game/joystick_sw_pad.h index 0cd4132a5..2f62aab19 100644 --- a/src/game/joystick_sw_pad.h +++ b/src/game/joystick_sw_pad.h @@ -8,7 +8,7 @@ * * Definitions for the Sidewinder Pro driver. * - * Version: @(#)joystick_sw_pad.h 1.0.2 2018/03/15 + * * * Authors: Miran Grca, * Sarah Walker, diff --git a/src/game/joystick_tm_fcs.c b/src/game/joystick_tm_fcs.c index afb4ac1b5..8b6e1e115 100644 --- a/src/game/joystick_tm_fcs.c +++ b/src/game/joystick_tm_fcs.c @@ -8,7 +8,7 @@ * * Implementation of Thrust Master Flight Control System. * - * Version: @(#)tm_fcs.c 1.0.3 2018/03/15 + * * * Authors: Miran Grca, * Sarah Walker, diff --git a/src/game/joystick_tm_fcs.h b/src/game/joystick_tm_fcs.h index 7ada355ed..60067d88a 100644 --- a/src/game/joystick_tm_fcs.h +++ b/src/game/joystick_tm_fcs.h @@ -8,7 +8,7 @@ * * Definitions for the Flight Control System driver. * - * Version: @(#)joystick_tm_fcs.h 1.0.2 2018/03/15 + * * * Authors: Miran Grca, * Sarah Walker, diff --git a/src/hwm.c b/src/hwm.c index b3142c7a4..1ebd6de00 100644 --- a/src/hwm.c +++ b/src/hwm.c @@ -8,7 +8,7 @@ * * Common functions for hardware monitor chips. * - * Version: @(#)hwm.c 1.0.0 2020/03/22 + * * * Author: RichardG, * Copyright 2020 RichardG. diff --git a/src/hwm.h b/src/hwm.h index c5d482fb7..b88627841 100644 --- a/src/hwm.h +++ b/src/hwm.h @@ -8,7 +8,7 @@ * * Definitions for the hardware monitor chips. * - * Version: @(#)hwm.h 1.0.0 2020/03/21 + * * * Author: RichardG, * Copyright 2020 RichardG. diff --git a/src/hwm_w83781d.c b/src/hwm_w83781d.c index 1f6b3ab26..d78ad3762 100644 --- a/src/hwm_w83781d.c +++ b/src/hwm_w83781d.c @@ -8,7 +8,7 @@ * * Emulation of the Winbond W83781D hardware monitoring chip. * - * Version: @(#)hwm_w83781d.c 1.0.0 2020/03/21 + * * * Author: RichardG, * Copyright 2020 RichardG. diff --git a/src/ibm_5161.c b/src/ibm_5161.c index 2374bdec3..61b38704b 100644 --- a/src/ibm_5161.c +++ b/src/ibm_5161.c @@ -6,7 +6,7 @@ * * Emulation of the IBM Expansion Unit (5161). * - * Version: @(#)ibm_5161.c 1.0.0 2019/06/28 + * * * Authors: Miran Grca, * diff --git a/src/ibm_5161.h b/src/ibm_5161.h index 7ae1913d3..69f9d23a8 100644 --- a/src/ibm_5161.h +++ b/src/ibm_5161.h @@ -6,7 +6,7 @@ * * Emulation of the IBM Expansion Unit (5161). * - * Version: @(#)ibm_5161.h 1.0.0 2019/06/218 + * * * Author: Miran Grca, * Copyright 2016-2018 Miran Grca. diff --git a/src/intel_flash.c b/src/intel_flash.c index 396899621..6b32b7ed0 100644 --- a/src/intel_flash.c +++ b/src/intel_flash.c @@ -9,7 +9,7 @@ * Implementation of the Intel 1 Mbit and 2 Mbit, 8-bit and * 16-bit flash devices. * - * Version: @(#)intel_flash.c 1.0.19 2019/06/25 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/intel_flash.h b/src/intel_flash.h index 3c76ec52a..60eaeacd8 100644 --- a/src/intel_flash.h +++ b/src/intel_flash.h @@ -8,7 +8,7 @@ * * Implementation of the Intel 1 Mbit 8-bit flash devices. * - * Version: @(#)intel_flash.h 1.0.2 2019/06/25 + * * * Author: Sarah Walker, * Miran Grca, diff --git a/src/intel_piix.c b/src/intel_piix.c index 09c46f37c..6ec84cfcf 100644 --- a/src/intel_piix.c +++ b/src/intel_piix.c @@ -10,7 +10,7 @@ * word 0 - base address * word 1 - bits 1-15 = byte count, bit 31 = end of transfer * - * Version: @(#)intel_piix.c 1.0.23 2020/01/24 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/intel_sio.c b/src/intel_sio.c index d0a5da9f4..85ba3d7df 100644 --- a/src/intel_sio.c +++ b/src/intel_sio.c @@ -6,7 +6,7 @@ * * Emulation of Intel System I/O PCI chip. * - * Version: @(#)intel_sio.c 1.0.9 2018/10/02 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/intel_sio.h b/src/intel_sio.h index 3793c6c58..924de555c 100644 --- a/src/intel_sio.h +++ b/src/intel_sio.h @@ -6,7 +6,7 @@ * * Emulation of Intel System I/O PCI chip. * - * Version: @(#)sio.h 1.0.3 2018/03/26 + * * * Author: Sarah Walker, * Miran Grca, diff --git a/src/io.c b/src/io.c index 6e53aafe2..34e26a968 100644 --- a/src/io.c +++ b/src/io.c @@ -8,7 +8,7 @@ * * Implement I/O ports and their operations. * - * Version: @(#)io.c 1.0.7 2019/09/23 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/isamem.c b/src/isamem.c index 9a37909c2..fc3c3f602 100644 --- a/src/isamem.c +++ b/src/isamem.c @@ -32,7 +32,7 @@ * TODO: The EV159 is supposed to support 16b EMS transfers, but the * EMM.sys driver for it doesn't seem to want to do that.. * - * Version: @(#)isamem.c 1.0.8 2018/10/23 + * * * Author: Fred N. van Kempen, * diff --git a/src/isamem.h b/src/isamem.h index a612df500..90d7666ec 100644 --- a/src/isamem.h +++ b/src/isamem.h @@ -8,7 +8,7 @@ * * Definitions for the ISAMEM cards. * - * Version: @(#)isamem.h 1.0.1 2018/08/18 + * * * Authors: Fred N. van Kempen, * diff --git a/src/isartc.c b/src/isartc.c index c83460aaa..0e89caee5 100644 --- a/src/isartc.c +++ b/src/isartc.c @@ -28,7 +28,7 @@ * NOTE: The IRQ functionalities have been implemented, but not yet * tested, as I need to write test software for them first :) * - * Version: @(#)isartc.c 1.0.7 2018/10/17 + * * * Author: Fred N. van Kempen, * diff --git a/src/isartc.h b/src/isartc.h index 457cb1c6d..0d5147251 100644 --- a/src/isartc.h +++ b/src/isartc.h @@ -8,7 +8,7 @@ * * Definitions for the ISARTC cards. * - * Version: @(#)isartc.h 1.0.1 2018/08/27 + * * * Authors: Fred N. van Kempen, * diff --git a/src/keyboard.c b/src/keyboard.c index 1c770f69d..77f17d600 100644 --- a/src/keyboard.c +++ b/src/keyboard.c @@ -8,7 +8,7 @@ * * General keyboard driver interface. * - * Version: @(#)keyboard.c 1.0.16 2019/03/05 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/keyboard.h b/src/keyboard.h index 78cd50a86..649d33f8d 100644 --- a/src/keyboard.h +++ b/src/keyboard.h @@ -8,7 +8,7 @@ * * Definitions for the keyboard interface. * - * Version: @(#)keyboard.h 1.0.19 2019/10/30 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/keyboard_at.c b/src/keyboard_at.c index c81f07bfa..f1c336b31 100644 --- a/src/keyboard_at.c +++ b/src/keyboard_at.c @@ -8,7 +8,7 @@ * * Intel 8042 (AT keyboard controller) emulation. * - * Version: @(#)keyboard_at.c 1.0.46 2020/01/11 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/keyboard_xt.c b/src/keyboard_xt.c index e74e926fb..bba7d3a37 100644 --- a/src/keyboard_xt.c +++ b/src/keyboard_xt.c @@ -8,7 +8,7 @@ * * Implementation of the XT-style keyboard. * - * Version: @(#)keyboard_xt.c 1.0.19 2019/11/15 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/lang/language.h b/src/lang/language.h index 7150fbe2d..061356dd4 100644 --- a/src/lang/language.h +++ b/src/lang/language.h @@ -10,7 +10,7 @@ * * NOTE: FIXME: Strings 2176 and 2193 are same. * - * Version: @(#)language.h 1.0.10 2018/11/19 + * * * Author: Fred N. van Kempen, * diff --git a/src/machine/m_amstrad.c b/src/machine/m_amstrad.c index d2c4325e3..7897f107a 100644 --- a/src/machine/m_amstrad.c +++ b/src/machine/m_amstrad.c @@ -29,7 +29,7 @@ * All models: The internal mouse controller does not work correctly with * version 7.04 of the mouse driver. * - * Version: @(#)m_amstrad.c 1.0.21 2019/11/15 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/machine/m_amstrad.h b/src/machine/m_amstrad.h index d85c3375b..b190ab0a5 100644 --- a/src/machine/m_amstrad.h +++ b/src/machine/m_amstrad.h @@ -10,7 +10,7 @@ * PC1512, PC1640 and PC200, including their keyboard, mouse and * video devices, as well as the PC2086 and PC3086 systems. * - * Version: @(#)m_amstrad.h 1.0.0 2019/03/21 + * * * Authors: Sarah Walker, * diff --git a/src/machine/m_at.c b/src/machine/m_at.c index 25666f7bc..43bb0f5cc 100644 --- a/src/machine/m_at.c +++ b/src/machine/m_at.c @@ -8,7 +8,7 @@ * * Standard PC/AT implementation. * - * Version: @(#)m_at.c 1.0.12 2020/01/13 + * * * Authors: Fred N. van Kempen, * Miran Grca, diff --git a/src/machine/m_at_286_386sx.c b/src/machine/m_at_286_386sx.c index 70c78226b..b16382f78 100644 --- a/src/machine/m_at_286_386sx.c +++ b/src/machine/m_at_286_386sx.c @@ -8,7 +8,7 @@ * * Implementation of 286 and 386SX machines. * - * Version: @(#)m_at_286_386sx.c 1.0.3 2020/01/22 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/machine/m_at_386dx_486.c b/src/machine/m_at_386dx_486.c index 78562d82f..e36e4876c 100644 --- a/src/machine/m_at_386dx_486.c +++ b/src/machine/m_at_386dx_486.c @@ -8,7 +8,7 @@ * * Implementation of 386DX and 486 machines. * - * Version: @(#)m_at_386dx_486.c 1.0.2 2020/01/20 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/machine/m_at_commodore.c b/src/machine/m_at_commodore.c index 066a8ab7a..39742f3f3 100644 --- a/src/machine/m_at_commodore.c +++ b/src/machine/m_at_commodore.c @@ -8,7 +8,7 @@ * * Implementation of the Commodore PC3 system. * - * Version: @(#)m_at_commodore.c 1.0.2 2018/11/12 + * * * Authors: Fred N. van Kempen, * Miran Grca, diff --git a/src/machine/m_at_compaq.c b/src/machine/m_at_compaq.c index ac8175b27..d22797090 100644 --- a/src/machine/m_at_compaq.c +++ b/src/machine/m_at_compaq.c @@ -8,7 +8,7 @@ * * Emulation of various Compaq PC's. * - * Version: @(#)m_at_compaq.c 1.0.6 2018/09/02 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/machine/m_at_socket4_5.c b/src/machine/m_at_socket4_5.c index 15012e856..da85e87c0 100644 --- a/src/machine/m_at_socket4_5.c +++ b/src/machine/m_at_socket4_5.c @@ -8,7 +8,7 @@ * * Implementation of Socket 4 and 5 machines. * - * Version: @(#)m_at_socket4_5.c 1.0.1 2019/10/20 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/machine/m_at_socket7_s7.c b/src/machine/m_at_socket7_s7.c index f48db0542..5898fb908 100644 --- a/src/machine/m_at_socket7_s7.c +++ b/src/machine/m_at_socket7_s7.c @@ -8,7 +8,7 @@ * * Implementation of Socket 7 and Super Socket 7 machines. * - * Version: @(#)m_at_socket7_s7.c 1.0.3 2020/01/24 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/machine/m_at_socket8.c b/src/machine/m_at_socket8.c index d6f590d7b..064bcb7c2 100644 --- a/src/machine/m_at_socket8.c +++ b/src/machine/m_at_socket8.c @@ -8,7 +8,7 @@ * * Implementation of Socket 8 and Slot 1 machines. * - * Version: @(#)m_at_socket8.c 1.0.0 2019/05/16 + * * * Authors: Miran Grca, * diff --git a/src/machine/m_at_t3100e.c b/src/machine/m_at_t3100e.c index 4244a96e5..2d35c5f49 100644 --- a/src/machine/m_at_t3100e.c +++ b/src/machine/m_at_t3100e.c @@ -117,7 +117,7 @@ * bit 2 set for single-pixel LCD font * bits 0,1 for display font * - * Version: @(#)m_at_t3100e.c 1.0.6 2018/10/22 + * * * Authors: Fred N. van Kempen, * Miran Grca, diff --git a/src/machine/m_at_t3100e.h b/src/machine/m_at_t3100e.h index e92d23b73..216f490e2 100644 --- a/src/machine/m_at_t3100e.h +++ b/src/machine/m_at_t3100e.h @@ -8,7 +8,7 @@ * * Definitions for the Toshiba T3100e system. * - * Version: @(#)m_at_t3100e.h 1.0.3 2018/03/18 + * * * Authors: Fred N. van Kempen, * Miran Grca, diff --git a/src/machine/m_at_t3100e_vid.c b/src/machine/m_at_t3100e_vid.c index 6f9f20200..a05c93689 100644 --- a/src/machine/m_at_t3100e_vid.c +++ b/src/machine/m_at_t3100e_vid.c @@ -22,7 +22,7 @@ * 61 50 52 0F 19 06 19 19 02 0D 0B 0C MONO * 2D 28 22 0A 67 00 64 67 02 03 06 07 640x400 * - * Version: @(#)m_at_t3100e_vid.c 1.0.8 2019/10/01 + * * * Authors: Fred N. van Kempen, * Miran Grca, diff --git a/src/machine/m_europc.c b/src/machine/m_europc.c index d642b0099..8555b514b 100644 --- a/src/machine/m_europc.c +++ b/src/machine/m_europc.c @@ -68,7 +68,7 @@ * * WARNING THIS IS A WORK-IN-PROGRESS MODULE. USE AT OWN RISK. * - * Version: @(#)europc.c 1.0.12 2019/11/15 + * * * Author: Fred N. van Kempen, * diff --git a/src/machine/m_olivetti_m24.c b/src/machine/m_olivetti_m24.c index f2fef9bb8..025d4e69f 100644 --- a/src/machine/m_olivetti_m24.c +++ b/src/machine/m_olivetti_m24.c @@ -8,7 +8,7 @@ * * Emulation of the Olivetti M24. * - * Version: @(#)m_olivetti_m24.c 1.0.21 2019/11/15 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/machine/m_pcjr.c b/src/machine/m_pcjr.c index 77628a800..735c62113 100644 --- a/src/machine/m_pcjr.c +++ b/src/machine/m_pcjr.c @@ -8,7 +8,7 @@ * * Emulation of the IBM PCjr. * - * Version: @(#)m_pcjr.c 1.0.14 2019/11/15 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/machine/m_ps1.c b/src/machine/m_ps1.c index c8a3ee8b2..3afc933f2 100644 --- a/src/machine/m_ps1.c +++ b/src/machine/m_ps1.c @@ -22,7 +22,7 @@ * The reserved 384K is remapped to the top of extended memory. * If this is not done then you get an error on startup. * - * Version: @(#)m_ps1.c 1.0.17 2019/11/15 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/machine/m_ps1_hdc.c b/src/machine/m_ps1_hdc.c index d767b7aa8..fe0c3d036 100644 --- a/src/machine/m_ps1_hdc.c +++ b/src/machine/m_ps1_hdc.c @@ -43,7 +43,7 @@ * Type table with the main code, so the user can only select * items from that list... * - * Version: @(#)m_ps1_hdc.c 1.0.8 2019/03/08 + * * * Author: Fred N. van Kempen, * diff --git a/src/machine/m_ps2_mca.c b/src/machine/m_ps2_mca.c index c4b755a6d..800ceaead 100644 --- a/src/machine/m_ps2_mca.c +++ b/src/machine/m_ps2_mca.c @@ -8,7 +8,7 @@ * * Implementation of MCA-based PS/2 machines. * - * Version: @(#)m_ps2_mca.c 1.0.6 2019/11/01 + * * * Authors: Fred N. van Kempen, * Miran Grca, diff --git a/src/machine/m_tandy.c b/src/machine/m_tandy.c index 658f8c1f0..08d55ee18 100644 --- a/src/machine/m_tandy.c +++ b/src/machine/m_tandy.c @@ -8,7 +8,7 @@ * * Emulation of Tandy models 1000, 1000HX and 1000SL2. * - * Version: @(#)m_tandy.c 1.0.11 2019/12/28 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/machine/m_xt_compaq.c b/src/machine/m_xt_compaq.c index edc3cf007..699aa15f7 100644 --- a/src/machine/m_xt_compaq.c +++ b/src/machine/m_xt_compaq.c @@ -8,7 +8,7 @@ * * Emulation of various Compaq XT-class PC's. * - * Version: @(#)m_xt_compaq.c 1.0.5 2019/11/15 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/machine/m_xt_t1000.c b/src/machine/m_xt_t1000.c index 2e8fd40f9..13e099e53 100644 --- a/src/machine/m_xt_t1000.c +++ b/src/machine/m_xt_t1000.c @@ -51,7 +51,7 @@ * NOTE: Still need to figure out a way to load/save ConfigSys and * HardRAM stuff. Needs to be linked in to the NVR code. * - * Version: @(#)m_xt_t1000.c 1.0.14 2019/11/15 + * * * Authors: Fred N. van Kempen, * Miran Grca, diff --git a/src/machine/m_xt_t1000.h b/src/machine/m_xt_t1000.h index d76b792e1..8945b24e8 100644 --- a/src/machine/m_xt_t1000.h +++ b/src/machine/m_xt_t1000.h @@ -8,7 +8,7 @@ * * Definitions for the Toshiba T1000/T1200 machines. * - * Version: @(#)m_xt_t1000.h 1.0.5 2018/08/15 + * * * Authors: Fred N. van Kempen, * Miran Grca, diff --git a/src/machine/m_xt_t1000_vid.c b/src/machine/m_xt_t1000_vid.c index 8196e8e59..395b16276 100644 --- a/src/machine/m_xt_t1000_vid.c +++ b/src/machine/m_xt_t1000_vid.c @@ -9,7 +9,7 @@ * Implementation of the Toshiba T1000 plasma display, which * has a fixed resolution of 640x200 pixels. * - * Version: @(#)m_xt_t1000_vid.c 1.0.12 2019/10/01 + * * * Authors: Fred N. van Kempen, * Miran Grca, diff --git a/src/machine/m_xt_zenith.c b/src/machine/m_xt_zenith.c index d6b1b5261..cfbda25c8 100644 --- a/src/machine/m_xt_zenith.c +++ b/src/machine/m_xt_zenith.c @@ -9,7 +9,7 @@ * Emulation of various Zenith PC compatible machines. * Currently only the Zenith Data Systems Supersport is emulated. * - * Version: @(#)m_xt_compaq.c 1.0.1 2019/11/15 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/machine/machine.c b/src/machine/machine.c index d5a5680b1..016468b4a 100644 --- a/src/machine/machine.c +++ b/src/machine/machine.c @@ -8,7 +8,7 @@ * * Handling of the emulated machines. * - * Version: @(#)machine.c 1.0.39 2020/01/24 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/machine/machine.h b/src/machine/machine.h index 0a9bf8b35..7f584a5ea 100644 --- a/src/machine/machine.h +++ b/src/machine/machine.h @@ -8,7 +8,7 @@ * * Handling of the emulated machines. * - * Version: @(#)machine.h 1.0.38 2020/01/24 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/machine/machine_table.c b/src/machine/machine_table.c index c3e4c4959..be958aa0f 100644 --- a/src/machine/machine_table.c +++ b/src/machine/machine_table.c @@ -11,7 +11,7 @@ * NOTES: OpenAT wip for 286-class machine with open BIOS. * PS2_M80-486 wip, pending receipt of TRM's for machine. * - * Version: @(#)machine_table.c 1.0.55 2020/01/24 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/mem.c b/src/mem.c index 114bca468..281951a30 100644 --- a/src/mem.c +++ b/src/mem.c @@ -12,7 +12,7 @@ * the DYNAMIC_TABLES=1 enables this. Will eventually go * away, either way... * - * Version: @(#)mem.c 1.0.23 2020/01/25 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/mem.h b/src/mem.h index badcb2d3c..015a6273c 100644 --- a/src/mem.h +++ b/src/mem.h @@ -8,7 +8,7 @@ * * Definitions for the memory interface. * - * Version: @(#)mem.h 1.0.11 2020/01/25 + * * * Authors: Sarah Walker, * Fred N. van Kempen, diff --git a/src/mouse.c b/src/mouse.c index bd01892f7..609419af7 100644 --- a/src/mouse.c +++ b/src/mouse.c @@ -11,7 +11,7 @@ * TODO: Add the Genius bus- and serial mouse. * Remove the '3-button' flag from mouse types. * - * Version: @(#)mouse.c 1.0.29 2018/11/04 + * * * Authors: Miran Grca, * Fred N. van Kempen, diff --git a/src/mouse.h b/src/mouse.h index a743a0676..a3e192c46 100644 --- a/src/mouse.h +++ b/src/mouse.h @@ -8,7 +8,7 @@ * * Definitions for the mouse driver. * - * Version: @(#)mouse.h 1.0.15 2019/09/27 + * * * Authors: Miran Grca, * Fred N. van Kempen, diff --git a/src/mouse_bus.c b/src/mouse_bus.c index df7794adf..8d8cceae0 100644 --- a/src/mouse_bus.c +++ b/src/mouse_bus.c @@ -57,7 +57,7 @@ * Microsoft Windows NT 3.1 * Microsoft Windows 98 SE * - * Version: @(#)mouse_bus.c 1.0.4 2019/09/27 + * * * Authors: Miran Grca, * Fred N. van Kempen, diff --git a/src/mouse_ps2.c b/src/mouse_ps2.c index cbd3e5695..48e22bb08 100644 --- a/src/mouse_ps2.c +++ b/src/mouse_ps2.c @@ -8,7 +8,7 @@ * * Implementation of PS/2 series Mouse devices. * - * Version: @(#)mouse_ps2.c 1.0.12 2018/10/17 + * * * Authors: Fred N. van Kempen, */ diff --git a/src/mouse_serial.c b/src/mouse_serial.c index b306e1252..53ee47b43 100644 --- a/src/mouse_serial.c +++ b/src/mouse_serial.c @@ -10,7 +10,7 @@ * * TODO: Add the Genius Serial Mouse. * - * Version: @(#)mouse_serial.c 1.0.29 2019/10/31 + * * * Author: Fred N. van Kempen, */ diff --git a/src/network/bswap.h b/src/network/bswap.h index 75311d39b..a49c4f1bc 100644 --- a/src/network/bswap.h +++ b/src/network/bswap.h @@ -8,7 +8,7 @@ * * Various definitions for portable byte-swapping. * - * Version: @(#)bswap.h 1.0.2 2018/03/12 + * * * Authors: Fred N. van Kempen, * neozeed, diff --git a/src/network/net_3c503.c b/src/network/net_3c503.c index 51084ed79..3bc0960c9 100644 --- a/src/network/net_3c503.c +++ b/src/network/net_3c503.c @@ -8,7 +8,7 @@ * Implementation of the following network controllers: * - 3Com Etherlink II 3c503 (ISA 8-bit). * - * Version: @(#)net_3c503.c 1.0.2 2018/10/17 + * * * Based on @(#)3c503.cpp Carl (MAME) * diff --git a/src/network/net_dp8390.c b/src/network/net_dp8390.c index 4b1fa3edd..4f5cc708b 100644 --- a/src/network/net_dp8390.c +++ b/src/network/net_dp8390.c @@ -7,7 +7,7 @@ * Emulation of the DP8390 Network Interface Controller used by * the WD family, NE1000/NE2000 family, and 3Com 3C503 NIC's. * - * Version: @(#)net_dp8390.c 1.0.3 2020/03/23 + * * * Authors: Miran Grca, * Bochs project, diff --git a/src/network/net_dp8390.h b/src/network/net_dp8390.h index 313538b5a..02c9763fa 100644 --- a/src/network/net_dp8390.h +++ b/src/network/net_dp8390.h @@ -8,7 +8,7 @@ * Controller used by the WD family, NE1000/NE2000 family, and * 3Com 3C503 NIC's. * - * Version: @(#)net_dp8390.h 1.0.1 2018/10/20 + * * * Authors: Miran Grca, * Bochs project, diff --git a/src/network/net_ne2000.c b/src/network/net_ne2000.c index 8feb13c5c..5b9067c9c 100644 --- a/src/network/net_ne2000.c +++ b/src/network/net_ne2000.c @@ -13,7 +13,7 @@ * - Realtek RTL8019AS (ISA 16-bit, PnP); * - Realtek RTL8029AS (PCI). * - * Version: @(#)net_ne2000.c 1.0.11 2018/10/20 + * * * Based on @(#)ne2k.cc v1.56.2.1 2004/02/02 22:37:22 cbothamy * diff --git a/src/network/net_ne2000.h b/src/network/net_ne2000.h index f87943122..c7e466080 100644 --- a/src/network/net_ne2000.h +++ b/src/network/net_ne2000.h @@ -8,7 +8,7 @@ * * Definitions for the NE2000 ethernet controller. * - * Version: @(#)net_ne2000.h 1.0.4 2018/08/11 + * * * Authors: Fred N. van Kempen, * diff --git a/src/network/net_pcap.c b/src/network/net_pcap.c index 6ca9a2fe3..a89b37527 100644 --- a/src/network/net_pcap.c +++ b/src/network/net_pcap.c @@ -8,7 +8,7 @@ * * Handle WinPcap library processing. * - * Version: @(#)net_pcap.c 1.0.10 2019/11/14 + * * * Author: Fred N. van Kempen, * diff --git a/src/network/net_pcnet.c b/src/network/net_pcnet.c index d2e20acd3..0bdd57f21 100644 --- a/src/network/net_pcnet.c +++ b/src/network/net_pcnet.c @@ -7,7 +7,7 @@ * Emulation of the AMD PCnet LANCE NIC controller for both the ISA, VLB, * and PCI buses. * - * Version: @(#)net_pcnet.c 1.0.1 2020/03/23 + * * * Authors: Miran Grca, * TheCollector1995, diff --git a/src/network/net_pcnet.h b/src/network/net_pcnet.h index eb6a51d7b..cab123c83 100644 --- a/src/network/net_pcnet.h +++ b/src/network/net_pcnet.h @@ -7,7 +7,7 @@ * Emulation of the AMD PCnet LANCE NIC controller for both the ISA * and PCI buses. * - * Version: @(#)net_pcnet.c 1.0.1 2020/03/23 + * * * Authors: Miran Grca, * TheCollector1995, diff --git a/src/network/net_slirp.c b/src/network/net_slirp.c index 66d26a31b..56e23cfbd 100644 --- a/src/network/net_slirp.c +++ b/src/network/net_slirp.c @@ -8,7 +8,7 @@ * * Handle SLiRP library processing. * - * Version: @(#)net_slirp.c 1.0.9 2019/11/14 + * * * Author: Fred N. van Kempen, * diff --git a/src/network/net_wd8003.c b/src/network/net_wd8003.c index e11fb1e57..276879730 100644 --- a/src/network/net_wd8003.c +++ b/src/network/net_wd8003.c @@ -11,7 +11,7 @@ * - SMC/WD 8013EBT (ISA 16-bit); * - SMC/WD 8013EP/A (MCA). * - * Version: @(#)net_wd8003.c 1.0.6 2019/09/21 + * * * Authors: Fred N. van Kempen, * TheCollector1995, diff --git a/src/network/net_wd8003.h b/src/network/net_wd8003.h index ecf1b09e6..5b6e2113e 100644 --- a/src/network/net_wd8003.h +++ b/src/network/net_wd8003.h @@ -11,7 +11,7 @@ * - SMC/WD 8013EBT (ISA 16-bit); * - SMC/WD 8013EP/A (MCA). * - * Version: @(#)net_wd8003.c 1.0.1 2018/10/22 + * * * Authors: Fred N. van Kempen, * TheCollector1995, diff --git a/src/network/network.c b/src/network/network.c index 3b3e08ca5..a8d341b41 100644 --- a/src/network/network.c +++ b/src/network/network.c @@ -12,7 +12,7 @@ * it should be malloc'ed and then linked to the NETCARD def. * Will be done later. * - * Version: @(#)network.c 1.0.14 2020/03/23 + * * * Author: Fred N. van Kempen, * diff --git a/src/network/network.h b/src/network/network.h index 7edfabf5c..39dbe49bc 100644 --- a/src/network/network.h +++ b/src/network/network.h @@ -8,7 +8,7 @@ * * Definitions for the network module. * - * Version: @(#)network.h 1.0.3 2019/11/14 + * * * Author: Fred N. van Kempen, * diff --git a/src/network/pcap_if.c b/src/network/pcap_if.c index b73639b48..f5a9a4111 100644 --- a/src/network/pcap_if.c +++ b/src/network/pcap_if.c @@ -10,7 +10,7 @@ * * Based on the "libpcap" examples. * - * Version: @(#)pcap_if.c 1.0.10 2018/03/10 + * * * Author: Fred N. van Kempen, * diff --git a/src/nvr.c b/src/nvr.c index 28b099ba1..090aa2e3c 100644 --- a/src/nvr.c +++ b/src/nvr.c @@ -8,7 +8,7 @@ * * Implement a generic NVRAM/CMOS/RTC device. * - * Version: @(#)nvr.c 1.0.19 2019/11/19 + * * * Authors: Fred N. van Kempen, , * David Hrdlička, diff --git a/src/nvr.h b/src/nvr.h index ce283fe92..511b88643 100644 --- a/src/nvr.h +++ b/src/nvr.h @@ -8,7 +8,7 @@ * * Definitions for the generic NVRAM/CMOS driver. * - * Version: @(#)nvr.h 1.0.14 2020/01/24 + * * * Author: Fred N. van Kempen, , * David Hrdlička, diff --git a/src/nvr_at.c b/src/nvr_at.c index cfc3509f5..9a2858454 100644 --- a/src/nvr_at.c +++ b/src/nvr_at.c @@ -189,7 +189,7 @@ * including the later update (DS12887A) which implemented a * "century" register to be compatible with Y2K. * - * Version: @(#)nvr_at.c 1.0.19 2020/01/24 + * * * Authors: Fred N. van Kempen, * Miran Grca, diff --git a/src/nvr_ps2.c b/src/nvr_ps2.c index b4074039d..e222bbd09 100644 --- a/src/nvr_ps2.c +++ b/src/nvr_ps2.c @@ -8,7 +8,7 @@ * * Handling of the PS/2 series CMOS devices. * - * Version: @(#)nvr_ps2.c 1.0.10 2018/10/02 + * * * Authors: Fred N. van Kempen, * Sarah Walker, diff --git a/src/nvr_ps2.h b/src/nvr_ps2.h index 57293f212..f0058d9b1 100644 --- a/src/nvr_ps2.h +++ b/src/nvr_ps2.h @@ -8,7 +8,7 @@ * * Definitions for the PS/2 cmos/nvr device. * - * Version: @(#)nvr_ps2.h 1.0.2 2018/03/18 + * * * Authors: Fred N. van Kempen, * Sarah Walker, diff --git a/src/pc.c b/src/pc.c index 3c67989c0..f778b7e23 100644 --- a/src/pc.c +++ b/src/pc.c @@ -8,7 +8,7 @@ * * Main emulator module where most things are controlled. * - * Version: @(#)pc.c 1.0.94 2020/01/19 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/pci.c b/src/pci.c index ada976629..ec6e6c86a 100644 --- a/src/pci.c +++ b/src/pci.c @@ -8,7 +8,7 @@ * * Implementation the PCI bus. * - * Version: @(#)pci.c 1.0.6 2020/01/11 + * * * Authors: Miran Grca, * Fred N. van Kempen, diff --git a/src/pci.h b/src/pci.h index 473f27389..8063e27c9 100644 --- a/src/pci.h +++ b/src/pci.h @@ -8,7 +8,7 @@ * * Definitions for the PCI handler module. * - * Version: @(#)pci.h 1.0.2 2020/01/11 + * * * Authors: Miran Grca, * Fred N. van Kempen, diff --git a/src/pic.c b/src/pic.c index ad8cc00d5..8e3a6e943 100644 --- a/src/pic.c +++ b/src/pic.c @@ -8,7 +8,7 @@ * * Implementation of the Intel PIC chip emulation. * - * Version: @(#)pic.c 1.0.7 2020/01/21 + * * * Author: Miran Grca, * diff --git a/src/piix.h b/src/piix.h index 2987cef7e..5ad26a7b7 100644 --- a/src/piix.h +++ b/src/piix.h @@ -8,7 +8,7 @@ * * Emulation core dispatcher. * - * Version: @(#)piix.h 1.0.4 2020/01/24 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/pit.c b/src/pit.c index f3421a8f4..b3743138f 100644 --- a/src/pit.c +++ b/src/pit.c @@ -9,7 +9,7 @@ * Implementation of the Intel 8253/8254 Programmable Interval * Timer. * - * Version: @(#)pit.c 1.0.0 2019/12/02 + * * * Author: Miran Grca, * Copyright 2019 Miran Grca. diff --git a/src/pit.h b/src/pit.h index f019327a6..7b8ac98b7 100644 --- a/src/pit.h +++ b/src/pit.h @@ -9,7 +9,7 @@ * Header of the implementation of the Intel 8253/8254 * Programmable Interval Timer. * - * Version: @(#)pit.h 1.0.1 2020/01/17 + * * * Author: Miran Grca, * Copyright 2019,2020 Miran Grca. diff --git a/src/plat.h b/src/plat.h index ec5391bae..cb2096d75 100644 --- a/src/plat.h +++ b/src/plat.h @@ -8,7 +8,7 @@ * * Define the various platform support functions. * - * Version: @(#)plat.h 1.0.28 2019/03/06 + * * * Authors: Miran Grca, * Fred N. van Kempen, diff --git a/src/plat_dynld.h b/src/plat_dynld.h index 72bc75c2f..0eb8f33c2 100644 --- a/src/plat_dynld.h +++ b/src/plat_dynld.h @@ -8,7 +8,7 @@ * * Define the Dynamic Module Loader interface. * - * Version: @(#)plat_dynld.h 1.0.1 2017/05/21 + * * * Author: Fred N. van Kempen, * Copyright 2017 Fred N. van Kempen diff --git a/src/port_92.c b/src/port_92.c index 7230111f2..f20f4f984 100644 --- a/src/port_92.c +++ b/src/port_92.c @@ -9,7 +9,7 @@ * Implementation of Port 92 used by PS/2 machines and 386+ * clones. * - * Version: @(#)port_92.c 1.0.0 2019/05/14 + * * * Authors: Miran Grca, * diff --git a/src/port_92.h b/src/port_92.h index 4b41eb09d..52812edb8 100644 --- a/src/port_92.h +++ b/src/port_92.h @@ -9,7 +9,7 @@ * Header for the implementation of Port 92 used by PS/2 * machines and 386+ clones. * - * Version: @(#)port_92.h 1.0.0 2019/05/14 + * * * Authors: Miran Grca, * diff --git a/src/postcard.c b/src/postcard.c index 9662d3ae6..3820665fb 100644 --- a/src/postcard.c +++ b/src/postcard.c @@ -8,7 +8,7 @@ * * Implementation of a port 80h POST diagnostic card. * - * Version: @(#)postcard.c 1.0.0 2020/03/23 + * * * Author: RichardG, * Copyright 2020 RichardG. diff --git a/src/postcard.h b/src/postcard.h index 4bfc912f5..ac5ac9fd4 100644 --- a/src/postcard.h +++ b/src/postcard.h @@ -8,7 +8,7 @@ * * Implementation of a port 80h POST diagnostic card. * - * Version: @(#)postcard.c 1.0.0 2020/03/23 + * * * Author: RichardG, * Copyright 2020 RichardG. diff --git a/src/printer/png.c b/src/printer/png.c index 7d4555bd2..37951912b 100644 --- a/src/printer/png.c +++ b/src/printer/png.c @@ -8,7 +8,7 @@ * * Provide centralized access to the PNG image handler. * - * Version: @(#)png.c 1.0.5 2018/11/19 + * * * Author: Fred N. van Kempen, * diff --git a/src/printer/png_struct.h b/src/printer/png_struct.h index 6647b41b9..694fcfc20 100644 --- a/src/printer/png_struct.h +++ b/src/printer/png_struct.h @@ -8,7 +8,7 @@ * * Definitions for the centralized PNG image handler. * - * Version: @(#)png_struct.h 1.0.2 2018/11/19 + * * * Author: Fred N. van Kempen, * diff --git a/src/printer/printer.h b/src/printer/printer.h index 33f7d58c9..44dfa6371 100644 --- a/src/printer/printer.h +++ b/src/printer/printer.h @@ -8,7 +8,7 @@ * * Definitions for the printers module. * - * Version: @(#)printer.h 1.0.3 2018/09/03 + * * * Author: Fred N. van Kempen, * diff --git a/src/printer/prt_cpmap.c b/src/printer/prt_cpmap.c index 8713d0809..4a1e6c995 100644 --- a/src/printer/prt_cpmap.c +++ b/src/printer/prt_cpmap.c @@ -8,7 +8,7 @@ * * Various ASCII to Unicode maps, for the various codepages. * - * Version: @(#)prt_cpmap.c 1.0.2 2018/10/05 + * * * Authors: Michael Dr�ing, * Fred N. van Kempen, diff --git a/src/printer/prt_escp.c b/src/printer/prt_escp.c index c965285ab..110839282 100644 --- a/src/printer/prt_escp.c +++ b/src/printer/prt_escp.c @@ -8,7 +8,7 @@ * * Implementation of the Generic ESC/P Dot-Matrix printer. * - * Version: @(#)prt_escp.c 1.0.7 2019/09/23 + * * * Authors: Michael Dr�ing, * Fred N. van Kempen, diff --git a/src/printer/prt_ps.c b/src/printer/prt_ps.c index 22d5f85b8..e849b57c9 100644 --- a/src/printer/prt_ps.c +++ b/src/printer/prt_ps.c @@ -8,7 +8,7 @@ * * Implementation of a generic PostScript printer. * - * Version: @(#)prt_ps.c 1.0.2 2019/12/08 + * * * Authors: David Hrdlička, * diff --git a/src/printer/prt_text.c b/src/printer/prt_text.c index 9219221f1..6bbffb34a 100644 --- a/src/printer/prt_text.c +++ b/src/printer/prt_text.c @@ -15,7 +15,7 @@ * printer mechanics. This would lead to a page being 66 lines * of 80 characters each. * - * Version: @(#)prt_text.c 1.0.7 2019/09/23 + * * * Author: Fred N. van Kempen, * diff --git a/src/random.c b/src/random.c index c4f28548f..1d644f3e3 100644 --- a/src/random.c +++ b/src/random.c @@ -9,7 +9,7 @@ * A better random number generation, used for floppy weak bits * and network MAC address generation. * - * Version: @(#)random.c 1.0.4 2018/10/02 + * * * Author: Miran Grca, * Copyright 2016-2018 Miran Grca. diff --git a/src/random.h b/src/random.h index d6f56bca9..75ceb4c13 100644 --- a/src/random.h +++ b/src/random.h @@ -9,7 +9,7 @@ * A better random number generation, used for floppy weak bits * and network MAC address generation. * - * Version: @(#)random.h 1.0.2 2017/09/03 + * * * Author: Miran Grca, * Copyright 2016,2017 Miran Grca. diff --git a/src/rom.c b/src/rom.c index 1853fb3f0..3d4d6fcdf 100644 --- a/src/rom.c +++ b/src/rom.c @@ -12,7 +12,7 @@ * - pc2386 video BIOS is underdumped (16k instead of 24k) * - c386sx16 BIOS fails checksum * - * Version: @(#)rom.c 1.0.45 2019/03/03 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/rom.h b/src/rom.h index 38cd033b0..f837d2b68 100644 --- a/src/rom.h +++ b/src/rom.h @@ -8,7 +8,7 @@ * * Definitions for the ROM image handler. * - * Version: @(#)rom.h 1.0.23 2019/03/03 + * * * Author: Fred N. van Kempen, * Copyright 2018,2019 Fred N. van Kempen. diff --git a/src/scsi/scsi.c b/src/scsi/scsi.c index a5a509494..21742c469 100644 --- a/src/scsi/scsi.c +++ b/src/scsi/scsi.c @@ -8,7 +8,7 @@ * * Handling of the SCSI controllers. * - * Version: @(#)scsi.c 1.0.25 2018/10/31 + * * * Authors: Miran Grca, * Fred N. van Kempen, diff --git a/src/scsi/scsi.h b/src/scsi/scsi.h index 011d2569a..364c2c60a 100644 --- a/src/scsi/scsi.h +++ b/src/scsi/scsi.h @@ -8,7 +8,7 @@ * * SCSI controller handler header. * - * Version: @(#)scsi_h 1.0.19 2018/10/02 + * * * Authors: TheCollector1995, * Miran Grca, diff --git a/src/scsi/scsi_aha154x.c b/src/scsi/scsi_aha154x.c index b3ec5f4a9..7ca6d6f90 100644 --- a/src/scsi/scsi_aha154x.c +++ b/src/scsi/scsi_aha154x.c @@ -10,7 +10,7 @@ * made by Adaptec, Inc. These controllers were designed for * the ISA bus. * - * Version: @(#)scsi_aha154x.c 1.0.44 2018/10/18 + * * * Authors: Fred N. van Kempen, * Original Buslogic version by SA1988 and Miran Grca. diff --git a/src/scsi/scsi_buslogic.c b/src/scsi/scsi_buslogic.c index 48d19c9f5..90b80587b 100644 --- a/src/scsi/scsi_buslogic.c +++ b/src/scsi/scsi_buslogic.c @@ -11,7 +11,7 @@ * 1 - BT-545S ISA; * 2 - BT-958D PCI * - * Version: @(#)scsi_buslogic.c 1.0.45 2019/02/11 + * * * Authors: TheCollector1995, * Miran Grca, diff --git a/src/scsi/scsi_buslogic.h b/src/scsi/scsi_buslogic.h index 87f79d522..203e45e12 100644 --- a/src/scsi/scsi_buslogic.h +++ b/src/scsi/scsi_buslogic.h @@ -7,7 +7,7 @@ * Emulation of BusLogic BT-542B ISA and BT-958D PCI SCSI * controllers. * - * Version: @(#)scsi_buslogic.h 1.0.3 2018/03/18 + * * * Authors: TheCollector1995, * Miran Grca, diff --git a/src/scsi/scsi_cdrom.c b/src/scsi/scsi_cdrom.c index 6527340f9..7515af9ca 100644 --- a/src/scsi/scsi_cdrom.c +++ b/src/scsi/scsi_cdrom.c @@ -9,7 +9,7 @@ * Implementation of the CD-ROM drive with SCSI(-like) * commands, for both ATAPI and SCSI usage. * - * Version: @(#)scsi_cdrom.c 1.0.75 2020/03/23 + * * * Author: Miran Grca, * diff --git a/src/scsi/scsi_cdrom.h b/src/scsi/scsi_cdrom.h index 1c8be1382..00f263ad6 100644 --- a/src/scsi/scsi_cdrom.h +++ b/src/scsi/scsi_cdrom.h @@ -9,7 +9,7 @@ * Implementation of the CD-ROM drive with SCSI(-like) * commands, for both ATAPI and SCSI usage. * - * Version: @(#)scsi_cdrom.h 1.0.2 2019/11/19 + * * * Author: Miran Grca, * diff --git a/src/scsi/scsi_device.c b/src/scsi/scsi_device.c index 61aca0b81..099bd2f90 100644 --- a/src/scsi/scsi_device.c +++ b/src/scsi/scsi_device.c @@ -8,7 +8,7 @@ * * The generic SCSI device command handler. * - * Version: @(#)scsi_device.c 1.0.23 2018/10/31 + * * * Authors: Miran Grca, * Fred N. van Kempen, diff --git a/src/scsi/scsi_device.h b/src/scsi/scsi_device.h index 181e4ea7e..37ecfe866 100644 --- a/src/scsi/scsi_device.h +++ b/src/scsi/scsi_device.h @@ -8,7 +8,7 @@ * * Definitions for the generic SCSI device command handler. * - * Version: @(#)scsi_device.h 1.0.18 2020/03/23 + * * * Authors: Miran Grca, * Fred N. van Kempen, diff --git a/src/scsi/scsi_disk.c b/src/scsi/scsi_disk.c index a8fcc73bc..ad596fa31 100644 --- a/src/scsi/scsi_disk.c +++ b/src/scsi/scsi_disk.c @@ -6,7 +6,7 @@ * * Emulation of SCSI fixed disks. * - * Version: @(#)scsi_disk.c 1.0.30 2018/11/02 + * * * Author: Miran Grca, * diff --git a/src/scsi/scsi_disk.h b/src/scsi/scsi_disk.h index 54c872e2b..86245f625 100644 --- a/src/scsi/scsi_disk.h +++ b/src/scsi/scsi_disk.h @@ -6,7 +6,7 @@ * * Emulation of SCSI fixed and removable disks. * - * Version: @(#)scsi_disk.h 1.0.7 2018/10/26 + * * * Author: Miran Grca, * Copyright 2017,2018 Miran Grca. diff --git a/src/scsi/scsi_ncr5380.c b/src/scsi/scsi_ncr5380.c index 9a652e8e1..e54436a2f 100644 --- a/src/scsi/scsi_ncr5380.c +++ b/src/scsi/scsi_ncr5380.c @@ -9,7 +9,7 @@ * Implementation of the NCR 5380 series of SCSI Host Adapters * made by NCR. These controllers were designed for the ISA bus. * - * Version: @(#)scsi_ncr5380.c 1.0.25 2019/10/16 + * * * Authors: Sarah Walker, * TheCollector1995, diff --git a/src/scsi/scsi_ncr5380.h b/src/scsi/scsi_ncr5380.h index 5e14f77a2..aa1f4ad89 100644 --- a/src/scsi/scsi_ncr5380.h +++ b/src/scsi/scsi_ncr5380.h @@ -10,7 +10,7 @@ * made by NCR. These controllers were designed for * the ISA bus. * - * Version: @(#)scsi_ncr5380.c 1.0.2 2018/03/18 + * * * Authors: Sarah Walker, * TheCollector1995, diff --git a/src/scsi/scsi_ncr53c8xx.c b/src/scsi/scsi_ncr53c8xx.c index 77c9d0143..bd824bb9c 100644 --- a/src/scsi/scsi_ncr53c8xx.c +++ b/src/scsi/scsi_ncr53c8xx.c @@ -13,7 +13,7 @@ * To do: Identify the type of serial EEPROM used and its * interface. * - * Version: @(#)scsi_ncr53c8xx.c 1.0.18 2019/11/19 + * * * Authors: Paul Brook (QEMU) * Artyom Tarasenko (QEMU) diff --git a/src/scsi/scsi_ncr53c8xx.h b/src/scsi/scsi_ncr53c8xx.h index b84c91c1c..f0cc4c5ec 100644 --- a/src/scsi/scsi_ncr53c8xx.h +++ b/src/scsi/scsi_ncr53c8xx.h @@ -10,7 +10,7 @@ * Adapters made by NCR and later Symbios and LSI. These * controllers were designed for the PCI bus. * - * Version: @(#)scsi_ncr53c8xx.c 1.0.2 2018/10/30 + * * * Authors: TheCollector1995, * Miran Grca, diff --git a/src/scsi/scsi_spock.c b/src/scsi/scsi_spock.c index 1a26b6b49..08e1647e3 100644 --- a/src/scsi/scsi_spock.c +++ b/src/scsi/scsi_spock.c @@ -9,7 +9,7 @@ * Implementation of the IBM PS/2 SCSI controller with * cache for MCA only. * - * Version: @(#)scsi_spock.c 1.0.1 2020/03/23 + * * * Authors: Sarah Walker, * TheCollector1995, diff --git a/src/scsi/scsi_spock.h b/src/scsi/scsi_spock.h index bf064421c..959fe3d04 100644 --- a/src/scsi/scsi_spock.h +++ b/src/scsi/scsi_spock.h @@ -9,7 +9,7 @@ * Implementation of the IBM PS/2 SCSI controller with * cache for MCA only. * - * Version: @(#)scsi_spock.h 1.0.0 2020/03/10 + * * * Authors: Sarah Walker, * TheCollector1995, diff --git a/src/scsi/scsi_x54x.c b/src/scsi/scsi_x54x.c index f41d013a0..24253f98d 100644 --- a/src/scsi/scsi_x54x.c +++ b/src/scsi/scsi_x54x.c @@ -11,7 +11,7 @@ * series of SCSI Host Adapters made by Mylex. * These controllers were designed for various buses. * - * Version: @(#)scsi_x54x.c 1.0.29 2019/05/16 + * * * Authors: TheCollector1995, * Miran Grca, diff --git a/src/scsi/scsi_x54x.h b/src/scsi/scsi_x54x.h index cd0948c43..7b403e39d 100644 --- a/src/scsi/scsi_x54x.h +++ b/src/scsi/scsi_x54x.h @@ -11,7 +11,7 @@ * of SCSI Host Adapters made by Mylex. * These controllers were designed for various buses. * - * Version: @(#)scsi_x54x.h 1.0.10 2018/10/28 + * * * Authors: TheCollector1995, * Miran Grca, diff --git a/src/serial.c b/src/serial.c index 7d35466a7..2b3ad801f 100644 --- a/src/serial.c +++ b/src/serial.c @@ -10,7 +10,7 @@ * * Now passes all the AMIDIAG tests. * - * Version: @(#)serial.h 1.0.14 2020/01/24 + * * * Author: Sarah Walker, * Miran Grca, diff --git a/src/serial.h b/src/serial.h index 7ec03dc66..90159cfae 100644 --- a/src/serial.h +++ b/src/serial.h @@ -8,7 +8,7 @@ * * Definitions for the NS8250/16450/16550 UART emulation. * - * Version: @(#)serial.h 1.0.13 2020/01/24 + * * * Author: Sarah Walker, * Miran Grca, diff --git a/src/sio.h b/src/sio.h index 6009545ee..5888406c9 100644 --- a/src/sio.h +++ b/src/sio.h @@ -8,7 +8,7 @@ * * Definitions for the Super I/O chips. * - * Version: @(#)sio.h 1.0.7 2020/01/25 + * * * Author: Fred N. van Kempen, * Copyright 2017-2020 Fred N. van Kempen. diff --git a/src/sio_acc3221.c b/src/sio_acc3221.c index 93de9cb0a..870a4f702 100644 --- a/src/sio_acc3221.c +++ b/src/sio_acc3221.c @@ -8,7 +8,7 @@ * * Implementation of the ACC 3221-SP Super I/O Chip. * - * Version: @(#)sio_acc3221.c 1.0.0 2019/04/05 + * * * Authors: Sarah Walker, * diff --git a/src/sio_detect.c b/src/sio_detect.c index 189ef3caf..48588740b 100644 --- a/src/sio_detect.c +++ b/src/sio_detect.c @@ -8,7 +8,7 @@ * * Super I/O chip detection code. * - * Version: @(#)sio_detect.c 1.0.1 2018/11/05 + * * * Authors: Miran Grca, * diff --git a/src/sio_fdc37c669.c b/src/sio_fdc37c669.c index 1bee36e59..fcd4fc04d 100644 --- a/src/sio_fdc37c669.c +++ b/src/sio_fdc37c669.c @@ -8,7 +8,7 @@ * * Implementation of the SMC FDC37C669 Super I/O Chip. * - * Version: @(#)sio_fdc37c669.c 1.0.10 2018/11/05 + * * * Author: Miran Grca, * Copyright 2016-2018 Miran Grca. diff --git a/src/sio_fdc37c66x.c b/src/sio_fdc37c66x.c index 78d49c991..707dc24a1 100644 --- a/src/sio_fdc37c66x.c +++ b/src/sio_fdc37c66x.c @@ -9,7 +9,7 @@ * Implementation of the SMC FDC37C663 and FDC37C665 Super * I/O Chips. * - * Version: @(#)sio_fdc37c66x.c 1.0.15 2020/01/11 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/sio_fdc37c67x.c b/src/sio_fdc37c67x.c index 3560f8fde..6e51d5028 100644 --- a/src/sio_fdc37c67x.c +++ b/src/sio_fdc37c67x.c @@ -11,7 +11,7 @@ * Winbond W83977F Super I/O Chip * Used by the Award 430TX * - * Version: @(#)sio_w83977f.c 1.0.0 2020/01/24 + * * * Author: Miran Grca, * Copyright 2016-2020 Miran Grca. diff --git a/src/sio_fdc37c93x.c b/src/sio_fdc37c93x.c index f34bc7e8e..0342833e7 100644 --- a/src/sio_fdc37c93x.c +++ b/src/sio_fdc37c93x.c @@ -9,7 +9,7 @@ * Implementation of the SMC FDC37C932FR and FDC37C935 Super * I/O Chips. * - * Version: @(#)sio_fdc37c93x.c 1.0.15 2018/11/12 + * * * Author: Miran Grca, * Copyright 2016-2018 Miran Grca. diff --git a/src/sio_pc87306.c b/src/sio_pc87306.c index 7b9a733b6..315f44e9e 100644 --- a/src/sio_pc87306.c +++ b/src/sio_pc87306.c @@ -8,7 +8,7 @@ * * Emulation of the NatSemi PC87306 Super I/O chip. * - * Version: @(#)sio_pc87306.c 1.0.15 2018/11/12 + * * * Author: Miran Grca, * Copyright 2016-2018 Miran Grca. diff --git a/src/sio_w83787f.c b/src/sio_w83787f.c index df77b5062..20603db8c 100644 --- a/src/sio_w83787f.c +++ b/src/sio_w83787f.c @@ -11,7 +11,7 @@ * Winbond W83787F Super I/O Chip * Used by the Award 430HX * - * Version: @(#)sio_w83787f.c 1.0.0 2020/01/11 + * * * Author: Miran Grca, * Copyright 2020 Miran Grca. diff --git a/src/sio_w83877f.c b/src/sio_w83877f.c index c9304e7db..a6d093da3 100644 --- a/src/sio_w83877f.c +++ b/src/sio_w83877f.c @@ -11,7 +11,7 @@ * Winbond W83877F Super I/O Chip * Used by the Award 430HX * - * Version: @(#)sio_w83877f.c 1.0.17 2020/01/25 + * * * Author: Miran Grca, * Copyright 2016-2020 Miran Grca. diff --git a/src/sio_w83977f.c b/src/sio_w83977f.c index 770ce2c7a..401665dee 100644 --- a/src/sio_w83977f.c +++ b/src/sio_w83977f.c @@ -11,7 +11,7 @@ * Winbond W83977F Super I/O Chip * Used by the Award 430TX * - * Version: @(#)sio_w83977f.c 1.0.0 2020/01/24 + * * * Author: Miran Grca, * Copyright 2016-2020 Miran Grca. diff --git a/src/smbus.c b/src/smbus.c index 171d4fad5..b436be703 100644 --- a/src/smbus.c +++ b/src/smbus.c @@ -8,7 +8,7 @@ * * Implement SMBus (System Management Bus) and its operations. * - * Version: @(#)smbus.c 1.0.0 2020/03/21 + * * * Authors: RichardG, * diff --git a/src/smbus.h b/src/smbus.h index a4fec4a5c..058b70ffc 100644 --- a/src/smbus.h +++ b/src/smbus.h @@ -8,7 +8,7 @@ * * Definitions for the SMBus handler. * - * Version: @(#)smbus.h 1.0.0 2020/03/21 + * * * Authors: RichardG, * diff --git a/src/sound/midi.c b/src/sound/midi.c index 3c7da9966..35483e323 100644 --- a/src/sound/midi.c +++ b/src/sound/midi.c @@ -8,7 +8,7 @@ * * MIDI device core module. * - * Version: @(#)midi.c 1.0.3 2020/01/19 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/sound/openal.c b/src/sound/openal.c index ad0d5f957..c63baceec 100644 --- a/src/sound/openal.c +++ b/src/sound/openal.c @@ -8,7 +8,7 @@ * * Interface to the OpenAL sound processing library. * - * Version: @(#)openal.c 1.0.7 2019/10/31 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/sound/snd_mpu401.c b/src/sound/snd_mpu401.c index bdea9d911..51762f1df 100644 --- a/src/sound/snd_mpu401.c +++ b/src/sound/snd_mpu401.c @@ -8,7 +8,7 @@ * * Roland MPU-401 emulation. * - * Version: @(#)snd_mpu401.c 1.0.20 2020/01/23 + * * * Authors: Sarah Walker, * DOSBox Team, diff --git a/src/sound/snd_mpu401.h b/src/sound/snd_mpu401.h index 99fe8b288..0a6dc5d1b 100644 --- a/src/sound/snd_mpu401.h +++ b/src/sound/snd_mpu401.h @@ -8,7 +8,7 @@ * * Roland MPU-401 emulation. * - * Version: @(#)sound_mpu401.h 1.0.5 2020/01/19 + * * * Author: Sarah Walker, * DOSBox Team, diff --git a/src/sound/snd_sb.c b/src/sound/snd_sb.c index 25ed6b87d..464c92b13 100644 --- a/src/sound/snd_sb.c +++ b/src/sound/snd_sb.c @@ -8,7 +8,7 @@ * * Sound Blaster emulation. * - * Version: @(#)sound_sb.c 1.0.17 2020/01/19 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/sound/snd_speaker.c b/src/sound/snd_speaker.c index 9423966db..763116200 100644 --- a/src/sound/snd_speaker.c +++ b/src/sound/snd_speaker.c @@ -8,7 +8,7 @@ * * Emulation of the PC speaker. * - * Version: @(#)snd_speaker.c 1.0.1 2019/11/15 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/sound/snd_speaker.h b/src/sound/snd_speaker.h index c27869f64..91e3edfe3 100644 --- a/src/sound/snd_speaker.h +++ b/src/sound/snd_speaker.h @@ -8,7 +8,7 @@ * * Header of the emulation of the PC speaker. * - * Version: @(#)snd_speaker.h 1.0.0 2019/11/15 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/sound/snd_wss.c b/src/sound/snd_wss.c index 5de5674b9..ec81b50d4 100644 --- a/src/sound/snd_wss.c +++ b/src/sound/snd_wss.c @@ -8,7 +8,7 @@ * * Windows Sound System emulation. * - * Version: @(#)snd_wss.c 1.0.0 2018/08/11 + * * * Authors: Sarah Walker, * TheCollector1995, diff --git a/src/sound/sound.c b/src/sound/sound.c index df17cb865..42130d353 100644 --- a/src/sound/sound.c +++ b/src/sound/sound.c @@ -8,7 +8,7 @@ * * Sound emulation core. * - * Version: @(#)sound.c 1.0.28 2020/01/19 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/sound/sound.h b/src/sound/sound.h index 34f5d0ca9..8f75d0834 100644 --- a/src/sound/sound.h +++ b/src/sound/sound.h @@ -8,7 +8,7 @@ * * Sound emulation core. * - * Version: @(#)sound.h 1.0.8 2018/10/26 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/sst_flash.c b/src/sst_flash.c index 7cb3e3292..c6a4c8471 100644 --- a/src/sst_flash.c +++ b/src/sst_flash.c @@ -8,7 +8,7 @@ * * Implementation of an SST flash chip. * - * Version: @(#)sst_flash.c 1.0.1 2020/02/03 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/sst_flash.h b/src/sst_flash.h index 32607661c..f473d4d33 100644 --- a/src/sst_flash.h +++ b/src/sst_flash.h @@ -8,7 +8,7 @@ * * Implementation of an SST flash chip. * - * Version: @(#)sst_flash.h 1.0.4 2020/02/03 + * * * Author: Melissa Goad, * Copyright 2020 Melissa Goad. diff --git a/src/ui.h b/src/ui.h index 4c66d218b..88623f13e 100644 --- a/src/ui.h +++ b/src/ui.h @@ -8,7 +8,7 @@ * * Define the various UI functions. * - * Version: @(#)ui.h 1.0.16 2019/09/22 + * * * Authors: Miran Grca, * Fred N. van Kempen, diff --git a/src/via_vt82c586b.c b/src/via_vt82c586b.c index 3e2887ecc..9b7d7c074 100644 --- a/src/via_vt82c586b.c +++ b/src/via_vt82c586b.c @@ -6,7 +6,7 @@ * * Emulation of the VIA Apollo MVP3 southbridge * - * Version: @(#)via_vt82c586b.c 1.0.2 2020/01/26 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/via_vt82c586b.h b/src/via_vt82c586b.h index c2fd06a57..8f26a474d 100644 --- a/src/via_vt82c586b.h +++ b/src/via_vt82c586b.h @@ -6,7 +6,7 @@ * * Emulation of the VIA Apollo MVP3 southbridge * - * Version: @(#)via_vt82c586b.c 1.0.0 2020/01/14 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/video/vid_ati18800.c b/src/video/vid_ati18800.c index 2a4f9380d..ac39efb64 100644 --- a/src/video/vid_ati18800.c +++ b/src/video/vid_ati18800.c @@ -8,7 +8,7 @@ * * ATI 18800 emulation (VGA Edge-16) * - * Version: @(#)vid_ati18800.c 1.0.17 2020/01/20 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/video/vid_ati28800.c b/src/video/vid_ati28800.c index 29dd9cc4f..60a622980 100644 --- a/src/video/vid_ati28800.c +++ b/src/video/vid_ati28800.c @@ -8,7 +8,7 @@ * * ATI 28800 emulation (VGA Charger and Korean VGA) * - * Version: @(#)vid_ati28800.c 1.0.27 2019/05/17 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/video/vid_ati68860_ramdac.c b/src/video/vid_ati68860_ramdac.c index e0af06b45..cdca9ab52 100644 --- a/src/video/vid_ati68860_ramdac.c +++ b/src/video/vid_ati68860_ramdac.c @@ -28,7 +28,7 @@ * 7 If set can remove "snow" in some cases * (A860_Delay_L ?) ?? * - * Version: @(#)vid_ati68860.c 1.0.5 2018/10/04 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/video/vid_ati_eeprom.c b/src/video/vid_ati_eeprom.c index ea499788d..2ebb42af6 100644 --- a/src/video/vid_ati_eeprom.c +++ b/src/video/vid_ati_eeprom.c @@ -8,7 +8,7 @@ * * Emulation of the EEPROM on select ATI cards. * - * Version: @(#)vid_ati_eeprom.c 1.0.3 2020/01/20 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/video/vid_ati_mach64.c b/src/video/vid_ati_mach64.c index 576b2c774..8552c0e52 100644 --- a/src/video/vid_ati_mach64.c +++ b/src/video/vid_ati_mach64.c @@ -8,7 +8,7 @@ * * ATi Mach64 graphics card emulation. * - * Version: @(#)vid_ati_mach64.c 1.0.27 2019/09/28 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/video/vid_att20c49x_ramdac.c b/src/video/vid_att20c49x_ramdac.c index bce0a21c9..6bfa8a6e3 100644 --- a/src/video/vid_att20c49x_ramdac.c +++ b/src/video/vid_att20c49x_ramdac.c @@ -8,7 +8,7 @@ * * Emulation of a AT&T 20c490/491 and 492/493 RAMDAC. * - * Version: @(#)vid_att20c49x_ramdac.c 1.0.1 2019/01/12 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/video/vid_av9194.c b/src/video/vid_av9194.c index bc48c08b7..8f372eda6 100644 --- a/src/video/vid_av9194.c +++ b/src/video/vid_av9194.c @@ -10,7 +10,7 @@ * * Used by the S3 86c801 (V7-Mirage) card. * - * Version: @(#)vid_av9194.c 1.0.1 2019/01/12 + * * * Authors: Miran Grca, * diff --git a/src/video/vid_bt48x_ramdac.c b/src/video/vid_bt48x_ramdac.c index 20baf13eb..f1a396034 100644 --- a/src/video/vid_bt48x_ramdac.c +++ b/src/video/vid_bt48x_ramdac.c @@ -9,7 +9,7 @@ * Emulation of the Brooktree BT484-485A true colour RAMDAC * family. * - * Version: @(#)vid_bt48x_ramdac.c 1.0.16 2019/01/12 + * * * Authors: Miran Grca, * TheCollector1995, diff --git a/src/video/vid_cga.c b/src/video/vid_cga.c index 91f04501b..d1e9e22ae 100644 --- a/src/video/vid_cga.c +++ b/src/video/vid_cga.c @@ -8,7 +8,7 @@ * * Emulation of the old and new IBM CGA graphics cards. * - * Version: @(#)vid_cga.c 1.0.20 2019/09/29 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/video/vid_cga.h b/src/video/vid_cga.h index aa37f7fad..708879fdd 100644 --- a/src/video/vid_cga.h +++ b/src/video/vid_cga.h @@ -8,7 +8,7 @@ * * Emulation of the old and new IBM CGA graphics cards. * - * Version: @(#)vid_cga.h 1.0.4 2018/10/02 + * * * Author: Sarah Walker, * Miran Grca, diff --git a/src/video/vid_cga_comp.c b/src/video/vid_cga_comp.c index 0d4d5a0a5..6ae084e4c 100644 --- a/src/video/vid_cga_comp.c +++ b/src/video/vid_cga_comp.c @@ -9,7 +9,7 @@ * IBM CGA composite filter, borrowed from reenigne's DOSBox * patch and ported to C. * - * Version: @(#)vid_cga_comp.c 1.0.5 2019/03/24 + * * * Authors: reenigne, * Miran Grca, diff --git a/src/video/vid_cga_comp.h b/src/video/vid_cga_comp.h index fc19ae252..5ce52e61a 100644 --- a/src/video/vid_cga_comp.h +++ b/src/video/vid_cga_comp.h @@ -9,7 +9,7 @@ * IBM CGA composite filter, borrowed from reenigne's DOSBox * patch and ported to C. * - * Version: @(#)vid_cga.h 1.0.1 2018/03/24 + * * * Author: reenigne, * Miran Grca, diff --git a/src/video/vid_cl54xx.c b/src/video/vid_cl54xx.c index 4b3df6ddc..61d1d7cc5 100644 --- a/src/video/vid_cl54xx.c +++ b/src/video/vid_cl54xx.c @@ -9,7 +9,7 @@ * Emulation of select Cirrus Logic cards (CL-GD 5428, * CL-GD 5429, CL-GD 5430, CL-GD 5434 and CL-GD 5436 are supported). * - * Version: @(#)vid_cl_54xx.c 1.0.34 2020/03/23 + * * * Authors: TheCollector1995, * Miran Grca, diff --git a/src/video/vid_colorplus.c b/src/video/vid_colorplus.c index 93fad1cc8..e281100ed 100644 --- a/src/video/vid_colorplus.c +++ b/src/video/vid_colorplus.c @@ -8,7 +8,7 @@ * * Plantronics ColorPlus emulation. * - * Version: @(#)vid_colorplus.c 1.0.10 2018/09/19 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/video/vid_compaq_cga.c b/src/video/vid_compaq_cga.c index d6bf29a72..f4d5b89aa 100644 --- a/src/video/vid_compaq_cga.c +++ b/src/video/vid_compaq_cga.c @@ -8,7 +8,7 @@ * * Emulation of the Compaq CGA graphics cards. * - * Version: @(#)vid_compaq_cga.c 1.0.0 2019/01/02 + * * * Authors: John Elliott, * Sarah Walker, diff --git a/src/video/vid_ega.c b/src/video/vid_ega.c index 0b8753bd1..0f793f7bc 100644 --- a/src/video/vid_ega.c +++ b/src/video/vid_ega.c @@ -9,7 +9,7 @@ * Emulation of the EGA and Chips & Technologies SuperEGA * graphics cards. * - * Version: @(#)vid_ega.c 1.0.24 2019/11/20 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/video/vid_ega.h b/src/video/vid_ega.h index 170a91090..caa7c0822 100644 --- a/src/video/vid_ega.h +++ b/src/video/vid_ega.h @@ -9,7 +9,7 @@ * Emulation of the EGA and Chips & Technologies SuperEGA * graphics cards. * - * Version: @(#)vid_ega.h 1.0.9 2020/01/20 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/video/vid_ega_render.c b/src/video/vid_ega_render.c index 471d3c531..45a86346f 100644 --- a/src/video/vid_ega_render.c +++ b/src/video/vid_ega_render.c @@ -8,7 +8,7 @@ * * EGA renderers. * - * Version: @(#)vid_ega_render.c 1.0.7 2019/11/19 + * * * Author: Sarah Walker, * Miran Grca, diff --git a/src/video/vid_et4000.c b/src/video/vid_et4000.c index ad4bd13a9..0c1e67478 100644 --- a/src/video/vid_et4000.c +++ b/src/video/vid_et4000.c @@ -8,7 +8,7 @@ * * Emulation of the Tseng Labs ET4000. * - * Version: @(#)vid_et4000.c 1.0.20 2018/10/04e + * * * Authors: Fred N. van Kempen, * Miran Grca, diff --git a/src/video/vid_et4000w32.c b/src/video/vid_et4000w32.c index ccd8a6aee..b6e71ae1c 100644 --- a/src/video/vid_et4000w32.c +++ b/src/video/vid_et4000w32.c @@ -10,7 +10,7 @@ * * Known bugs: Accelerator doesn't work in planar modes * - * Version: @(#)vid_et4000w32.c 1.0.22 2019/09/28 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/video/vid_genius.c b/src/video/vid_genius.c index 9f76ada3e..7d3c0bef7 100644 --- a/src/video/vid_genius.c +++ b/src/video/vid_genius.c @@ -8,7 +8,7 @@ * * MDSI Genius VHR emulation. * - * Version: @(#)vid_genius.c 1.0.12 2019/03/17 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/video/vid_hercules.c b/src/video/vid_hercules.c index 15538431f..8f14670ac 100644 --- a/src/video/vid_hercules.c +++ b/src/video/vid_hercules.c @@ -8,7 +8,7 @@ * * Hercules emulation. * - * Version: @(#)vid_hercules.c 1.0.17 2019/02/07 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/video/vid_herculesplus.c b/src/video/vid_herculesplus.c index fc4f0ad97..b24688f06 100644 --- a/src/video/vid_herculesplus.c +++ b/src/video/vid_herculesplus.c @@ -8,7 +8,7 @@ * * Hercules Plus emulation. * - * Version: @(#)vid_herculesplus.c 1.0.15 2019/02/07 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/video/vid_ht216.c b/src/video/vid_ht216.c index bb7be328c..ad291294e 100644 --- a/src/video/vid_ht216.c +++ b/src/video/vid_ht216.c @@ -8,7 +8,7 @@ * * Video 7 VGA 1024i emulation. * - * Version: @(#)vid_ht216.c 1.0.3 2019/12/04 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/video/vid_icd2061.c b/src/video/vid_icd2061.c index 7dbe9d3ca..57b791f69 100644 --- a/src/video/vid_icd2061.c +++ b/src/video/vid_icd2061.c @@ -14,7 +14,7 @@ * Used by ET4000w32/p (Diamond Stealth 32) and the S3 * Vision964 family. * - * Version: @(#)vid_icd2061.c 1.0.8 2018/10/04 + * * * Authors: Miran Grca, * diff --git a/src/video/vid_ics2595.c b/src/video/vid_ics2595.c index 374dda318..2f5dffdfe 100644 --- a/src/video/vid_ics2595.c +++ b/src/video/vid_ics2595.c @@ -8,7 +8,7 @@ * * ICS2595 clock chip emulation. Used by ATI Mach64. * - * Version: @(#)vid_ics2595.c 1.0.3 2018/10/04 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/video/vid_im1024.c b/src/video/vid_im1024.c index 301c0fd6e..7ea42375f 100644 --- a/src/video/vid_im1024.c +++ b/src/video/vid_im1024.c @@ -38,7 +38,7 @@ * This is implemented by holding a FIFO of unlimited depth in * the IM1024 to receive the data. * - * Version: @(#)vid_im1024.c 1.0.4 2019/11/04 + * * * Authors: Fred N. van Kempen, * John Elliott, diff --git a/src/video/vid_incolor.c b/src/video/vid_incolor.c index d2373a836..a438fcfb4 100644 --- a/src/video/vid_incolor.c +++ b/src/video/vid_incolor.c @@ -8,7 +8,7 @@ * * Hercules InColor emulation. * - * Version: @(#)vid_incolor.c 1.0.14 2019/02/08 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/video/vid_mda.c b/src/video/vid_mda.c index 5e8abac8d..dbeeaa2c1 100644 --- a/src/video/vid_mda.c +++ b/src/video/vid_mda.c @@ -8,7 +8,7 @@ * * MDA emulation. * - * Version: @(#)vid_mda.c 1.0.14 2019/11/24 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/video/vid_mga.c b/src/video/vid_mga.c index fd27f7a54..437d17b65 100644 --- a/src/video/vid_mga.c +++ b/src/video/vid_mga.c @@ -8,7 +8,7 @@ * * Matrox MGA graphics card emulation. * - * Version: @(#)vid_mga.c 1.0.3 2020/01/20 + * * * Author: Sarah Walker, * Copyright 2008-2020 Sarah Walker. diff --git a/src/video/vid_oak_oti.c b/src/video/vid_oak_oti.c index 09e56cb10..562674b33 100644 --- a/src/video/vid_oak_oti.c +++ b/src/video/vid_oak_oti.c @@ -8,7 +8,7 @@ * * Oak OTI037C/67/077 emulation. * - * Version: @(#)vid_oak_oti.c 1.0.18 2018/10/09 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/video/vid_paradise.c b/src/video/vid_paradise.c index ad05e824b..818ba182c 100644 --- a/src/video/vid_paradise.c +++ b/src/video/vid_paradise.c @@ -10,7 +10,7 @@ * PC2086, PC3086 use PVGA1A * MegaPC uses W90C11A * - * Version: @(#)vid_paradise.c 1.0.9 2019/03/23 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/video/vid_pgc.c b/src/video/vid_pgc.c index 3db6b4521..724c1fd85 100644 --- a/src/video/vid_pgc.c +++ b/src/video/vid_pgc.c @@ -44,7 +44,7 @@ * * This is expected to be done shortly. * - * Version: @(#)vid_pgc.c 1.0.5 2019/11/04 + * * * Authors: Fred N. van Kempen, * John Elliott, diff --git a/src/video/vid_pgc.h b/src/video/vid_pgc.h index d1e8c4ffa..1a179a775 100644 --- a/src/video/vid_pgc.h +++ b/src/video/vid_pgc.h @@ -8,7 +8,7 @@ * * Definitions for the PGC driver. * - * Version: @(#)vid_pgc.h 1.0.2 2019/03/03 + * * * Authors: Fred N. van Kempen, * John Elliott, diff --git a/src/video/vid_pgc_palette.h b/src/video/vid_pgc_palette.h index dd89a58dc..ccc9ac2bd 100644 --- a/src/video/vid_pgc_palette.h +++ b/src/video/vid_pgc_palette.h @@ -8,7 +8,7 @@ * * Palette definitions for the PGC core. * - * Version: @(#)vid_pgc_palette.h 1.0.1 2019/03/01 + * * * Authors: Fred N. van Kempen, * John Elliott, diff --git a/src/video/vid_s3.c b/src/video/vid_s3.c index 60d3a5f4b..96e3b00fe 100644 --- a/src/video/vid_s3.c +++ b/src/video/vid_s3.c @@ -8,7 +8,7 @@ * * S3 emulation. * - * Version: @(#)vid_s3.c 1.0.28 2019/10/31 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/video/vid_s3_virge.c b/src/video/vid_s3_virge.c index 358c3c749..b1534b57f 100644 --- a/src/video/vid_s3_virge.c +++ b/src/video/vid_s3_virge.c @@ -8,7 +8,7 @@ * * S3 ViRGE emulation. * - * Version: @(#)vid_s3_virge.c 1.0.17 2018/10/27 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/video/vid_sc1502x_ramdac.c b/src/video/vid_sc1502x_ramdac.c index 882f892b0..1908d624e 100644 --- a/src/video/vid_sc1502x_ramdac.c +++ b/src/video/vid_sc1502x_ramdac.c @@ -10,7 +10,7 @@ * * Used by the TLIVESA1 driver for ET4000. * - * Version: @(#)vid_sc1502x_ramdac.c 1.0.3 2018/10/04 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/video/vid_sdac_ramdac.c b/src/video/vid_sdac_ramdac.c index 498daf432..767e16d78 100644 --- a/src/video/vid_sdac_ramdac.c +++ b/src/video/vid_sdac_ramdac.c @@ -8,7 +8,7 @@ * * 87C716 'SDAC' true colour RAMDAC emulation. * - * Version: @(#)vid_sdac_ramdac.c 1.0.6 2019/09/13 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/video/vid_sigma.c b/src/video/vid_sigma.c index 7193783f1..81c6c7e11 100644 --- a/src/video/vid_sigma.c +++ b/src/video/vid_sigma.c @@ -8,7 +8,7 @@ * * Sigma Color 400 emulation. * - * Version: @(#)vid_sigma.c 1.0.5 2019/11/08 + * * * Authors: John Elliott, * diff --git a/src/video/vid_stg_ramdac.c b/src/video/vid_stg_ramdac.c index 4900ff5b8..d03485346 100644 --- a/src/video/vid_stg_ramdac.c +++ b/src/video/vid_stg_ramdac.c @@ -8,7 +8,7 @@ * * STG1702 true colour RAMDAC emulation. * - * Version: @(#)vid_stg_ramdac.c 1.0.5 2018/10/04 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/video/vid_svga.c b/src/video/vid_svga.c index efceec413..a16c65bf2 100644 --- a/src/video/vid_svga.c +++ b/src/video/vid_svga.c @@ -11,7 +11,7 @@ * This is intended to be used by another SVGA driver, * and not as a card in it's own right. * - * Version: @(#)vid_svga.c 1.0.42 2020/01/20 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/video/vid_svga.h b/src/video/vid_svga.h index d2076c2eb..7adfff274 100644 --- a/src/video/vid_svga.h +++ b/src/video/vid_svga.h @@ -8,7 +8,7 @@ * * Generic SVGA handling. * - * Version: @(#)vid_svga.h 1.0.16 2020/01/18 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/video/vid_svga_render.c b/src/video/vid_svga_render.c index 499c02f91..812d25d74 100644 --- a/src/video/vid_svga_render.c +++ b/src/video/vid_svga_render.c @@ -8,7 +8,7 @@ * * SVGA renderers. * - * Version: @(#)vid_svga_render.c 1.0.14 2019/11/19 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/video/vid_svga_render.h b/src/video/vid_svga_render.h index a99e25e16..6b8b50613 100644 --- a/src/video/vid_svga_render.h +++ b/src/video/vid_svga_render.h @@ -8,7 +8,7 @@ * * SVGA renderers. * - * Version: @(#)vid_svga_render.h 1.0.1 2018/03/12 + * * * Author: Sarah Walker, * Miran Grca, diff --git a/src/video/vid_table.c b/src/video/vid_table.c index e5db46fd0..becbef0db 100644 --- a/src/video/vid_table.c +++ b/src/video/vid_table.c @@ -8,7 +8,7 @@ * * Define all known video cards. * - * Version: @(#)vid_table.c 1.0.49 2020/01/22 + * * * Authors: Miran Grca, * Fred N. van Kempen, diff --git a/src/video/vid_tgui9440.c b/src/video/vid_tgui9440.c index 3290d25cf..e8fd94333 100644 --- a/src/video/vid_tgui9440.c +++ b/src/video/vid_tgui9440.c @@ -47,7 +47,7 @@ * access size or host data has any affect, but the Windows 3.1 * driver always reads bytes and write words of 0xffff. * - * Version: @(#)vid_tgui9440.c 1.0.10 2019/09/28 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/video/vid_ti_cf62011.c b/src/video/vid_ti_cf62011.c index dde469ba7..4b46e42ea 100644 --- a/src/video/vid_ti_cf62011.c +++ b/src/video/vid_ti_cf62011.c @@ -42,7 +42,7 @@ * which are the same as the XGA. It supports up to 1MB of VRAM, * but we lock it down to 512K. The PS/1 2122 had 256K. * - * Version: @(#)vid_ti_cf62011.c 1.0.9 2018/10/02 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/video/vid_tkd8001_ramdac.c b/src/video/vid_tkd8001_ramdac.c index 26118f1a4..2dc09606a 100644 --- a/src/video/vid_tkd8001_ramdac.c +++ b/src/video/vid_tkd8001_ramdac.c @@ -8,7 +8,7 @@ * * Trident TKD8001 RAMDAC emulation. * - * Version: @(#)vid_tkd8001_ramdac.c 1.0.3 2018/10/04 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/video/vid_tvga.c b/src/video/vid_tvga.c index 301e03816..9548cb37d 100644 --- a/src/video/vid_tvga.c +++ b/src/video/vid_tvga.c @@ -8,7 +8,7 @@ * * Trident TVGA (8900D) emulation. * - * Version: @(#)vid_tvga.c 1.0.9 2018/12/28 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/video/vid_vga.c b/src/video/vid_vga.c index e38afa6d7..340d6572a 100644 --- a/src/video/vid_vga.c +++ b/src/video/vid_vga.c @@ -8,7 +8,7 @@ * * IBM VGA emulation. * - * Version: @(#)vid_vga.c 1.0.6 2018/09/19 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/video/vid_voodoo.c b/src/video/vid_voodoo.c index e3c0d91a6..37afe78db 100644 --- a/src/video/vid_voodoo.c +++ b/src/video/vid_voodoo.c @@ -8,7 +8,7 @@ * * Emulation of the 3DFX Voodoo Graphics controller. * - * Version: @(#)vid_voodoo.c 1.0.15 2018/10/18 + * * * Authors: Sarah Walker, * leilei diff --git a/src/video/vid_wy700.c b/src/video/vid_wy700.c index 00fb1b822..db26ee07c 100644 --- a/src/video/vid_wy700.c +++ b/src/video/vid_wy700.c @@ -8,7 +8,7 @@ * * Wyse-700 emulation. * - * Version: @(#)vid_wy700.c 1.0.10 2018/09/19 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/video/video.c b/src/video/video.c index d3ed0794b..788f165ce 100644 --- a/src/video/video.c +++ b/src/video/video.c @@ -40,7 +40,7 @@ * W = 3 bus clocks * L = 4 bus clocks * - * Version: @(#)video.c 1.0.35 2019/12/06 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/video/video.h b/src/video/video.h index fad5359d4..3232c6908 100644 --- a/src/video/video.h +++ b/src/video/video.h @@ -8,7 +8,7 @@ * * Definitions for the video controller module. * - * Version: @(#)video.h 1.0.37 2019/12/06 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/vnc.c b/src/vnc.c index 143b60964..86534a11f 100644 --- a/src/vnc.c +++ b/src/vnc.c @@ -8,7 +8,7 @@ * * Implement the VNC remote renderer with LibVNCServer. * - * Version: @(#)vnc.c 1.0.15 2019/12/06 + * * * Authors: Fred N. van Kempen, * Based on raw code by RichardG, diff --git a/src/vnc.h b/src/vnc.h index c8c3a3f8a..2d3dea3cd 100644 --- a/src/vnc.h +++ b/src/vnc.h @@ -8,7 +8,7 @@ * * Definitions for the VNC renderer. * - * Version: @(#)vnc.h 1.0.4 2017/10/22 + * * * Author: Fred N. van Kempen, * diff --git a/src/vnc_keymap.c b/src/vnc_keymap.c index d8b453066..86a323cc2 100644 --- a/src/vnc_keymap.c +++ b/src/vnc_keymap.c @@ -22,7 +22,7 @@ * NOTE: The values are as defined in the Microsoft document named * "Keyboard Scan Code Specification", version 1.3a of 2000/03/16. * - * Version: @(#)vnc_keymap.c 1.0.4 2019/03/24 + * * * Authors: Fred N. van Kempen, * Based on raw code by RichardG, diff --git a/src/win/86Box.rc b/src/win/86Box.rc index fe204a04b..6f180a212 100644 --- a/src/win/86Box.rc +++ b/src/win/86Box.rc @@ -8,7 +8,7 @@ * * Application resource script for Windows. * - * Version: @(#)86Box.rc 1.0.56 2019/12/21 + * * * Authors: Miran Grca, * Fred N. van Kempen, diff --git a/src/win/plat_dir.h b/src/win/plat_dir.h index 6eb372aa0..948db8c84 100644 --- a/src/win/plat_dir.h +++ b/src/win/plat_dir.h @@ -8,7 +8,7 @@ * * Definitions for the platform OpenDir module. * - * Version: @(#)plat_dir.h 1.0.1 2017/05/17 + * * * Author: Fred N. van Kempen, * Copyright 2017 Fred N. van Kempen. diff --git a/src/win/resource.h b/src/win/resource.h index c4ffc2728..55e906960 100644 --- a/src/win/resource.h +++ b/src/win/resource.h @@ -8,7 +8,7 @@ * * Windows resource defines. * - * Version: @(#)resource.h 1.0.32 2019/12/21 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/win/win.c b/src/win/win.c index 4197edd4c..6fadcc591 100644 --- a/src/win/win.c +++ b/src/win/win.c @@ -8,7 +8,7 @@ * * Platform main support module for Windows. * - * Version: @(#)win.c 1.0.60 2019/12/05 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/win/win.h b/src/win/win.h index 6c8444a33..62f0062e6 100644 --- a/src/win/win.h +++ b/src/win/win.h @@ -8,7 +8,7 @@ * * Platform support defintions for Win32. * - * Version: @(#)win.h 1.0.29 2019/12/05 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/win/win_about.c b/src/win/win_about.c index b714cf334..68c215394 100644 --- a/src/win/win_about.c +++ b/src/win/win_about.c @@ -8,7 +8,7 @@ * * Handle the About dialog. * - * Version: @(#)win_about.c 1.0.7 2018/06/02 + * * * Authors: Miran Grca, * Fred N. van Kempen, diff --git a/src/win/win_cdrom.c b/src/win/win_cdrom.c index e808ced53..8802615c6 100644 --- a/src/win/win_cdrom.c +++ b/src/win/win_cdrom.c @@ -8,7 +8,7 @@ * * Handle the platform-side of CDROM drives. * - * Version: @(#)win_cdrom.c 1.0.12 2018/10/26 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/win/win_crashdump.c b/src/win/win_crashdump.c index cbec1b680..d7b4cd38b 100644 --- a/src/win/win_crashdump.c +++ b/src/win/win_crashdump.c @@ -8,7 +8,7 @@ * * Handle generation of crash-dump reports. * - * Version: @(#)win_crashdump.c 1.0.3 2017/12/13 + * * * Authors: Riley * Miran Grca, diff --git a/src/win/win_d2d.c b/src/win/win_d2d.c index 45ff1e83b..bda8d0eb2 100644 --- a/src/win/win_d2d.c +++ b/src/win/win_d2d.c @@ -8,7 +8,7 @@ * * Rendering module for Microsoft Direct2D. * - * Version: @(#)win_d2d.c 1.0.7 2019/12/13 + * * * Authors: David Hrdlička, * diff --git a/src/win/win_d2d.h b/src/win/win_d2d.h index cc3fe4881..06d6356fa 100644 --- a/src/win/win_d2d.h +++ b/src/win/win_d2d.h @@ -8,7 +8,7 @@ * * Definitions for the Direct2D rendering module. * - * Version: @(#)win_d2d.h 1.0.2 2019/12/13 + * * * Authors: David Hrdlička, * diff --git a/src/win/win_devconf.c b/src/win/win_devconf.c index fa925eb33..0146be57d 100644 --- a/src/win/win_devconf.c +++ b/src/win/win_devconf.c @@ -8,7 +8,7 @@ * * Windows device configuration dialog implementation. * - * Version: @(#)win_devconf.c 1.0.20 2018/10/23 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/win/win_dialog.c b/src/win/win_dialog.c index 5d867f67f..f5bfd3c56 100644 --- a/src/win/win_dialog.c +++ b/src/win/win_dialog.c @@ -8,7 +8,7 @@ * * Several dialogs for the application. * - * Version: @(#)win_dialog.c 1.0.11 2019/09/22 + * * * Author: Miran Grca, * Fred N. van Kempen, diff --git a/src/win/win_discord.c b/src/win/win_discord.c index 04253b5b6..087fad7b5 100644 --- a/src/win/win_discord.c +++ b/src/win/win_discord.c @@ -8,7 +8,7 @@ * * Discord integration module. * - * Version: @(#)win_discord.c 1.0.0 2019/12/05 + * * * Authors: David Hrdlička, * diff --git a/src/win/win_discord.h b/src/win/win_discord.h index 944ac8ff2..9e56b9a32 100644 --- a/src/win/win_discord.h +++ b/src/win/win_discord.h @@ -8,7 +8,7 @@ * * Definitions for the Discord integration module. * - * Version: @(#)win_discord.h 1.0.0 2019/12/05 + * * * Authors: David Hrdlička, * diff --git a/src/win/win_dynld.c b/src/win/win_dynld.c index b5e89aaff..4ae3b8b70 100644 --- a/src/win/win_dynld.c +++ b/src/win/win_dynld.c @@ -8,7 +8,7 @@ * * Try to load a support DLL. * - * Version: @(#)win_dynld.c 1.0.8 2018/10/18 + * * * Author: Fred N. van Kempen, * diff --git a/src/win/win_joystick.cpp b/src/win/win_joystick.cpp index 437b506e6..d2e569cb4 100644 --- a/src/win/win_joystick.cpp +++ b/src/win/win_joystick.cpp @@ -8,7 +8,7 @@ * * Joystick interface to host device. * - * Version: @(#)win_joystick.cpp 1.0.12 2019/10/23 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/win/win_joystick_xinput.cpp b/src/win/win_joystick_xinput.cpp index 5d3e2fbbb..5fc636580 100644 --- a/src/win/win_joystick_xinput.cpp +++ b/src/win/win_joystick_xinput.cpp @@ -8,7 +8,7 @@ * * Xinput joystick interface. * - * Version: @(#)win_joystick_xinput.cpp 1.0.0 2019/3/19 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/win/win_keyboard.c b/src/win/win_keyboard.c index 8fb761a44..36897c9be 100644 --- a/src/win/win_keyboard.c +++ b/src/win/win_keyboard.c @@ -8,7 +8,7 @@ * * Windows raw keyboard input handler. * - * Version: @(#)win_keyboard.c 1.0.10 2018/04/29 + * * * Author: Miran Grca, * diff --git a/src/win/win_new_floppy.c b/src/win/win_new_floppy.c index bbae1551e..e15a3e342 100644 --- a/src/win/win_new_floppy.c +++ b/src/win/win_new_floppy.c @@ -8,7 +8,7 @@ * * Handle the New Floppy Image dialog. * - * Version: @(#)win_new_floppy.c 1.0.13 2019/11/19 + * * * Authors: Miran Grca, * diff --git a/src/win/win_opendir.c b/src/win/win_opendir.c index 74309eb25..f518ea686 100644 --- a/src/win/win_opendir.c +++ b/src/win/win_opendir.c @@ -10,7 +10,7 @@ * * Based on old original code @(#)dir_win32.c 1.2.0 2007/04/19 * - * Version: @(#)win_opendir.c 1.0.4 2017/11/18 + * * * Author: Fred N. van Kempen, * diff --git a/src/win/win_sdl.c b/src/win/win_sdl.c index f4c415d11..a4c71c033 100644 --- a/src/win/win_sdl.c +++ b/src/win/win_sdl.c @@ -12,7 +12,7 @@ * we will not use that, but, instead, use a new window which * coverrs the entire desktop. * - * Version: @(#)win_sdl.c 1.0.11 2020/01/22 + * * * Authors: Fred N. van Kempen, * Michael Dring, diff --git a/src/win/win_sdl.h b/src/win/win_sdl.h index 896b3b8ef..c157c6f59 100644 --- a/src/win/win_sdl.h +++ b/src/win/win_sdl.h @@ -8,7 +8,7 @@ * * Definitions for the libSDL2 rendering module. * - * Version: @(#)win_sdl.h 1.0.2 2019/12/05 + * * * Authors: Fred N. van Kempen, * Michael Dring, diff --git a/src/win/win_settings.c b/src/win/win_settings.c index 6d5476295..97c1e60e3 100644 --- a/src/win/win_settings.c +++ b/src/win/win_settings.c @@ -8,7 +8,7 @@ * * Windows 86Box Settings dialog handler. * - * Version: @(#)win_settings.c 1.0.63 2019/12/21 + * * * Authors: Miran Grca, * David Hrdlička, diff --git a/src/win/win_snd_gain.c b/src/win/win_snd_gain.c index 7f23a1aee..983c593e8 100644 --- a/src/win/win_snd_gain.c +++ b/src/win/win_snd_gain.c @@ -8,7 +8,7 @@ * * Handle the sound gain dialog. * - * Version: @(#)win_snd_gain.c 1.0.1 2018/02/10 + * * * Authors: Miran Grca, * diff --git a/src/win/win_stbar.c b/src/win/win_stbar.c index 43554f159..ce3f3ae17 100644 --- a/src/win/win_stbar.c +++ b/src/win/win_stbar.c @@ -8,7 +8,7 @@ * * Implement the application's Status Bar. * - * Version: @(#)win_stbar.c 1.0.27 2019/12/06 + * * * Authors: Miran Grca, * Fred N. van Kempen, diff --git a/src/win/win_thread.c b/src/win/win_thread.c index 31a087cab..eb10b54f4 100644 --- a/src/win/win_thread.c +++ b/src/win/win_thread.c @@ -8,7 +8,7 @@ * * Implement threads and mutexes for the Win32 platform. * - * Version: @(#)win_thread.c 1.0.6 2018/03/28 + * * * Authors: Sarah Walker, * Fred N. van Kempen, diff --git a/src/win/win_ui.c b/src/win/win_ui.c index cfe5d37fb..a2216e3c8 100644 --- a/src/win/win_ui.c +++ b/src/win/win_ui.c @@ -8,7 +8,7 @@ * * user Interface module for WinAPI on Windows. * - * Version: @(#)win_ui.c 1.0.46 2020/01/19 + * * * Authors: Sarah Walker, * Miran Grca, diff --git a/src/x87_bak/x87_ops.h b/src/x87_bak/x87_ops.h index 57416251f..44d73a0b1 100644 --- a/src/x87_bak/x87_ops.h +++ b/src/x87_bak/x87_ops.h @@ -8,7 +8,7 @@ * * x87 FPU instructions core. * - * Version: @(#)x87_ops.h 1.0.8 2019/06/11 + * * * Authors: Fred N. van Kempen, * Sarah Walker, diff --git a/src/x87_bak/x87_ops_loadstore.h b/src/x87_bak/x87_ops_loadstore.h index b5ad491f9..925fe87bd 100644 --- a/src/x87_bak/x87_ops_loadstore.h +++ b/src/x87_bak/x87_ops_loadstore.h @@ -8,7 +8,7 @@ * * x87 FPU instructions core. * - * Version: @(#)x87_ops_loadstore.h 1.0.2 2019/06/11 + * * * Author: Sarah Walker, * Miran Grca, From 6f4ac0de350d9d5ece2879adab9e0857a23e9208 Mon Sep 17 00:00:00 2001 From: TC1995 Date: Wed, 25 Mar 2020 00:49:25 +0100 Subject: [PATCH 15/33] Added the Aztech Sound Galaxy 16 cards. Added the reset function of MCA from PCem. Made the MCA devices use the reset parameter if available. --- src/machine/m_ps2_mca.c | 4 +- src/mca.c | 87 ++- src/mca.h | 3 +- src/network/net_ne2000.c | 2 +- src/network/net_wd8003.c | 2 +- src/scsi/scsi_aha154x.c | 2 +- src/scsi/scsi_buslogic.c | 2 +- src/scsi/scsi_spock.c | 3 +- src/sound/snd_ad1848.c | 71 +- src/sound/snd_ad1848.h | 10 +- src/sound/snd_azt2316a.c | 1399 ++++++++++++++++++++++++++++++++++++ src/sound/snd_azt2316a.h | 1 + src/sound/snd_mpu401.c | 7 +- src/sound/snd_mpu401.h | 1 + src/sound/snd_pas16.c | 2 +- src/sound/snd_sb.c | 359 ++++----- src/sound/snd_sb.h | 143 ++++ src/sound/snd_sb_dsp.c | 107 ++- src/sound/snd_sb_dsp.h | 139 ++-- src/sound/snd_wss.c | 132 ++-- src/sound/sound.c | 3 + src/sound/sound.h | 4 + src/video/vid_cl54xx.c | 2 +- src/video/vid_et4000.c | 2 +- src/win/Makefile.mingw | 1 + src/win/Makefile_ndr.mingw | 1 + 26 files changed, 2049 insertions(+), 440 deletions(-) create mode 100644 src/sound/snd_azt2316a.c create mode 100644 src/sound/snd_azt2316a.h create mode 100644 src/sound/snd_sb.h diff --git a/src/machine/m_ps2_mca.c b/src/machine/m_ps2_mca.c index c4b755a6d..9560b50cd 100644 --- a/src/machine/m_ps2_mca.c +++ b/src/machine/m_ps2_mca.c @@ -718,6 +718,8 @@ static void ps2_mca_write(uint16_t port, uint8_t val, void *p) ps2.setup = val; break; case 0x96: + if ((val & 0x80) && !(ps2.adapter_setup & 0x80)) + mca_reset(); ps2.adapter_setup = val; mca_set_index(val & 7); break; @@ -856,7 +858,7 @@ static void ps2_mca_mem_fffc_init(int start_mb) break; } - mca_add(ps2_mem_expansion_read, ps2_mem_expansion_write, ps2_mem_expansion_feedb, NULL); + mca_add(ps2_mem_expansion_read, ps2_mem_expansion_write, ps2_mem_expansion_feedb, NULL, NULL); mem_mapping_add(&ps2.expansion_mapping, expansion_start, (mem_size - (start_mb << 10)) << 10, diff --git a/src/mca.c b/src/mca.c index b9ab31487..d2bd9270f 100644 --- a/src/mca.c +++ b/src/mca.c @@ -9,6 +9,7 @@ void (*mca_card_write[8])(int addr, uint8_t val, void *priv); uint8_t (*mca_card_read[8])(int addr, void *priv); uint8_t (*mca_card_feedb[8])(void *priv); +void (*mca_card_reset[8])(void *priv); void *mca_priv[8]; static int mca_index; @@ -17,62 +18,72 @@ static int mca_nr_cards; void mca_init(int nr_cards) { - int c; + int c; + + for (c = 0; c < 8; c++) { + mca_card_read[c] = NULL; + mca_card_write[c] = NULL; + mca_card_reset[c] = NULL; + mca_priv[c] = NULL; + } - for (c = 0; c < 8; c++) - { - mca_card_read[c] = NULL; - mca_card_write[c] = NULL; - mca_priv[c] = NULL; - } - - mca_index = 0; - mca_nr_cards = nr_cards; + mca_index = 0; + mca_nr_cards = nr_cards; } void mca_set_index(int index) { - mca_index = index; + mca_index = index; } uint8_t mca_read(uint16_t port) { - if (mca_index >= mca_nr_cards) - return 0xff; - if (!mca_card_read[mca_index]) - return 0xff; - return mca_card_read[mca_index](port, mca_priv[mca_index]); + if (mca_index >= mca_nr_cards) + return 0xff; + if (!mca_card_read[mca_index]) + return 0xff; + return mca_card_read[mca_index](port, mca_priv[mca_index]); } void mca_write(uint16_t port, uint8_t val) { - if (mca_index >= mca_nr_cards) - return; - if (mca_card_write[mca_index]) - mca_card_write[mca_index](port, val, mca_priv[mca_index]); + if (mca_index >= mca_nr_cards) + return; + if (mca_card_write[mca_index]) + mca_card_write[mca_index](port, val, mca_priv[mca_index]); } uint8_t mca_feedb(void) { - if (mca_card_feedb[mca_index]) - return !!(mca_card_feedb[mca_index](mca_priv[mca_index])); - else - return 0; + if (mca_card_feedb[mca_index]) + return !!(mca_card_feedb[mca_index](mca_priv[mca_index])); + else + return 0; } -void mca_add(uint8_t (*read)(int addr, void *priv), void (*write)(int addr, uint8_t val, void *priv), uint8_t (*feedb)(void *priv), void *priv) +void mca_reset(void) { - int c; - - for (c = 0; c < mca_nr_cards; c++) - { - if (!mca_card_read[c] && !mca_card_write[c]) - { - mca_card_read[c] = read; - mca_card_write[c] = write; - mca_card_feedb[c] = feedb; - mca_priv[c] = priv; - return; - } - } + int c; + + for (c = 0; c < 8; c++) { + if (mca_card_reset[c]) + mca_card_reset[c](mca_priv[c]); + } +} + + +void mca_add(uint8_t (*read)(int addr, void *priv), void (*write)(int addr, uint8_t val, void *priv), uint8_t (*feedb)(void *priv), void (*reset)(void *priv), void *priv) +{ + int c; + + for (c = 0; c < mca_nr_cards; c++) { + if (!mca_card_read[c] && !mca_card_write[c]) { + mca_card_read[c] = read; + mca_card_write[c] = write; + mca_card_feedb[c] = feedb; + mca_card_reset[c] = reset; + mca_priv[c] = priv; + return; + } + } } diff --git a/src/mca.h b/src/mca.h index d38156352..e0def3fe5 100644 --- a/src/mca.h +++ b/src/mca.h @@ -1,8 +1,9 @@ extern void mca_init(int nr_cards); -extern void mca_add(uint8_t (*read)(int addr, void *priv), void (*write)(int addr, uint8_t val, void *priv), uint8_t (*feedb)(void *priv), void *priv); +extern void mca_add(uint8_t (*read)(int addr, void *priv), void (*write)(int addr, uint8_t val, void *priv), uint8_t (*feedb)(void *priv), void (*reset)(void *priv), void *priv); extern void mca_set_index(int index); extern uint8_t mca_read(uint16_t port); extern void mca_write(uint16_t port, uint8_t val); extern uint8_t mca_feedb(void); +extern void mca_reset(void); extern void ps2_cache_clean(void); \ No newline at end of file diff --git a/src/network/net_ne2000.c b/src/network/net_ne2000.c index 8feb13c5c..b4de899a1 100644 --- a/src/network/net_ne2000.c +++ b/src/network/net_ne2000.c @@ -1238,7 +1238,7 @@ nic_init(const device_t *info) } } else { - mca_add(nic_mca_read, nic_mca_write, nic_mca_feedb, dev); + mca_add(nic_mca_read, nic_mca_write, nic_mca_feedb, NULL, dev); } } diff --git a/src/network/net_wd8003.c b/src/network/net_wd8003.c index e11fb1e57..a8ecedeba 100644 --- a/src/network/net_wd8003.c +++ b/src/network/net_wd8003.c @@ -675,7 +675,7 @@ wd_init(const device_t *info) } if ((dev->board == WD8003ETA) || (dev->board == WD8003EA)) - mca_add(wd_mca_read, wd_mca_write, wd_mca_feedb, dev); + mca_add(wd_mca_read, wd_mca_write, wd_mca_feedb, NULL, dev); else { dev->base_address = device_get_config_hex16("base"); dev->irq = device_get_config_int("irq"); diff --git a/src/scsi/scsi_aha154x.c b/src/scsi/scsi_aha154x.c index b3ec5f4a9..5ff977f50 100644 --- a/src/scsi/scsi_aha154x.c +++ b/src/scsi/scsi_aha154x.c @@ -861,7 +861,7 @@ aha_init(const device_t *info) /* Enable MCA. */ dev->pos_regs[0] = 0x1F; /* MCA board ID */ dev->pos_regs[1] = 0x0F; - mca_add(aha_mca_read, aha_mca_write, aha_mca_feedb, dev); + mca_add(aha_mca_read, aha_mca_write, aha_mca_feedb, NULL, dev); dev->ha_bps = 5000000.0; /* normal SCSI */ break; } diff --git a/src/scsi/scsi_buslogic.c b/src/scsi/scsi_buslogic.c index 48d19c9f5..b03c453ed 100644 --- a/src/scsi/scsi_buslogic.c +++ b/src/scsi/scsi_buslogic.c @@ -1626,7 +1626,7 @@ buslogic_init(const device_t *info) dev->flags |= X54X_32BIT; dev->pos_regs[0] = 0x08; /* MCA board ID */ dev->pos_regs[1] = 0x07; - mca_add(buslogic_mca_read, buslogic_mca_write, buslogic_mca_feedb, dev); + mca_add(buslogic_mca_read, buslogic_mca_write, buslogic_mca_feedb, NULL, dev); dev->ha_bps = 5000000.0; /* normal SCSI */ dev->max_id = 7; /* narrow SCSI */ break; diff --git a/src/scsi/scsi_spock.c b/src/scsi/scsi_spock.c index 1a26b6b49..cbad41176 100644 --- a/src/scsi/scsi_spock.c +++ b/src/scsi/scsi_spock.c @@ -1091,8 +1091,7 @@ spock_init(const device_t *info) scsi->pos_regs[0] = 0xff; scsi->pos_regs[1] = 0x8e; - // mca_add(spock_mca_read, spock_mca_write, spock_mca_feedb, spock_mca_reset, scsi); - mca_add(spock_mca_read, spock_mca_write, spock_mca_feedb, scsi); + mca_add(spock_mca_read, spock_mca_write, spock_mca_feedb, spock_mca_reset, scsi); scsi->in_reset = 2; scsi->cmd_timer = SPOCK_TIME * 50; diff --git a/src/sound/snd_ad1848.c b/src/sound/snd_ad1848.c index f8681ff86..2817ed36d 100644 --- a/src/sound/snd_ad1848.c +++ b/src/sound/snd_ad1848.c @@ -15,7 +15,8 @@ #include "snd_ad1848.h" -static int ad1848_vols[64]; +static int ad1848_vols_6bits[64]; +static uint32_t ad1848_vols_5bits_aux_gain[32]; void ad1848_setirq(ad1848_t *ad1848, int irq) @@ -51,10 +52,14 @@ void ad1848_write(uint16_t addr, uint8_t val, void *p) { ad1848_t *ad1848 = (ad1848_t *)p; double freq; + uint32_t new_cd_vol_l, new_cd_vol_r; switch (addr & 3) { case 0: /*Index*/ - ad1848->index = val & 0xf; + if ((ad1848->regs[12] & 0x40) && (ad1848->type == AD1848_TYPE_CS4231)) + ad1848->index = val & 0x1f; /* cs4231a extended mode enabled */ + else + ad1848->index = val & 0x0f; /* ad1848/cs4248 mode TODO: some variants/clones DO NOT mirror, just ignore the writes? */ ad1848->trd = val & 0x20; ad1848->mce = val & 0x40; break; @@ -93,6 +98,8 @@ void ad1848_write(uint16_t addr, uint8_t val, void *p) break; case 12: + if (ad1848->type != AD1848_TYPE_DEFAULT) + ad1848->regs[12] = ((ad1848->regs[12] & 0x0f) + (val & 0xf0)) | 0x80; return; case 14: @@ -100,6 +107,22 @@ void ad1848_write(uint16_t addr, uint8_t val, void *p) break; } ad1848->regs[ad1848->index] = val; + + if (ad1848->type == AD1848_TYPE_CS4231) { /* TODO: configure CD volume for CS4248/AD1848 too */ + if (ad1848->regs[0x12] & 0x80) + new_cd_vol_l = 0; + else + new_cd_vol_l = ad1848_vols_5bits_aux_gain[ad1848->regs[0x12] & 0x1f]; + if (ad1848->regs[0x13] & 0x80) + new_cd_vol_r = 0; + else + new_cd_vol_r = ad1848_vols_5bits_aux_gain[ad1848->regs[0x13] & 0x1f]; + + /* Apparently there is no master volume to modulate here + (The windows mixer just adjusts all registers at the same + time when the master slider is adjusted) */ + sound_set_cd_volume(new_cd_vol_l, new_cd_vol_r); + } break; case 2: ad1848->status &= 0xfe; @@ -161,12 +184,12 @@ static void ad1848_poll(void *p) if (ad1848->regs[6] & 0x80) ad1848->out_l = 0; else - ad1848->out_l = (ad1848->out_l * ad1848_vols[ad1848->regs[6] & 0x3f]) >> 16; + ad1848->out_l = (ad1848->out_l * ad1848_vols_6bits[ad1848->regs[6] & 0x3f]) >> 16; if (ad1848->regs[7] & 0x80) ad1848->out_r = 0; else - ad1848->out_r = (ad1848->out_r * ad1848_vols[ad1848->regs[7] & 0x3f]) >> 16; + ad1848->out_r = (ad1848->out_r * ad1848_vols_6bits[ad1848->regs[7] & 0x3f]) >> 16; if (ad1848->count < 0) { @@ -184,10 +207,11 @@ static void ad1848_poll(void *p) else { ad1848->out_l = ad1848->out_r = 0; + sound_set_cd_volume(0, 0); } } -void ad1848_init(ad1848_t *ad1848) +void ad1848_init(ad1848_t *ad1848, int type) { int c; double attenuation; @@ -197,21 +221,29 @@ void ad1848_init(ad1848_t *ad1848) ad1848->mce = 0x40; ad1848->regs[0] = ad1848->regs[1] = 0; - ad1848->regs[2] = ad1848->regs[3] = 0x80; + ad1848->regs[2] = ad1848->regs[3] = 0x80; /* AZT2316A Line-in */ ad1848->regs[4] = ad1848->regs[5] = 0x80; - ad1848->regs[6] = ad1848->regs[7] = 0x80; + ad1848->regs[6] = ad1848->regs[7] = 0x80; /* AZT2316A Master? */ ad1848->regs[8] = 0; ad1848->regs[9] = 0x08; ad1848->regs[10] = ad1848->regs[11] = 0; - ad1848->regs[12] = 0xa; + if ((type == AD1848_TYPE_CS4248) || (type == AD1848_TYPE_CS4231)) + ad1848->regs[12] = 0x8a; + else + ad1848->regs[12] = 0xa; ad1848->regs[13] = 0; ad1848->regs[14] = ad1848->regs[15] = 0; + if (type == AD1848_TYPE_CS4231) + { + ad1848->regs[0x12] = ad1848->regs[0x13] = 0x80; // AZT2316A CD + ad1848->regs[0x1A] = 0x80; // AZT2316A Mic + } + ad1848->out_l = 0; ad1848->out_r = 0; - for (c = 0; c < 64; c++) - { + for (c = 0; c < 64; c++) { attenuation = 0.0; if (c & 0x01) attenuation -= 1.5; if (c & 0x02) attenuation -= 3.0; @@ -222,8 +254,23 @@ void ad1848_init(ad1848_t *ad1848) attenuation = pow(10, attenuation / 10); - ad1848_vols[c] = (int)(attenuation * 65536); + ad1848_vols_6bits[c] = (int)(attenuation * 65536); } - timer_add(&ad1848->timer_count, ad1848_poll, ad1848, 0); + for (c = 0; c < 32; c++) { + attenuation = 12.0; + if (c & 0x01) attenuation -= 1.5; + if (c & 0x02) attenuation -= 3.0; + if (c & 0x04) attenuation -= 6.0; + if (c & 0x08) attenuation -= 12.0; + if (c & 0x10) attenuation -= 24.0; + + attenuation = pow(10, attenuation / 10); + + ad1848_vols_5bits_aux_gain[c] = (int)(attenuation * 65536); + } + + ad1848->type = type; + + timer_add(&ad1848->timer_count, ad1848_poll, ad1848, 0); } diff --git a/src/sound/snd_ad1848.h b/src/sound/snd_ad1848.h index 0778cdfec..9c71f084b 100644 --- a/src/sound/snd_ad1848.h +++ b/src/sound/snd_ad1848.h @@ -1,7 +1,11 @@ +#define AD1848_TYPE_DEFAULT 0 +#define AD1848_TYPE_CS4248 1 +#define AD1848_TYPE_CS4231 2 + typedef struct ad1848_t { int index; - uint8_t regs[16]; + uint8_t regs[32]; /* 16 original + 16 CS4231A extensions */ uint8_t status; int trd; @@ -22,6 +26,8 @@ typedef struct ad1848_t int16_t buffer[SOUNDBUFLEN * 2]; int pos; + + int type; } ad1848_t; void ad1848_setirq(ad1848_t *ad1848, int irq); @@ -33,4 +39,4 @@ void ad1848_write(uint16_t addr, uint8_t val, void *p); void ad1848_update(ad1848_t *ad1848); void ad1848_speed_changed(ad1848_t *ad1848); -void ad1848_init(ad1848_t *ad1848); +void ad1848_init(ad1848_t *ad1848, int type); diff --git a/src/sound/snd_azt2316a.c b/src/sound/snd_azt2316a.c new file mode 100644 index 000000000..3193f1af1 --- /dev/null +++ b/src/sound/snd_azt2316a.c @@ -0,0 +1,1399 @@ +/* + * TYPE 0x11: (Washington) + * Aztech MMPRO16AB, + * Aztech Sound Galaxy Pro 16 AB + * Aztech Sound Galaxy Washington 16 + * ...and other OEM names + * FCC ID I38-MMSN824 and others + * + * TYPE 0x0C: (Clinton) + * Packard Bell FORTE16 + * Aztech Sound Galaxy Nova 16 Extra + * Aztech Sound Galaxy Clinton 16 + * ...and other OEM names + * + * Also works more or less for drivers of other models with the same chipsets. + * + * Copyright (c) 2020 Eluan Costa Miranda All rights reserved. + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + * + * ============================================================================= + * + * The CS4248 DSP used is pin and software compatible with the AD1848. + * I also have one of these cards with a CS4231. The driver talks to the + * emulated card as if it was a CS4231 and I still don't know how to tell the + * drivers to see the CS4248. The CS4231 more advanced features are NOT used, + * just the new input/output channels. Apparently some drivers are hardcoded + * for one or the other, so there is an option for this. + * + * There is lots more to be learned form the Win95 drivers. The Linux driver is + * very straightforward and doesn't do much. + * + * Recording and voice modes in the windows mixer still do nothing in 86Box, so + * this is missing. + * + * There is a jumper to load the startup configuration from an EEPROM. This is + * implemented, so any software-configured parameters will be saved. + * + * The CD-ROM interface commands are just ignored, along with gameport. + * The MPU401 is always enabled. + * The OPL3 is always active in some (all?) drivers/cards, so there is no + * configuration for this. + * + * Tested with DOS (driver installation, tools, diagnostics), Win3.1 (driver + * installation, tools), Win95 (driver auto-detection), lots of games. + * + * I consider type 0x11 (Washington) to be very well tested. Type 0x0C (Clinton) + * wasn't fully tested, but works well for WSS/Windows. BEWARE that there are + * *too many* driver types and OEM versions for each card. Maybe yours isn't + * emulated or you have the wrong driver. Some features of each card may work + * when using wrong drivers. CODEC selection is also important. + * + * Any updates to the WSS and SBPROV2 sound cards should be synced here when + * appropriate. The WSS was completely cloned here, while the SBPROV2 tends + * to call the original functions, except for initialization. + * + * TODO/Notes: + * -Some stuff still not understood on I/O addresses 0x624 and 0x530-0x533. + * -Is the CS42xx dither mode used anywhere? Implement. + * -What are the voice commands mode in Win95 mixer again? + * -Configuration options not present on Aztech's CONFIG.EXE have been commented + * out or deleted. Other types of cards with this chipset may need them. + * -Sfademo on the Descent CD fails under Win95, works under DOS, see if it + * happens on real hardware (and OPL3 stops working after the failure) + * -There appears to be some differences in sound volumes bertween MIDI, + * SBPROV2, WSS and OPL3? Also check relationship between the SBPROV2 mixer and + * the WSS mixer! Are they independent? Current mode selects which mixer? Are + * they entangled? + * -Check real hardware to see if advanced, mic boost, etc appear in the mixer? + * -CD-ROM driver shipped with the card (SGIDECD.SYS) checks for model strings. + * I have implemented mine (Aztech CDA 468-02I 4x) in PCem. + * -Descent 2 W95 version can't start cd music. Happens on real hardware. + * Explanation further below. + * -DOSQuake and Descent 2 DOS cd music do not work under Win95. The mode + * selects get truncated and send all zeros for output channel selection and + * volume, Descent 2 also has excess zeros! This is a PCem bug, happens on all + * sound cards. CD audio works in Winquake and Descent 2 DOS setup program. + * -DOSQuake CD audio works under DOS with VIDE-CDD.SYS and SGIDECD.SYS. + * Descent 2 DOS is still mute but volume selection appears to be working. + * Descent 2 fails to launch with SGIDECD.SYS with "Device failed to request + * command". SGIDECD.SYS is the CD-ROM driver included with the sound card + * drivers. My real CD-ROM drive can't read anything so I can't check the + * real behavior of this driver. + * -Some cards just have regular IDE ports while other have proprietary ports. + * The regular IDE ports just have a option to enable an almost-generic CD-ROM + * driver in CONFIG.SYS/AUTOEXEC.BAT (like SGIDECD.SYS) and the onboard port + * is enabled/disabled by jumpers. The proprietary ones also have + * address/dma/irq settings. Since the configuration options are ignored here, + * this behaves like a card with a regular interface disabled by jumper and + * the configuration just adds/removes the drivers (which will see other IDE + * interfaces present) from the boot process. + * -Continue reverse engineering to see if the AZT1605 shares the SB DMA with + * WSS or if it is set separately by the TSR loaded on boot. Currently it is + * only set by PCem config and then saved to EEPROM (which would make it fixed + * if loading from EEPROM too). + * -Related to the previous note, part of the SBPROV2 emulation on the CLINTON + * family appears to be implemented with a TSR. It's better to remove the TSR + * for now. I need to investigate this. Mixer is also weird under DOS (and + * wants to save to EEPROM? I don't think the WASHINGTON does this). + * -Search for TODO in this file. :-) + * + * Misc things I use to test for regressions: Windows sounds, Descent under + * dos/windows, Descent 2 dos/windows (+ cd music option), Descent 2 W95 + cd + * music, Age of Empires (CD + Midi), cd-audio under Windows + volume, + * cd-audio under dos + volume, Aztech diagnose.exe, Aztech volset /M:3 then + * volset /D, Aztech setmode, mixer (volume + balance) under dos and windows, + * DOSQuake under dos and windows (+ cd music and volumes, + Winquake). + * + * Reason for Descent 2 Win95 CD-Audio not working: + * The game calls auxGetNumDevs() to check if any of the AUX devices has + * caps.wTechnology == AUXCAPS_CDAUDIO, but this fails because the Aztech + * Win95 driver only returns a "Line-In" device. I'm not aware of any other + * game that does this and this is completely unnecessary. Other games that + * play cd audio correctly have the exact *same* initialization code, minus + * this check that only Descent 2 Win95 does. It would work if it just skipped + * this check and progressed with calling mciSendCommand() with + * mciOpenParms.lpstrDeviceType = "cdaudio", like other games do. There are + * some sound cards listed as incompatible in the game's README.TXT file that + * are probably due to this. + */ + +#include +#include +#include +#include +#include +#include +#include +#define HAVE_STDARG_H +#include "86box.h" +#include "86box_io.h" +#include "timer.h" +#include "pic.h" +#include "nvr.h" +#include "device.h" +#include "sound.h" +#include "midi.h" +#include "snd_ad1848.h" +#include "snd_azt2316a.h" +#include "snd_sb.h" + +/*530, 11, 3 - 530=23*/ +/*530, 11, 1 - 530=22*/ +/*530, 11, 0 - 530=21*/ +/*530, 10, 1 - 530=1a*/ +/*530, 10, 0 - 530=19*/ +/*530, 9, 1 - 530=12*/ +/*530, 7, 1 - 530=0a*/ +/*604, 11, 1 - 530=22*/ +/*e80, 11, 1 - 530=22*/ +/*f40, 11, 1 - 530=22*/ + + +static int azt2316a_wss_dma[4] = {0, 0, 1, 3}; +static int azt2316a_wss_irq[8] = {5, 7, 9, 10, 11, 12, 14, 15}; /* W95 only uses 7-10, others may be wrong */ +//static uint16_t azt2316a_wss_addr[4] = {0x530, 0x604, 0xe80, 0xf40}; + +typedef struct azt2316a_t +{ + int type; + int wss_interrupt_after_config; + + uint8_t wss_config; + + uint16_t cur_addr, cur_wss_addr, cur_mpu401_addr; + + int cur_irq, cur_dma; + int cur_wss_enabled, cur_wss_irq, cur_wss_dma; + int cur_mpu401_irq; + int cur_mpu401_enabled; + + uint32_t config_word; + uint32_t config_word_unlocked; + + uint8_t cur_mode; + + ad1848_t ad1848; + mpu_t *mpu; + + sb_t *sb; +} azt2316a_t; + +static uint8_t +azt2316a_wss_read(uint16_t addr, void *p) +{ + azt2316a_t *azt2316a = (azt2316a_t *)p; + uint8_t temp; + + /* TODO: when windows is initializing, writing 0x48, 0x58 and 0x60 to + 0x530 makes reading from 0x533 return 0x44, but writing 0x50 + makes this return 0x04. Why? */ + if (addr & 1) + temp = 4 | (azt2316a->wss_config & 0x40); + else + temp = 4 | (azt2316a->wss_config & 0xC0); + + return temp; +} + +static void +azt2316a_wss_write(uint16_t addr, uint8_t val, void *p) +{ + azt2316a_t *azt2316a = (azt2316a_t *)p; + int interrupt = 0; + + if (azt2316a->wss_interrupt_after_config) + if ((azt2316a->wss_config & 0x40) && !(val & 0x40)) // TODO: is this the right edge? + interrupt = 1; + + azt2316a->wss_config = val; + azt2316a->cur_wss_dma = azt2316a_wss_dma[val & 3]; + azt2316a->cur_wss_irq = azt2316a_wss_irq[(val >> 3) & 7]; + ad1848_setdma(&azt2316a->ad1848, azt2316a_wss_dma[val & 3]); + ad1848_setirq(&azt2316a->ad1848, azt2316a_wss_irq[(val >> 3) & 7]); + + if (interrupt) + picint(1 << azt2316a->cur_wss_irq); +} + +/* generate a config word based on current settings */ +static void +azt1605_create_config_word(void *p) +{ + azt2316a_t *azt2316a = (azt2316a_t *)p; + uint32_t temp = 0; + + /* not implemented / hardcoded */ + uint8_t game_enable = 1; + uint8_t cd_type = 0; /* TODO: see if the cd-rom was originally connected there on the real machines emulated by 86Box (Packard Bell Legend 100CD, Itautec Infoway Multimidia, etc) */ + uint8_t cd_dma8 = -1; + uint8_t cd_irq = 0; + + switch (azt2316a->cur_addr) { + case 0x220: + /* do nothing + temp += 0 << 0; */ + break; + case 0x240: + temp += 1 << 0; + break; +/* + case 0x260: // TODO: INVALID? + temp += 2 << 0; + break; + case 0x280: // TODO: INVALID? + temp += 3 << 0; + break; +*/ + } + + switch (azt2316a->cur_irq) { + case 2: + temp += 1 << 8; + break; + case 3: + temp += 1 << 9; + break; + case 5: + temp += 1 << 10; + break; + case 7: + temp += 1 << 11; + break; + } + + switch (azt2316a->cur_wss_addr) { + case 0x530: + /* do nothing + temp += 0 << 16; */ + break; + case 0x604: + temp += 1 << 16; + break; + case 0xE80: + temp += 2 << 16; + break; + case 0xF40: + temp += 3 << 16; + break; + } + + if (azt2316a->cur_wss_enabled) + temp += 1 << 18; + + if (game_enable) + temp += 1 << 4; + + switch (azt2316a->cur_mpu401_addr) { + case 0x300: + /* do nothing + temp += 0 << 2; */ + break; + case 0x330: + temp += 1 << 2; + break; + } + + if (azt2316a->cur_mpu401_enabled) + temp += 1 << 3; + + switch (cd_type) { + case 0: /* disabled + do nothing + temp += 0 << 5; */ + break; + case 1: // panasonic + temp += 1 << 5; + break; + case 2: // mitsumi/sony/aztech + temp += 2 << 5; + break; + case 3: // all enabled + temp += 3 << 5; + break; + case 4: // unused + temp += 4 << 5; + break; + case 5: // unused + temp += 5 << 5; + break; + case 6: // unused + temp += 6 << 5; + break; + case 7: // unused + temp += 7 << 5; + break; + } + + switch (cd_dma8) { + case 0xFF: /* -1 + do nothing + temp += 0 << 22;*/ + break; + case 0: + temp += 1 << 22; + break; + case 1: + temp += 2 << 22; + break; + case 3: + temp += 3 << 22; + break; + } + + switch (azt2316a->cur_mpu401_irq) { + case 2: + temp += 1 << 12; + break; + case 3: + temp += 1 << 13; + break; + case 5: + temp += 1 << 14; + break; + case 7: + temp += 1 << 15; + break; + } + + switch (cd_irq) { + case 0: // disabled + // do nothing + break; + case 11: + temp += 1 << 19; + break; + case 12: + temp += 1 << 20; + break; + case 15: + temp += 1 << 21; + break; + } + + azt2316a->config_word = temp; +} + +static void +azt2316a_create_config_word(void *p) +{ + azt2316a_t *azt2316a = (azt2316a_t *)p; + uint32_t temp = 0; + + /* not implemented / hardcoded */ + uint8_t game_enable = 1; + uint16_t cd_addr = 0x310; + uint8_t cd_type = 0; /* TODO: see if the cd-rom was originally connected there on the real machines emulated by 86Box (Packard Bell Legend 100CD, Itautec Infoway Multimidia, etc) */ + uint8_t cd_dma8 = -1; + uint8_t cd_dma16 = -1; + uint8_t cd_irq = 15; + + if (azt2316a->type == SB_SUBTYPE_CLONE_AZT1605_0X0C) { + azt1605_create_config_word(p); + return; + } + + switch (azt2316a->cur_addr) { + case 0x220: + /* do nothing + temp += 0 << 0; */ + break; + case 0x240: + temp += 1 << 0; + break; +/* + case 0x260: // TODO: INVALID? + temp += 2 << 0; + break; + case 0x280: // TODO: INVALID? + temp += 3 << 0; + break; +*/ + } + + switch (azt2316a->cur_irq) { + case 2: + temp += 1 << 2; + break; + case 5: + temp += 1 << 3; + break; + case 7: + temp += 1 << 4; + break; + case 10: + temp += 1 << 5; + break; + } + + switch (azt2316a->cur_dma) { +/* + // TODO: INVALID? + case 0xFF: // -1 + // do nothing + //temp += 0 << 6; + break; +*/ + case 0: + temp += 1 << 6; + break; + case 1: + temp += 2 << 6; + break; + case 3: + temp += 3 << 6; + break; + } + + switch (azt2316a->cur_wss_addr) + { + case 0x530: + // do nothing + //temp += 0 << 8; + break; + case 0x604: + temp += 1 << 8; + break; + case 0xE80: + temp += 2 << 8; + break; + case 0xF40: + temp += 3 << 8; + break; + } + if (azt2316a->cur_wss_enabled) + temp += 1 << 10; + if (game_enable) + temp += 1 << 11; + switch (azt2316a->cur_mpu401_addr) + { + case 0x300: + // do nothing + //temp += 0 << 12; + break; + case 0x330: + temp += 1 << 12; + break; + } + + if (azt2316a->cur_mpu401_enabled) + temp += 1 << 13; + + switch (cd_addr) { + case 0x310: + // do nothing + //temp += 0 << 14; + break; + case 0x320: + temp += 1 << 14; + break; + case 0x340: + temp += 2 << 14; + break; + case 0x350: + temp += 3 << 14; + break; + } + switch (cd_type) { + case 0: /* disabled + do nothing + temp += 0 << 16; */ + break; + case 1: /* panasonic */ + temp += 1 << 16; + break; + case 2: /* sony */ + temp += 2 << 16; + break; + case 3: /* mitsumi */ + temp += 3 << 16; + break; + case 4: /* aztech */ + temp += 4 << 16; + break; + case 5: /* unused */ + temp += 5 << 16; + break; + case 6: /* unused */ + temp += 6 << 16; + break; + case 7: /* unused */ + temp += 7 << 16; + break; + } + + switch (cd_dma8) { + case 0xFF: /* -1 + do nothing + temp += 0 << 20; */ + break; + case 0: + temp += 1 << 20; + break; +/* + case 1: // TODO: INVALID? + temp += 2 << 20; + break; +*/ + case 3: + temp += 3 << 20; + break; + } + + switch (cd_dma16) { + case 0xFF: /* -1 + do nothing + temp += 0 << 22; */ + break; + case 5: + temp += 1 << 22; + break; + case 6: + temp += 2 << 22; + break; + case 7: + temp += 3 << 22; + break; + } + + switch (azt2316a->cur_mpu401_irq) { + case 2: + temp += 1 << 24; + break; + case 5: + temp += 1 << 25; + break; + case 7: + temp += 1 << 26; + break; + case 10: + temp += 1 << 27; + break; + } + + switch (cd_irq) { + case 5: + temp += 1 << 28; + break; + case 11: + temp += 1 << 29; + break; + case 12: + temp += 1 << 30; + break; + case 15: + temp += 1 << 31; + break; + } + + azt2316a->config_word = temp; +} + +static uint8_t +azt2316a_config_read(uint16_t addr, void *p) +{ + azt2316a_t *azt2316a = (azt2316a_t *)p; + uint8_t temp = 0; + + /* Some WSS config here + config change enable bit + (setting bit 7 and writing back) */ + + if (addr == (azt2316a->cur_addr + 0x404)) { + /* TODO: what is the real meaning of the read value? + I got a mention of bit 0x10 for WSS from disassembling the source + code of the driver, and when playing with the I/O ports on real + hardware after doing some configuration, but didn't dig into it. + Bit 0x08 seems to be a busy flag and generates a timeout + (continuous re-reading when initializing windows 98) */ + temp = azt2316a->cur_mode ? 0x07 : 0x0F; + if (azt2316a->config_word_unlocked) { + temp |= 0x80; + } + } else { + // Rest of config. These are documented in the Linux driver. + switch (addr & 0x3) + { + case 0: + temp = azt2316a->config_word & 0xFF; + break; + case 1: + temp = (azt2316a->config_word >> 8); + break; + case 2: + temp = (azt2316a->config_word >> 16); + break; + case 3: + temp = (azt2316a->config_word >> 24); + break; + } + } + + return temp; +} + + +static void +azt1605_config_write(uint16_t addr, uint8_t val, void *p) +{ + azt2316a_t *azt2316a = (azt2316a_t *)p; + uint8_t temp; + + if (addr == (azt2316a->cur_addr + 0x404)) { + if (val & 0x80) + azt2316a->config_word_unlocked = 1; + else + azt2316a->config_word_unlocked = 0; + } else if (azt2316a->config_word_unlocked) { + if (val == 0xFF) { /* TODO: check if this still happens on eeprom.sys after having more complete emulation! */ + return; + } + switch (addr & 3) { + case 0: + azt2316a->config_word = (azt2316a->config_word & 0xFFFFFF00) | val; + + temp = val & 3; + if (temp == 0) + azt2316a->cur_addr = 0x220; + else if (temp == 1) + azt2316a->cur_addr = 0x240; +/* + else if (temp == 2) + azt2316a->cur_addr = 0x260; // TODO: INVALID + else if (temp == 3) + azt2316a->cur_addr = 0x280; // TODO: INVALID +*/ + if (val & 0x4) + azt2316a->cur_mpu401_addr = 0x330; + else + azt2316a->cur_mpu401_addr = 0x300; + + if (val & 0x8) + azt2316a->cur_mpu401_enabled = 1; + else + azt2316a->cur_mpu401_enabled = 0; + break; + case 1: + azt2316a->config_word = (azt2316a->config_word & 0xFFFF00FF) | (val << 8); + + if (val & 0x1) + azt2316a->cur_irq = 2; + else if (val & 0x2) + azt2316a->cur_irq = 3; + else if (val & 0x4) + azt2316a->cur_irq = 5; + else if (val & 0x8) + azt2316a->cur_irq = 7; + /* else undefined? */ + + if (val & 0x10) + azt2316a->cur_mpu401_irq = 2; + else if (val & 0x20) + azt2316a->cur_mpu401_irq = 3; + else if (val & 0x40) + azt2316a->cur_mpu401_irq = 5; + else if (val & 0x80) + azt2316a->cur_mpu401_irq = 7; + /* else undefined? */ + break; + case 2: + azt2316a->config_word = (azt2316a->config_word & 0xFF00FFFF) | (val << 16); + + io_removehandler(azt2316a->cur_wss_addr, 0x0004, azt2316a_wss_read, NULL, NULL, azt2316a_wss_write, NULL, NULL, azt2316a); + io_removehandler(azt2316a->cur_wss_addr + 0x0004, 0x0004, ad1848_read, NULL, NULL, ad1848_write, NULL, NULL, &azt2316a->ad1848); + + temp = val & 0x3; + if (temp == 0) + azt2316a->cur_wss_addr = 0x530; + else if (temp == 1) + azt2316a->cur_wss_addr = 0x604; + else if (temp == 2) + azt2316a->cur_wss_addr = 0xE80; + else if (temp == 3) + azt2316a->cur_wss_addr = 0xF40; + + io_sethandler(azt2316a->cur_wss_addr, 0x0004, azt2316a_wss_read, NULL, NULL, azt2316a_wss_write, NULL, NULL, azt2316a); + io_sethandler(azt2316a->cur_wss_addr + 0x0004, 0x0004, ad1848_read, NULL, NULL, ad1848_write, NULL, NULL, &azt2316a->ad1848); + + /* no actual effect */ + if (val & 0x4) + azt2316a->cur_wss_enabled = 1; + else + azt2316a->cur_wss_enabled = 0; + break; + case 3: + break; + } + /* update sbprov2 configs */ + sb_dsp_setaddr(&azt2316a->sb->dsp, azt2316a->cur_addr); + sb_dsp_setirq(&azt2316a->sb->dsp, azt2316a->cur_irq); + sb_dsp_setdma8(&azt2316a->sb->dsp, azt2316a->cur_dma); + + mpu401_change_addr(azt2316a->mpu, azt2316a->cur_mpu401_addr); + mpu401_setirq(azt2316a->mpu, azt2316a->cur_mpu401_irq); + } +} + +static void +azt2316a_config_write(uint16_t addr, uint8_t val, void *p) +{ + azt2316a_t *azt2316a = (azt2316a_t *)p; + uint8_t temp; + + if (azt2316a->type == SB_SUBTYPE_CLONE_AZT1605_0X0C) { + azt1605_config_write(addr, val, azt2316a); + return; + } + + if (addr == (azt2316a->cur_addr + 0x404)) { + if (val & 0x80) + azt2316a->config_word_unlocked = 1; + else + azt2316a->config_word_unlocked = 0; + } else if (azt2316a->config_word_unlocked) { + if (val == 0xFF) // TODO: check if this still happens on eeprom.sys after having more complete emulation! + return; + switch (addr & 3) { + case 0: + azt2316a->config_word = (azt2316a->config_word & 0xFFFFFF00) | val; + temp = val & 3; + + if (temp == 0) + azt2316a->cur_addr = 0x220; + else if (temp == 1) + azt2316a->cur_addr = 0x240; + + if (val & 0x4) + azt2316a->cur_irq = 2; + else if (val & 0x8) + azt2316a->cur_irq = 5; + else if (val & 0x10) + azt2316a->cur_irq = 7; + else if (val & 0x20) + azt2316a->cur_irq = 10; + + temp = (val >> 6) & 3; + if (temp == 1) + azt2316a->cur_dma = 0; + else if (temp == 2) + azt2316a->cur_dma = 1; + else if (temp == 3) + azt2316a->cur_dma = 3; + break; + case 1: + azt2316a->config_word = (azt2316a->config_word & 0xFFFF00FF) | (val << 8); + + io_removehandler(azt2316a->cur_wss_addr, 0x0004, azt2316a_wss_read, NULL, NULL, azt2316a_wss_write, NULL, NULL, azt2316a); + io_removehandler(azt2316a->cur_wss_addr + 0x0004, 0x0004, ad1848_read, NULL, NULL, ad1848_write, NULL, NULL, &azt2316a->ad1848); + + temp = val & 0x3; + if (temp == 0) + azt2316a->cur_wss_addr = 0x530; + else if (temp == 1) + azt2316a->cur_wss_addr = 0x604; + else if (temp == 2) + azt2316a->cur_wss_addr = 0xE80; + else if (temp == 3) + azt2316a->cur_wss_addr = 0xF40; + + io_sethandler(azt2316a->cur_wss_addr, 0x0004, azt2316a_wss_read, NULL, NULL, azt2316a_wss_write, NULL, NULL, azt2316a); + io_sethandler(azt2316a->cur_wss_addr + 0x0004, 0x0004, ad1848_read, NULL, NULL, ad1848_write, NULL, NULL, &azt2316a->ad1848); + + /* no actual effect */ + if (val & 0x4) + azt2316a->cur_wss_enabled = 1; + else + azt2316a->cur_wss_enabled = 0; + + if (val & 0x10) + azt2316a->cur_mpu401_addr = 0x330; + else + azt2316a->cur_mpu401_addr = 0x300; + + if (val & 0x20) + azt2316a->cur_mpu401_enabled = 1; + else + azt2316a->cur_mpu401_enabled = 0; + break; + case 2: + azt2316a->config_word = (azt2316a->config_word & 0xFF00FFFF) | (val << 16); + break; + case 3: + azt2316a->config_word = (azt2316a->config_word & 0x00FFFFFF) | (val << 24); + + if (val & 0x1) + azt2316a->cur_mpu401_irq = 2; + else if (val & 0x2) + azt2316a->cur_mpu401_irq = 5; + else if (val & 0x4) + azt2316a->cur_mpu401_irq = 7; + else if (val & 0x8) + azt2316a->cur_mpu401_irq = 10; + /* else undefined? */ + break; + } + /* update sbprov2 configs */ + sb_dsp_setaddr(&azt2316a->sb->dsp, azt2316a->cur_addr); + sb_dsp_setirq(&azt2316a->sb->dsp, azt2316a->cur_irq); + sb_dsp_setdma8(&azt2316a->sb->dsp, azt2316a->cur_dma); + + mpu401_change_addr(azt2316a->mpu, azt2316a->cur_mpu401_addr); + mpu401_setirq(azt2316a->mpu, azt2316a->cur_mpu401_irq); + } +} + +/* How it behaves when one or another is activated may affect games auto-detecting (and will also use more of the limited system resources!) */ +void +azt2316a_enable_wss(uint8_t enable, void *p) +{ + azt2316a_t *azt2316a = (azt2316a_t *)p; + + if (enable) + azt2316a->cur_mode = 1; + else + azt2316a->cur_mode = 0; +} + +static void +azt2316a_get_buffer(int32_t *buffer, int len, void *p) +{ + azt2316a_t *azt2316a = (azt2316a_t *)p; + int c; + + /* wss part */ + ad1848_update(&azt2316a->ad1848); + for (c = 0; c < len * 2; c++) + buffer[c] += (azt2316a->ad1848.buffer[c] / 2); + + azt2316a->ad1848.pos = 0; + + /* sbprov2 part */ + sb_get_buffer_sbpro(buffer, len, azt2316a->sb); +} + +static void * +azt_init(const device_t *info) +{ + FILE *f; + wchar_t *fn = NULL; + int i; + int loaded_from_eeprom = 0; + uint16_t addr_setting; + uint8_t read_eeprom[AZTECH_EEPROM_SIZE]; + azt2316a_t *azt2316a = malloc(sizeof(azt2316a_t)); + memset(azt2316a, 0, sizeof(azt2316a_t)); + + azt2316a->type = info->local; + + if (azt2316a->type == SB_SUBTYPE_CLONE_AZT1605_0X0C) { + fn = L"azt1605.nvr"; + } else if (azt2316a->type == SB_SUBTYPE_CLONE_AZT2316A_0X11) { + fn = L"azt2316a.nvr"; + } + + /* config */ + f = nvr_fopen(fn, L"rb"); + if (f) { + uint8_t checksum = 0x7f; + uint8_t saved_checksum; + size_t res; + + res = fread(read_eeprom, AZTECH_EEPROM_SIZE, 1, f); + for (i = 0; i < AZTECH_EEPROM_SIZE; i++) + checksum += read_eeprom[i]; + + res = fread(&saved_checksum, sizeof(saved_checksum), 1, f); + (void)res; + + fclose(f); + + if (checksum == saved_checksum) + loaded_from_eeprom = 1; + } + + if (!loaded_from_eeprom) { + if (azt2316a->type == SB_SUBTYPE_CLONE_AZT2316A_0X11) { + read_eeprom[0] = 0x00; + read_eeprom[1] = 0x00; + read_eeprom[2] = 0x00; + read_eeprom[3] = 0x00; + read_eeprom[4] = 0x00; + read_eeprom[5] = 0x00; + read_eeprom[6] = 0x00; + read_eeprom[7] = 0x00; + read_eeprom[8] = 0x00; + read_eeprom[9] = 0x00; + read_eeprom[10] = 0x00; + read_eeprom[11] = 0x88; + read_eeprom[12] = 0xbc; + read_eeprom[13] = 0x00; + read_eeprom[14] = 0x01; + read_eeprom[15] = 0x00; + } else if (azt2316a->type == SB_SUBTYPE_CLONE_AZT1605_0X0C) { + read_eeprom[0] = 0x80; + read_eeprom[1] = 0x80; + read_eeprom[2] = 0x9F; + read_eeprom[3] = 0x13; + read_eeprom[4] = 0x16; + read_eeprom[5] = 0x13; + read_eeprom[6] = 0x00; + read_eeprom[7] = 0x00; + read_eeprom[8] = 0x16; + read_eeprom[9] = 0x0B; + read_eeprom[10] = 0x06; + read_eeprom[11] = 0x01; + read_eeprom[12] = 0x1C; + read_eeprom[13] = 0x14; + read_eeprom[14] = 0x04; + read_eeprom[15] = 0x1C; + } + } + + if (azt2316a->type == SB_SUBTYPE_CLONE_AZT2316A_0X11) { + azt2316a->config_word = read_eeprom[11] | (read_eeprom[12] << 8) | (read_eeprom[13] << 16) | (read_eeprom[14] << 24); + + switch (azt2316a->config_word & (3 << 0)) { + case 0: + azt2316a->cur_addr = 0x220; + break; + case 1: + azt2316a->cur_addr = 0x240; + break; + default: + fatal("AZT2316A: invalid sb addr in config word %08X\n", azt2316a->config_word); + } + + if (azt2316a->config_word & (1 << 2)) + azt2316a->cur_irq = 2; + else if (azt2316a->config_word & (1 << 3)) + azt2316a->cur_irq = 5; + else if (azt2316a->config_word & (1 << 4)) + azt2316a->cur_irq = 7; + else if (azt2316a->config_word & (1 << 5)) + azt2316a->cur_irq = 10; + else + fatal("AZT2316A: invalid sb irq in config word %08X\n", azt2316a->config_word); + + switch (azt2316a->config_word & (3 << 6)) { + case 1 << 6: + azt2316a->cur_dma = 0; + break; + case 2 << 6: + azt2316a->cur_dma = 1; + break; + case 3 << 6: + azt2316a->cur_dma = 3; + break; + default: + fatal("AZT2316A: invalid sb dma in config word %08X\n", azt2316a->config_word); + } + + switch (azt2316a->config_word & (3 << 8)) { + case 0: + azt2316a->cur_wss_addr = 0x530; + break; + case 1 << 8: + azt2316a->cur_wss_addr = 0x604; + break; + case 2 << 8: + azt2316a->cur_wss_addr = 0xE80; + break; + case 3 << 8: + azt2316a->cur_wss_addr = 0xF40; + break; + default: + fatal("AZT2316A: invalid wss addr in config word %08X\n", azt2316a->config_word); + } + + if (azt2316a->config_word & (1 << 10)) + azt2316a->cur_wss_enabled = 1; + else + azt2316a->cur_wss_enabled = 0; + + if (azt2316a->config_word & (1 << 12)) + azt2316a->cur_mpu401_addr = 0x330; + else + azt2316a->cur_mpu401_addr = 0x300; + + if (azt2316a->config_word & (1 << 13)) + azt2316a->cur_mpu401_enabled = 1; + else + azt2316a->cur_mpu401_enabled = 0; + + if (azt2316a->config_word & (1 << 24)) + azt2316a->cur_mpu401_irq = 2; + else if (azt2316a->config_word & (1 << 25)) + azt2316a->cur_mpu401_irq = 5; + else if (azt2316a->config_word & (1 << 26)) + azt2316a->cur_mpu401_irq = 7; + else if (azt2316a->config_word & (1 << 27)) + azt2316a->cur_mpu401_irq = 10; + else + fatal("AZT2316A: invalid mpu401 irq in config word %08X\n", azt2316a->config_word); + + /* these are not present on the EEPROM */ + if (azt2316a->cur_irq == 10) + azt2316a->cur_wss_irq = 10; + else if (azt2316a->cur_irq == 7) + azt2316a->cur_wss_irq = 7; + else + azt2316a->cur_wss_irq = 10; + + azt2316a->cur_wss_dma = azt2316a->cur_dma; + azt2316a->cur_mode = 0; + } else if (azt2316a->type == SB_SUBTYPE_CLONE_AZT1605_0X0C) { + azt2316a->config_word = read_eeprom[12] + (read_eeprom[13] << 8) + (read_eeprom[14] << 16); + + switch (azt2316a->config_word & (3 << 0)) { + case 0: + azt2316a->cur_addr = 0x220; + break; + case 1: + azt2316a->cur_addr = 0x240; + break; + default: + fatal("AZT1605: invalid sb addr in config word %08X\n", azt2316a->config_word); + } + + if (azt2316a->config_word & (1 << 2)) + azt2316a->cur_mpu401_addr = 0x330; + else + azt2316a->cur_mpu401_addr = 0x300; + + if (azt2316a->config_word & (1 << 3)) + azt2316a->cur_mpu401_enabled = 1; + else + azt2316a->cur_mpu401_enabled = 0; + + if (azt2316a->config_word & (1 << 8)) + azt2316a->cur_irq = 2; + else if (azt2316a->config_word & (1 << 9)) + azt2316a->cur_irq = 3; + else if (azt2316a->config_word & (1 << 10)) + azt2316a->cur_irq = 5; + else if (azt2316a->config_word & (1 << 11)) + azt2316a->cur_irq = 7; + else + fatal("AZT1605: invalid sb irq in config word %08X\n", azt2316a->config_word); + + if (azt2316a->config_word & (1 << 12)) + azt2316a->cur_mpu401_irq = 2; + else if (azt2316a->config_word & (1 << 13)) + azt2316a->cur_mpu401_irq = 3; + else if (azt2316a->config_word & (1 << 14)) + azt2316a->cur_mpu401_irq = 5; + else if (azt2316a->config_word & (1 << 15)) + azt2316a->cur_mpu401_irq = 7; + else + fatal("AZT1605: invalid mpu401 irq in config word %08X\n", azt2316a->config_word); + + switch (azt2316a->config_word & (3 << 16)) { + case 0: + azt2316a->cur_wss_addr = 0x530; + break; + case 1 << 16: + azt2316a->cur_wss_addr = 0x604; + break; + case 2 << 16: + azt2316a->cur_wss_addr = 0xE80; + break; + case 3 << 16: + azt2316a->cur_wss_addr = 0xF40; + break; + default: + fatal("AZT1605: invalid wss addr in config word %08X\n", azt2316a->config_word); + } + + if (azt2316a->config_word & (1 << 18)) + azt2316a->cur_wss_enabled = 1; + else + azt2316a->cur_wss_enabled = 0; + + // these are not present on the EEPROM + azt2316a->cur_dma = device_get_config_int("sb_dma8"); // TODO: investigate TSR to make this work with it - there is no software configurable DMA8? + + if (azt2316a->cur_irq == 7) + azt2316a->cur_wss_irq = 7; + else + azt2316a->cur_wss_irq = 10; + + azt2316a->cur_wss_dma = azt2316a->cur_dma; + azt2316a->cur_mode = 0; + } + + addr_setting = device_get_config_hex16("addr"); + if (addr_setting) + azt2316a->cur_addr = addr_setting; + + azt2316a->wss_interrupt_after_config = device_get_config_int("wss_interrupt_after_config"); + + /* wss part */ + ad1848_init(&azt2316a->ad1848, device_get_config_int("codec")); + + ad1848_setirq(&azt2316a->ad1848, azt2316a->cur_wss_irq); + ad1848_setdma(&azt2316a->ad1848, azt2316a->cur_wss_dma); + + io_sethandler(azt2316a->cur_addr + 0x0400, 0x0040, azt2316a_config_read, NULL, NULL, azt2316a_config_write, NULL, NULL, azt2316a); + io_sethandler(azt2316a->cur_wss_addr, 0x0004, azt2316a_wss_read, NULL, NULL, azt2316a_wss_write, NULL, NULL, azt2316a); + io_sethandler(azt2316a->cur_wss_addr + 0x0004, 0x0004, ad1848_read, NULL, NULL, ad1848_write, NULL, NULL, &azt2316a->ad1848); + + /* sbprov2 part */ + /*sbpro port mappings. 220h or 240h. + 2x0 to 2x3 -> FM chip (18 voices) + 2x4 to 2x5 -> Mixer interface + 2x6, 2xA, 2xC, 2xE -> DSP chip + 2x8, 2x9, 388 and 389 FM chip (9 voices).*/ + azt2316a->sb = malloc(sizeof(sb_t)); + memset(azt2316a->sb, 0, sizeof(sb_t)); + + azt2316a->sb->opl_enabled = device_get_config_int("opl"); + + for (i = 0; i < AZTECH_EEPROM_SIZE; i++) + azt2316a->sb->dsp.azt_eeprom[i] = read_eeprom[i]; + + if (azt2316a->sb->opl_enabled) + opl3_init(&azt2316a->sb->opl); + + sb_dsp_init(&azt2316a->sb->dsp, SBPRO2, azt2316a->type, azt2316a); + sb_dsp_setaddr(&azt2316a->sb->dsp, azt2316a->cur_addr); + sb_dsp_setirq(&azt2316a->sb->dsp, azt2316a->cur_irq); + sb_dsp_setdma8(&azt2316a->sb->dsp, azt2316a->cur_dma); + sb_ct1345_mixer_reset(azt2316a->sb); + /* DSP I/O handler is activated in sb_dsp_setaddr */ + if (azt2316a->sb->opl_enabled) { + io_sethandler(azt2316a->cur_addr+0, 0x0004, opl3_read, NULL, NULL, opl3_write, NULL, NULL, &azt2316a->sb->opl); + io_sethandler(azt2316a->cur_addr+8, 0x0002, opl3_read, NULL, NULL, opl3_write, NULL, NULL, &azt2316a->sb->opl); + io_sethandler(0x0388, 0x0004, opl3_read, NULL, NULL, opl3_write, NULL, NULL, &azt2316a->sb->opl); + } + + io_sethandler(azt2316a->cur_addr+4, 0x0002, sb_ct1345_mixer_read, NULL, NULL, sb_ct1345_mixer_write, NULL, NULL, azt2316a->sb); + + azt2316a_create_config_word(azt2316a); + sound_add_handler(azt2316a_get_buffer, azt2316a); + + if (azt2316a->cur_mpu401_enabled) { + azt2316a->mpu = (mpu_t *) malloc(sizeof(mpu_t)); + memset(azt2316a->mpu, 0, sizeof(mpu_t)); + mpu401_init(azt2316a->mpu, azt2316a->cur_mpu401_addr, azt2316a->cur_mpu401_irq, M_UART, device_get_config_int("receive_input401")); + } else + azt2316a->mpu = NULL; + sb_dsp_set_mpu(azt2316a->mpu); + + if (device_get_config_int("receive_input")) + midi_in_handler(1, sb_dsp_input_msg, sb_dsp_input_sysex, &azt2316a->sb->dsp); + + return azt2316a; +} + +static void +azt_close(void *p) +{ + azt2316a_t *azt2316a = (azt2316a_t *)p; + wchar_t *fn = NULL; + FILE *f; + uint8_t checksum = 0x7f; + int i; + + if (azt2316a->type == SB_SUBTYPE_CLONE_AZT1605_0X0C) { + fn = L"azt1605.nvr"; + } else if (azt2316a->type == SB_SUBTYPE_CLONE_AZT2316A_0X11) { + fn = L"azt2316a.nvr"; + } + + /* always save to eeprom (recover from bad values) */ + f = nvr_fopen(fn, L"wb"); + if (f) { + for (i = 0; i < AZTECH_EEPROM_SIZE; i++) + checksum += azt2316a->sb->dsp.azt_eeprom[i]; + fwrite(azt2316a->sb->dsp.azt_eeprom, AZTECH_EEPROM_SIZE, 1, f); + + // TODO: confirm any models saving mixer settings to EEPROM and implement reading back + // TODO: should remember to save wss duplex setting if 86Box has voice recording implemented in the future? Also, default azt2316a->wss_config + // TODO: azt2316a->cur_mode is not saved to EEPROM? + fwrite(&checksum, sizeof(checksum), 1, f); + + fclose(f); + } + + sb_close(azt2316a->sb); + + free(azt2316a); +} + +static void +azt_speed_changed(void *p) +{ + azt2316a_t *azt2316a = (azt2316a_t *)p; + + ad1848_speed_changed(&azt2316a->ad1848); + sb_speed_changed(azt2316a->sb); +} + +static const device_config_t azt1605_config[] = +{ + { + .name = "codec", + .description = "CODEC", + .type = CONFIG_SELECTION, + .selection = + { + { + .description = "CS4248", + .value = AD1848_TYPE_CS4248 + }, + { + .description = "CS4231", + .value = AD1848_TYPE_CS4231 + }, + }, + .default_int = AD1848_TYPE_CS4248 + }, + { + .name = "wss_interrupt_after_config", + .description = "Raise CODEC interrupt on CODEC setup (needed by some drivers)", + .type = CONFIG_BINARY, + .default_int = 0 + }, + { + "addr", "SB Address", CONFIG_HEX16, "", 0, + { + { + "0x220", 0x220 + }, + { + "0x240", 0x240 + }, + { + "Use EEPROM setting", 0 + }, + { + "" + } + } + }, + { + .name = "sb_dma8", + .description = "SB low DMA", + .type = CONFIG_SELECTION, + .selection = + { + { + .description = "DMA 0", + .value = 0 + }, + { + .description = "DMA 1", + .value = 1 + }, + { + .description = "DMA 3", + .value = 3 + }, + { + .description = "" + } + }, + .default_int = 1 + }, + { + "opl", "Enable OPL", CONFIG_BINARY, "", 1 + }, + { + "receive_input", "Receive input (SB MIDI)", CONFIG_BINARY, "", 1 + }, + { + "receive_input401", "Receive input (MPU-401)", CONFIG_BINARY, "", 0 + }, + { + "", "", -1 + } +}; + +static const device_config_t azt2316a_config[] = +{ + { + .name = "codec", + .description = "CODEC", + .type = CONFIG_SELECTION, + .selection = + { + { + .description = "CS4248", + .value = AD1848_TYPE_CS4248 + }, + { + .description = "CS4231", + .value = AD1848_TYPE_CS4231 + }, + }, + .default_int = AD1848_TYPE_CS4248 + }, + { + .name = "wss_interrupt_after_config", + .description = "Raise CODEC interrupt on CODEC setup (needed by some drivers)", + .type = CONFIG_BINARY, + .default_int = 0 + }, + { + "addr", "SB Address", CONFIG_HEX16, "", 0, + { + { + "0x220", 0x220 + }, + { + "0x240", 0x240 + }, + { + "Use EEPROM setting", 0 + }, + { + "" + } + } + }, + { + "opl", "Enable OPL", CONFIG_BINARY, "", 1 + }, + { + "receive_input", "Receive input (SB MIDI)", CONFIG_BINARY, "", 1 + }, + { + "receive_input401", "Receive input (MPU-401)", CONFIG_BINARY, "", 0 + }, + { + "", "", -1 + } +}; + +const device_t azt2316a_device = +{ + "Aztech Sound Galaxy Pro 16 AB (Washington)", + DEVICE_ISA | DEVICE_AT, + SB_SUBTYPE_CLONE_AZT2316A_0X11, + azt_init, azt_close, NULL, NULL, + azt_speed_changed, + NULL, + azt2316a_config +}; + +const device_t azt1605_device = +{ + "Aztech Sound Galaxy Nova 16 Extra (Clinton)", + DEVICE_ISA | DEVICE_AT, + SB_SUBTYPE_CLONE_AZT1605_0X0C, + azt_init, azt_close, NULL, NULL, + azt_speed_changed, + NULL, + azt1605_config +}; diff --git a/src/sound/snd_azt2316a.h b/src/sound/snd_azt2316a.h new file mode 100644 index 000000000..852de6c92 --- /dev/null +++ b/src/sound/snd_azt2316a.h @@ -0,0 +1 @@ +extern void azt2316a_enable_wss(uint8_t enable, void *p); \ No newline at end of file diff --git a/src/sound/snd_mpu401.c b/src/sound/snd_mpu401.c index bdea9d911..21ccc99d8 100644 --- a/src/sound/snd_mpu401.c +++ b/src/sound/snd_mpu401.c @@ -1593,6 +1593,11 @@ MPU401_InputMsg(void *p, uint8_t *msg) MPU401_QueueByte(mpu, msg[i]); } +void +mpu401_setirq(mpu_t *mpu, int irq) +{ + mpu->irq = irq; +} void mpu401_change_addr(mpu_t *mpu, uint16_t addr) @@ -1711,7 +1716,7 @@ mpu401_standalone_init(const device_t *info) mpu401_log("mpu_init\n"); if (info->flags & DEVICE_MCA) { - mca_add(mpu401_mca_read, mpu401_mca_write, mpu401_mca_feedb, mpu); + mca_add(mpu401_mca_read, mpu401_mca_write, mpu401_mca_feedb, NULL, mpu); mpu->pos_regs[0] = 0x0F; mpu->pos_regs[1] = 0x6C; base = 0; /* Tell mpu401_init() that this is the MCA variant. */ diff --git a/src/sound/snd_mpu401.h b/src/sound/snd_mpu401.h index 99fe8b288..61eaa654b 100644 --- a/src/sound/snd_mpu401.h +++ b/src/sound/snd_mpu401.h @@ -150,6 +150,7 @@ extern const device_t mpu401_mca_device; extern uint8_t MPU401_ReadData(mpu_t *mpu); +extern void mpu401_setirq(mpu_t *mpu, int irq); extern void mpu401_change_addr(mpu_t *mpu, uint16_t addr); extern void mpu401_init(mpu_t *mpu, uint16_t addr, int irq, int mode, int receive_input); extern void mpu401_device_add(void); diff --git a/src/sound/snd_pas16.c b/src/sound/snd_pas16.c index 19aae50dc..717b45122 100644 --- a/src/sound/snd_pas16.c +++ b/src/sound/snd_pas16.c @@ -737,7 +737,7 @@ static void *pas16_init(const device_t *info) memset(pas16, 0, sizeof(pas16_t)); opl3_init(&pas16->opl); - sb_dsp_init(&pas16->dsp, SB2); + sb_dsp_init(&pas16->dsp, SB2, SB_SUBTYPE_DEFAULT, pas16); io_sethandler(0x9a01, 0x0001, NULL, NULL, NULL, pas16_out_base, NULL, NULL, pas16); diff --git a/src/sound/snd_sb.c b/src/sound/snd_sb.c index 25ed6b87d..ce489d022 100644 --- a/src/sound/snd_sb.c +++ b/src/sound/snd_sb.c @@ -35,10 +35,7 @@ #include "sound.h" #include "midi.h" #include "filters.h" -#include "snd_emu8k.h" -#include "snd_mpu401.h" -#include "snd_opl.h" -#include "snd_sb_dsp.h" +#include "snd_sb.h" //#define SB_DSP_RECORD_DEBUG @@ -48,102 +45,6 @@ FILE* soundfsbin = 0/*NULL*/; #endif - -/* SB 2.0 CD version */ -typedef struct sb_ct1335_mixer_t -{ - int32_t master; - int32_t voice; - int32_t fm; - int32_t cd; - - uint8_t index; - uint8_t regs[256]; -} sb_ct1335_mixer_t; -/* SB PRO */ -typedef struct sb_ct1345_mixer_t -{ - int32_t master_l, master_r; - int32_t voice_l, voice_r; - int32_t fm_l, fm_r; - int32_t cd_l, cd_r; - int32_t line_l, line_r; - int32_t mic; - /*see sb_ct1745_mixer for values for input selector*/ - int32_t input_selector; - - int input_filter; - int in_filter_freq; - int output_filter; - - int stereo; - int stereo_isleft; - - uint8_t index; - uint8_t regs[256]; - -} sb_ct1345_mixer_t; -/* SB16 and AWE32 */ -typedef struct sb_ct1745_mixer_t -{ - int32_t master_l, master_r; - int32_t voice_l, voice_r; - int32_t fm_l, fm_r; - int32_t cd_l, cd_r; - int32_t line_l, line_r; - int32_t mic; - int32_t speaker; - - int bass_l, bass_r; - int treble_l, treble_r; - - int output_selector; - #define OUTPUT_MIC 1 - #define OUTPUT_CD_R 2 - #define OUTPUT_CD_L 4 - #define OUTPUT_LINE_R 8 - #define OUTPUT_LINE_L 16 - - int input_selector_left; - int input_selector_right; - #define INPUT_MIC 1 - #define INPUT_CD_R 2 - #define INPUT_CD_L 4 - #define INPUT_LINE_R 8 - #define INPUT_LINE_L 16 - #define INPUT_MIDI_R 32 - #define INPUT_MIDI_L 64 - - int mic_agc; - - int32_t input_gain_L; - int32_t input_gain_R; - int32_t output_gain_L; - int32_t output_gain_R; - - uint8_t index; - uint8_t regs[256]; -} sb_ct1745_mixer_t; - -typedef struct sb_t -{ - uint8_t opl_enabled; - opl_t opl; - sb_dsp_t dsp; - union { - sb_ct1335_mixer_t mixer_sb2; - sb_ct1345_mixer_t mixer_sbpro; - sb_ct1745_mixer_t mixer_sb16; - }; - mpu_t *mpu; - emu8k_t emu8k; - - int pos; - - uint8_t pos_regs[8]; - - int opl_emu; -} sb_t; /* 0 to 7 -> -14dB to 0dB i 2dB steps. 8 to 15 -> 0 to +14dB in 2dB steps. Note that for positive dB values, this is not amplitude, it is amplitude-1. */ const float sb_bass_treble_4bits[]= { @@ -247,7 +148,7 @@ static void sb_get_buffer_sb2_mixer(int32_t *buffer, int len, void *p) sb->dsp.pos = 0; } -static void sb_get_buffer_sbpro(int32_t *buffer, int len, void *p) +void sb_get_buffer_sbpro(int32_t *buffer, int len, void *p) { sb_t *sb = (sb_t *)p; sb_ct1345_mixer_t *mixer = &sb->mixer_sbpro; @@ -860,149 +761,147 @@ void sb_ct1745_mixer_write(uint16_t addr, uint8_t val, void *p) uint8_t sb_ct1745_mixer_read(uint16_t addr, void *p) { - sb_t *sb = (sb_t *)p; - sb_ct1745_mixer_t *mixer = &sb->mixer_sb16; + sb_t *sb = (sb_t *)p; + sb_ct1745_mixer_t *mixer = &sb->mixer_sb16; uint8_t temp, ret = 0xff; - if (!(addr & 1)) - ret = mixer->index; + if (!(addr & 1)) + ret = mixer->index; - sb_log("sb_ct1745: received register READ: %02X\t%02X\n", mixer->index, mixer->regs[mixer->index]); + sb_log("sb_ct1745: received register READ: %02X\t%02X\n", mixer->index, mixer->regs[mixer->index]); - if (mixer->index>=0x30 && mixer->index<=0x47) - ret = mixer->regs[mixer->index]; - else switch (mixer->index) - { - case 0x00: - ret = mixer->regs[mixer->index]; - break; + if (mixer->index>=0x30 && mixer->index<=0x47) + ret = mixer->regs[mixer->index]; + else switch (mixer->index) { + case 0x00: + ret = mixer->regs[mixer->index]; + break; - /*SB Pro compatibility*/ - case 0x04: - ret = ((mixer->regs[0x33] >> 4) & 0x0f) | (mixer->regs[0x32] & 0xf0); - break; - case 0x0a: - // ret = (mixer->regs[0x3a] - 10) / 3; - ret = (mixer->regs[0x3a] >> 5); - break; - case 0x02: - ret = ((mixer->regs[0x30] >> 4) & 0x0f); - break; - case 0x06: - ret = ((mixer->regs[0x34] >> 4) & 0x0f); - break; - case 0x08: - ret = ((mixer->regs[0x36] >> 4) & 0x0f); - break; - case 0x22: - ret = ((mixer->regs[0x31] >> 4) & 0x0f) | (mixer->regs[0x30] & 0xf0); - break; - case 0x26: - ret = ((mixer->regs[0x35] >> 4) & 0x0f) | (mixer->regs[0x34] & 0xf0); - break; - case 0x28: - ret = ((mixer->regs[0x37] >> 4) & 0x0f) | (mixer->regs[0x36] & 0xf0); - break; - case 0x2e: - ret = ((mixer->regs[0x39] >> 4) & 0x0f) | (mixer->regs[0x38] & 0xf0); - break; + /*SB Pro compatibility*/ + case 0x04: + ret = ((mixer->regs[0x33] >> 4) & 0x0f) | (mixer->regs[0x32] & 0xf0); + break; + case 0x0a: + // ret = (mixer->regs[0x3a] - 10) / 3; + ret = (mixer->regs[0x3a] >> 5); + break; + case 0x02: + ret = ((mixer->regs[0x30] >> 4) & 0x0f); + break; + case 0x06: + ret = ((mixer->regs[0x34] >> 4) & 0x0f); + break; + case 0x08: + ret = ((mixer->regs[0x36] >> 4) & 0x0f); + break; + case 0x22: + ret = ((mixer->regs[0x31] >> 4) & 0x0f) | (mixer->regs[0x30] & 0xf0); + break; + case 0x26: + ret = ((mixer->regs[0x35] >> 4) & 0x0f) | (mixer->regs[0x34] & 0xf0); + break; + case 0x28: + ret = ((mixer->regs[0x37] >> 4) & 0x0f) | (mixer->regs[0x36] & 0xf0); + break; + case 0x2e: + ret = ((mixer->regs[0x39] >> 4) & 0x0f) | (mixer->regs[0x38] & 0xf0); + break; - case 0x48: - // Undocumented. The Creative Windows Mixer calls this after calling 3C (input selector). even when writing. - // Also, the version I have (5.17) does not use the MIDI.L/R input selectors. it uses the volume to mute (Affecting the output, obviously) - ret = mixer->regs[mixer->index]; - break; + case 0x48: + // Undocumented. The Creative Windows Mixer calls this after calling 3C (input selector). even when writing. + // Also, the version I have (5.17) does not use the MIDI.L/R input selectors. it uses the volume to mute (Affecting the output, obviously) + ret = mixer->regs[mixer->index]; + break; - case 0x80: - /*TODO: Unaffected by mixer reset or soft reboot. - * Enabling multiple bits enables multiple IRQs. - */ + case 0x80: + /*TODO: Unaffected by mixer reset or soft reboot. + * Enabling multiple bits enables multiple IRQs. + */ - switch (sb->dsp.sb_irqnum) - { - case 2: ret = 1; break; - case 5: ret = 2; break; - case 7: ret = 4; break; - case 10: ret = 8; break; - } - break; + switch (sb->dsp.sb_irqnum) { + case 2: ret = 1; break; + case 5: ret = 2; break; + case 7: ret = 4; break; + case 10: ret = 8; break; + } + break; - case 0x81: - /* TODO: Unaffected by mixer reset or soft reboot. - * Enabling multiple 8 or 16-bit DMA bits enables multiple DMA channels. - * Disabling all 8-bit DMA channel bits disables 8-bit DMA requests, - including translated 16-bit DMA requests. - * Disabling all 16-bit DMA channel bits enables translation of 16-bit DMA - requests to 8-bit ones, using the selected 8-bit DMA channel.*/ + case 0x81: + /* TODO: Unaffected by mixer reset or soft reboot. + * Enabling multiple 8 or 16-bit DMA bits enables multiple DMA channels. + * Disabling all 8-bit DMA channel bits disables 8-bit DMA requests, + including translated 16-bit DMA requests. + * Disabling all 16-bit DMA channel bits enables translation of 16-bit DMA + requests to 8-bit ones, using the selected 8-bit DMA channel.*/ - ret = 0; - switch (sb->dsp.sb_8_dmanum) { - case 0: ret |= 1; break; - case 1: ret |= 2; break; - case 3: ret |= 8; break; - } - switch (sb->dsp.sb_16_dmanum) - { - case 5: ret |= 0x20; break; - case 6: ret |= 0x40; break; - case 7: ret |= 0x80; break; - } - break; + ret = 0; + switch (sb->dsp.sb_8_dmanum) { + case 0: ret |= 1; break; + case 1: ret |= 2; break; + case 3: ret |= 8; break; + } + switch (sb->dsp.sb_16_dmanum) { + case 5: ret |= 0x20; break; + case 6: ret |= 0x40; break; + case 7: ret |= 0x80; break; + } + break; - /* The Interrupt status register, addressed as register 82h on the Mixer register map, + /* The Interrupt status register, addressed as register 82h on the Mixer register map, is used by the ISR to determine whether the interrupt is meant for it or for some other ISR, - in which case it should chain to the previous routine. - */ - case 0x82: - /* 0 = none, 1 = digital 8bit or SBMIDI, 2 = digital 16bit, 4 = MPU-401 */ - /* 0x02000 DSP v4.04, 0x4000 DSP v4.05 0x8000 DSP v4.12. I haven't seen this making any difference, but I'm keeping it for now. */ - temp = ((sb->dsp.sb_irq8) ? 1 : 0) | ((sb->dsp.sb_irq16) ? 2 : 0) | 0x4000; - if (sb->mpu) - temp |= ((sb->mpu->state.irq_pending) ? 4 : 0); - ret = temp; - break; + in which case it should chain to the previous routine. + */ + case 0x82: + /* 0 = none, 1 = digital 8bit or SBMIDI, 2 = digital 16bit, 4 = MPU-401 */ + /* 0x02000 DSP v4.04, 0x4000 DSP v4.05 0x8000 DSP v4.12. I haven't seen this making any difference, but I'm keeping it for now. */ + temp = ((sb->dsp.sb_irq8) ? 1 : 0) | ((sb->dsp.sb_irq16) ? 2 : 0) | 0x4000; + if (sb->mpu) + temp |= ((sb->mpu->state.irq_pending) ? 4 : 0); + ret = temp; + break; case 0x83: - /* Interrupt mask. */ - ret = mixer->regs[mixer->index]; - break; + /* Interrupt mask. */ + ret = mixer->regs[mixer->index]; + break; case 0x84: - /* MPU Control. */ - if (sb->mpu == NULL) - ret = 0x02; - else { - if (sb->mpu->addr == 0x330) - ret = 0x00; - else if (sb->mpu->addr == 0x300) - ret = 0x04; - else if (sb->mpu->addr == 0) + /* MPU Control. */ + if (sb->mpu == NULL) ret = 0x02; - else - ret = 0x06; /* Should never happen. */ - } - break; + else { + if (sb->mpu->addr == 0x330) + ret = 0x00; + else if (sb->mpu->addr == 0x300) + ret = 0x04; + else if (sb->mpu->addr == 0) + ret = 0x02; + else + ret = 0x06; /* Should never happen. */ + } + break; case 0x90: - /* 3D Enhancement switch. */ - ret = mixer->regs[mixer->index]; - break; + /* 3D Enhancement switch. */ + ret = mixer->regs[mixer->index]; + break; /* TODO: creative drivers read and write on 0xFE and 0xFF. not sure what they are supposed to be. */ - case 0xfd: - ret = 16; - break; + case 0xfd: + ret = 16; + break; case 0xfe: - ret = 6; - break; + ret = 6; + break; - default: - sb_log("sb_ct1745: Unknown register READ: %02X\t%02X\n", mixer->index, mixer->regs[mixer->index]); - break; - } + default: + sb_log("sb_ct1745: Unknown register READ: %02X\t%02X\n", mixer->index, mixer->regs[mixer->index]); + break; + } - return ret; + sb_log("CT1745: read REG%02X: %02X\n", mixer->index, ret); + return ret; } void sb_ct1745_mixer_reset(sb_t* sb) @@ -1126,7 +1025,7 @@ void *sb_1_init(const device_t *info) sb->opl_enabled = device_get_config_int("opl"); if (sb->opl_enabled) opl2_init(&sb->opl); - sb_dsp_init(&sb->dsp, SB1); + sb_dsp_init(&sb->dsp, SB1, SB_SUBTYPE_DEFAULT, sb); sb_dsp_setaddr(&sb->dsp, addr); sb_dsp_setirq(&sb->dsp, device_get_config_int("irq")); sb_dsp_setdma8(&sb->dsp, device_get_config_int("dma")); @@ -1156,7 +1055,7 @@ void *sb_15_init(const device_t *info) sb->opl_enabled = device_get_config_int("opl"); if (sb->opl_enabled) opl2_init(&sb->opl); - sb_dsp_init(&sb->dsp, SB15); + sb_dsp_init(&sb->dsp, SB15, SB_SUBTYPE_DEFAULT, sb); sb_dsp_setaddr(&sb->dsp, addr); sb_dsp_setirq(&sb->dsp, device_get_config_int("irq")); sb_dsp_setdma8(&sb->dsp, device_get_config_int("dma")); @@ -1185,13 +1084,13 @@ void *sb_mcv_init(const device_t *info) sb->opl_enabled = device_get_config_int("opl"); if (sb->opl_enabled) opl2_init(&sb->opl); - sb_dsp_init(&sb->dsp, SB15); + sb_dsp_init(&sb->dsp, SB15, SB_SUBTYPE_DEFAULT, sb); sb_dsp_setaddr(&sb->dsp, 0);//addr); sb_dsp_setirq(&sb->dsp, device_get_config_int("irq")); sb_dsp_setdma8(&sb->dsp, device_get_config_int("dma")); sound_add_handler(sb_get_buffer_sb2, sb); /* I/O handlers activated in sb_mcv_write */ - mca_add(sb_mcv_read, sb_mcv_write, sb_mcv_feedb, sb); + mca_add(sb_mcv_read, sb_mcv_write, sb_mcv_feedb, NULL, sb); sb->pos_regs[0] = 0x84; sb->pos_regs[1] = 0x50; @@ -1222,7 +1121,7 @@ void *sb_2_init(const device_t *info) sb->opl_enabled = device_get_config_int("opl"); if (sb->opl_enabled) opl2_init(&sb->opl); - sb_dsp_init(&sb->dsp, SB2); + sb_dsp_init(&sb->dsp, SB2, SB_SUBTYPE_DEFAULT, sb); sb_dsp_setaddr(&sb->dsp, addr); sb_dsp_setirq(&sb->dsp, device_get_config_int("irq")); sb_dsp_setdma8(&sb->dsp, device_get_config_int("dma")); @@ -1266,7 +1165,7 @@ void *sb_pro_v1_init(const device_t *info) sb->opl_enabled = device_get_config_int("opl"); if (sb->opl_enabled) opl2_init(&sb->opl); - sb_dsp_init(&sb->dsp, SBPRO); + sb_dsp_init(&sb->dsp, SBPRO, SB_SUBTYPE_DEFAULT, sb); sb_dsp_setaddr(&sb->dsp, addr); sb_dsp_setirq(&sb->dsp, device_get_config_int("irq")); sb_dsp_setdma8(&sb->dsp, device_get_config_int("dma")); @@ -1302,7 +1201,7 @@ void *sb_pro_v2_init(const device_t *info) sb->opl_enabled = device_get_config_int("opl"); if (sb->opl_enabled) opl3_init(&sb->opl); - sb_dsp_init(&sb->dsp, SBPRO2); + sb_dsp_init(&sb->dsp, SBPRO2, SB_SUBTYPE_DEFAULT, sb); sb_dsp_setaddr(&sb->dsp, addr); sb_dsp_setirq(&sb->dsp, device_get_config_int("irq")); sb_dsp_setdma8(&sb->dsp, device_get_config_int("dma")); @@ -1334,13 +1233,13 @@ void *sb_pro_mcv_init(const device_t *info) sb->opl_enabled = 1; opl3_init(&sb->opl); - sb_dsp_init(&sb->dsp, SBPRO2); + sb_dsp_init(&sb->dsp, SBPRO2, SB_SUBTYPE_DEFAULT, sb); sb_ct1345_mixer_reset(sb); /* I/O handlers activated in sb_mcv_write */ sound_add_handler(sb_get_buffer_sbpro, sb); /* I/O handlers activated in sb_pro_mcv_write */ - mca_add(sb_pro_mcv_read, sb_pro_mcv_write, sb_mcv_feedb, sb); + mca_add(sb_pro_mcv_read, sb_pro_mcv_write, sb_mcv_feedb, NULL, sb); sb->pos_regs[0] = 0x03; sb->pos_regs[1] = 0x51; @@ -1360,7 +1259,7 @@ void *sb_16_init(const device_t *info) sb->opl_enabled = device_get_config_int("opl"); if (sb->opl_enabled) opl3_init(&sb->opl); - sb_dsp_init(&sb->dsp, SB16); + sb_dsp_init(&sb->dsp, SB16, SB_SUBTYPE_DEFAULT, sb); sb_dsp_setaddr(&sb->dsp, addr); sb_dsp_setirq(&sb->dsp, device_get_config_int("irq")); sb_dsp_setdma8(&sb->dsp, device_get_config_int("dma")); @@ -1406,7 +1305,7 @@ void *sb_awe32_init(const device_t *info) if (sb->opl_enabled) opl3_init(&sb->opl); - sb_dsp_init(&sb->dsp, SB16 + 1); + sb_dsp_init(&sb->dsp, SB16 + 1, SB_SUBTYPE_DEFAULT, sb); sb_dsp_setaddr(&sb->dsp, addr); sb_dsp_setirq(&sb->dsp, device_get_config_int("irq")); sb_dsp_setdma8(&sb->dsp, device_get_config_int("dma")); diff --git a/src/sound/snd_sb.h b/src/sound/snd_sb.h new file mode 100644 index 000000000..ee996b923 --- /dev/null +++ b/src/sound/snd_sb.h @@ -0,0 +1,143 @@ +/* + * 86Box A hypervisor and IBM PC system emulator that specializes in + * running old operating systems and software designed for IBM + * PC systems and compatibles from 1981 through fairly recent + * system designs based on the PCI bus. + * + * This file is part of the 86Box distribution. + * + * Sound Blaster emulation. + * + * Version: @(#)sound_sb.h 1.0.4 2020/02/17 + * + * Authors: Sarah Walker, + * Miran Grca, + * TheCollector1995, + * + * Copyright 2008-2018 Sarah Walker. + * Copyright 2016-2018 Miran Grca. + */ +#ifndef SOUND_SND_SB_H +# define SOUND_SND_SB_H + +#include "snd_emu8k.h" +#include "snd_mpu401.h" +#include "snd_opl.h" +#include "snd_sb_dsp.h" + +#define SADLIB 1 /* No DSP */ +#define SB1 2 /* DSP v1.05 */ +#define SB15 3 /* DSP v2.00 */ +#define SB2 4 /* DSP v2.01 - needed for high-speed DMA */ +#define SBPRO 5 /* DSP v3.00 */ +#define SBPRO2 6 /* DSP v3.02 + OPL3 */ +#define SB16 7 /* DSP v4.05 + OPL3 */ +#define SADGOLD 8 /* AdLib Gold */ +#define SND_WSS 9 /* Windows Sound System */ +#define SND_PAS16 10 /* Pro Audio Spectrum 16 */ + +/* SB 2.0 CD version */ +typedef struct sb_ct1335_mixer_t +{ + int32_t master; + int32_t voice; + int32_t fm; + int32_t cd; + + uint8_t index; + uint8_t regs[256]; +} sb_ct1335_mixer_t; +/* SB PRO */ +typedef struct sb_ct1345_mixer_t +{ + int32_t master_l, master_r; + int32_t voice_l, voice_r; + int32_t fm_l, fm_r; + int32_t cd_l, cd_r; + int32_t line_l, line_r; + int32_t mic; + /*see sb_ct1745_mixer for values for input selector*/ + int32_t input_selector; + + int input_filter; + int in_filter_freq; + int output_filter; + + int stereo; + int stereo_isleft; + + uint8_t index; + uint8_t regs[256]; + +} sb_ct1345_mixer_t; +/* SB16 and AWE32 */ +typedef struct sb_ct1745_mixer_t +{ + int32_t master_l, master_r; + int32_t voice_l, voice_r; + int32_t fm_l, fm_r; + int32_t cd_l, cd_r; + int32_t line_l, line_r; + int32_t mic; + int32_t speaker; + + int bass_l, bass_r; + int treble_l, treble_r; + + int output_selector; + #define OUTPUT_MIC 1 + #define OUTPUT_CD_R 2 + #define OUTPUT_CD_L 4 + #define OUTPUT_LINE_R 8 + #define OUTPUT_LINE_L 16 + + int input_selector_left; + int input_selector_right; + #define INPUT_MIC 1 + #define INPUT_CD_R 2 + #define INPUT_CD_L 4 + #define INPUT_LINE_R 8 + #define INPUT_LINE_L 16 + #define INPUT_MIDI_R 32 + #define INPUT_MIDI_L 64 + + int mic_agc; + + int32_t input_gain_L; + int32_t input_gain_R; + int32_t output_gain_L; + int32_t output_gain_R; + + uint8_t index; + uint8_t regs[256]; +} sb_ct1745_mixer_t; + +typedef struct sb_t +{ + uint8_t opl_enabled; + opl_t opl; + sb_dsp_t dsp; + union { + sb_ct1335_mixer_t mixer_sb2; + sb_ct1345_mixer_t mixer_sbpro; + sb_ct1745_mixer_t mixer_sb16; + }; + mpu_t *mpu; + emu8k_t emu8k; + + int pos; + + uint8_t pos_regs[8]; + + int opl_emu; +} sb_t; + +extern void sb_ct1345_mixer_write(uint16_t addr, uint8_t val, void *p); +extern uint8_t sb_ct1345_mixer_read(uint16_t addr, void *p); +extern void sb_ct1345_mixer_reset(sb_t* sb); + +extern void sb_get_buffer_sbpro(int32_t *buffer, int len, void *p); +extern void sb_close(void *p); +extern void sb_speed_changed(void *p); + +#endif /*SOUND_SND_SB_H*/ diff --git a/src/sound/snd_sb_dsp.c b/src/sound/snd_sb_dsp.c index 5f86e79e6..5006b9b25 100644 --- a/src/sound/snd_sb_dsp.c +++ b/src/sound/snd_sb_dsp.c @@ -22,8 +22,8 @@ #include "sound.h" #include "midi.h" #include "sound.h" -#include "snd_mpu401.h" -#include "snd_sb_dsp.h" +#include "snd_azt2316a.h" +#include "snd_sb.h" #define ADPCM_4 1 @@ -244,10 +244,16 @@ sb_doreset(sb_dsp_t *dsp) sb_dsp_reset(dsp); - if (dsp->sb_type==SB16) - sb_commands[8] = 1; - else - sb_commands[8] = -1; + + if (IS_AZTECH(dsp)) { + sb_commands[8] = 1; + sb_commands[9] = 1; + } else { + if (dsp->sb_type==SB16) + sb_commands[8] = 1; + else + sb_commands[8] = -1; + } for (c = 0; c < 256; c++) dsp->sb_asp_regs[c] = 0; @@ -648,6 +654,16 @@ sb_exec_command(sb_dsp_t *dsp) sb_add_data(dsp, ~dsp->sb_data[0]); break; case 0xE1: /* Get DSP version */ + if (IS_AZTECH(dsp)) { + if (dsp->sb_subtype == SB_SUBTYPE_CLONE_AZT2316A_0X11) { + sb_add_data(dsp, 0x3); + sb_add_data(dsp, 0x1); + } else if (dsp->sb_subtype == SB_SUBTYPE_CLONE_AZT1605_0X0C) { + sb_add_data(dsp, 0x2); + sb_add_data(dsp, 0x1); + } + break; + } sb_add_data(dsp, sb_dsp_versions[dsp->sb_type] >> 8); sb_add_data(dsp, sb_dsp_versions[dsp->sb_type] & 0xff); break; @@ -687,6 +703,29 @@ sb_exec_command(sb_dsp_t *dsp) case 0x07: case 0xFF: /* No, that's not how you program auto-init DMA */ break; case 0x08: /* ASP get version */ + if (IS_AZTECH(dsp)) { + if ((dsp->sb_data[0] == 0x05 || dsp->sb_data[0] == 0x55)&& dsp->sb_subtype == SB_SUBTYPE_CLONE_AZT2316A_0X11) + sb_add_data(dsp, 0x11); /* AZTECH get type, WASHINGTON/latest - according to devkit. E.g.: The one in the Itautec Infoway Multimidia */ + else if ((dsp->sb_data[0] == 0x05 || dsp->sb_data[0] == 0x55) && dsp->sb_subtype == SB_SUBTYPE_CLONE_AZT1605_0X0C) + sb_add_data(dsp, 0x0C); /* AZTECH get type, CLINTON - according to devkit. E.g.: The one in the Packard Bell Legend 100CD */ + else if (dsp->sb_data[0] == 0x08) { + /* EEPROM address to write followed by byte */ + if (dsp->sb_data[1] < 0 || dsp->sb_data[1] >= AZTECH_EEPROM_SIZE) + fatal("AZT EEPROM: out of bounds write to %02X\n", dsp->sb_data[1]); + sb_dsp_log("EEPROM write = %02x\n", dsp->sb_data[2]); + dsp->azt_eeprom[dsp->sb_data[1]] = dsp->sb_data[2]; + break; + } else if (dsp->sb_data[0] == 0x07) { + /* EEPROM address to read */ + if (dsp->sb_data[1] < 0 || dsp->sb_data[1] >= AZTECH_EEPROM_SIZE) + fatal("AZT EEPROM: out of bounds read to %02X\n", dsp->sb_data[1]); + sb_dsp_log("EEPROM read = %02x\n", dsp->azt_eeprom[dsp->sb_data[1]]); + sb_add_data(dsp, dsp->azt_eeprom[dsp->sb_data[1]]); + break; + } else + sb_dsp_log("AZT2316A: UNKNOWN 0x08 COMMAND: %02X\n", dsp->sb_data[0]); /* 0x08 (when shutting down, driver tries to read 1 byte of response), 0x55, 0x0D, 0x08D seen */ + break; + } if (dsp->sb_type >= SB16) sb_add_data(dsp, 0x18); break; @@ -716,6 +755,17 @@ sb_exec_command(sb_dsp_t *dsp) case 0x04: case 0x05: break; + case 0x09: /*AZTECH mode set*/ + if (dsp->sb_data[0] == 0x00) { + sb_dsp_log("AZT2316A: WSS MODE!\n"); + azt2316a_enable_wss(1, dsp->parent); + } else if (dsp->sb_data[0] == 0x01) { + sb_dsp_log("AZT2316A: SB8PROV2 MODE!\n"); + azt2316a_enable_wss(0, dsp->parent); + } else + sb_dsp_log("AZT2316A: UNKNOWN MODE! = %02x\n", dsp->sb_data[0]); // sequences 0x02->0xFF, 0x04->0xFF seen + break; + /* TODO: Some more data about the DSP registeres * http://the.earth.li/~tfm/oldpage/sb_dsp.html * http://www.synchrondata.com/pheaven/www/area19.htm @@ -770,11 +820,24 @@ sb_write(uint16_t a, uint8_t v, void *priv) if (v == 0x01) sb_add_data(dsp, 0); dsp->sb_data_stat++; - } else + } else { dsp->sb_data[dsp->sb_data_stat++] = v; + if (IS_AZTECH(dsp)) { + /* variable length commands */ + if (dsp->sb_command == 0x08 && dsp->sb_data_stat == 1 && dsp->sb_data[0] == 0x08) + sb_commands[dsp->sb_command] = 3; + else if (dsp->sb_command == 0x08 && dsp->sb_data_stat == 1 && dsp->sb_data[0] == 0x07) + sb_commands[dsp->sb_command] = 2; + } + } if (dsp->sb_data_stat == sb_commands[dsp->sb_command] || sb_commands[dsp->sb_command] == -1) { sb_exec_command(dsp); dsp->sb_data_stat = -1; + if (IS_AZTECH(dsp)) { + /* variable length commands */ + if (dsp->sb_command == 0x08) + sb_commands[dsp->sb_command] = 1; + } } break; } @@ -807,19 +870,39 @@ sb_read(uint16_t a, void *priv) dsp->busy_count = 0; if (dsp->wb_full || (dsp->busy_count & 2)) { dsp->wb_full = timer_is_enabled(&dsp->wb_timer); - return 0xff; + if (IS_AZTECH(dsp)) { + sb_dsp_log("SB Write Data Aztech read 0x80\n"); + return 0x80; + } else { + sb_dsp_log("SB Write Data Creative read 0xff\n"); + return 0xff; + } + } + if (IS_AZTECH(dsp)) { + sb_dsp_log("SB Write Data Aztech read 0x00\n"); + ret = 0x00; + } else { + sb_dsp_log("SB Write Data Creative read 0x7f\n"); + ret = 0x7f; } - ret = 0x7f; break; case 0xE: /* Read data ready */ picintc(1 << dsp->sb_irqnum); dsp->sb_irq8 = dsp->sb_irq16 = 0; - ret = (dsp->sb_read_rp == dsp->sb_read_wp) ? 0x7f : 0xff; + /* Only bit 7 is defined but aztech diagnostics fail if the others are set. Keep the original behavior to not interfere with what's already working. */ + if (IS_AZTECH(dsp)) { + sb_dsp_log("SB Read Data Aztech read %02X, Read RP = %d, Read WP = %d\n",(dsp->sb_read_rp == dsp->sb_read_wp) ? 0x00 : 0x80, dsp->sb_read_rp, dsp->sb_read_wp); + ret = (dsp->sb_read_rp == dsp->sb_read_wp) ? 0x00 : 0x80; + } else { + sb_dsp_log("SB Read Data Creative read %02X\n",(dsp->sb_read_rp == dsp->sb_read_wp) ? 0x7f : 0xff); + ret = (dsp->sb_read_rp == dsp->sb_read_wp) ? 0x7f : 0xff; + } break; case 0xF: /* 16-bit ack */ dsp->sb_irq16 = 0; if (!dsp->sb_irq8) picintc(1 << dsp->sb_irqnum); + sb_dsp_log("SB 16-bit ACK read 0xFF\n"); ret = 0xff; break; } @@ -892,9 +975,11 @@ sb_dsp_input_sysex(void *p, uint8_t *buffer, uint32_t len, int abort) } void -sb_dsp_init(sb_dsp_t *dsp, int type) +sb_dsp_init(sb_dsp_t *dsp, int type, int subtype, void *parent) { dsp->sb_type = type; + dsp->sb_subtype = subtype; + dsp->parent = parent; /* Default values. Use sb_dsp_setxxx() methods to change. */ dsp->sb_irqnum = 7; diff --git a/src/sound/snd_sb_dsp.h b/src/sound/snd_sb_dsp.h index 96743e77e..47cc2570f 100644 --- a/src/sound/snd_sb_dsp.h +++ b/src/sound/snd_sb_dsp.h @@ -1,92 +1,96 @@ -#define SADLIB 1 /* No DSP */ -#define SB1 2 /* DSP v1.05 */ -#define SB15 3 /* DSP v2.00 */ -#define SB2 4 /* DSP v2.01 - needed for high-speed DMA */ -#define SBPRO 5 /* DSP v3.00 */ -#define SBPRO2 6 /* DSP v3.02 + OPL3 */ -#define SB16 7 /* DSP v4.05 + OPL3 */ -#define SADGOLD 8 /* AdLib Gold */ -#define SND_WSS 9 /* Windows Sound System */ -#define SND_PAS16 10 /* Pro Audio Spectrum 16 */ +#ifndef SOUND_SND_SB_DSP_H +#define SOUND_SND_SB_DSP_H +/*Sound Blaster Clones, for quirks*/ +#define SB_SUBTYPE_DEFAULT 0 /*Handle as a Creative card*/ +#define SB_SUBTYPE_CLONE_AZT2316A_0X11 1 /*Aztech Sound Galaxy Pro 16 AB, DSP 3.1 - SBPRO2 clone*/ +#define SB_SUBTYPE_CLONE_AZT1605_0X0C 2 /*Aztech Sound Galaxy Nova 16 Extra / Packard Bell Forte 16, DSP 2.1 - SBPRO2 clone*/ + +/* aztech-related */ +#define IS_AZTECH(dsp) ((dsp)->sb_subtype == SB_SUBTYPE_CLONE_AZT2316A_0X11 || (dsp)->sb_subtype == SB_SUBTYPE_CLONE_AZT1605_0X0C) /* check for future AZT cards here */ +#define AZTECH_EEPROM_SIZE 16 typedef struct sb_dsp_t { - int sb_type; + int sb_type; + int sb_subtype; /* which clone */ + void *parent; /* "sb_t *" if default subtype, "azt2316a_t *" if aztech. */ - int sb_8_length, sb_8_format, sb_8_autoinit, sb_8_pause, sb_8_enable, sb_8_autolen, sb_8_output; - int sb_8_dmanum; - int sb_16_length, sb_16_format, sb_16_autoinit, sb_16_pause, sb_16_enable, sb_16_autolen, sb_16_output; - int sb_16_dmanum; - int sb_pausetime; + int sb_8_length, sb_8_format, sb_8_autoinit, sb_8_pause, sb_8_enable, sb_8_autolen, sb_8_output; + int sb_8_dmanum; + int sb_16_length, sb_16_format, sb_16_autoinit, sb_16_pause, sb_16_enable, sb_16_autolen, sb_16_output; + int sb_16_dmanum; + int sb_pausetime; - uint8_t sb_read_data[256]; - int sb_read_wp, sb_read_rp; - int sb_speaker; - int muted; + uint8_t sb_read_data[256]; + int sb_read_wp, sb_read_rp; + int sb_speaker; + int muted; - int sb_data_stat; - - int midi_in_sysex; - int midi_in_poll; - int uart_midi; - int uart_irq; - int onebyte_midi; - int midi_in_timestamp; + int sb_data_stat; - int sb_irqnum; + int midi_in_sysex; + int midi_in_poll; + int uart_midi; + int uart_irq; + int onebyte_midi; + int midi_in_timestamp; - uint8_t sbe2; - int sbe2count; + int sb_irqnum; - uint8_t sb_data[8]; + uint8_t sbe2; + int sbe2count; - int sb_freq; + uint8_t sb_data[8]; + + int sb_freq; - int16_t sbdat; - int sbdat2; - int16_t sbdatl, sbdatr; + int16_t sbdat; + int sbdat2; + int16_t sbdatl, sbdatr; - uint8_t sbref; - int8_t sbstep; + uint8_t sbref; + int8_t sbstep; - int sbdacpos; + int sbdacpos; - int sbleftright; + int sbleftright; - int sbreset; - uint8_t sbreaddat; - uint8_t sb_command; - uint8_t sb_test; - int sb_timei, sb_timeo; + int sbreset; + uint8_t sbreaddat; + uint8_t sb_command; + uint8_t sb_test; + int sb_timei, sb_timeo; - int sb_irq8, sb_irq16; - int sb_irqm8, sb_irqm16; + int sb_irq8, sb_irq16; + int sb_irqm8, sb_irqm16; - uint8_t sb_asp_regs[256]; + uint8_t sb_asp_regs[256]; - int sbenable, sb_enable_i; + int sbenable, sb_enable_i; - pc_timer_t output_timer, input_timer; + pc_timer_t output_timer, input_timer; - uint64_t sblatcho, sblatchi; - - uint16_t sb_addr; - - int stereo; - - int asp_data_len; - - pc_timer_t wb_timer; - int wb_full; + uint64_t sblatcho, sblatchi; + + uint16_t sb_addr; + + int stereo; + + int asp_data_len; + + pc_timer_t wb_timer; + int wb_full; int busy_count; - int record_pos_read; - int record_pos_write; - int16_t record_buffer[0xFFFF]; - int16_t buffer[SOUNDBUFLEN * 2]; - int pos; + int record_pos_read; + int record_pos_write; + int16_t record_buffer[0xFFFF]; + int16_t buffer[SOUNDBUFLEN * 2]; + int pos; + + uint8_t azt_eeprom[AZTECH_EEPROM_SIZE]; /* the eeprom in the Aztech cards is attached to the DSP */ } sb_dsp_t; @@ -96,7 +100,7 @@ int sb_dsp_input_sysex(void *p, uint8_t *buffer, uint32_t len, int abort); void sb_dsp_set_mpu(mpu_t *src_mpu); -void sb_dsp_init(sb_dsp_t *dsp, int type); +void sb_dsp_init(sb_dsp_t *dsp, int type, int subtype, void *parent); void sb_dsp_close(sb_dsp_t *dsp); void sb_dsp_setirq(sb_dsp_t *dsp, int irq); @@ -111,4 +115,5 @@ void sb_dsp_poll(sb_dsp_t *dsp, int16_t *l, int16_t *r); void sb_dsp_set_stereo(sb_dsp_t *dsp, int stereo); void sb_dsp_update(sb_dsp_t *dsp); -void sb_irqc(sb_dsp_t *dsp, int irq8); + +#endif /* SOUND_SND_SB_DSP_H */ \ No newline at end of file diff --git a/src/sound/snd_wss.c b/src/sound/snd_wss.c index 5de5674b9..48859c408 100644 --- a/src/sound/snd_wss.c +++ b/src/sound/snd_wss.c @@ -48,76 +48,75 @@ static int wss_dma[4] = {0, 0, 1, 3}; static int wss_irq[8] = {5, 7, 9, 10, 11, 12, 14, 15}; /*W95 only uses 7-9, others may be wrong*/ - typedef struct wss_t { - uint8_t config; + uint8_t config; - ad1848_t ad1848; - opl_t opl; - - int opl_enabled; - uint8_t pos_regs[8]; + ad1848_t ad1848; + opl_t opl; + + int opl_enabled; + uint8_t pos_regs[8]; } wss_t; uint8_t wss_read(uint16_t addr, void *p) { - wss_t *wss = (wss_t *)p; - uint8_t temp; - temp = 4 | (wss->config & 0x40); - return temp; + wss_t *wss = (wss_t *)p; + uint8_t temp; + temp = 4 | (wss->config & 0x40); + return temp; } void wss_write(uint16_t addr, uint8_t val, void *p) { - wss_t *wss = (wss_t *)p; + wss_t *wss = (wss_t *)p; - wss->config = val; - ad1848_setdma(&wss->ad1848, wss_dma[val & 3]); - ad1848_setirq(&wss->ad1848, wss_irq[(val >> 3) & 7]); + wss->config = val; + ad1848_setdma(&wss->ad1848, wss_dma[val & 3]); + ad1848_setirq(&wss->ad1848, wss_irq[(val >> 3) & 7]); } static void wss_get_buffer(int32_t *buffer, int len, void *p) { - wss_t *wss = (wss_t *)p; - + wss_t *wss = (wss_t *)p; int c; - opl3_update2(&wss->opl); - ad1848_update(&wss->ad1848); - for (c = 0; c < len * 2; c++) - { - buffer[c] += wss->opl.buffer[c]; - buffer[c] += (wss->ad1848.buffer[c] / 2); - } + opl3_update2(&wss->opl); + ad1848_update(&wss->ad1848); + for (c = 0; c < len * 2; c++) { + buffer[c] += wss->opl.buffer[c]; + buffer[c] += (wss->ad1848.buffer[c] / 2); + } - wss->opl.pos = 0; - wss->ad1848.pos = 0; + wss->opl.pos = 0; + wss->ad1848.pos = 0; } void *wss_init(const device_t *info) { - wss_t *wss = malloc(sizeof(wss_t)); - memset(wss, 0, sizeof(wss_t)); - - uint16_t addr = device_get_config_hex16("base"); - wss->opl_enabled = device_get_config_int("opl"); - - opl3_init(&wss->opl); - ad1848_init(&wss->ad1848); - - ad1848_setirq(&wss->ad1848, 7); - ad1848_setdma(&wss->ad1848, 3); + wss_t *wss = malloc(sizeof(wss_t)); + memset(wss, 0, sizeof(wss_t)); - if (wss->opl_enabled) - io_sethandler(0x0388, 0x0004, opl3_read, NULL, NULL, opl3_write, NULL, NULL, &wss->opl); + uint16_t addr = device_get_config_hex16("base"); + wss->opl_enabled = device_get_config_int("opl"); + + if (wss->opl_enabled) + opl3_init(&wss->opl); - io_sethandler(addr, 0x0004, wss_read, NULL, NULL, wss_write, NULL, NULL, wss); - io_sethandler(addr+4, 0x0004, ad1848_read, NULL, NULL, ad1848_write, NULL, NULL, &wss->ad1848); - - sound_add_handler(wss_get_buffer, wss); + ad1848_init(&wss->ad1848, AD1848_TYPE_DEFAULT); + + ad1848_setirq(&wss->ad1848, 7); + ad1848_setdma(&wss->ad1848, 3); + + if (wss->opl_enabled) + io_sethandler(0x0388, 0x0004, opl3_read, NULL, NULL, opl3_write, NULL, NULL, &wss->opl); - return wss; + io_sethandler(addr, 0x0004, wss_read, NULL, NULL, wss_write, NULL, NULL, wss); + io_sethandler(addr+4, 0x0004, ad1848_read, NULL, NULL, ad1848_write, NULL, NULL, &wss->ad1848); + + sound_add_handler(wss_get_buffer, wss); + + return wss; } static uint8_t ncr_audio_mca_read(int port, void *p) @@ -129,10 +128,10 @@ static uint8_t ncr_audio_mca_read(int port, void *p) static void ncr_audio_mca_write(int port, uint8_t val, void *p) { - wss_t *wss = (wss_t *)p; + wss_t *wss = (wss_t *)p; uint16_t ports[4] = {0x530, 0xE80, 0xF40, 0x604}; uint16_t addr; - + if (port < 0x102) return; @@ -142,15 +141,12 @@ static void ncr_audio_mca_write(int port, uint8_t val, void *p) io_removehandler(0x0388, 0x0004, opl3_read, NULL, NULL, opl3_write, NULL, NULL, &wss->opl); io_removehandler(addr, 0x0004, wss_read, NULL, NULL, wss_write, NULL, NULL, wss); io_removehandler(addr+4, 0x0004, ad1848_read, NULL, NULL, ad1848_write, NULL, NULL, &wss->ad1848); - - //pclog("WSS MCA: opl=%d, addr=%03x\n", wss->opl_enabled, addr); wss->pos_regs[port & 7] = val; - - if (wss->pos_regs[2] & 1) - { + + if (wss->pos_regs[2] & 1) { addr = ports[(wss->pos_regs[2] & 0x18) >> 3]; - + if (wss->opl_enabled) io_sethandler(0x0388, 0x0004, opl3_read, NULL, NULL, opl3_write, NULL, NULL, &wss->opl); @@ -168,37 +164,37 @@ static uint8_t ncr_audio_mca_feedb(void *p) void *ncr_audio_init(const device_t *info) { - wss_t *wss = malloc(sizeof(wss_t)); + wss_t *wss = malloc(sizeof(wss_t)); - memset(wss, 0, sizeof(wss_t)); + memset(wss, 0, sizeof(wss_t)); - opl3_init(&wss->opl); - ad1848_init(&wss->ad1848); + opl3_init(&wss->opl); + ad1848_init(&wss->ad1848, AD1848_TYPE_DEFAULT); ad1848_setirq(&wss->ad1848, 7); ad1848_setdma(&wss->ad1848, 3); - - mca_add(ncr_audio_mca_read, ncr_audio_mca_write, ncr_audio_mca_feedb, wss); + + mca_add(ncr_audio_mca_read, ncr_audio_mca_write, ncr_audio_mca_feedb, NULL, wss); wss->pos_regs[0] = 0x16; wss->pos_regs[1] = 0x51; - - sound_add_handler(wss_get_buffer, wss); - - return wss; + + sound_add_handler(wss_get_buffer, wss); + + return wss; } void wss_close(void *p) { - wss_t *wss = (wss_t *)p; - - free(wss); + wss_t *wss = (wss_t *)p; + + free(wss); } void wss_speed_changed(void *p) { - wss_t *wss = (wss_t *)p; - - ad1848_speed_changed(&wss->ad1848); + wss_t *wss = (wss_t *)p; + + ad1848_speed_changed(&wss->ad1848); } static const device_config_t wss_config[] = diff --git a/src/sound/sound.c b/src/sound/sound.c index df17cb865..c67dcd3b4 100644 --- a/src/sound/sound.c +++ b/src/sound/sound.c @@ -34,6 +34,7 @@ #include "snd_opl.h" #include "snd_mpu401.h" #include "snd_sb_dsp.h" +#include "snd_azt2316a.h" #include "filters.h" @@ -80,6 +81,8 @@ static const SOUND_CARD sound_cards[] = { "None", "none", NULL }, { "[ISA] Adlib", "adlib", &adlib_device }, { "[ISA] Adlib Gold", "adlibgold", &adgold_device }, + { "[ISA] Aztech Sound Galaxy Pro 16 AB (Washington)", "azt2316a", &azt2316a_device }, + { "[ISA] Aztech Sound Galaxy Nova 16 Extra (Clinton)", "azt1605", &azt1605_device }, { "[ISA] Sound Blaster 1.0", "sb", &sb_1_device }, { "[ISA] Sound Blaster 1.5", "sb1.5", &sb_15_device }, { "[ISA] Sound Blaster 2.0", "sb2.0", &sb_2_device }, diff --git a/src/sound/sound.h b/src/sound/sound.h index 34f5d0ca9..31dca9afe 100644 --- a/src/sound/sound.h +++ b/src/sound/sound.h @@ -73,6 +73,10 @@ extern const device_t adlib_device; extern const device_t adlib_mca_device; extern const device_t adgold_device; +/* Aztech Sound Galaxy 16 */ +extern const device_t azt2316a_device; +extern const device_t azt1605_device; + /* Ensoniq AudioPCI */ extern const device_t es1371_device; diff --git a/src/video/vid_cl54xx.c b/src/video/vid_cl54xx.c index 4b3df6ddc..55a50ce4d 100644 --- a/src/video/vid_cl54xx.c +++ b/src/video/vid_cl54xx.c @@ -3127,7 +3127,7 @@ static void if (gd54xx->mca) { gd54xx->pos_regs[0] = 0x7b; gd54xx->pos_regs[1] = 0x91; - mca_add(gd5428_mca_read, gd5428_mca_write, gd5428_mca_feedb, gd54xx); + mca_add(gd5428_mca_read, gd5428_mca_write, gd5428_mca_feedb, NULL, gd54xx); } return gd54xx; diff --git a/src/video/vid_et4000.c b/src/video/vid_et4000.c index ad4bd13a9..b5f27b3df 100644 --- a/src/video/vid_et4000.c +++ b/src/video/vid_et4000.c @@ -512,7 +512,7 @@ et4000_init(const device_t *info) et4000_in,NULL,NULL, et4000_out,NULL,NULL, dev); dev->pos_regs[0] = 0xf2; /* ET4000 MCA board ID */ dev->pos_regs[1] = 0x80; - mca_add(et4000_mca_read, et4000_mca_write, et4000_mca_feedb, dev); + mca_add(et4000_mca_read, et4000_mca_write, et4000_mca_feedb, NULL, dev); break; case 2: /* Korean ET4000 */ diff --git a/src/win/Makefile.mingw b/src/win/Makefile.mingw index bcc10bbd2..5ecbe9d47 100644 --- a/src/win/Makefile.mingw +++ b/src/win/Makefile.mingw @@ -673,6 +673,7 @@ SNDOBJ := sound.o \ snd_pssj.o \ snd_lpt_dac.o snd_lpt_dss.o \ snd_adlib.o snd_adlibgold.o snd_ad1848.o snd_audiopci.o \ + snd_azt2316a.o \ snd_cms.o \ snd_gus.o \ snd_sb.o snd_sb_dsp.o \ diff --git a/src/win/Makefile_ndr.mingw b/src/win/Makefile_ndr.mingw index 23466a8f6..6d697ef4b 100644 --- a/src/win/Makefile_ndr.mingw +++ b/src/win/Makefile_ndr.mingw @@ -678,6 +678,7 @@ SNDOBJ := sound.o \ snd_pssj.o \ snd_lpt_dac.o snd_lpt_dss.o \ snd_adlib.o snd_adlibgold.o snd_ad1848.o snd_audiopci.o \ + snd_azt2316a.o \ snd_cms.o \ snd_gus.o \ snd_sb.o snd_sb_dsp.o \ From ac96bc4cc6a048cd4637c544791f7338d001d7bb Mon Sep 17 00:00:00 2001 From: TC1995 Date: Wed, 25 Mar 2020 01:23:22 +0100 Subject: [PATCH 16/33] Changed the GPL license of the azt2316a.c source file. Added F82C710 SIO to the super286tr. --- src/machine/m_at_286_386sx.c | 3 + src/sio.h | 3 +- src/sio_f82c710.c | 239 +++++++++++++++++++++++++++++++++++ src/sound/snd_azt2316a.c | 2 +- 4 files changed, 245 insertions(+), 2 deletions(-) create mode 100644 src/sio_f82c710.c diff --git a/src/machine/m_at_286_386sx.c b/src/machine/m_at_286_386sx.c index b16382f78..a43efebe4 100644 --- a/src/machine/m_at_286_386sx.c +++ b/src/machine/m_at_286_386sx.c @@ -34,6 +34,7 @@ #include "fdd.h" #include "fdc.h" #include "hdc.h" +#include "sio.h" #include "video.h" #include "machine.h" @@ -293,6 +294,8 @@ machine_at_gw286ct_init(const machine_t *model) if (bios_only || !ret) return ret; + device_add(&f82c710_device); + machine_at_scat_init(model, 1); return ret; diff --git a/src/sio.h b/src/sio.h index 5888406c9..c38364504 100644 --- a/src/sio.h +++ b/src/sio.h @@ -8,7 +8,7 @@ * * Definitions for the Super I/O chips. * - * + * Version: @(#)sio.h 1.0.7 2020/01/25 * * Author: Fred N. van Kempen, * Copyright 2017-2020 Fred N. van Kempen. @@ -18,6 +18,7 @@ extern const device_t acc3221_device; +extern const device_t f82c710_device; extern const device_t fdc37c663_device; extern const device_t fdc37c665_device; extern const device_t fdc37c666_device; diff --git a/src/sio_f82c710.c b/src/sio_f82c710.c new file mode 100644 index 000000000..d6b988a97 --- /dev/null +++ b/src/sio_f82c710.c @@ -0,0 +1,239 @@ +/* + * 86Box A hypervisor and IBM PC system emulator that specializes in + * running old operating systems and software designed for IBM + * PC systems and compatibles from 1981 through fairly recent + * system designs based on the PCI bus. + * + * This file is part of the 86Box distribution. + * + * Implementation of the Chips & Technologies F82C710 Universal Peripheral Controller (UPC). + * + * Version: @(#)sio_f82c710.c 1.0.0 2020/03/12 + * + * Authors: Sarah Walker, + * Eluan Costa Miranda + * + * Copyright 2020 Sarah Walker. + * Copyright 2020 Eluan Costa Miranda. + */ +#include +#include +#include +#include +#include +#include "86box.h" +#include "86box_io.h" +#include "timer.h" +#include "device.h" +#include "lpt.h" +#include "serial.h" +#include "disk/hdc.h" +#include "disk/hdc_ide.h" +#include "floppy/fdd.h" +#include "floppy/fdc.h" +#include "sio.h" + +typedef struct upc_t +{ + int configuration_state; /* state of algorithm to enter configuration mode */ + int configuration_mode; + uint16_t cri_addr; /* cri = configuration index register, addr is even */ + uint16_t cap_addr; /* cap = configuration access port, addr is odd and is cri_addr + 1 */ + uint8_t cri; /* currently indexed register */ + + /* these regs are not affected by reset */ + uint8_t regs[15]; /* there are 16 indexes, but there is no need to store the last one which is: R = cri_addr / 4, W = exit config mode */ + fdc_t *fdc; + serial_t *uart[2]; +} upc_t; + +static void +f82c710_update_ports(upc_t *upc) +{ + uint16_t com_addr = 0; + uint16_t lpt_addr = 0; + + serial_remove(upc->uart[0]); + serial_remove(upc->uart[1]); + lpt1_remove(); + lpt2_remove(); + fdc_remove(upc->fdc); + ide_pri_disable(); + + if (upc->regs[0] & 4) { + com_addr = upc->regs[4] * 4; + if (com_addr == SERIAL1_ADDR) { + serial_setup(upc->uart[0], com_addr, 4); + } else if (com_addr == SERIAL2_ADDR) { + serial_setup(upc->uart[1], com_addr, 3); + } + } + + + if (upc->regs[0] & 8) { + lpt_addr = upc->regs[6] * 4; + lpt1_init(lpt_addr); + if ((lpt_addr == 0x378) || (lpt_addr == 0x3bc)) { + lpt1_irq(7); + } else if (lpt_addr == 0x278) { + lpt1_irq(5); + } + } + + if (upc->regs[12] & 0x80) { + ide_pri_enable(); + } + + if (upc->regs[12] & 0x20) { + fdc_set_base(upc->fdc, 0x03f0); + } +} + +static uint8_t +f82c710_config_read(uint16_t port, void *priv) +{ + upc_t *upc = (upc_t *)priv; + uint8_t temp = 0xff; + + if (upc->configuration_mode) { + if (port == upc->cri_addr) { + temp = upc->cri; + } else if (port == upc->cap_addr) { + if (upc->cri == 0xf) + temp = upc->cri_addr / 4; + else + temp = upc->regs[upc->cri]; + } + } + + return temp; +} + +static void +f82c710_config_write(uint16_t port, uint8_t val, void *priv) +{ + upc_t *upc = (upc_t *)priv; + int configuration_state_event = 0; + + switch(port) { + case 0x2fa: + if (upc->configuration_state == 0 && val == 0x55) + configuration_state_event = 1; + else if (upc->configuration_state == 4) { + uint8_t addr_verify = upc->cri_addr / 4; + addr_verify += val; + if (addr_verify == 0xff) { + upc->configuration_mode = 1; + /* TODO: is the value of cri reset here or when exiting configuration mode? */ + io_sethandler(upc->cri_addr, 0x0002, f82c710_config_read, NULL, NULL, f82c710_config_write, NULL, NULL, upc); + } else { + upc->configuration_mode = 0; + } + } + break; + case 0x3fa: + if (upc->configuration_state == 1 && val == 0xaa) + configuration_state_event = 1; + else if (upc->configuration_state == 2 && val == 0x36) + configuration_state_event = 1; + else if (upc->configuration_state == 3) { + upc->cri_addr = val * 4; + upc->cap_addr = upc->cri_addr + 1; + configuration_state_event = 1; + } + break; + default: + break; + } + + if (upc->configuration_mode) { + if (port == upc->cri_addr) { + upc->cri = val & 0xf; + } else if (port == upc->cap_addr) { + if (upc->cri == 0xf) { + upc->configuration_mode = 0; + io_removehandler(upc->cri_addr, 0x0002, f82c710_config_read, NULL, NULL, f82c710_config_write, NULL, NULL, upc); + f82c710_update_ports(upc); /* TODO: any benefit in updating at each register write instead of when exiting config mode? */ + } else { + upc->regs[upc->cri] = val; + } + } + } + + /* TODO: is the state only reset when accessing 0x2fa and 0x3fa wrongly? */ + if ((port == 0x2fa || port == 0x3fa) && configuration_state_event) + upc->configuration_state++; + else + upc->configuration_state = 0; +} + + +static void +f82c710_reset(upc_t *upc) +{ + serial_remove(upc->uart[0]); + serial_setup(upc->uart[0], SERIAL1_ADDR, SERIAL1_IRQ); + + serial_remove(upc->uart[1]); + serial_setup(upc->uart[1], SERIAL2_ADDR, SERIAL2_IRQ); + + lpt1_remove(); + lpt1_init(0x378); + lpt1_irq(7); + + fdc_reset(upc->fdc); +} + +static void * +f82c710_init(const device_t *info) +{ + upc_t *upc = (upc_t *) malloc(sizeof(upc_t)); + memset(upc, 0, sizeof(upc_t)); + + upc->fdc = device_add(&fdc_at_device); + + upc->uart[0] = device_add_inst(&ns16450_device, 1); + upc->uart[1] = device_add_inst(&ns16450_device, 2); + + io_sethandler(0x02fa, 0x0001, NULL, NULL, NULL, f82c710_config_write, NULL, NULL, upc); + io_sethandler(0x03fa, 0x0001, NULL, NULL, NULL, f82c710_config_write, NULL, NULL, upc); + + upc->regs[0] = 0x0c; + upc->regs[1] = 0x00; + upc->regs[2] = 0x00; + upc->regs[3] = 0x00; + upc->regs[4] = 0xfe; + upc->regs[5] = 0x00; + upc->regs[6] = 0x9e; + upc->regs[7] = 0x00; + upc->regs[8] = 0x00; + upc->regs[9] = 0xb0; + upc->regs[10] = 0x00; + upc->regs[11] = 0x00; + upc->regs[12] = 0xa0; + upc->regs[13] = 0x00; + upc->regs[14] = 0x00; + + f82c710_reset(upc); + + f82c710_update_ports(upc); + + return upc; +} + +static void +f82c710_close(void *priv) +{ + upc_t *upc = (upc_t *)priv; + + free(upc); +} + +const device_t f82c710_device = { + "F82C710 UPC Super I/O", + 0, + 0, + f82c710_init, f82c710_close, NULL, + NULL, NULL, NULL, + NULL +}; diff --git a/src/sound/snd_azt2316a.c b/src/sound/snd_azt2316a.c index 3193f1af1..6131f7b8f 100644 --- a/src/sound/snd_azt2316a.c +++ b/src/sound/snd_azt2316a.c @@ -18,7 +18,7 @@ * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or + * the Free Software Foundation, either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, From dfb55bddfa13f6f348e79c53af2730da58ec49ab Mon Sep 17 00:00:00 2001 From: TC1995 Date: Wed, 25 Mar 2020 01:39:29 +0100 Subject: [PATCH 17/33] Compile fix. --- src/disk/hdc_esdi_mca.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/disk/hdc_esdi_mca.c b/src/disk/hdc_esdi_mca.c index b1f04c0f6..432385274 100644 --- a/src/disk/hdc_esdi_mca.c +++ b/src/disk/hdc_esdi_mca.c @@ -1139,7 +1139,7 @@ esdi_init(const device_t *info) dev->pos_regs[1] = 0xdd; /* Enable the device. */ - mca_add(esdi_mca_read, esdi_mca_write, esdi_mca_feedb, dev); + mca_add(esdi_mca_read, esdi_mca_write, esdi_mca_feedb, NULL, dev); /* Mark for a reset. */ dev->in_reset = 1; From e042b4b112485bf54bcee026c3debd1bdfdbd65e Mon Sep 17 00:00:00 2001 From: TC1995 Date: Wed, 25 Mar 2020 01:42:22 +0100 Subject: [PATCH 18/33] Compile fix 2. --- src/sound/snd_adlib.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/sound/snd_adlib.c b/src/sound/snd_adlib.c index 29ace4e49..4457e61e7 100644 --- a/src/sound/snd_adlib.c +++ b/src/sound/snd_adlib.c @@ -110,7 +110,7 @@ void *adlib_mca_init(const device_t *info) adlib_t *adlib = adlib_init(info); io_removehandler(0x0388, 0x0002, opl2_read, NULL, NULL, opl2_write, NULL, NULL, &adlib->opl); - mca_add(adlib_mca_read, adlib_mca_write, adlib_mca_feedb, adlib); + mca_add(adlib_mca_read, adlib_mca_write, adlib_mca_feedb, NULL, adlib); adlib->pos_regs[0] = 0xd7; adlib->pos_regs[1] = 0x70; From 0f6e37efcc3b1d728fca7e0444a0fc5382aabd0c Mon Sep 17 00:00:00 2001 From: TC1995 Date: Wed, 25 Mar 2020 01:46:18 +0100 Subject: [PATCH 19/33] Compile fix 3 (I hate forgetting about stuff). --- src/win/Makefile.mingw | 1 + src/win/Makefile_ndr.mingw | 1 + 2 files changed, 2 insertions(+) diff --git a/src/win/Makefile.mingw b/src/win/Makefile.mingw index 5ecbe9d47..52ddb8a49 100644 --- a/src/win/Makefile.mingw +++ b/src/win/Makefile.mingw @@ -599,6 +599,7 @@ MCHOBJ := machine.o machine_table.o \ DEVOBJ := bugger.o hwm.o hwm_w83781d.o ibm_5161.o isamem.o isartc.o lpt.o postcard.o $(SERIAL) \ sio_acc3221.o \ + sio_f82c710.o \ sio_fdc37c66x.o sio_fdc37c669.o \ sio_fdc37c93x.o \ sio_pc87306.o \ diff --git a/src/win/Makefile_ndr.mingw b/src/win/Makefile_ndr.mingw index 6d697ef4b..daaf9af48 100644 --- a/src/win/Makefile_ndr.mingw +++ b/src/win/Makefile_ndr.mingw @@ -604,6 +604,7 @@ MCHOBJ := machine.o machine_table.o \ DEVOBJ := bugger.o hwm.o hwm_w83781d.o ibm_5161.o isamem.o isartc.o lpt.o postcard.o $(SERIAL) \ sio_acc3221.o \ + sio_f82c710.o \ sio_fdc37c66x.o sio_fdc37c669.o \ sio_fdc37c93x.o \ sio_pc87306.o \ From dbbc6375ba84193fb6c09edc146a513395090004 Mon Sep 17 00:00:00 2001 From: TC1995 Date: Wed, 25 Mar 2020 02:18:28 +0100 Subject: [PATCH 20/33] Added Compaq Plasma display and undev-branched the Compaq Portable III/386. --- src/machine/m_at_compaq.c | 705 +++++++++++++++++++++++++++++++++++- src/machine/machine.h | 3 +- src/machine/machine_table.c | 8 +- 3 files changed, 701 insertions(+), 15 deletions(-) diff --git a/src/machine/m_at_compaq.c b/src/machine/m_at_compaq.c index d22797090..915168a10 100644 --- a/src/machine/m_at_compaq.c +++ b/src/machine/m_at_compaq.c @@ -36,17 +36,701 @@ enum { - COMPAQ_PORTABLEII = 0 -#if defined(DEV_BRANCH) && defined(USE_PORTABLE3) - , COMPAQ_PORTABLEIII, + COMPAQ_PORTABLEII = 0, + COMPAQ_PORTABLEIII, COMPAQ_PORTABLEIII386 -#endif +}; + +#define CGA_RGB 0 +#define CGA_COMPOSITE 1 + +#define COMPOSITE_OLD 0 +#define COMPOSITE_NEW 1 + +/*Very rough estimate*/ +#define VID_CLOCK (double)(651 * 416 * 60) + + +/* Mapping of attributes to colours */ +static uint32_t amber, black; +static uint32_t blinkcols[256][2]; +static uint32_t normcols[256][2]; + +/* Video options set by the motherboard; they will be picked up by the card + * on the next poll. + * + * Bit 3: Disable built-in video (for add-on card) + * Bit 2: Thin font + * Bits 0,1: Font set (not currently implemented) + */ +static int8_t cpq_st_display_internal = -1; + +static void +compaq_plasma_display_set(uint8_t internal) +{ + cpq_st_display_internal = internal; +} + +static uint8_t +compaq_plasma_display_get(void) +{ + return cpq_st_display_internal; +} + + +typedef struct compaq_plasma_t +{ + mem_mapping_t plasma_mapping; + cga_t cga; + uint8_t port_23c6; + uint8_t internal_monitor; + uint8_t attrmap; /* Attribute mapping register */ + int linepos, displine; + uint8_t *vram; + uint64_t dispontime, dispofftime; + int dispon; +} compaq_plasma_t; + +static uint8_t cga_crtcmask[32] = +{ + 0xff, 0xff, 0xff, 0xff, 0x7f, 0x1f, 0x7f, 0x7f, 0xf3, 0x1f, 0x7f, 0x1f, 0x3f, 0xff, 0x3f, 0xff, + 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; /* Compaq Deskpro 386 remaps RAM from 0xA0000-0xFFFFF to 0xFA0000-0xFFFFFF */ static mem_mapping_t ram_mapping; +static void compaq_plasma_recalcattrs(compaq_plasma_t *self); + +static void +compaq_plasma_recalctimings(compaq_plasma_t *self) +{ + double _dispontime, _dispofftime, disptime; + + if (!self->internal_monitor && !(self->port_23c6 & 1)) { + cga_recalctimings(&self->cga); + return; + } + + disptime = 651; + _dispontime = 640; + _dispofftime = disptime - _dispontime; + self->dispontime = (uint64_t)(_dispontime * (cpuclock / VID_CLOCK) * (double)(1ull << 32)); + self->dispofftime = (uint64_t)(_dispofftime * (cpuclock / VID_CLOCK) * (double)(1ull << 32)); +} + +static void +compaq_plasma_write(uint32_t addr, uint8_t val, void *priv) +{ + compaq_plasma_t *self = (compaq_plasma_t *)priv; + + self->vram[addr & 0x7fff] = val; +} + + +static uint8_t +compaq_plasma_read(uint32_t addr, void *priv) +{ + compaq_plasma_t *self = (compaq_plasma_t *)priv; + uint8_t ret; + + ret = (self->vram[addr & 0x7fff]); + + return ret; +} + +/* Draw a row of text in 80-column mode */ +static void +compaq_plasma_text80(compaq_plasma_t *self) +{ + uint32_t cols[2]; + int x, c; + uint8_t chr, attr; + int drawcursor; + int cursorline; + int blink; + uint16_t addr; + uint8_t sc; + uint16_t ma = (self->cga.crtc[13] | (self->cga.crtc[12] << 8)) & 0x7fff; + uint16_t ca = (self->cga.crtc[15] | (self->cga.crtc[14] << 8)) & 0x7fff; + + sc = (self->displine) & 15; + addr = ((ma & ~1) + (self->displine >> 4) * 80) * 2; + ma += (self->displine >> 4) * 80; + + if ((self->cga.crtc[10] & 0x60) == 0x20) + cursorline = 0; + else + cursorline = ((self->cga.crtc[10] & 0x0F)*2 <= sc) && + ((self->cga.crtc[11] & 0x0F)*2 >= sc); + + for (x = 0; x < 80; x++) { + chr = self->vram[(addr + 2 * x) & 0x7FFF]; + attr = self->vram[(addr + 2 * x + 1) & 0x7FFF]; + drawcursor = ((ma == ca) && cursorline && + (self->cga.cgamode & 8) && (self->cga.cgablink & 16)); + + blink = ((self->cga.cgablink & 16) && (self->cga.cgamode & 0x20) && + (attr & 0x80) && !drawcursor); + + if (self->cga.cgamode & 0x20) { /* Blink */ + cols[1] = blinkcols[attr][1]; + cols[0] = blinkcols[attr][0]; + if (blink) + cols[1] = cols[0]; + } else { + cols[1] = normcols[attr][1]; + cols[0] = normcols[attr][0]; + } + if (drawcursor) { + for (c = 0; c < 8; c++) + ((uint32_t *)buffer32->line[self->displine])[(x << 3) + c] = cols[(fontdatm[chr][sc] & (1 << (c ^ 7))) ? 1 : 0] ^ (amber ^ black); + } else { + for (c = 0; c < 8; c++) + ((uint32_t *)buffer32->line[self->displine])[(x << 3) + c] = cols[(fontdatm[chr][sc] & (1 << (c ^ 7))) ? 1 : 0]; + } + ++ma; + } +} + +/* Draw a row of text in 40-column mode */ +static void +compaq_plasma_text40(compaq_plasma_t *self) +{ + uint32_t cols[2]; + int x, c; + uint8_t chr, attr; + int drawcursor; + int cursorline; + int blink; + uint16_t addr; + uint8_t sc; + uint16_t ma = (self->cga.crtc[13] | (self->cga.crtc[12] << 8)) & 0x7fff; + uint16_t ca = (self->cga.crtc[15] | (self->cga.crtc[14] << 8)) & 0x7fff; + + sc = (self->displine) & 15; + addr = ((ma & ~1) + (self->displine >> 4) * 40) * 2; + ma += (self->displine >> 4) * 40; + + if ((self->cga.crtc[10] & 0x60) == 0x20) + cursorline = 0; + else + cursorline = ((self->cga.crtc[10] & 0x0F)*2 <= sc) && + ((self->cga.crtc[11] & 0x0F)*2 >= sc); + + for (x = 0; x < 40; x++) { + chr = self->vram[(addr + 2 * x) & 0x7FFF]; + attr = self->vram[(addr + 2 * x + 1) & 0x7FFF]; + drawcursor = ((ma == ca) && cursorline && + (self->cga.cgamode & 8) && (self->cga.cgablink & 16)); + + blink = ((self->cga.cgablink & 16) && (self->cga.cgamode & 0x20) && + (attr & 0x80) && !drawcursor); + + if (self->cga.cgamode & 0x20) { /* Blink */ + cols[1] = blinkcols[attr][1]; + cols[0] = blinkcols[attr][0]; + if (blink) + cols[1] = cols[0]; + } else { + cols[1] = normcols[attr][1]; + cols[0] = normcols[attr][0]; + } + if (drawcursor) { + for (c = 0; c < 8; c++) { + ((uint32_t *)buffer32->line[self->displine])[(x << 4) + c*2] = + ((uint32_t *)buffer32->line[self->displine])[(x << 4) + c*2 + 1] = cols[(fontdatm[chr][sc] & (1 << (c ^ 7))) ? 1 : 0] ^ (amber ^ black); + } + } else { + for (c = 0; c < 8; c++) { + ((uint32_t *)buffer32->line[self->displine])[(x << 4) + c*2] = + ((uint32_t *)buffer32->line[self->displine])[(x << 4) + c*2+1] = cols[(fontdatm[chr][sc] & (1 << (c ^ 7))) ? 1 : 0]; + } + } + ++ma; + } +} + + +/* Draw a line in CGA 640x200 or Compaq Plasma 640x400 mode */ +static void +compaq_plasma_cgaline6(compaq_plasma_t *self) +{ + int x, c; + uint8_t dat; + uint32_t ink = 0; + uint16_t addr; + uint32_t fg = (self->cga.cgacol & 0x0F) ? amber : black; + uint32_t bg = black; + + uint16_t ma = (self->cga.crtc[13] | (self->cga.crtc[12] << 8)) & 0x7fff; + + if ((self->cga.crtc[9] == 3) || (self->port_23c6 & 1)) /* 640*400 */ { + addr = ((self->displine) & 1) * 0x2000 + + ((self->displine >> 1) & 1) * 0x4000 + + (self->displine >> 2) * 80 + + ((ma & ~1) << 1); + } else { + addr = ((self->displine >> 1) & 1) * 0x2000 + + (self->displine >> 2) * 80 + + ((ma & ~1) << 1); + } + for (x = 0; x < 80; x++) { + dat = self->vram[(addr & 0x7FFF)]; + addr++; + + for (c = 0; c < 8; c++) { + ink = (dat & 0x80) ? fg : bg; + if (!(self->cga.cgamode & 8)) ink = black; + ((uint32_t *)buffer32->line[self->displine])[x*8+c] = ink; + dat <<= 1; + } + } +} + +/* Draw a line in CGA 320x200 mode. Here the CGA colours are converted to + * dither patterns: colour 1 to 25% grey, colour 2 to 50% grey */ +static void +compaq_plasma_cgaline4(compaq_plasma_t *self) +{ + int x, c; + uint8_t dat, pattern; + uint32_t ink0 = 0, ink1 = 0; + uint16_t addr; + + uint16_t ma = (self->cga.crtc[13] | (self->cga.crtc[12] << 8)) & 0x7fff; + + /* 320*200 */ + addr = ((self->displine >> 1) & 1) * 0x2000 + + (self->displine >> 2) * 80 + + ((ma & ~1) << 1); + + for (x = 0; x < 80; x++) { + dat = self->vram[(addr & 0x7FFF)]; + addr++; + + for (c = 0; c < 4; c++) { + pattern = (dat & 0xC0) >> 6; + if (!(self->cga.cgamode & 8)) + pattern = 0; + + switch (pattern & 3) { + case 0: ink0 = ink1 = black; break; + case 1: if (self->displine & 1) { + ink0 = black; ink1 = black; + } else { + ink0 = amber; ink1 = black; + } + break; + case 2: if (self->displine & 1) { + ink0 = black; ink1 = amber; + } else { + ink0 = amber; ink1 = black; + } + break; + case 3: ink0 = ink1 = amber; break; + + } + ((uint32_t *)buffer32->line[self->displine])[x*8+2*c] = ink0; + ((uint32_t *)buffer32->line[self->displine])[x*8+2*c+1] = ink1; + dat <<= 2; + } + } +} + +static void +compaq_plasma_out(uint16_t addr, uint8_t val, void *priv) +{ + compaq_plasma_t *self = (compaq_plasma_t *)priv; + uint8_t old; + + switch (addr) { + /* Emulated CRTC, register select */ + case 0x3d4: + self->cga.crtcreg = val & 31; + break; + + /* Emulated CRTC, value */ + case 0x3d5: + old = self->cga.crtc[self->cga.crtcreg]; + self->cga.crtc[self->cga.crtcreg] = val & cga_crtcmask[self->cga.crtcreg]; + + /* Register 0x12 controls the attribute mappings for the + * plasma screen. */ + if (self->cga.crtcreg == 0x12) { + self->attrmap = val; + compaq_plasma_recalcattrs(self); + break; + } + + if (old != val) { + if (self->cga.crtcreg < 0xe || self->cga.crtcreg > 0x10) { + fullchange = changeframecount; + compaq_plasma_recalctimings(self); + } + } + break; + + case 0x3d8: + self->cga.cgamode = val; + break; + + case 0x3d9: + self->cga.cgacol = val; + break; + + case 0x13c6: + if (val & 8) + compaq_plasma_display_set(1); + else + compaq_plasma_display_set(0); + break; + + case 0x23c6: + self->port_23c6 = val; + if (val & 8) /* Disable internal CGA */ + mem_mapping_disable(&self->plasma_mapping); + else + mem_mapping_enable(&self->plasma_mapping); + break; + } +} + + +static uint8_t +compaq_plasma_in(uint16_t addr, void *priv) +{ + compaq_plasma_t *self = (compaq_plasma_t *)priv; + uint8_t ret = 0xff; + + switch (addr) { + case 0x3d4: + ret = self->cga.crtcreg; + break; + + case 0x3d5: + if (self->cga.crtcreg == 0x12) { + ret = self->attrmap & 0x0F; + if (self->internal_monitor) + ret |= 0x30; /* Plasma / CRT */ + } else + ret = self->cga.crtc[self->cga.crtcreg]; + break; + + case 0x3da: + ret = self->cga.cgastat; + break; + + case 0x13c6: + if (compaq_plasma_display_get()) + ret = 8; + else + ret = 0; + break; + + case 0x23c6: + ret = self->port_23c6; + break; + } + + return ret; +} + +static void +compaq_plasma_poll(void *p) +{ + compaq_plasma_t *self = (compaq_plasma_t *)p; + + /* Switch between internal plasma and external CRT display. */ + if (cpq_st_display_internal != -1 && cpq_st_display_internal != self->internal_monitor) { + self->internal_monitor = cpq_st_display_internal; + compaq_plasma_recalctimings(self); + } + + if (!self->internal_monitor && !(self->port_23c6 & 1)) { + cga_poll(&self->cga); + return; + } + + if (!self->linepos) { + timer_advance_u64(&self->cga.timer, self->dispofftime); + self->cga.cgastat |= 1; + self->linepos = 1; + if (self->dispon) { + if (self->displine == 0) + video_wait_for_buffer(); + + /* Graphics */ + if (self->cga.cgamode & 0x02) { + if (self->cga.cgamode & 0x10) + compaq_plasma_cgaline6(self); + else + compaq_plasma_cgaline4(self); + } + else if (self->cga.cgamode & 0x01) /* High-res text */ + compaq_plasma_text80(self); + else + compaq_plasma_text40(self); + } + self->displine++; + /* Hardcode a fixed refresh rate and VSYNC timing */ + if (self->displine == 400) { /* Start of VSYNC */ + self->cga.cgastat |= 8; + self->dispon = 0; + } + if (self->displine == 416) { /* End of VSYNC */ + self->displine = 0; + self->cga.cgastat &= ~8; + self->dispon = 1; + } + } else { + if (self->dispon) + self->cga.cgastat &= ~1; + + timer_advance_u64(&self->cga.timer, self->dispontime); + self->linepos = 0; + + if (self->displine == 400) { + /* Hardcode 640x400 window size */ + if ((640 != xsize) || (400 != ysize) || video_force_resize_get()) { + xsize = 640; + ysize = 400; + if (xsize < 64) + xsize = 656; + if (ysize < 32) + ysize = 200; + set_screen_size(xsize, ysize); + + if (video_force_resize_get()) + video_force_resize_set(0); + } + video_blit_memtoscreen(0, 0, 0, ysize, xsize, ysize); + frames++; + + /* Fixed 640x400 resolution */ + video_res_x = 640; + video_res_y = 400; + + if (self->cga.cgamode & 0x02) { + if (self->cga.cgamode & 0x10) + video_bpp = 1; + else + video_bpp = 2; + + } else + video_bpp = 0; + self->cga.cgablink++; + } + } +} + +static void +compaq_plasma_recalcattrs(compaq_plasma_t *self) +{ + int n; + + /* val behaves as follows: + * Bit 0: Attributes 01-06, 08-0E are inverse video + * Bit 1: Attributes 01-06, 08-0E are bold + * Bit 2: Attributes 11-16, 18-1F, 21-26, 28-2F ... F1-F6, F8-FF + * are inverse video + * Bit 3: Attributes 11-16, 18-1F, 21-26, 28-2F ... F1-F6, F8-FF + * are bold */ + + /* Set up colours */ + amber = makecol(0xff, 0x7D, 0x00); + black = makecol(0x64, 0x19, 0x00); + + /* Initialise the attribute mapping. Start by defaulting everything + * to black on amber, and with bold set by bit 3 */ + for (n = 0; n < 256; n++) { + blinkcols[n][0] = normcols[n][0] = amber; + blinkcols[n][1] = normcols[n][1] = black; + } + + /* Colours 0x11-0xFF are controlled by bits 2 and 3 of the + * passed value. Exclude x0 and x8, which are always black on + * amber. */ + for (n = 0x11; n <= 0xFF; n++) { + if ((n & 7) == 0) + continue; + if (self->attrmap & 4) { /* Inverse */ + blinkcols[n][0] = normcols[n][0] = amber; + blinkcols[n][1] = normcols[n][1] = black; + } else { /* Normal */ + blinkcols[n][0] = normcols[n][0] = black; + blinkcols[n][1] = normcols[n][1] = amber; + } + } + /* Set up the 01-0E range, controlled by bits 0 and 1 of the + * passed value. When blinking is enabled this also affects 81-8E. */ + for (n = 0x01; n <= 0x0E; n++) { + if (n == 7) + continue; + if (self->attrmap & 1) { + blinkcols[n][0] = normcols[n][0] = amber; + blinkcols[n][1] = normcols[n][1] = black; + blinkcols[n+128][0] = amber; + blinkcols[n+128][1] = black; + } else { + blinkcols[n][0] = normcols[n][0] = black; + blinkcols[n][1] = normcols[n][1] = amber; + blinkcols[n+128][0] = black; + blinkcols[n+128][1] = amber; + } + } + /* Colours 07 and 0F are always amber on black. If blinking is + * enabled so are 87 and 8F. */ + for (n = 0x07; n <= 0x0F; n += 8) { + blinkcols[n][0] = normcols[n][0] = black; + blinkcols[n][1] = normcols[n][1] = amber; + blinkcols[n+128][0] = black; + blinkcols[n+128][1] = amber; + } + /* When not blinking, colours 81-8F are always amber on black. */ + for (n = 0x81; n <= 0x8F; n ++) { + normcols[n][0] = black; + normcols[n][1] = amber; + } + + /* Finally do the ones which are solid black. These differ between + * the normal and blinking mappings */ + for (n = 0; n <= 0xFF; n += 0x11) + normcols[n][0] = normcols[n][1] = black; + + /* In the blinking range, 00 11 22 .. 77 and 80 91 A2 .. F7 are black */ + for (n = 0; n <= 0x77; n += 0x11) { + blinkcols[n][0] = blinkcols[n][1] = black; + blinkcols[n+128][0] = blinkcols[n+128][1] = black; + } +} + +static void * +compaq_plasma_init(const device_t *info) +{ + int display_type; + compaq_plasma_t *self = malloc(sizeof(compaq_plasma_t)); + memset(self, 0, sizeof(compaq_plasma_t)); + + display_type = device_get_config_int("display_type"); + self->cga.composite = (display_type != CGA_RGB); + self->cga.revision = device_get_config_int("composite_type"); + + self->vram = malloc(0x8000); + self->internal_monitor = 1; + + cga_comp_init(self->cga.revision); + timer_add(&self->cga.timer, compaq_plasma_poll, self, 1); + mem_mapping_add(&self->plasma_mapping, 0xb8000, 0x08000, compaq_plasma_read, NULL, NULL, compaq_plasma_write, NULL, NULL, NULL /*self->cga.vram*/, MEM_MAPPING_EXTERNAL, self); + io_sethandler(0x03d0, 0x0010, compaq_plasma_in, NULL, NULL, compaq_plasma_out, NULL, NULL, self); + io_sethandler(0x13c6, 0x0001, compaq_plasma_in, NULL, NULL, compaq_plasma_out, NULL, NULL, self); + io_sethandler(0x23c6, 0x0001, compaq_plasma_in, NULL, NULL, compaq_plasma_out, NULL, NULL, self); + + /* Default attribute mapping is 4 */ + self->attrmap = 4; + compaq_plasma_recalcattrs(self); + + self->cga.cgastat = 0xF4; + self->cga.vram = self->vram; + + overscan_x = overscan_y = 16; + + self->cga.rgb_type = device_get_config_int("rgb_type"); + cga_palette = (self->cga.rgb_type << 1); + cgapal_rebuild(); + + return self; +} + +static void +compaq_plasma_close(void *p) +{ + compaq_plasma_t *self = (compaq_plasma_t *)p; + + free(self->vram); + free(self); +} + +static void +compaq_plasma_speed_changed(void *p) +{ + compaq_plasma_t *self = (compaq_plasma_t *)p; + + compaq_plasma_recalctimings(self); +} + +const device_config_t compaq_plasma_config[] = +{ + { + "display_type", "Display type", CONFIG_SELECTION, "", CGA_RGB, + { + { + "RGB", CGA_RGB + }, + { + "Composite", CGA_COMPOSITE + }, + { + "" + } + } + }, + { + "composite_type", "Composite type", CONFIG_SELECTION, "", COMPOSITE_OLD, + { + { + "Old", COMPOSITE_OLD + }, + { + "New", COMPOSITE_NEW + }, + { + "" + } + } + }, + { + "rgb_type", "RGB type", CONFIG_SELECTION, "", 0, + { + { + "Color", 0 + }, + { + "Green Monochrome", 1 + }, + { + "Amber Monochrome", 2 + }, + { + "Gray Monochrome", 3 + }, + { + "Color (no brown)", 4 + }, + { + "" + } + } + }, + { + "", "", -1 + } +}; + + +static const device_t compaq_plasma_device = +{ + "Compaq Plasma", + 0, 0, + compaq_plasma_init, + compaq_plasma_close, + NULL, + NULL, + compaq_plasma_speed_changed, + NULL, + compaq_plasma_config +}; static uint8_t read_ram(uint32_t addr, void *priv) @@ -107,6 +791,11 @@ write_raml(uint32_t addr, uint32_t val, void *priv) mem_write_raml_page(addr, val, &pages[addr >> 12]); } +const device_t * +at_cpqiii_get_device(void) +{ + return &compaq_plasma_device; +} static void machine_at_compaq_init(const machine_t *model, int type) @@ -126,15 +815,17 @@ machine_at_compaq_init(const machine_t *model, int type) case COMPAQ_PORTABLEII: break; -#if defined(DEV_BRANCH) && defined(USE_PORTABLE3) case COMPAQ_PORTABLEIII: + if (gfxcard == VID_INTERNAL) + device_add(&compaq_plasma_device); break; case COMPAQ_PORTABLEIII386: if (hdc_current == 1) device_add(&ide_isa_device); + if (gfxcard == VID_INTERNAL) + device_add(&compaq_plasma_device); break; -#endif } } @@ -157,7 +848,6 @@ machine_at_portableii_init(const machine_t *model) } -#if defined(DEV_BRANCH) && defined(USE_PORTABLE3) int machine_at_portableiii_init(const machine_t *model) { @@ -192,4 +882,3 @@ machine_at_portableiii386_init(const machine_t *model) return ret; } -#endif diff --git a/src/machine/machine.h b/src/machine/machine.h index 7f584a5ea..48fac0728 100644 --- a/src/machine/machine.h +++ b/src/machine/machine.h @@ -237,9 +237,10 @@ extern int machine_at_cmdpc_init(const machine_t *); /* m_at_compaq.c */ extern int machine_at_portableii_init(const machine_t *); -#if defined(DEV_BRANCH) && defined(USE_PORTABLE3) extern int machine_at_portableiii_init(const machine_t *); extern int machine_at_portableiii386_init(const machine_t *); +#ifdef EMU_DEVICE_H +extern const device_t *at_cpqiii_get_device(void); #endif /* m_at_socket4_5.c */ diff --git a/src/machine/machine_table.c b/src/machine/machine_table.c index be958aa0f..f5721ad83 100644 --- a/src/machine/machine_table.c +++ b/src/machine/machine_table.c @@ -103,9 +103,7 @@ const machine_t machines[] = { { "[286 ISA] Quadtel 286 clone", "quadt286", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 512,16384, 128, 127, machine_at_quadt286_init, NULL }, { "[286 ISA] Commodore PC 30 III", "cmdpc30", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 640,16384, 128, 127, machine_at_cmdpc_init, NULL }, { "[286 ISA] Compaq Portable II", "portableii", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 640,16384, 128, 127, machine_at_portableii_init, NULL }, -#if defined(DEV_BRANCH) && defined(USE_PORTABLE3) - { "[286 ISA] Compaq Portable III", "portableiii", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_VIDEO | MACHINE_VIDEO_FIXED, 640,16384, 128, 127, machine_at_portableiii_init, NULL }, -#endif + { "[286 ISA] Compaq Portable III", "portableiii", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_VIDEO, 640,16384, 128, 127, machine_at_portableiii_init, at_cpqiii_get_device }, { "[286 ISA] GW-286CT GEAR", "gw286ct", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 512,16384, 128, 127, machine_at_gw286ct_init, NULL }, { "[286 ISA] Hyundai Super-286TR", "super286tr", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 512,16384, 128, 127, machine_at_super286tr_init, NULL }, { "[286 ISA] IBM AT", "ibmat", {{"", cpus_ibmat}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT, 256,15872, 128, 63, machine_at_ibm_init, NULL }, @@ -151,9 +149,7 @@ const machine_t machines[] = { #if defined(DEV_BRANCH) && defined(USE_MR495) { "[386DX ISA] MR 386DX clone", "mr386dx", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 32, 1, 127, machine_at_opti495_mr_init, NULL }, #endif -#if defined(DEV_BRANCH) && defined(USE_PORTABLE3) - { "[386DX ISA] Compaq Portable III (386)", "portableiii386", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_HDC | MACHINE_VIDEO | MACHINE_VIDEO_FIXED, 1, 14, 1, 127, machine_at_portableiii386_init, NULL }, -#endif + { "[386DX ISA] Compaq Portable III (386)", "portableiii386", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_AT | MACHINE_HDC | MACHINE_VIDEO, 1, 14, 1, 127, machine_at_portableiii386_init, at_cpqiii_get_device }, { "[386DX MCA] IBM PS/2 model 70 (type 3)", "ibmps2_m70_type3", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"IBM",cpus_IBM486BL},{"", NULL}}, MACHINE_MCA | MACHINE_AT | MACHINE_PS2 | MACHINE_VIDEO, 2, 16, 2, 63, machine_ps2_model_70_type3_init, NULL }, { "[386DX MCA] IBM PS/2 model 80", "ibmps2_m80", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"IBM",cpus_IBM486BL},{"", NULL}}, MACHINE_MCA | MACHINE_AT | MACHINE_PS2 | MACHINE_VIDEO, 1, 12, 1, 63, machine_ps2_model_80_init, NULL }, From 8b4e7301e837ee574506e0e22e8eb46ba7031c84 Mon Sep 17 00:00:00 2001 From: TC1995 Date: Wed, 25 Mar 2020 02:24:47 +0100 Subject: [PATCH 21/33] Compile fix (again). --- src/machine/m_at_compaq.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/src/machine/m_at_compaq.c b/src/machine/m_at_compaq.c index 915168a10..f29a55842 100644 --- a/src/machine/m_at_compaq.c +++ b/src/machine/m_at_compaq.c @@ -20,10 +20,14 @@ #include #include #include +#include #include +#include #include "86box.h" #include "cpu.h" +#include "86box_io.h" #include "timer.h" +#include "pit.h" #include "mem.h" #include "rom.h" #include "device.h" @@ -32,6 +36,9 @@ #include "hdc.h" #include "hdc_ide.h" #include "machine.h" +#include "video.h" +#include "vid_cga.h" +#include "vid_cga_comp.h" enum From 5e4a76f02086f34b6dc1cc240eb5446ed7589bf6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?David=20Hrdli=C4=8Dka?= Date: Wed, 25 Mar 2020 03:34:22 +0100 Subject: [PATCH 22/33] remove source file versions --- src/sio.h | 2 -- src/sio_f82c710.c | 2 -- src/sound/snd_sb.h | 2 -- src/win/win_joystick_rawinput.c | 2 -- 4 files changed, 8 deletions(-) diff --git a/src/sio.h b/src/sio.h index c38364504..b618bfe1e 100644 --- a/src/sio.h +++ b/src/sio.h @@ -8,8 +8,6 @@ * * Definitions for the Super I/O chips. * - * Version: @(#)sio.h 1.0.7 2020/01/25 - * * Author: Fred N. van Kempen, * Copyright 2017-2020 Fred N. van Kempen. */ diff --git a/src/sio_f82c710.c b/src/sio_f82c710.c index d6b988a97..fbd7a4848 100644 --- a/src/sio_f82c710.c +++ b/src/sio_f82c710.c @@ -8,8 +8,6 @@ * * Implementation of the Chips & Technologies F82C710 Universal Peripheral Controller (UPC). * - * Version: @(#)sio_f82c710.c 1.0.0 2020/03/12 - * * Authors: Sarah Walker, * Eluan Costa Miranda * diff --git a/src/sound/snd_sb.h b/src/sound/snd_sb.h index ee996b923..b844334bf 100644 --- a/src/sound/snd_sb.h +++ b/src/sound/snd_sb.h @@ -8,8 +8,6 @@ * * Sound Blaster emulation. * - * Version: @(#)sound_sb.h 1.0.4 2020/02/17 - * * Authors: Sarah Walker, * Miran Grca, * TheCollector1995, diff --git a/src/win/win_joystick_rawinput.c b/src/win/win_joystick_rawinput.c index 85e8f31df..2eb724ae0 100644 --- a/src/win/win_joystick_rawinput.c +++ b/src/win/win_joystick_rawinput.c @@ -8,8 +8,6 @@ * * RawInput joystick interface. * - * Version: @(#)win_joystick_rawinput.c 1.0.0 2020/1/19 - * * Authors: Sarah Walker, * Miran Grca, * GH Cao, From 98e6a48cefcddd57ba04e01f498b25111170f017 Mon Sep 17 00:00:00 2001 From: nerd73 Date: Tue, 24 Mar 2020 21:53:19 -0600 Subject: [PATCH 23/33] A port of the ECS 386/32 machine from PCem. --- src/chipset/chipset.h | 7 +- src/chipset/cs8230.c | 145 +++++++++++++++++++++++++++++++++++ src/chipset/cs8230.h | 1 + src/machine/m_at_386dx_486.c | 29 +++++++ src/machine/machine.h | 3 + src/machine/machine_table.c | 1 + 6 files changed, 182 insertions(+), 4 deletions(-) create mode 100644 src/chipset/cs8230.c create mode 100644 src/chipset/cs8230.h diff --git a/src/chipset/chipset.h b/src/chipset/chipset.h index 61ea87401..057df0cdb 100644 --- a/src/chipset/chipset.h +++ b/src/chipset/chipset.h @@ -47,16 +47,15 @@ extern const device_t i440fx_device; extern const device_t i440bx_device; extern const device_t i440zx_device; -/* NEAT */ -extern const device_t neat_device; - /* OPTi */ extern const device_t opti495_device; -/* SCAT */ +/* C&T */ +extern const device_t neat_device; extern const device_t scat_device; extern const device_t scat_4_device; extern const device_t scat_sx_device; +extern const device_t cs8230_device; /* SiS */ extern const device_t sis_85c471_device; diff --git a/src/chipset/cs8230.c b/src/chipset/cs8230.c new file mode 100644 index 000000000..9cd32551b --- /dev/null +++ b/src/chipset/cs8230.c @@ -0,0 +1,145 @@ +/* + * 86Box A hypervisor and IBM PC system emulator that specializes in + * running old operating systems and software designed for IBM + * PC systems and compatibles from 1981 through fairly recent + * system designs based on the PCI bus. + * + * This file is part of the 86Box distribution. + * + * Emulation of C&T CS8230 ("386/AT") chipset. + * + * + * + * Authors: Sarah Walker, + * + * Copyright 2020 Sarah Walker. + */ +#include +#include +#include +#include +#include +#include "86box.h" +#include "cpu.h" +#include "timer.h" +#include "86box_io.h" +#include "device.h" +#include "mem.h" +#include "fdd.h" +#include "fdc.h" +#include "chipset.h" + + +static struct +{ + int idx; + uint8_t regs[256]; +} cs8230; + +static void shadow_control(uint32_t addr, uint32_t size, int state) +{ +// pclog("shadow_control: addr=%08x size=%04x state=%02x\n", addr, size, state); + switch (state) + { + case 0x00: + mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); + break; + case 0x01: + mem_set_mem_state(addr, size, MEM_READ_EXTANY | MEM_WRITE_INTERNAL); + break; + case 0x10: + mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_EXTANY); + break; + case 0x11: + mem_set_mem_state(addr, size, MEM_READ_EXTANY | MEM_WRITE_EXTANY); + break; + } + flushmmucache_nopc(); +} + + +static void rethink_shadow_mappings(void) +{ + int c; + + for (c = 0; c < 4*8; c++) /*Addresses 40000-bffff in 16k blocks*/ + { + if (cs8230.regs[0xa + (c >> 3)] & (1 << (c & 7))) + mem_set_mem_state(0x40000 + c*0x4000, 0x4000, MEM_READ_EXTANY | MEM_WRITE_EXTANY); /*IO channel*/ + else + mem_set_mem_state(0x40000 + c*0x4000, 0x4000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); /*System board*/ + } + for (c = 0; c < 2*8; c++) /*Addresses c0000-fffff in 16k blocks. System board ROM can be mapped here*/ + { + if (cs8230.regs[0xe + (c >> 3)] & (1 << (c & 7))) + mem_set_mem_state(0xc0000 + c*0x4000, 0x4000, MEM_READ_EXTANY | MEM_WRITE_EXTANY); /*IO channel*/ + else + shadow_control(0xc0000 + c*0x4000, 0x4000, (cs8230.regs[9] >> (3-(c >> 2))) & 0x11); + } +} + +static uint8_t cs8230_read(uint16_t port, void *p) +{ + uint8_t ret = 0xff; + + if (port & 1) + { + switch (cs8230.idx) + { + case 0x04: /*82C301 ID/version*/ + ret = cs8230.regs[cs8230.idx] & ~0xe3; + break; + + case 0x08: /*82C302 ID/Version*/ + ret = cs8230.regs[cs8230.idx] & ~0xe0; + break; + + case 0x05: case 0x06: /*82C301 registers*/ + case 0x09: case 0x0a: case 0x0b: case 0x0c: /*82C302 registers*/ + case 0x0d: case 0x0e: case 0x0f: + case 0x10: case 0x11: case 0x12: case 0x13: + case 0x28: case 0x29: case 0x2a: + ret = cs8230.regs[cs8230.idx]; + break; + } + } + + return ret; +} + +static void cs8230_write(uint16_t port, uint8_t val, void *p) +{ + if (!(port & 1)) + cs8230.idx = val; + else + { +// pclog("cs8230_write: reg=%02x val=%02x\n", cs8230.idx, val); + cs8230.regs[cs8230.idx] = val; + switch (cs8230.idx) + { + case 0x09: /*RAM/ROM Configuration in boot area*/ + case 0x0a: case 0x0b: case 0x0c: case 0x0d: case 0x0e: case 0x0f: /*Address maps*/ +// rethink_shadow_mappings(); + break; + } + } +} + +static void * cs8230_init(const device_t *info) +{ + memset(&cs8230, 0, sizeof(cs8230)); + + io_sethandler(0x0022, 0x0002, + cs8230_read, NULL, NULL, + cs8230_write, NULL, NULL, + NULL); +} + +const device_t cs8230_device = { + "C&T CS8230 (386/AT)", + 0, + 0, + cs8230_init, NULL, NULL, + NULL, NULL, NULL, + NULL +}; \ No newline at end of file diff --git a/src/chipset/cs8230.h b/src/chipset/cs8230.h new file mode 100644 index 000000000..ed7dedc4b --- /dev/null +++ b/src/chipset/cs8230.h @@ -0,0 +1 @@ +void cs8230_init(void); diff --git a/src/machine/m_at_386dx_486.c b/src/machine/m_at_386dx_486.c index e36e4876c..b0230854e 100644 --- a/src/machine/m_at_386dx_486.c +++ b/src/machine/m_at_386dx_486.c @@ -41,7 +41,36 @@ #include "intel_flash.h" #include "intel_sio.h" #include "machine.h" +static void +machine_at_cs8230_init(const machine_t *model) +{ + machine_at_common_init(model); + + device_add(&cs8230_device); + +} + + +int +machine_at_ecs386_init(const machine_t *model) +{ + int ret; + + ret = bios_load_interleaved(L"roms/machines/ecs386/AMI BIOS for ECS-386_32 motherboard - L chip.bin", + L"roms/machines/ecs386/AMI BIOS for ECS-386_32 motherboard - H chip.bin", + 0x000f0000, 65536, 0); + + if (bios_only || !ret) + return ret; + + machine_at_cs8230_init(model); + + device_add(&keyboard_at_ami_device); + device_add(&fdc_at_device); + + return ret; +} int machine_at_pb410a_init(const machine_t *model) diff --git a/src/machine/machine.h b/src/machine/machine.h index 48fac0728..61cac0923 100644 --- a/src/machine/machine.h +++ b/src/machine/machine.h @@ -210,6 +210,9 @@ extern const device_t *at_commodore_sl386sx_get_device(void); #endif /* m_at_386dx_486.c */ + +extern int machine_at_ecs386_init(const machine_t *); + extern int machine_at_pb410a_init(const machine_t *); extern int machine_at_ali1429_init(const machine_t *); diff --git a/src/machine/machine_table.c b/src/machine/machine_table.c index f5721ad83..cca655def 100644 --- a/src/machine/machine_table.c +++ b/src/machine/machine_table.c @@ -144,6 +144,7 @@ const machine_t machines[] = { { "[386SX MCA] IBM PS/2 model 55SX", "ibmps2_m55sx", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"IBM",cpus_IBM486SLC},{"", NULL}}, MACHINE_MCA | MACHINE_AT | MACHINE_PS2 | MACHINE_VIDEO, 1, 8, 1, 63, machine_ps2_model_55sx_init, NULL }, + { "[386DX ISA] ECS 386/32", "ecs386", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}},MACHINE_ISA | MACHINE_AT, 512,16384, 512, 127, machine_at_ecs386_init, NULL }, { "[386DX ISA] Dataexpert SX495 (386DX)", "ami386dx", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 32, 1, 127, machine_at_opti495_ami_init, NULL }, { "[386DX ISA] Award 386DX clone", "award386dx", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_HDC, 1, 32, 1, 127, machine_at_opti495_init, NULL }, #if defined(DEV_BRANCH) && defined(USE_MR495) From df2e2b505d680adc0c5458b2e487e86162439bac Mon Sep 17 00:00:00 2001 From: nerd73 Date: Wed, 25 Mar 2020 01:50:09 -0600 Subject: [PATCH 24/33] Added cs8230.o to the makefile --- src/win/Makefile.mingw | 2 +- src/win/Makefile_ndr.mingw | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/win/Makefile.mingw b/src/win/Makefile.mingw index 008a0510c..48a3af329 100644 --- a/src/win/Makefile.mingw +++ b/src/win/Makefile.mingw @@ -572,7 +572,7 @@ CPUOBJ := cpu.o cpu_table.o \ x86seg.o x87.o \ $(DYNARECOBJ) -CHIPSETOBJ := acc2168.o acer_m3a.o ali1429.o headland.o \ +CHIPSETOBJ := acc2168.o acer_m3a.o cs8230.o ali1429.o headland.o \ intel_4x0.o neat.o opti495.o scamp.o scat.o \ sis_85c471.o sis_85c496.o \ via_mvp3.o wd76c10.o diff --git a/src/win/Makefile_ndr.mingw b/src/win/Makefile_ndr.mingw index c26eed470..ea9da29e9 100644 --- a/src/win/Makefile_ndr.mingw +++ b/src/win/Makefile_ndr.mingw @@ -577,7 +577,7 @@ CPUOBJ := cpu.o cpu_table.o \ x86seg.o x87.o \ $(DYNARECOBJ) -CHIPSETOBJ := acc2168.o acer_m3a.o ali1429.o headland.o \ +CHIPSETOBJ := acc2168.o acer_m3a.o cs8230.o ali1429.o headland.o \ intel_4x0.o neat.o opti495.o scamp.o scat.o \ sis_85c471.o sis_85c496.o \ via_mvp3.o wd76c10.o From 1f6d05f6375be2e6c7f76f0bee3e143ef250c4f5 Mon Sep 17 00:00:00 2001 From: tiseno100 <58827426+tiseno100@users.noreply.github.com> Date: Wed, 25 Mar 2020 12:22:51 +0200 Subject: [PATCH 25/33] Added the Packard Bell Bora Pro + Celeron changes Now Slot1 motherboards can access the Celeron processors at the Intel/PGA370 category Added the Packard Bell Bora Pro. A 440ZX based AMI board. It's just a MSI 6168 with the AMI PB OEM BIOS slapped in it. It reports excessive amounts of RAM and also looks for an SDRAM serial(which is not a huge deal). Roms can be found on the roms PR --- src/cpu_common/cpu.h | 1134 +++++++++++++------------- src/cpu_common/cpu_table.c | 1489 ++++++++++++++++++----------------- src/machines/m_at_socket8.c | 300 +++++++ 3 files changed, 1614 insertions(+), 1309 deletions(-) create mode 100644 src/machines/m_at_socket8.c diff --git a/src/cpu_common/cpu.h b/src/cpu_common/cpu.h index 4f164f748..bdba10437 100644 --- a/src/cpu_common/cpu.h +++ b/src/cpu_common/cpu.h @@ -1,567 +1,567 @@ -/* - * 86Box A hypervisor and IBM PC system emulator that specializes in - * running old operating systems and software designed for IBM - * PC systems and compatibles from 1981 through fairly recent - * system designs based on the PCI bus. - * - * This file is part of the 86Box distribution. - * - * CPU type handler. - * - * - * - * Authors: Sarah Walker, - * leilei, - * Miran Grca, - * - * Copyright 2008-2018 Sarah Walker. - * Copyright 2016-2018 leilei. - * Copyright 2016,2018 Miran Grca. - */ -#ifndef EMU_CPU_H -# define EMU_CPU_H -enum { - CPU_8088, /* 808x class CPUs */ - CPU_8086, -#ifdef USE_NEC_808X - CPU_V20, /* NEC 808x class CPUs - future proofing */ - CPU_V30, -#endif - CPU_286, /* 286 class CPUs */ - CPU_386SX, /* 386 class CPUs */ - CPU_386DX, - CPU_IBM386SLC, - CPU_IBM486SLC, - CPU_IBM486BL, - CPU_RAPIDCAD, - CPU_486SLC, - CPU_486DLC, - CPU_i486SX, /* 486 class CPUs */ - CPU_Am486SX, - CPU_Cx486S, - CPU_i486SX2, - CPU_Am486SX2, - CPU_i486DX, - CPU_i486DX2, - CPU_Am486DX, - CPU_Am486DX2, - CPU_Cx486DX, - CPU_Cx486DX2, - CPU_iDX4, - CPU_Am486DX4, - CPU_Cx486DX4, - CPU_Am5x86, - CPU_Cx5x86, - CPU_WINCHIP, /* 586 class CPUs */ -#ifdef USE_NEW_DYNAREC - CPU_WINCHIP2, -#endif - CPU_PENTIUM, - CPU_PENTIUMMMX, -#if (defined(USE_NEW_DYNAREC) || (defined(DEV_BRANCH) && defined(USE_CYRIX_6X86))) - CPU_Cx6x86, - CPU_Cx6x86MX, - CPU_Cx6x86L, - CPU_CxGX1, -#endif -#if (defined(USE_NEW_DYNAREC) || (defined(DEV_BRANCH) && defined(USE_AMD_K))) - CPU_K5, - CPU_5K86, - CPU_K6, -#endif -#ifdef USE_NEW_DYNAREC - CPU_K6_2, - CPU_K6_2C, - CPU_K6_3, - CPU_K6_2P, - CPU_K6_3P, -#endif - CPU_CYRIX3S, -#if defined(DEV_BRANCH) && defined(USE_I686) - CPU_PENTIUMPRO, /* 686 class CPUs */ - CPU_PENTIUM2, - CPU_PENTIUM2D, -#endif - CPU_MAX /* Only really needed to close the enum in a way independent of the #ifdef's. */ -}; - - -#define MANU_INTEL 0 -#define MANU_AMD 1 -#define MANU_CYRIX 2 -#define MANU_IDT 3 -#define MANU_NEC 4 - -#define CPU_SUPPORTS_DYNAREC 1 -#define CPU_REQUIRES_DYNAREC 2 -#define CPU_ALTERNATE_XTAL 4 - - -typedef struct { - const char *name; - int cpu_type; - int rspeed; - double multi; - uint32_t edx_reset; - uint32_t cpuid_model; - uint16_t cyrix_id; - uint8_t cpu_flags; - int8_t mem_read_cycles, mem_write_cycles; - int8_t cache_read_cycles, cache_write_cycles; - int8_t atclk_div; -} CPU; - - -extern CPU cpus_8088[]; -extern CPU cpus_8086[]; -extern CPU cpus_286[]; -extern CPU cpus_i386SX[]; -extern CPU cpus_i386DX[]; -extern CPU cpus_Am386SX[]; -extern CPU cpus_Am386DX[]; -extern CPU cpus_486SLC[]; -extern CPU cpus_486DLC[]; -extern CPU cpus_IBM386SLC[]; -extern CPU cpus_IBM486SLC[]; -extern CPU cpus_IBM486BL[]; -extern CPU cpus_i486S1[]; -extern CPU cpus_Am486S1[]; -extern CPU cpus_Cx486S1[]; -extern CPU cpus_i486[]; -extern CPU cpus_Am486[]; -extern CPU cpus_Cx486[]; -extern CPU cpus_WinChip[]; -#ifdef USE_NEW_DYNAREC -extern CPU cpus_WinChip_SS7[]; -#endif -extern CPU cpus_Pentium5V[]; -extern CPU cpus_Pentium5V50[]; -extern CPU cpus_PentiumS5[]; -extern CPU cpus_Pentium3V[]; -extern CPU cpus_Pentium[]; -#if (defined(USE_NEW_DYNAREC) || (defined(DEV_BRANCH) && defined(USE_AMD_K))) -extern CPU cpus_K5[]; -extern CPU cpus_K56[]; -#endif -#ifdef USE_NEW_DYNAREC -extern CPU cpus_K56_SS7[]; -#endif -#if (defined(USE_NEW_DYNAREC) || (defined(DEV_BRANCH) && defined(USE_CYRIX_6X86))) -extern CPU cpus_6x863V[]; -extern CPU cpus_6x86[]; -#endif -#ifdef USE_NEW_DYNAREC -extern CPU cpus_6x86SS7[]; -#endif -extern CPU cpus_Cyrix3[]; -#if defined(DEV_BRANCH) && defined(USE_I686) -extern CPU cpus_PentiumPro[]; -extern CPU cpus_PentiumII[]; -extern CPU cpus_PGA370[]; -#endif - - -#define C_FLAG 0x0001 -#define P_FLAG 0x0004 -#define A_FLAG 0x0010 -#define Z_FLAG 0x0040 -#define N_FLAG 0x0080 -#define T_FLAG 0x0100 -#define I_FLAG 0x0200 -#define D_FLAG 0x0400 -#define V_FLAG 0x0800 -#define NT_FLAG 0x4000 - -#define VM_FLAG 0x0002 /* in EFLAGS */ -#define VIF_FLAG 0x0008 /* in EFLAGS */ -#define VIP_FLAG 0x0010 /* in EFLAGS */ - -#define WP_FLAG 0x10000 /* in CR0 */ -#define CR4_VME (1 << 0) -#define CR4_PVI (1 << 1) -#define CR4_PSE (1 << 4) - -#define CPL ((cpu_state.seg_cs.access>>5)&3) - -#define IOPL ((cpu_state.flags>>12)&3) - -#define IOPLp ((!(msw&1)) || (CPL<=IOPL)) - - -typedef union { - uint32_t l; - uint16_t w; - struct { - uint8_t l, - h; - } b; -} x86reg; - -typedef struct { - uint32_t base; - uint32_t limit; - uint8_t access; - uint16_t seg; - uint32_t limit_low, - limit_high; - int checked; /*Non-zero if selector is known to be valid*/ -} x86seg; - -typedef union { - uint64_t q; - int64_t sq; - uint32_t l[2]; - int32_t sl[2]; - uint16_t w[4]; - int16_t sw[4]; - uint8_t b[8]; - int8_t sb[8]; - float f[2]; -} MMX_REG; - -typedef struct { - uint32_t tr1, tr12; - uint32_t cesr; - uint32_t fcr; - uint64_t fcr2, fcr3; -} msr_t; - -typedef union { - uint32_t l; - uint16_t w; -} cr0_t; - - -struct _cpustate_ { - x86reg regs[8]; - - uint8_t tag[8]; - - x86seg *ea_seg; - uint32_t eaaddr; - - int flags_op; - uint32_t flags_res; - uint32_t flags_op1, - flags_op2; - - uint32_t pc; - uint32_t oldpc; - uint32_t op32; - - int TOP; - - union { - struct { - int8_t rm, - mod, - reg; - } rm_mod_reg; - int32_t rm_mod_reg_data; - } rm_data; - - int8_t ssegs; - int8_t ismmx; - int8_t abrt; - - int _cycles; - int cpu_recomp_ins; - - uint16_t npxs, - npxc; - - double ST[8]; - - uint16_t MM_w4[8]; - - MMX_REG MM[8]; - - uint16_t old_npxc, - new_npxc; - uint32_t last_ea; - -#ifdef USE_NEW_DYNAREC - uint32_t old_fp_control, new_fp_control; -#if defined i386 || defined __i386 || defined __i386__ || defined _X86_ - uint16_t old_fp_control2, new_fp_control2; -#endif -#if defined i386 || defined __i386 || defined __i386__ || defined _X86_ || defined __amd64__ - uint32_t trunc_fp_control; -#endif -#endif - - x86seg seg_cs, - seg_ds, - seg_es, - seg_ss, - seg_fs, - seg_gs; - - uint16_t flags, eflags; -} cpu_state; - -/*The cpu_state.flags below must match in both cpu_cur_status and block->status for a block - to be valid*/ -#define CPU_STATUS_USE32 (1 << 0) -#define CPU_STATUS_STACK32 (1 << 1) -#define CPU_STATUS_PMODE (1 << 2) -#define CPU_STATUS_V86 (1 << 3) -#define CPU_STATUS_FLAGS 0xffff - -/*If the cpu_state.flags below are set in cpu_cur_status, they must be set in block->status. - Otherwise they are ignored*/ -#ifdef USE_NEW_DYNAREC -#define CPU_STATUS_NOTFLATDS (1 << 8) -#define CPU_STATUS_NOTFLATSS (1 << 9) -#define CPU_STATUS_MASK 0xff00 -#else -#define CPU_STATUS_NOTFLATDS (1 << 16) -#define CPU_STATUS_NOTFLATSS (1 << 17) -#define CPU_STATUS_MASK 0xffff0000 -#endif - -#ifdef __MSC__ -# define COMPILE_TIME_ASSERT(expr) /*nada*/ -#else -# ifdef EXTREME_DEBUG -# define COMPILE_TIME_ASSERT(expr) typedef char COMP_TIME_ASSERT[(expr) ? 1 : 0]; -# else -# define COMPILE_TIME_ASSERT(expr) /*nada*/ -# endif -#endif - -COMPILE_TIME_ASSERT(sizeof(cpu_state) <= 128) - -#define cpu_state_offset(MEMBER) ((uint8_t)((uintptr_t)&cpu_state.MEMBER - (uintptr_t)&cpu_state - 128)) - -#define EAX cpu_state.regs[0].l -#define AX cpu_state.regs[0].w -#define AL cpu_state.regs[0].b.l -#define AH cpu_state.regs[0].b.h -#define ECX cpu_state.regs[1].l -#define CX cpu_state.regs[1].w -#define CL cpu_state.regs[1].b.l -#define CH cpu_state.regs[1].b.h -#define EDX cpu_state.regs[2].l -#define DX cpu_state.regs[2].w -#define DL cpu_state.regs[2].b.l -#define DH cpu_state.regs[2].b.h -#define EBX cpu_state.regs[3].l -#define BX cpu_state.regs[3].w -#define BL cpu_state.regs[3].b.l -#define BH cpu_state.regs[3].b.h -#define ESP cpu_state.regs[4].l -#define EBP cpu_state.regs[5].l -#define ESI cpu_state.regs[6].l -#define EDI cpu_state.regs[7].l -#define SP cpu_state.regs[4].w -#define BP cpu_state.regs[5].w -#define SI cpu_state.regs[6].w -#define DI cpu_state.regs[7].w - -#define cycles cpu_state._cycles - -#define cpu_rm cpu_state.rm_data.rm_mod_reg.rm -#define cpu_mod cpu_state.rm_data.rm_mod_reg.mod -#define cpu_reg cpu_state.rm_data.rm_mod_reg.reg - -#define CR4_TSD (1 << 2) -#define CR4_DE (1 << 3) -#define CR4_MCE (1 << 6) -#define CR4_PCE (1 << 8) -#define CR4_OSFXSR (1 << 9) - - -/* Global variables. */ -extern int cpu_iscyrix; -extern int cpu_16bitbus; -extern int cpu_busspeed, cpu_pci_speed; -extern int cpu_multi; -extern double cpu_dmulti; -extern int cpu_cyrix_alignment; /*Cyrix 5x86/6x86 only has data misalignment - penalties when crossing 8-byte boundaries*/ - -extern int is8086, is286, is386, is486, is486sx, is486dx, is486sx2, is486dx2, isdx4; -extern int isibmcpu; -extern int is_rapidcad; -extern int hasfpu; -#define CPU_FEATURE_RDTSC (1 << 0) -#define CPU_FEATURE_MSR (1 << 1) -#define CPU_FEATURE_MMX (1 << 2) -#define CPU_FEATURE_CR4 (1 << 3) -#define CPU_FEATURE_VME (1 << 4) -#define CPU_FEATURE_CX8 (1 << 5) -#define CPU_FEATURE_3DNOW (1 << 6) - -extern uint32_t cpu_features; - -extern int in_smm, smi_line, smi_latched; -extern uint32_t smbase; - -#ifdef USE_NEW_DYNAREC -extern uint16_t cpu_cur_status; -#else -extern uint32_t cpu_cur_status; -#endif -extern uint64_t cpu_CR4_mask; -extern uint64_t tsc; -extern msr_t msr; -extern uint8_t opcode; -extern int insc; -extern int fpucount; -extern float mips,flops; -extern int clockrate; -extern int cgate16; -extern int cpl_override; -extern int CPUID; -extern uint64_t xt_cpu_multi; -extern int isa_cycles; -extern uint32_t oldds,oldss,olddslimit,oldsslimit,olddslimitw,oldsslimitw; -extern int ins,output; -extern uint32_t pccache; -extern uint8_t *pccache2; - -extern double bus_timing, pci_timing; -extern uint64_t pmc[2]; -extern uint16_t temp_seg_data[4]; -extern uint16_t cs_msr; -extern uint32_t esp_msr; -extern uint32_t eip_msr; - -/* For the AMD K6. */ -extern uint64_t star; - -#define FPU_CW_Reserved_Bits (0xe0c0) - -extern cr0_t CR0; -#define cr0 CR0.l -#define msw CR0.w -extern uint32_t cr2, cr3, cr4; -extern uint32_t dr[8]; - - -/*Segments - - _cs,_ds,_es,_ss are the segment structures - CS,DS,ES,SS is the 16-bit data - cs,ds,es,ss are defines to the bases*/ -extern x86seg gdt,ldt,idt,tr; -extern x86seg _oldds; -#define CS cpu_state.seg_cs.seg -#define DS cpu_state.seg_ds.seg -#define ES cpu_state.seg_es.seg -#define SS cpu_state.seg_ss.seg -#define FS cpu_state.seg_fs.seg -#define GS cpu_state.seg_gs.seg -#define cs cpu_state.seg_cs.base -#define ds cpu_state.seg_ds.base -#define es cpu_state.seg_es.base -#define ss cpu_state.seg_ss.base -#define fs_seg cpu_state.seg_fs.base -#define gs cpu_state.seg_gs.base - - -#define ISA_CYCLES(x) (x * isa_cycles) - -extern int cpu_cycles_read, cpu_cycles_read_l, cpu_cycles_write, cpu_cycles_write_l; -extern int cpu_prefetch_cycles, cpu_prefetch_width, cpu_mem_prefetch_cycles, cpu_rom_prefetch_cycles; -extern int cpu_waitstates; -extern int cpu_cache_int_enabled, cpu_cache_ext_enabled; -extern int cpu_pci_speed; - -extern int timing_rr; -extern int timing_mr, timing_mrl; -extern int timing_rm, timing_rml; -extern int timing_mm, timing_mml; -extern int timing_bt, timing_bnt; -extern int timing_int, timing_int_rm, timing_int_v86, timing_int_pm; -extern int timing_int_pm_outer, timing_iret_rm, timing_iret_v86, timing_iret_pm; -extern int timing_iret_pm_outer, timing_call_rm, timing_call_pm; -extern int timing_call_pm_gate, timing_call_pm_gate_inner; -extern int timing_retf_rm, timing_retf_pm, timing_retf_pm_outer; -extern int timing_jmp_rm, timing_jmp_pm, timing_jmp_pm_gate; -extern int timing_misaligned; - - -extern CPU cpus_pcjr[]; // FIXME: should be in machine file! -extern CPU cpus_europc[]; // FIXME: should be in machine file! -extern CPU cpus_pc1512[]; // FIXME: should be in machine file! -extern CPU cpus_ibmat[]; // FIXME: should be in machine file! -extern CPU cpus_ibmxt286[]; // FIXME: should be in machine file! -extern CPU cpus_ps1_m2011[]; // FIXME: should be in machine file! -extern CPU cpus_ps2_m30_286[]; // FIXME: should be in machine file! -#if 0 -extern CPU cpus_acer[]; // FIXME: should be in machine file! -#endif - - -/* Functions. */ -extern int cpu_has_feature(int feature); - -#ifdef USE_NEW_DYNAREC -extern void loadseg_dynarec(uint16_t seg, x86seg *s); -extern int loadseg(uint16_t seg, x86seg *s); -extern void loadcs(uint16_t seg); -#else -extern void loadseg(uint16_t seg, x86seg *s); -extern void loadcs(uint16_t seg); -#endif - -extern char *cpu_current_pc(char *bufp); - -extern void cpu_update_waitstates(void); -extern void cpu_set(void); - -extern void cpu_CPUID(void); -extern void cpu_RDMSR(void); -extern void cpu_WRMSR(void); - -extern int checkio(int port); -extern void codegen_block_end(void); -extern void codegen_reset(void); -extern void cpu_set_edx(void); -extern int divl(uint32_t val); -extern void execx86(int cycs); -extern void enter_smm(); -extern void leave_smm(); -extern void exec386(int cycs); -extern void exec386_dynarec(int cycs); -extern int idivl(int32_t val); -#ifdef USE_NEW_DYNAREC -extern void loadcscall(uint16_t seg, uint32_t old_pc); -extern void loadcsjmp(uint16_t seg, uint32_t old_pc); -extern void pmodeint(int num, int soft); -extern void pmoderetf(int is32, uint16_t off); -extern void pmodeiret(int is32); -#else -extern void loadcscall(uint16_t seg); -extern void loadcsjmp(uint16_t seg, uint32_t old_pc); -extern void pmodeint(int num, int soft); -extern void pmoderetf(int is32, uint16_t off); -extern void pmodeiret(int is32); -#endif -extern void resetmcr(void); -extern void resetx86(void); -extern void refreshread(void); -extern void resetreadlookup(void); -extern void softresetx86(void); -extern void x86_int(int num); -extern void x86_int_sw(int num); -extern int x86_int_sw_rm(int num); -extern void x86gpf(char *s, uint16_t error); -extern void x86np(char *s, uint16_t error); -extern void x86ss(char *s, uint16_t error); -extern void x86ts(char *s, uint16_t error); - -#ifdef ENABLE_808X_LOG -extern void dumpregs(int __force); -extern void x87_dumpregs(void); -extern void x87_reset(void); -#endif - -extern int cpu_effective, cpu_alt_reset; -extern void cpu_dynamic_switch(int new_cpu); - -extern void cpu_ven_reset(void); - - -#endif /*EMU_CPU_H*/ +/* + * 86Box A hypervisor and IBM PC system emulator that specializes in + * running old operating systems and software designed for IBM + * PC systems and compatibles from 1981 through fairly recent + * system designs based on the PCI bus. + * + * This file is part of the 86Box distribution. + * + * CPU type handler. + * + * + * + * Authors: Sarah Walker, + * leilei, + * Miran Grca, + * + * Copyright 2008-2018 Sarah Walker. + * Copyright 2016-2018 leilei. + * Copyright 2016,2018 Miran Grca. + */ +#ifndef EMU_CPU_H +# define EMU_CPU_H +enum { + CPU_8088, /* 808x class CPUs */ + CPU_8086, +#ifdef USE_NEC_808X + CPU_V20, /* NEC 808x class CPUs - future proofing */ + CPU_V30, +#endif + CPU_286, /* 286 class CPUs */ + CPU_386SX, /* 386 class CPUs */ + CPU_386DX, + CPU_IBM386SLC, + CPU_IBM486SLC, + CPU_IBM486BL, + CPU_RAPIDCAD, + CPU_486SLC, + CPU_486DLC, + CPU_i486SX, /* 486 class CPUs */ + CPU_Am486SX, + CPU_Cx486S, + CPU_i486SX2, + CPU_Am486SX2, + CPU_i486DX, + CPU_i486DX2, + CPU_Am486DX, + CPU_Am486DX2, + CPU_Cx486DX, + CPU_Cx486DX2, + CPU_iDX4, + CPU_Am486DX4, + CPU_Cx486DX4, + CPU_Am5x86, + CPU_Cx5x86, + CPU_WINCHIP, /* 586 class CPUs */ +#ifdef USE_NEW_DYNAREC + CPU_WINCHIP2, +#endif + CPU_PENTIUM, + CPU_PENTIUMMMX, +#if (defined(USE_NEW_DYNAREC) || (defined(DEV_BRANCH) && defined(USE_CYRIX_6X86))) + CPU_Cx6x86, + CPU_Cx6x86MX, + CPU_Cx6x86L, + CPU_CxGX1, +#endif +#if (defined(USE_NEW_DYNAREC) || (defined(DEV_BRANCH) && defined(USE_AMD_K))) + CPU_K5, + CPU_5K86, + CPU_K6, +#endif +#ifdef USE_NEW_DYNAREC + CPU_K6_2, + CPU_K6_2C, + CPU_K6_3, + CPU_K6_2P, + CPU_K6_3P, +#endif + CPU_CYRIX3S, +#if defined(DEV_BRANCH) && defined(USE_I686) + CPU_PENTIUMPRO, /* 686 class CPUs */ + CPU_PENTIUM2, + CPU_PENTIUM2D, +#endif + CPU_MAX /* Only really needed to close the enum in a way independent of the #ifdef's. */ +}; + + +#define MANU_INTEL 0 +#define MANU_AMD 1 +#define MANU_CYRIX 2 +#define MANU_IDT 3 +#define MANU_NEC 4 + +#define CPU_SUPPORTS_DYNAREC 1 +#define CPU_REQUIRES_DYNAREC 2 +#define CPU_ALTERNATE_XTAL 4 + + +typedef struct { + const char *name; + int cpu_type; + int rspeed; + double multi; + uint32_t edx_reset; + uint32_t cpuid_model; + uint16_t cyrix_id; + uint8_t cpu_flags; + int8_t mem_read_cycles, mem_write_cycles; + int8_t cache_read_cycles, cache_write_cycles; + int8_t atclk_div; +} CPU; + + +extern CPU cpus_8088[]; +extern CPU cpus_8086[]; +extern CPU cpus_286[]; +extern CPU cpus_i386SX[]; +extern CPU cpus_i386DX[]; +extern CPU cpus_Am386SX[]; +extern CPU cpus_Am386DX[]; +extern CPU cpus_486SLC[]; +extern CPU cpus_486DLC[]; +extern CPU cpus_IBM386SLC[]; +extern CPU cpus_IBM486SLC[]; +extern CPU cpus_IBM486BL[]; +extern CPU cpus_i486S1[]; +extern CPU cpus_Am486S1[]; +extern CPU cpus_Cx486S1[]; +extern CPU cpus_i486[]; +extern CPU cpus_Am486[]; +extern CPU cpus_Cx486[]; +extern CPU cpus_WinChip[]; +#ifdef USE_NEW_DYNAREC +extern CPU cpus_WinChip_SS7[]; +#endif +extern CPU cpus_Pentium5V[]; +extern CPU cpus_Pentium5V50[]; +extern CPU cpus_PentiumS5[]; +extern CPU cpus_Pentium3V[]; +extern CPU cpus_Pentium[]; +#if (defined(USE_NEW_DYNAREC) || (defined(DEV_BRANCH) && defined(USE_AMD_K))) +extern CPU cpus_K5[]; +extern CPU cpus_K56[]; +#endif +#ifdef USE_NEW_DYNAREC +extern CPU cpus_K56_SS7[]; +#endif +#if (defined(USE_NEW_DYNAREC) || (defined(DEV_BRANCH) && defined(USE_CYRIX_6X86))) +extern CPU cpus_6x863V[]; +extern CPU cpus_6x86[]; +#endif +#ifdef USE_NEW_DYNAREC +extern CPU cpus_6x86SS7[]; +#endif +extern CPU cpus_Cyrix3[]; +#if defined(DEV_BRANCH) && defined(USE_I686) +extern CPU cpus_PentiumPro[]; +extern CPU cpus_PentiumII[]; +extern CPU cpus_Celeron[]; +#endif + + +#define C_FLAG 0x0001 +#define P_FLAG 0x0004 +#define A_FLAG 0x0010 +#define Z_FLAG 0x0040 +#define N_FLAG 0x0080 +#define T_FLAG 0x0100 +#define I_FLAG 0x0200 +#define D_FLAG 0x0400 +#define V_FLAG 0x0800 +#define NT_FLAG 0x4000 + +#define VM_FLAG 0x0002 /* in EFLAGS */ +#define VIF_FLAG 0x0008 /* in EFLAGS */ +#define VIP_FLAG 0x0010 /* in EFLAGS */ + +#define WP_FLAG 0x10000 /* in CR0 */ +#define CR4_VME (1 << 0) +#define CR4_PVI (1 << 1) +#define CR4_PSE (1 << 4) + +#define CPL ((cpu_state.seg_cs.access>>5)&3) + +#define IOPL ((cpu_state.flags>>12)&3) + +#define IOPLp ((!(msw&1)) || (CPL<=IOPL)) + + +typedef union { + uint32_t l; + uint16_t w; + struct { + uint8_t l, + h; + } b; +} x86reg; + +typedef struct { + uint32_t base; + uint32_t limit; + uint8_t access; + uint16_t seg; + uint32_t limit_low, + limit_high; + int checked; /*Non-zero if selector is known to be valid*/ +} x86seg; + +typedef union { + uint64_t q; + int64_t sq; + uint32_t l[2]; + int32_t sl[2]; + uint16_t w[4]; + int16_t sw[4]; + uint8_t b[8]; + int8_t sb[8]; + float f[2]; +} MMX_REG; + +typedef struct { + uint32_t tr1, tr12; + uint32_t cesr; + uint32_t fcr; + uint64_t fcr2, fcr3; +} msr_t; + +typedef union { + uint32_t l; + uint16_t w; +} cr0_t; + + +struct _cpustate_ { + x86reg regs[8]; + + uint8_t tag[8]; + + x86seg *ea_seg; + uint32_t eaaddr; + + int flags_op; + uint32_t flags_res; + uint32_t flags_op1, + flags_op2; + + uint32_t pc; + uint32_t oldpc; + uint32_t op32; + + int TOP; + + union { + struct { + int8_t rm, + mod, + reg; + } rm_mod_reg; + int32_t rm_mod_reg_data; + } rm_data; + + int8_t ssegs; + int8_t ismmx; + int8_t abrt; + + int _cycles; + int cpu_recomp_ins; + + uint16_t npxs, + npxc; + + double ST[8]; + + uint16_t MM_w4[8]; + + MMX_REG MM[8]; + + uint16_t old_npxc, + new_npxc; + uint32_t last_ea; + +#ifdef USE_NEW_DYNAREC + uint32_t old_fp_control, new_fp_control; +#if defined i386 || defined __i386 || defined __i386__ || defined _X86_ + uint16_t old_fp_control2, new_fp_control2; +#endif +#if defined i386 || defined __i386 || defined __i386__ || defined _X86_ || defined __amd64__ + uint32_t trunc_fp_control; +#endif +#endif + + x86seg seg_cs, + seg_ds, + seg_es, + seg_ss, + seg_fs, + seg_gs; + + uint16_t flags, eflags; +} cpu_state; + +/*The cpu_state.flags below must match in both cpu_cur_status and block->status for a block + to be valid*/ +#define CPU_STATUS_USE32 (1 << 0) +#define CPU_STATUS_STACK32 (1 << 1) +#define CPU_STATUS_PMODE (1 << 2) +#define CPU_STATUS_V86 (1 << 3) +#define CPU_STATUS_FLAGS 0xffff + +/*If the cpu_state.flags below are set in cpu_cur_status, they must be set in block->status. + Otherwise they are ignored*/ +#ifdef USE_NEW_DYNAREC +#define CPU_STATUS_NOTFLATDS (1 << 8) +#define CPU_STATUS_NOTFLATSS (1 << 9) +#define CPU_STATUS_MASK 0xff00 +#else +#define CPU_STATUS_NOTFLATDS (1 << 16) +#define CPU_STATUS_NOTFLATSS (1 << 17) +#define CPU_STATUS_MASK 0xffff0000 +#endif + +#ifdef __MSC__ +# define COMPILE_TIME_ASSERT(expr) /*nada*/ +#else +# ifdef EXTREME_DEBUG +# define COMPILE_TIME_ASSERT(expr) typedef char COMP_TIME_ASSERT[(expr) ? 1 : 0]; +# else +# define COMPILE_TIME_ASSERT(expr) /*nada*/ +# endif +#endif + +COMPILE_TIME_ASSERT(sizeof(cpu_state) <= 128) + +#define cpu_state_offset(MEMBER) ((uint8_t)((uintptr_t)&cpu_state.MEMBER - (uintptr_t)&cpu_state - 128)) + +#define EAX cpu_state.regs[0].l +#define AX cpu_state.regs[0].w +#define AL cpu_state.regs[0].b.l +#define AH cpu_state.regs[0].b.h +#define ECX cpu_state.regs[1].l +#define CX cpu_state.regs[1].w +#define CL cpu_state.regs[1].b.l +#define CH cpu_state.regs[1].b.h +#define EDX cpu_state.regs[2].l +#define DX cpu_state.regs[2].w +#define DL cpu_state.regs[2].b.l +#define DH cpu_state.regs[2].b.h +#define EBX cpu_state.regs[3].l +#define BX cpu_state.regs[3].w +#define BL cpu_state.regs[3].b.l +#define BH cpu_state.regs[3].b.h +#define ESP cpu_state.regs[4].l +#define EBP cpu_state.regs[5].l +#define ESI cpu_state.regs[6].l +#define EDI cpu_state.regs[7].l +#define SP cpu_state.regs[4].w +#define BP cpu_state.regs[5].w +#define SI cpu_state.regs[6].w +#define DI cpu_state.regs[7].w + +#define cycles cpu_state._cycles + +#define cpu_rm cpu_state.rm_data.rm_mod_reg.rm +#define cpu_mod cpu_state.rm_data.rm_mod_reg.mod +#define cpu_reg cpu_state.rm_data.rm_mod_reg.reg + +#define CR4_TSD (1 << 2) +#define CR4_DE (1 << 3) +#define CR4_MCE (1 << 6) +#define CR4_PCE (1 << 8) +#define CR4_OSFXSR (1 << 9) + + +/* Global variables. */ +extern int cpu_iscyrix; +extern int cpu_16bitbus; +extern int cpu_busspeed, cpu_pci_speed; +extern int cpu_multi; +extern double cpu_dmulti; +extern int cpu_cyrix_alignment; /*Cyrix 5x86/6x86 only has data misalignment + penalties when crossing 8-byte boundaries*/ + +extern int is8086, is286, is386, is486, is486sx, is486dx, is486sx2, is486dx2, isdx4; +extern int isibmcpu; +extern int is_rapidcad; +extern int hasfpu; +#define CPU_FEATURE_RDTSC (1 << 0) +#define CPU_FEATURE_MSR (1 << 1) +#define CPU_FEATURE_MMX (1 << 2) +#define CPU_FEATURE_CR4 (1 << 3) +#define CPU_FEATURE_VME (1 << 4) +#define CPU_FEATURE_CX8 (1 << 5) +#define CPU_FEATURE_3DNOW (1 << 6) + +extern uint32_t cpu_features; + +extern int in_smm, smi_line, smi_latched; +extern uint32_t smbase; + +#ifdef USE_NEW_DYNAREC +extern uint16_t cpu_cur_status; +#else +extern uint32_t cpu_cur_status; +#endif +extern uint64_t cpu_CR4_mask; +extern uint64_t tsc; +extern msr_t msr; +extern uint8_t opcode; +extern int insc; +extern int fpucount; +extern float mips,flops; +extern int clockrate; +extern int cgate16; +extern int cpl_override; +extern int CPUID; +extern uint64_t xt_cpu_multi; +extern int isa_cycles; +extern uint32_t oldds,oldss,olddslimit,oldsslimit,olddslimitw,oldsslimitw; +extern int ins,output; +extern uint32_t pccache; +extern uint8_t *pccache2; + +extern double bus_timing, pci_timing; +extern uint64_t pmc[2]; +extern uint16_t temp_seg_data[4]; +extern uint16_t cs_msr; +extern uint32_t esp_msr; +extern uint32_t eip_msr; + +/* For the AMD K6. */ +extern uint64_t star; + +#define FPU_CW_Reserved_Bits (0xe0c0) + +extern cr0_t CR0; +#define cr0 CR0.l +#define msw CR0.w +extern uint32_t cr2, cr3, cr4; +extern uint32_t dr[8]; + + +/*Segments - + _cs,_ds,_es,_ss are the segment structures + CS,DS,ES,SS is the 16-bit data + cs,ds,es,ss are defines to the bases*/ +extern x86seg gdt,ldt,idt,tr; +extern x86seg _oldds; +#define CS cpu_state.seg_cs.seg +#define DS cpu_state.seg_ds.seg +#define ES cpu_state.seg_es.seg +#define SS cpu_state.seg_ss.seg +#define FS cpu_state.seg_fs.seg +#define GS cpu_state.seg_gs.seg +#define cs cpu_state.seg_cs.base +#define ds cpu_state.seg_ds.base +#define es cpu_state.seg_es.base +#define ss cpu_state.seg_ss.base +#define fs_seg cpu_state.seg_fs.base +#define gs cpu_state.seg_gs.base + + +#define ISA_CYCLES(x) (x * isa_cycles) + +extern int cpu_cycles_read, cpu_cycles_read_l, cpu_cycles_write, cpu_cycles_write_l; +extern int cpu_prefetch_cycles, cpu_prefetch_width, cpu_mem_prefetch_cycles, cpu_rom_prefetch_cycles; +extern int cpu_waitstates; +extern int cpu_cache_int_enabled, cpu_cache_ext_enabled; +extern int cpu_pci_speed; + +extern int timing_rr; +extern int timing_mr, timing_mrl; +extern int timing_rm, timing_rml; +extern int timing_mm, timing_mml; +extern int timing_bt, timing_bnt; +extern int timing_int, timing_int_rm, timing_int_v86, timing_int_pm; +extern int timing_int_pm_outer, timing_iret_rm, timing_iret_v86, timing_iret_pm; +extern int timing_iret_pm_outer, timing_call_rm, timing_call_pm; +extern int timing_call_pm_gate, timing_call_pm_gate_inner; +extern int timing_retf_rm, timing_retf_pm, timing_retf_pm_outer; +extern int timing_jmp_rm, timing_jmp_pm, timing_jmp_pm_gate; +extern int timing_misaligned; + + +extern CPU cpus_pcjr[]; // FIXME: should be in machine file! +extern CPU cpus_europc[]; // FIXME: should be in machine file! +extern CPU cpus_pc1512[]; // FIXME: should be in machine file! +extern CPU cpus_ibmat[]; // FIXME: should be in machine file! +extern CPU cpus_ibmxt286[]; // FIXME: should be in machine file! +extern CPU cpus_ps1_m2011[]; // FIXME: should be in machine file! +extern CPU cpus_ps2_m30_286[]; // FIXME: should be in machine file! +#if 0 +extern CPU cpus_acer[]; // FIXME: should be in machine file! +#endif + + +/* Functions. */ +extern int cpu_has_feature(int feature); + +#ifdef USE_NEW_DYNAREC +extern void loadseg_dynarec(uint16_t seg, x86seg *s); +extern int loadseg(uint16_t seg, x86seg *s); +extern void loadcs(uint16_t seg); +#else +extern void loadseg(uint16_t seg, x86seg *s); +extern void loadcs(uint16_t seg); +#endif + +extern char *cpu_current_pc(char *bufp); + +extern void cpu_update_waitstates(void); +extern void cpu_set(void); + +extern void cpu_CPUID(void); +extern void cpu_RDMSR(void); +extern void cpu_WRMSR(void); + +extern int checkio(int port); +extern void codegen_block_end(void); +extern void codegen_reset(void); +extern void cpu_set_edx(void); +extern int divl(uint32_t val); +extern void execx86(int cycs); +extern void enter_smm(); +extern void leave_smm(); +extern void exec386(int cycs); +extern void exec386_dynarec(int cycs); +extern int idivl(int32_t val); +#ifdef USE_NEW_DYNAREC +extern void loadcscall(uint16_t seg, uint32_t old_pc); +extern void loadcsjmp(uint16_t seg, uint32_t old_pc); +extern void pmodeint(int num, int soft); +extern void pmoderetf(int is32, uint16_t off); +extern void pmodeiret(int is32); +#else +extern void loadcscall(uint16_t seg); +extern void loadcsjmp(uint16_t seg, uint32_t old_pc); +extern void pmodeint(int num, int soft); +extern void pmoderetf(int is32, uint16_t off); +extern void pmodeiret(int is32); +#endif +extern void resetmcr(void); +extern void resetx86(void); +extern void refreshread(void); +extern void resetreadlookup(void); +extern void softresetx86(void); +extern void x86_int(int num); +extern void x86_int_sw(int num); +extern int x86_int_sw_rm(int num); +extern void x86gpf(char *s, uint16_t error); +extern void x86np(char *s, uint16_t error); +extern void x86ss(char *s, uint16_t error); +extern void x86ts(char *s, uint16_t error); + +#ifdef ENABLE_808X_LOG +extern void dumpregs(int __force); +extern void x87_dumpregs(void); +extern void x87_reset(void); +#endif + +extern int cpu_effective, cpu_alt_reset; +extern void cpu_dynamic_switch(int new_cpu); + +extern void cpu_ven_reset(void); + + +#endif /*EMU_CPU_H*/ diff --git a/src/cpu_common/cpu_table.c b/src/cpu_common/cpu_table.c index 3903317dc..c1c73f4c4 100644 --- a/src/cpu_common/cpu_table.c +++ b/src/cpu_common/cpu_table.c @@ -1,743 +1,748 @@ -/* - * 86Box A hypervisor and IBM PC system emulator that specializes in - * running old operating systems and software designed for IBM - * PC systems and compatibles from 1981 through fairly recent - * system designs based on the PCI bus. - * - * This file is part of the 86Box distribution. - * - * Define all known processor types. - * - * Available cpuspeeds: - * - * 0 = 16 MHz - * 1 = 20 MHz - * 2 = 25 MHz - * 3 = 33 MHz - * 4 = 40 MHz - * 5 = 50 MHz - * 6 = 66 MHz - * 7 = 75 MHz - * 8 = 80 MHz - * 9 = 90 MHz - * 10 = 100 MHz - * 11 = 120 MHz - * 12 = 133 MHz - * 13 = 150 MHz - * 14 = 160 MHz - * 15 = 166 MHz - * 16 = 180 MHz - * 17 = 200 MHz - * - * - * - * Authors: Sarah Walker, - * leilei, - * Miran Grca, - * Fred N. van Kempen, - * - * Copyright 2008-2019 Sarah Walker. - * Copyright 2016-2019 leilei. - * Copyright 2016-2019 Miran Grca. - * Copyright 2017-2019 Fred N. van Kempen. - */ -#include -#include -#include -#include -#include "86box.h" -#include "cpu.h" -#include "machine.h" - - -CPU cpus_8088[] = { - /*8088 standard*/ - {"8088/4.77", CPU_8088, 4772728, 1, 0, 0, 0, 0, 0,0,0,0, 1}, - {"8088/7.16", CPU_8088, 7159092, 1, 0, 0, 0, 0, 0,0,0,0, 1}, - {"8088/8", CPU_8088, 8000000, 1, 0, 0, 0, 0, 0,0,0,0, 1}, - {"8088/10", CPU_8088, 10000000, 1, 0, 0, 0, 0, 0,0,0,0, 1}, - {"8088/12", CPU_8088, 12000000, 1, 0, 0, 0, 0, 0,0,0,0, 1}, - {"8088/16", CPU_8088, 16000000, 1, 0, 0, 0, 0, 0,0,0,0, 1}, - {"", -1, 0, 0, 0, 0, 0, 0, 0,0,0,0, 0} -}; - -CPU cpus_pcjr[] = { - /*8088 PCjr*/ - {"8088/4.77", CPU_8088, 4772728, 1, 0, 0, 0, 0, 0,0,0,0, 1}, - {"", -1, 0, 0, 0, 0, 0, 0, 0,0,0,0, 0} -}; - -CPU cpus_europc[] = { - /*8088 EuroPC*/ - {"8088/4.77", CPU_8088, 4772728, 1, 0, 0, 0, CPU_ALTERNATE_XTAL, 0,0,0,0, 1}, - {"8088/7.16", CPU_8088, 7159092, 1, 0, 0, 0, CPU_ALTERNATE_XTAL, 0,0,0,0, 1}, - {"8088/9.54", CPU_8088, 9545456, 1, 0, 0, 0, 0, 0,0,0,0, 1}, - {"", -1, 0, 0, 0, 0, 0, 0, 0,0,0,0, 0} -}; - -CPU cpus_8086[] = { - /*8086 standard*/ - {"8086/7.16", CPU_8086, 7159092, 1, 0, 0, 0, CPU_ALTERNATE_XTAL, 0,0,0,0, 1}, - {"8086/8", CPU_8086, 8000000, 1, 0, 0, 0, 0, 0,0,0,0, 1}, - {"8086/9.54", CPU_8086, 9545456, 1, 0, 0, 0, CPU_ALTERNATE_XTAL, 0,0,0,0, 1}, - {"8086/10", CPU_8086, 10000000, 1, 0, 0, 0, 0, 0,0,0,0, 1}, - {"8086/12", CPU_8086, 12000000, 1, 0, 0, 0, 0, 0,0,0,0, 1}, - {"8086/16", CPU_8086, 16000000, 1, 0, 0, 0, 0, 0,0,0,0, 2}, - {"", -1, 0, 0, 0, 0, 0, 0, 0,0,0,0, 0} -}; - -CPU cpus_pc1512[] = { - /*8086 Amstrad*/ - {"8086/8", CPU_8086, 8000000, 1, 0, 0, 0, 0, 0,0,0,0, 1}, - {"", -1, 0, 0, 0, 0, 0, 0, 0,0,0,0, 0} -}; - -CPU cpus_286[] = { - /*286*/ - {"286/6", CPU_286, 6000000, 1, 0, 0, 0, 0, 2,2,2,2, 1}, - {"286/8", CPU_286, 8000000, 1, 0, 0, 0, 0, 2,2,2,2, 1}, - {"286/10", CPU_286, 10000000, 1, 0, 0, 0, 0, 2,2,2,2, 1}, - {"286/12", CPU_286, 12500000, 1, 0, 0, 0, 0, 3,3,3,3, 2}, - {"286/16", CPU_286, 16000000, 1, 0, 0, 0, 0, 3,3,3,3, 2}, - {"286/20", CPU_286, 20000000, 1, 0, 0, 0, 0, 4,4,4,4, 3}, - {"286/25", CPU_286, 25000000, 1, 0, 0, 0, 0, 4,4,4,4, 3}, - {"", -1, 0, 0, 0, 0, 0, 0, 0,0,0,0, 0} -}; - -CPU cpus_ibmat[] = { - /*286*/ - {"286/6", CPU_286, 6000000, 1, 0, 0, 0, 0, 3,3,3,3, 1}, - {"286/8", CPU_286, 8000000, 1, 0, 0, 0, 0, 3,3,3,3, 1}, - {"", -1, 0, 0, 0, 0, 0, 0, 0,0,0,0, 0} -}; - -CPU cpus_ibmxt286[] = { - /*286*/ - {"286/6", CPU_286, 6000000, 1, 0, 0, 0, 0, 2,2,2,2, 1}, - {"", -1, 0, 0, 0, 0, 0, 0, 0,0,0,0, 0} -}; - -CPU cpus_ps1_m2011[] = { - /*286*/ - {"286/10", CPU_286, 10000000, 1, 0, 0, 0, 0, 2,2,2,2, 1}, - {"", -1, 0, 0, 0, 0, 0, 0, 0,0,0,0, 9} -}; - -CPU cpus_ps2_m30_286[] = { - /*286*/ - {"286/10", CPU_286, 10000000, 1, 0, 0, 0, 0, 2,2,2,2, 1}, - {"286/12", CPU_286, 12500000, 1, 0, 0, 0, 0, 3,3,3,3, 2}, - {"286/16", CPU_286, 16000000, 1, 0, 0, 0, 0, 3,3,3,3, 2}, - {"286/20", CPU_286, 20000000, 1, 0, 0, 0, 0, 4,4,4,4, 3}, - {"286/25", CPU_286, 25000000, 1, 0, 0, 0, 0, 4,4,4,4, 3}, - {"", -1, 0, 0, 0, 0, 0, 0, 0,0,0,0, 0} -}; - -CPU cpus_i386SX[] = { - /*i386SX*/ - {"i386SX/16", CPU_386SX, 16000000, 1, 0x2308, 0, 0, 0, 3,3,3,3, 2}, - {"i386SX/20", CPU_386SX, 20000000, 1, 0x2308, 0, 0, 0, 4,4,3,3, 3}, - {"i386SX/25", CPU_386SX, 25000000, 1, 0x2308, 0, 0, 0, 4,4,3,3, 3}, - {"i386SX/33", CPU_386SX, 33333333, 1, 0x2308, 0, 0, 0, 6,6,3,3, 4}, - {"i386SX/40", CPU_386SX, 40000000, 1, 0x2308, 0, 0, 0, 7,7,3,3, 5}, - {"", -1, 0, 0, 0, 0, 0, 0, 0,0,0,0, 0} -}; - -CPU cpus_i386DX[] = { - /*i386DX/RapidCAD*/ - {"i386DX/16", CPU_386DX, 16000000, 1, 0x0308, 0, 0, 0, 3,3,3,3, 2}, - {"i386DX/20", CPU_386DX, 20000000, 1, 0x0308, 0, 0, 0, 4,4,3,3, 3}, - {"i386DX/25", CPU_386DX, 25000000, 1, 0x0308, 0, 0, 0, 4,4,3,3, 3}, - {"i386DX/33", CPU_386DX, 33333333, 1, 0x0308, 0, 0, 0, 6,6,3,3, 4}, - {"i386DX/40", CPU_386DX, 40000000, 1, 0x0308, 0, 0, 0, 7,7,3,3, 5}, - {"RapidCAD/25", CPU_RAPIDCAD, 25000000, 1, 0x0430, 0, 0, CPU_SUPPORTS_DYNAREC, 4,4,3,3, 3}, - {"RapidCAD/33", CPU_RAPIDCAD, 33333333, 1, 0x0430, 0, 0, CPU_SUPPORTS_DYNAREC, 6,6,3,3, 4}, - {"RapidCAD/40", CPU_RAPIDCAD, 40000000, 1, 0x0430, 0, 0, CPU_SUPPORTS_DYNAREC, 7,7,3,3, 5}, - {"", -1, 0, 0, 0, 0, 0, 0, 0,0,0,0, 0} -}; - -CPU cpus_Am386SX[] = { - /*Am386SX*/ - {"Am386SX/16", CPU_386SX, 16000000, 1, 0x2308, 0, 0, 0, 3,3,3,3, 2}, - {"Am386SX/20", CPU_386SX, 20000000, 1, 0x2308, 0, 0, 0, 4,4,3,3, 3}, - {"Am386SX/25", CPU_386SX, 25000000, 1, 0x2308, 0, 0, 0, 4,4,3,3, 3}, - {"Am386SX/33", CPU_386SX, 33333333, 1, 0x2308, 0, 0, 0, 6,6,3,3, 4}, - {"Am386SX/40", CPU_386SX, 40000000, 1, 0x2308, 0, 0, 0, 7,7,3,3, 5}, - {"", -1, 0, 0, 0, 0, 0, 0, 0,0,0,0, 0} -}; - -CPU cpus_Am386DX[] = { - /*Am386DX*/ - {"Am386DX/25", CPU_386DX, 25000000, 1, 0x0308, 0, 0, 0, 4,4,3,3, 3}, - {"Am386DX/33", CPU_386DX, 33333333, 1, 0x0308, 0, 0, 0, 6,6,3,3, 4}, - {"Am386DX/40", CPU_386DX, 40000000, 1, 0x0308, 0, 0, 0, 7,7,3,3, 5}, - {"", -1, 0, 0, 0, 0, 0, 0, 0,0,0,0, 0} -}; - -CPU cpus_486SLC[] = { - /*Cx486SLC*/ - {"Cx486SLC/20", CPU_486SLC, 20000000, 1, 0x400, 0, 0x0000, 0, 4,4,3,3, 3}, - {"Cx486SLC/25", CPU_486SLC, 25000000, 1, 0x400, 0, 0x0000, 0, 4,4,3,3, 3}, - {"Cx486SLC/33", CPU_486SLC, 33333333, 1, 0x400, 0, 0x0000, 0, 6,6,3,3, 4}, - {"Cx486SRx2/32", CPU_486SLC, 32000000, 2, 0x406, 0, 0x0006, 0, 6,6,6,6, 4}, - {"Cx486SRx2/40", CPU_486SLC, 40000000, 2, 0x406, 0, 0x0006, 0, 8,8,6,6, 6}, - {"Cx486SRx2/50", CPU_486SLC, 50000000, 2, 0x406, 0, 0x0006, 0, 8,8,6,6, 6}, - {"", -1, 0, 0, 0, 0, 0, 0, 0,0,0,0, 0} -}; - -CPU cpus_IBM386SLC[] = { - /*IBM 386SLC*/ - {"386SLC/16", CPU_IBM386SLC, 16000000, 1, 0x300, 0, 0, 0, 3,3,3,3, 2}, - {"386SLC/20", CPU_IBM386SLC, 20000000, 1, 0x300, 0, 0, 0, 4,4,3,3, 3}, - {"386SLC/25", CPU_IBM386SLC, 25000000, 1, 0x300, 0, 0, 0, 4,4,3,3, 3}, - {"", -1, 0, 0, 0, 0, 0, 0, 0,0,0,0, 0} -}; - -CPU cpus_IBM486SLC[] = { - /*IBM 486SLC*/ - {"486SLC/33", CPU_IBM486SLC, 33333333, 1, 0x400, 0, 0, 0, 6,6,3,3, 4}, - {"486SLC2/40", CPU_IBM486SLC, 40000000, 2, 0x400, 0, 0, 0, 7,7,6,6, 5}, - {"486SLC2/50", CPU_IBM486SLC, 50000000, 2, 0x400, 0, 0, 0, 8,8,6,6, 6}, - {"486SLC2/66", CPU_IBM486SLC, 66666666, 2, 0x400, 0, 0, 0, 12,12,6,6, 8}, - {"486SLC3/60", CPU_IBM486SLC, 60000000, 3, 0x400, 0, 0, 0, 12,12,9,9, 7}, - {"486SLC3/75", CPU_IBM486SLC, 75000000, 3, 0x400, 0, 0, 0, 12,12,9,9, 9}, - {"486SLC3/100", CPU_IBM486SLC, 100000000, 3, 0x400, 0, 0, 0, 18,18,9,9, 12}, - {"", -1, 0, 0, 0, 0, 0, 0, 0,0,0,0, 0} -}; - -CPU cpus_IBM486BL[] = { - /*IBM Blue Lightning*/ - {"486BL2/50", CPU_IBM486BL, 50000000, 2, 0x400, 0, 0, 0, 8,8,6,6, 6}, - {"486BL2/66", CPU_IBM486BL, 66666666, 2, 0x400, 0, 0, 0, 12,12,6,6, 8}, - {"486BL3/75", CPU_IBM486BL, 75000000, 3, 0x400, 0, 0, 0, 12,12,9,9, 9}, - {"486BL3/100", CPU_IBM486BL, 100000000, 3, 0x400, 0, 0, 0, 18,18,9,9, 12}, - {"", -1, 0, 0, 0, 0, 0, 0, 0,0,0,0, 0} -}; - -CPU cpus_486DLC[] = { - /*Cx486DLC*/ - {"Cx486DLC/25", CPU_486DLC, 25000000, 1, 0x401, 0, 0x0001, 0, 4, 4,3,3, 3}, - {"Cx486DLC/33", CPU_486DLC, 33333333, 1, 0x401, 0, 0x0001, 0, 6, 6,3,3, 4}, - {"Cx486DLC/40", CPU_486DLC, 40000000, 1, 0x401, 0, 0x0001, 0, 7, 7,3,3, 5}, - {"Cx486DRx2/32", CPU_486DLC, 32000000, 2, 0x407, 0, 0x0007, 0, 6, 6,6,6, 4}, - {"Cx486DRx2/40", CPU_486DLC, 40000000, 2, 0x407, 0, 0x0007, 0, 8, 8,6,6, 6}, - {"Cx486DRx2/50", CPU_486DLC, 50000000, 2, 0x407, 0, 0x0007, 0, 8, 8,6,6, 6}, - {"Cx486DRx2/66", CPU_486DLC, 66666666, 2, 0x407, 0, 0x0007, 0, 12,12,6,6, 8}, - {"", -1, 0, 0, 0, 0, 0, 0, 0, 0,0,0, 0} -}; - -CPU cpus_i486S1[] = { - /*i486*/ - {"i486SX/16", CPU_i486SX, 16000000, 1, 0x420, 0, 0, CPU_SUPPORTS_DYNAREC, 3, 3,3,3, 2}, - {"i486SX/20", CPU_i486SX, 20000000, 1, 0x420, 0, 0, CPU_SUPPORTS_DYNAREC, 4, 4,3,3, 3}, - {"i486SX/25", CPU_i486SX, 25000000, 1, 0x422, 0, 0, CPU_SUPPORTS_DYNAREC, 4, 4,3,3, 3}, - {"i486SX/33", CPU_i486SX, 33333333, 1, 0x42a, 0, 0, CPU_SUPPORTS_DYNAREC, 6, 6,3,3, 4}, - {"i486SX2/50", CPU_i486SX, 50000000, 2, 0x45b, 0, 0, CPU_SUPPORTS_DYNAREC, 8, 8,6,6, 6}, - {"i486SX2/66 (Q0569)", CPU_i486SX, 66666666, 2, 0x45b, 0, 0, CPU_SUPPORTS_DYNAREC, 8, 8,6,6, 8}, - {"i486DX/25", CPU_i486DX, 25000000, 1, 0x404, 0, 0, CPU_SUPPORTS_DYNAREC, 4, 4,3,3, 3}, - {"i486DX/33", CPU_i486DX, 33333333, 1, 0x414, 0, 0, CPU_SUPPORTS_DYNAREC, 6, 6,3,3, 4}, - {"i486DX/50", CPU_i486DX, 50000000, 1, 0x411, 0, 0, CPU_SUPPORTS_DYNAREC, 8, 8,4,4, 6}, - {"i486DX2/40", CPU_i486DX, 40000000, 2, 0x430, 0x430, 0, CPU_SUPPORTS_DYNAREC, 7, 7,6,6, 5}, - {"i486DX2/50", CPU_i486DX, 50000000, 2, 0x433, 0x433, 0, CPU_SUPPORTS_DYNAREC, 8, 8,6,6, 6}, - {"i486DX2/66", CPU_i486DX, 66666666, 2, 0x435, 0x435, 0, CPU_SUPPORTS_DYNAREC, 12,12,6,6, 8}, - {"iDX4 OverDrive 75", CPU_iDX4, 75000000, 3, 0x1480, 0x1480, 0, CPU_SUPPORTS_DYNAREC, 12,12,9,9, 9}, /*Only added the DX4 OverDrive as the others would be redundant*/ - {"iDX4 OverDrive 100", CPU_iDX4, 100000000, 3, 0x1480, 0x1480, 0, CPU_SUPPORTS_DYNAREC, 18,18,9,9, 12}, - {"", -1, 0, 0, 0, 0, 0, 0, 0, 0,0,0, 0} -}; -CPU cpus_Am486S1[] = { - /*Am486*/ - {"Am486SX/33", CPU_Am486SX, 33333333, 1, 0x42a, 0, 0, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 4}, - {"Am486SX/40", CPU_Am486SX, 40000000, 1, 0x42a, 0, 0, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5}, - {"Am486SX2/50", CPU_Am486SX2, 50000000, 2, 0x45b, 0x45b, 0, CPU_SUPPORTS_DYNAREC, 8, 8, 6, 6, 6}, /*CPUID available on SX2, DX2, DX4, 5x86, >= 50 MHz*/ - {"Am486SX2/66", CPU_Am486SX2, 66666666, 2, 0x45b, 0x45b, 0, CPU_SUPPORTS_DYNAREC, 12,12, 6, 6, 8}, /*Isn't on all real AMD SX2s and DX2s, availability here is pretty arbitary (and distinguishes them from the Intel chips)*/ - {"Am486DX/33", CPU_Am486DX, 33333333, 1, 0x430, 0, 0, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 4}, - {"Am486DX/40", CPU_Am486DX, 40000000, 1, 0x430, 0, 0, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5}, - {"Am486DX2/50", CPU_Am486DX2, 50000000, 2, 0x470, 0x470, 0, CPU_SUPPORTS_DYNAREC, 8, 8, 6, 6, 6}, - {"Am486DX2/66", CPU_Am486DX2, 66666666, 2, 0x470, 0x470, 0, CPU_SUPPORTS_DYNAREC, 12,12, 6, 6, 8}, - {"Am486DX2/80", CPU_Am486DX2, 80000000, 2, 0x470, 0x470, 0, CPU_SUPPORTS_DYNAREC, 14,14, 6, 6, 10}, - {"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} -}; -CPU cpus_Cx486S1[] = { - /*Cyrix 486*/ - {"Cx486S/25", CPU_Cx486S, 25000000, 1, 0x420, 0, 0x0010, CPU_SUPPORTS_DYNAREC, 4, 4, 3, 3, 3}, - {"Cx486S/33", CPU_Cx486S, 33333333, 1, 0x420, 0, 0x0010, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 4}, - {"Cx486S/40", CPU_Cx486S, 40000000, 1, 0x420, 0, 0x0010, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5}, - {"Cx486DX/33", CPU_Cx486DX, 33333333, 1, 0x430, 0, 0x051a, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 4}, - {"Cx486DX/40", CPU_Cx486DX, 40000000, 1, 0x430, 0, 0x051a, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5}, - {"Cx486DX2/50", CPU_Cx486DX2, 50000000, 2, 0x430, 0, 0x081b, CPU_SUPPORTS_DYNAREC, 8, 8, 6, 6, 6}, - {"Cx486DX2/66", CPU_Cx486DX2, 66666666, 2, 0x430, 0, 0x0b1b, CPU_SUPPORTS_DYNAREC, 12,12, 6, 6, 8}, - {"Cx486DX2/80", CPU_Cx486DX2, 80000000, 2, 0x430, 0, 0x311b, CPU_SUPPORTS_DYNAREC, 14,14, 6, 6, 10}, - {"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} -}; - -CPU cpus_i486[] = { - /*i486/P24T*/ - {"i486SX/16", CPU_i486SX, 16000000, 1, 0x420, 0, 0, CPU_SUPPORTS_DYNAREC, 3, 3,3,3, 2}, - {"i486SX/20", CPU_i486SX, 20000000, 1, 0x420, 0, 0, CPU_SUPPORTS_DYNAREC, 4, 4,3,3, 3}, - {"i486SX/25", CPU_i486SX, 25000000, 1, 0x422, 0, 0, CPU_SUPPORTS_DYNAREC, 4, 4,3,3, 3}, - {"i486SX/33", CPU_i486SX, 33333333, 1, 0x42a, 0, 0, CPU_SUPPORTS_DYNAREC, 6, 6,3,3, 4}, - {"i486SX2/50", CPU_i486SX, 50000000, 2, 0x45b, 0, 0, CPU_SUPPORTS_DYNAREC, 8, 8,6,6, 6}, - {"i486SX2/66 (Q0569)", CPU_i486SX, 66666666, 2, 0x45b, 0, 0, CPU_SUPPORTS_DYNAREC, 8, 8,6,6, 8}, - {"i486DX/25", CPU_i486DX, 25000000, 1, 0x404, 0, 0, CPU_SUPPORTS_DYNAREC, 4, 4,3,3, 3}, - {"i486DX/33", CPU_i486DX, 33333333, 1, 0x414, 0, 0, CPU_SUPPORTS_DYNAREC, 6, 6,3,3, 4}, - {"i486DX/50", CPU_i486DX, 50000000, 1, 0x411, 0, 0, CPU_SUPPORTS_DYNAREC, 8, 8,4,4, 6}, - {"i486DX2/40", CPU_i486DX, 40000000, 2, 0x430, 0x430, 0, CPU_SUPPORTS_DYNAREC, 7, 7,6,6, 5}, - {"i486DX2/50", CPU_i486DX, 50000000, 2, 0x433, 0x433, 0, CPU_SUPPORTS_DYNAREC, 8, 8,6,6, 6}, - {"i486DX2/66", CPU_i486DX, 66666666, 2, 0x435, 0x435, 0, CPU_SUPPORTS_DYNAREC, 12,12,6,6, 8}, - {"iDX4/75", CPU_iDX4, 75000000, 3, 0x480, 0x480, 0, CPU_SUPPORTS_DYNAREC, 12,12,9,9, 9}, /*CPUID available on DX4, >= 75 MHz*/ - {"iDX4/100", CPU_iDX4, 100000000, 3, 0x483, 0x483, 0, CPU_SUPPORTS_DYNAREC, 18,18,9,9, 12}, /*Is on some real Intel DX2s, limit here is pretty arbitary*/ - {"iDX4 OverDrive 75", CPU_iDX4, 75000000, 3, 0x1480, 0x1480, 0, CPU_SUPPORTS_DYNAREC, 12,12,9,9, 9}, - {"iDX4 OverDrive 100", CPU_iDX4, 100000000, 3, 0x1480, 0x1480, 0, CPU_SUPPORTS_DYNAREC, 18,18,9,9, 12}, - {"Pentium OverDrive 63", CPU_PENTIUM, 62500000, 5/2, 0x1531, 0x1531, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10,7,7, 15/2}, - {"Pentium OverDrive 83", CPU_PENTIUM, 83333333, 5/2, 0x1532, 0x1532, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,8,8, 10}, - {"", -1, 0, 0, 0, 0, 0, 0, 0, 0,0,0, 0} -}; - -CPU cpus_Am486[] = { - /*Am486/5x86*/ - {"Am486SX/33", CPU_Am486SX, 33333333, 1, 0x42a, 0, 0, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 4}, - {"Am486SX/40", CPU_Am486SX, 40000000, 1, 0x42a, 0, 0, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5}, - {"Am486SX2/50", CPU_Am486SX2, 50000000, 2, 0x45b, 0x45b, 0, CPU_SUPPORTS_DYNAREC, 8, 8, 6, 6, 6}, /*CPUID available on SX2, DX2, DX4, 5x86, >= 50 MHz*/ - {"Am486SX2/66", CPU_Am486SX2, 66666666, 2, 0x45b, 0x45b, 0, CPU_SUPPORTS_DYNAREC, 12,12, 6, 6, 8}, - {"Am486DX/33", CPU_Am486DX, 33333333, 1, 0x430, 0, 0, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 4}, - {"Am486DX/40", CPU_Am486DX, 40000000, 1, 0x430, 0, 0, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5}, - {"Am486DX2/50", CPU_Am486DX2, 50000000, 2, 0x470, 0x470, 0, CPU_SUPPORTS_DYNAREC, 8, 8, 6, 6, 6}, - {"Am486DX2/66", CPU_Am486DX2, 66666666, 2, 0x470, 0x470, 0, CPU_SUPPORTS_DYNAREC, 12,12, 6, 6, 8}, - {"Am486DX2/80", CPU_Am486DX2, 80000000, 2, 0x470, 0x470, 0, CPU_SUPPORTS_DYNAREC, 14,14, 6, 6, 10}, - {"Am486DX4/75", CPU_Am486DX4, 75000000, 3, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC, 12,12, 9, 9, 9}, - {"Am486DX4/90", CPU_Am486DX4, 90000000, 3, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC, 15,15, 9, 9, 12}, - {"Am486DX4/100", CPU_Am486DX4, 100000000, 3, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC, 15,15, 9, 9, 12}, - {"Am486DX4/120", CPU_Am486DX4, 120000000, 3, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC, 21,21, 9, 9, 15}, - {"Am5x86/P75", CPU_Am5x86, 133333333, 4, 0x4e0, 0x4e0, 0, CPU_SUPPORTS_DYNAREC, 24,24,12,12, 16}, - {"Am5x86/P75+", CPU_Am5x86, 150000000, 3, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC, 28,28,12,12, 20},/*The rare P75+ was indeed a triple-clocked 150 MHz according to research*/ - {"Am5x86/P90", CPU_Am5x86, 160000000, 4, 0x4e0, 0x4e0, 0, CPU_SUPPORTS_DYNAREC, 28,28,12,12, 20},/*160 MHz on a 40 MHz bus was a common overclock and "5x86/P90" was used by a number of BIOSes to refer to that configuration*/ - {"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} -}; - -CPU cpus_Cx486[] = { - /*Cyrix 486*/ - {"Cx486S/25", CPU_Cx486S, 25000000, 1, 0x420, 0, 0x0010, CPU_SUPPORTS_DYNAREC, 4, 4, 3, 3, 3}, - {"Cx486S/33", CPU_Cx486S, 33333333, 1, 0x420, 0, 0x0010, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 4}, - {"Cx486S/40", CPU_Cx486S, 40000000, 1, 0x420, 0, 0x0010, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5}, - {"Cx486DX/33", CPU_Cx486DX, 33333333, 1, 0x430, 0, 0x051a, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 4}, - {"Cx486DX/40", CPU_Cx486DX, 40000000, 1, 0x430, 0, 0x051a, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5}, - {"Cx486DX2/50", CPU_Cx486DX2, 50000000, 2, 0x430, 0, 0x081b, CPU_SUPPORTS_DYNAREC, 8, 8, 6, 6, 6}, - {"Cx486DX2/66", CPU_Cx486DX2, 66666666, 2, 0x430, 0, 0x0b1b, CPU_SUPPORTS_DYNAREC, 12,12, 6, 6, 8}, - {"Cx486DX2/80", CPU_Cx486DX2, 80000000, 2, 0x430, 0, 0x311b, CPU_SUPPORTS_DYNAREC, 14,14, 6, 6, 10}, - {"Cx486DX4/75", CPU_Cx486DX4, 75000000, 3, 0x480, 0, 0x361f, CPU_SUPPORTS_DYNAREC, 12,12, 9, 9, 9}, - {"Cx486DX4/100", CPU_Cx486DX4, 100000000, 3, 0x480, 0, 0x361f, CPU_SUPPORTS_DYNAREC, 15,15, 9, 9, 12}, - - /*Cyrix 5x86*/ - {"Cx5x86/80", CPU_Cx5x86, 80000000, 2, 0x480, 0, 0x002f, CPU_SUPPORTS_DYNAREC, 14,14, 6, 6, 10}, /*If we're including the Pentium 50, might as well include this*/ - {"Cx5x86/100", CPU_Cx5x86, 100000000, 3, 0x480, 0, 0x002f, CPU_SUPPORTS_DYNAREC, 15,15, 9, 9, 12}, - {"Cx5x86/120", CPU_Cx5x86, 120000000, 3, 0x480, 0, 0x002f, CPU_SUPPORTS_DYNAREC, 21,21, 9, 9, 15}, - {"Cx5x86/133", CPU_Cx5x86, 133333333, 4, 0x480, 0, 0x002f, CPU_SUPPORTS_DYNAREC, 24,24,12,12, 16}, - {"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} -}; - -#if defined(USE_NEW_DYNAREC) || (defined(DEV_BRANCH) && defined(USE_CYRIX_6X86)) -CPU cpus_6x863V[] = { - /*Cyrix 6x86*/ - {"Cx6x86/P90", CPU_Cx6x86, 80000000, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 8, 8, 6, 6, 10}, - {"Cx6x86/PR120+", CPU_Cx6x86, 100000000, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 12}, - {"Cx6x86/PR133+", CPU_Cx6x86, 110000000, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 14}, - {"Cx6x86/PR150+", CPU_Cx6x86, 120000000, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 14}, - {"Cx6x86/PR166+", CPU_Cx6x86, 133333333, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16}, - {"Cx6x86/PR200+", CPU_Cx6x86, 150000000, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 18}, - {"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} -}; - -CPU cpus_6x86[] = { - /*Cyrix 6x86*/ - {"Cx6x86/P90", CPU_Cx6x86, 80000000, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 8, 8, 6, 6, 10}, - {"Cx6x86/PR120+", CPU_Cx6x86, 100000000, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 12}, - {"Cx6x86/PR133+", CPU_Cx6x86, 110000000, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 14}, - {"Cx6x86/PR150+", CPU_Cx6x86, 120000000, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 14}, - {"Cx6x86/PR166+", CPU_Cx6x86, 133333333, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16}, - {"Cx6x86/PR200+", CPU_Cx6x86, 150000000, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 18}, - - /*Cyrix 6x86L*/ - {"Cx6x86L/PR133+", CPU_Cx6x86L, 110000000, 2, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 14}, - {"Cx6x86L/PR150+", CPU_Cx6x86L, 120000000, 2, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 14}, - {"Cx6x86L/PR166+", CPU_Cx6x86L, 133333333, 2, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16}, - {"Cx6x86L/PR200+", CPU_Cx6x86L, 150000000, 2, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 18}, - - /*Cyrix 6x86MX/MII*/ - {"Cx6x86MX/PR166", CPU_Cx6x86MX, 133333333, 2, 0x600, 0x600, 0x0451, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16}, - {"Cx6x86MX/PR200", CPU_Cx6x86MX, 166666666, 5/2, 0x600, 0x600, 0x0452, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20}, - {"Cx6x86MX/PR233", CPU_Cx6x86MX, 187500000, 5/2, 0x600, 0x600, 0x0452, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 45/2}, - {"Cx6x86MX/PR266", CPU_Cx6x86MX, 208333333, 5/2, 0x600, 0x600, 0x0452, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 17,17, 7, 7, 25}, - {"MII/PR300", CPU_Cx6x86MX, 233333333, 7/2, 0x601, 0x601, 0x0852, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,11,11, 28}, - {"MII/PR333", CPU_Cx6x86MX, 250000000, 3, 0x601, 0x601, 0x0853, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 23,23, 9, 9, 30}, - {"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} - }; -#endif - -#ifdef USE_NEW_DYNAREC - CPU cpus_6x86SS7[] = { - /*Cyrix 6x86*/ - {"Cx6x86/P90", CPU_Cx6x86, 80000000, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 8, 8, 6, 6, 10}, - {"Cx6x86/PR120+", CPU_Cx6x86, 100000000, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 12}, - {"Cx6x86/PR133+", CPU_Cx6x86, 110000000, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 14}, - {"Cx6x86/PR150+", CPU_Cx6x86, 120000000, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 14}, - {"Cx6x86/PR166+", CPU_Cx6x86, 133333333, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16}, - {"Cx6x86/PR200+", CPU_Cx6x86, 150000000, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 18}, - - /*Cyrix 6x86L*/ - {"Cx6x86L/PR133+", CPU_Cx6x86L, 110000000, 2, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 14}, - {"Cx6x86L/PR150+", CPU_Cx6x86L, 120000000, 2, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 14}, - {"Cx6x86L/PR166+", CPU_Cx6x86L, 133333333, 2, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16}, - {"Cx6x86L/PR200+", CPU_Cx6x86L, 150000000, 2, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 18}, - - /*Cyrix 6x86MX/MII*/ - {"Cx6x86MX/PR166", CPU_Cx6x86MX, 133333333, 2, 0x600, 0x600, 0x0451, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16}, - {"Cx6x86MX/PR200", CPU_Cx6x86MX, 166666666, 5/2, 0x600, 0x600, 0x0452, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20}, - {"Cx6x86MX/PR233", CPU_Cx6x86MX, 187500000, 5/2, 0x600, 0x600, 0x0452, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 45/2}, - {"Cx6x86MX/PR266", CPU_Cx6x86MX, 208333333, 5/2, 0x600, 0x600, 0x0452, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 17,17, 7, 7, 25}, - {"MII/PR300", CPU_Cx6x86MX, 233333333, 7/2, 0x601, 0x601, 0x0852, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,11,11, 28}, - {"MII/PR333", CPU_Cx6x86MX, 250000000, 3, 0x601, 0x601, 0x0853, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 23,23, 9, 9, 30}, - {"MII/PR366", CPU_Cx6x86MX, 250000000, 5/2, 0x601, 0x601, 0x0853, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 23,23, 7, 7, 30}, - {"MII/PR400", CPU_Cx6x86MX, 285000000, 3, 0x601, 0x601, 0x0853, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27, 9, 9, 34}, - {"MII/PR433", CPU_Cx6x86MX, 300000000, 3, 0x601, 0x601, 0x0853, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27, 9, 9, 36}, - {"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} - }; -#endif - -CPU cpus_WinChip[] = { - /*IDT WinChip*/ - {"WinChip 75", CPU_WINCHIP, 75000000, 3/2, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 8, 8, 4, 4, 9}, - {"WinChip 90", CPU_WINCHIP, 90000000, 3/2, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 9, 9, 4, 4, 21/2}, - {"WinChip 100", CPU_WINCHIP, 100000000, 3/2, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 9, 9, 4, 4, 12}, - {"WinChip 120", CPU_WINCHIP, 120000000, 2, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 12, 12, 6, 6, 14}, - {"WinChip 133", CPU_WINCHIP, 133333333, 2, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 12, 12, 6, 6, 16}, - {"WinChip 150", CPU_WINCHIP, 150000000, 5/2, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 15, 15, 7, 7, 35/2}, - {"WinChip 166", CPU_WINCHIP, 166666666, 5/2, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 15, 15, 7, 7, 40}, - {"WinChip 180", CPU_WINCHIP, 180000000, 3, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 21}, - {"WinChip 200", CPU_WINCHIP, 200000000, 3, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 24}, - {"WinChip 225", CPU_WINCHIP, 225000000, 3, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 27}, - {"WinChip 240", CPU_WINCHIP, 240000000, 4, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 24, 24, 12, 12, 28}, -#ifdef USE_NEW_DYNAREC - {"WinChip 2/200", CPU_WINCHIP2, 200000000, 3, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 24}, - {"WinChip 2/225", CPU_WINCHIP2, 225000000, 3, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 27}, - {"WinChip 2/240", CPU_WINCHIP2, 240000000, 4, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 24, 24, 12, 12, 30}, - {"WinChip 2/250", CPU_WINCHIP2, 250000000, 3, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 24, 24, 12, 12, 30}, - {"WinChip 2A/200", CPU_WINCHIP2, 200000000, 3, 0x587, 0x587, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 24}, - {"WinChip 2A/233", CPU_WINCHIP2, 233333333, 7/2, 0x587, 0x587, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, (7*8)/2}, -#endif - {"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} -}; - -#ifdef USE_NEW_DYNAREC -CPU cpus_WinChip_SS7[] = { - /*IDT WinChip*/ - {"WinChip 75", CPU_WINCHIP, 75000000, 3/2, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 8, 8, 4, 4, 9}, - {"WinChip 90", CPU_WINCHIP, 90000000, 3/2, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 9, 9, 4, 4, 21/2}, - {"WinChip 100", CPU_WINCHIP, 100000000, 3/2, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 9, 9, 4, 4, 12}, - {"WinChip 120", CPU_WINCHIP, 120000000, 2, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 12, 12, 6, 6, 14}, - {"WinChip 133", CPU_WINCHIP, 133333333, 2, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 12, 12, 6, 6, 16}, - {"WinChip 150", CPU_WINCHIP, 150000000, 5/2, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 15, 15, 7, 7, 35/2}, - {"WinChip 166", CPU_WINCHIP, 166666666, 5/2, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 15, 15, 7, 7, 40}, - {"WinChip 180", CPU_WINCHIP, 180000000, 3, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 21}, - {"WinChip 200", CPU_WINCHIP, 200000000, 3, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 24}, - {"WinChip 225", CPU_WINCHIP, 225000000, 3, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 27}, - {"WinChip 240", CPU_WINCHIP, 240000000, 4, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 24, 24, 12, 12, 28}, - {"WinChip 2/200", CPU_WINCHIP2, 200000000, 3, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 3*8}, - {"WinChip 2/225", CPU_WINCHIP2, 225000000, 3, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 3*9}, - {"WinChip 2/240", CPU_WINCHIP2, 240000000, 4, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 24, 24, 12, 12, 30}, - {"WinChip 2/250", CPU_WINCHIP2, 250000000, 3, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 24, 24, 12, 12, 30}, - {"WinChip 2A/200", CPU_WINCHIP2, 200000000, 3, 0x587, 0x587, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 3*8}, - {"WinChip 2A/233", CPU_WINCHIP2, 233333333, 7/2, 0x587, 0x587, 0, CPU_SUPPORTS_DYNAREC, 21, 21, 9, 9, (7*8)/2}, - {"WinChip 2A/266", CPU_WINCHIP2, 233333333, 7/3, 0x587, 0x587, 0, CPU_SUPPORTS_DYNAREC, 21, 21, 7, 7, 28}, - {"WinChip 2A/300", CPU_WINCHIP2, 250000000, 5/2, 0x587, 0x587, 0, CPU_SUPPORTS_DYNAREC, 24, 24, 8, 8, 30}, - {"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} -}; -#endif - -CPU cpus_Pentium5V[] = { - /*Intel Pentium (5V, socket 4)*/ - {"Pentium 60", CPU_PENTIUM, 60000000, 1, 0x517, 0x517, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6,3,3, 7}, - {"Pentium 66", CPU_PENTIUM, 66666666, 1, 0x517, 0x517, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6,3,3, 8}, - {"Pentium OverDrive 120", CPU_PENTIUM, 120000000, 2, 0x51A, 0x51A, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6, 14}, - {"Pentium OverDrive 133", CPU_PENTIUM, 133333333, 2, 0x51A, 0x51A, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6, 16}, - {"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} -}; - -CPU cpus_Pentium5V50[] = { - /*Intel Pentium (5V, socket 4, including 50 MHz FSB)*/ - {"Pentium 50 (Q0399)", CPU_PENTIUM, 50000000, 1, 0x513, 0x513, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 4, 4,3,3, 6}, - {"Pentium 60", CPU_PENTIUM, 60000000, 1, 0x517, 0x517, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6,3,3, 7}, - {"Pentium 66", CPU_PENTIUM, 66666666, 1, 0x517, 0x517, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6,3,3, 8}, - {"Pentium OverDrive 100", CPU_PENTIUM, 100000000, 2, 0x51A, 0x51A, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 8, 8,6,6, 12}, - {"Pentium OverDrive 120", CPU_PENTIUM, 120000000, 2, 0x51A, 0x51A, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6, 14}, - {"Pentium OverDrive 133", CPU_PENTIUM, 133333333, 2, 0x51A, 0x51A, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6, 16}, - {"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} -}; - -CPU cpus_PentiumS5[] = { - /*Intel Pentium (Socket 5)*/ - {"Pentium 75", CPU_PENTIUM, 75000000, 3/2, 0x522, 0x522, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7,4,4, 9}, - {"Pentium OverDrive MMX 75", CPU_PENTIUMMMX, 75000000, 3/2, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7,4,4, 9}, - {"Pentium 90", CPU_PENTIUM, 90000000, 3/2, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9,4,4, 21/2}, - {"Pentium 100/50", CPU_PENTIUM, 100000000, 2, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10,6,6, 12}, - {"Pentium 100/66", CPU_PENTIUM, 100000000, 3/2, 0x526, 0x526, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9,4,4, 12}, - {"Pentium 120", CPU_PENTIUM, 120000000, 2, 0x526, 0x526, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6, 14}, - - /*Intel Pentium OverDrive*/ - {"Pentium OverDrive 125", CPU_PENTIUM, 125000000, 3, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,7,7, 16}, - {"Pentium OverDrive 150", CPU_PENTIUM, 150000000, 5/2, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7, 35/2}, - {"Pentium OverDrive 166", CPU_PENTIUM, 166666666, 5/2, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7, 40}, - {"Pentium OverDrive MMX 125", CPU_PENTIUMMMX, 125000000, 5/2, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,7,7, 15}, - {"Pentium OverDrive MMX 150/60", CPU_PENTIUMMMX, 150000000, 5/2, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7, 35/2}, - {"Pentium OverDrive MMX 166", CPU_PENTIUMMMX, 166000000, 5/2, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7, 20}, - {"Pentium OverDrive MMX 180", CPU_PENTIUMMMX, 180000000, 3, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9, 21}, - {"Pentium OverDrive MMX 200", CPU_PENTIUMMMX, 200000000, 3, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9, 24}, - {"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} -}; - -CPU cpus_Pentium3V[] = { - /*Intel Pentium*/ - {"Pentium 75", CPU_PENTIUM, 75000000, 3/2, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7, 4, 4, 9}, - {"Pentium OverDrive MMX 75", CPU_PENTIUMMMX, 75000000, 3/2, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7, 4, 4, 9}, - {"Pentium 90", CPU_PENTIUM, 90000000, 3/2, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 4, 4, 21/2}, - {"Pentium 100/50", CPU_PENTIUM, 100000000, 2, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 12}, - {"Pentium 100/66", CPU_PENTIUM, 100000000, 3/2, 0x526, 0x526, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 4, 4, 12}, - {"Pentium 120", CPU_PENTIUM, 120000000, 2, 0x526, 0x526, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 14}, - {"Pentium 133", CPU_PENTIUM, 133333333, 2, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16}, - {"Pentium 150", CPU_PENTIUM, 150000000, 5/2, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 35/2}, - {"Pentium 166", CPU_PENTIUM, 166666666, 5/2, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20}, - {"Pentium 200", CPU_PENTIUM, 200000000, 3, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24}, - - /*Intel Pentium OverDrive*/ - {"Pentium OverDrive 125", CPU_PENTIUM, 125000000, 5/2, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 7, 7, 15}, - {"Pentium OverDrive 150", CPU_PENTIUM, 150000000, 5/2, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 35/2}, - {"Pentium OverDrive 166", CPU_PENTIUM, 166666666, 5/2, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20}, - {"Pentium OverDrive MMX 125", CPU_PENTIUMMMX, 125000000, 5/2, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 7, 7, 15}, - {"Pentium OverDrive MMX 150/60", CPU_PENTIUMMMX, 150000000, 5/2, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 35/2}, - {"Pentium OverDrive MMX 166", CPU_PENTIUMMMX, 166000000, 5/2, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20}, - {"Pentium OverDrive MMX 180", CPU_PENTIUMMMX, 180000000, 3, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 21}, - {"Pentium OverDrive MMX 200", CPU_PENTIUMMMX, 200000000, 3, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24}, - {"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} -}; - -CPU cpus_Pentium[] = { - /*Intel Pentium*/ - {"Pentium 75", CPU_PENTIUM, 75000000, 3/2, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7, 4, 4, 9}, - {"Pentium OverDrive MMX 75", CPU_PENTIUMMMX, 75000000, 3/2, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7, 4, 4, 9}, - {"Pentium 90", CPU_PENTIUM, 90000000, 3/2, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 4, 4, 21/2}, - {"Pentium 100/50", CPU_PENTIUM, 100000000, 2, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 12}, - {"Pentium 100/66", CPU_PENTIUM, 100000000, 3/2, 0x526, 0x526, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 4, 4, 12}, - {"Pentium 120", CPU_PENTIUM, 120000000, 2, 0x526, 0x526, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 14}, - {"Pentium 133", CPU_PENTIUM, 133333333, 2, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16}, - {"Pentium 150", CPU_PENTIUM, 150000000, 5/2, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 35/2}, - {"Pentium 166", CPU_PENTIUM, 166666666, 5/2, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20}, - {"Pentium 200", CPU_PENTIUM, 200000000, 3, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24}, - - /*Intel Pentium MMX*/ - {"Pentium MMX 166", CPU_PENTIUMMMX, 166666666, 5/2, 0x543, 0x543, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20}, - {"Pentium MMX 200", CPU_PENTIUMMMX, 200000000, 3, 0x543, 0x543, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24}, - {"Pentium MMX 233", CPU_PENTIUMMMX, 233333333, 7/2, 0x543, 0x543, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,10,10, 28}, - - /*Mobile Pentium*/ - {"Mobile Pentium MMX 120", CPU_PENTIUMMMX, 120000000, 2, 0x543, 0x543, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 14}, - {"Mobile Pentium MMX 133", CPU_PENTIUMMMX, 133333333, 2, 0x543, 0x543, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16}, - {"Mobile Pentium MMX 150", CPU_PENTIUMMMX, 150000000, 5/2, 0x544, 0x544, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 35/2}, - {"Mobile Pentium MMX 166", CPU_PENTIUMMMX, 166666666, 5/2, 0x544, 0x544, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20}, - {"Mobile Pentium MMX 200", CPU_PENTIUMMMX, 200000000, 3, 0x581, 0x581, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24}, - {"Mobile Pentium MMX 233", CPU_PENTIUMMMX, 233333333, 7/2, 0x581, 0x581, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,10,10, 28}, - {"Mobile Pentium MMX 266", CPU_PENTIUMMMX, 266666666, 4, 0x582, 0x582, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24,12,12, 32}, - {"Mobile Pentium MMX 300", CPU_PENTIUMMMX, 300000000, 9/2, 0x582, 0x582, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 36}, - - /*Intel Pentium OverDrive*/ - {"Pentium OverDrive 125", CPU_PENTIUM, 125000000, 5/2, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 7, 7, 15}, - {"Pentium OverDrive 150", CPU_PENTIUM, 150000000, 5/2, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 35/2}, - {"Pentium OverDrive 166", CPU_PENTIUM, 166666666, 5/2, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20}, - {"Pentium OverDrive MMX 125", CPU_PENTIUMMMX, 125000000, 5/2, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 7, 7, 15}, - {"Pentium OverDrive MMX 150/60", CPU_PENTIUMMMX, 150000000, 5/2, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 35/2}, - {"Pentium OverDrive MMX 166", CPU_PENTIUMMMX, 166000000, 5/2, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20}, - {"Pentium OverDrive MMX 180", CPU_PENTIUMMMX, 180000000, 3, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 21}, - {"Pentium OverDrive MMX 200", CPU_PENTIUMMMX, 200000000, 3, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24}, - {"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} -}; - -#if defined(USE_NEW_DYNAREC) || (defined(DEV_BRANCH) && defined(USE_AMD_K)) -CPU cpus_K5[] = { - /*AMD K5 (Socket 5)*/ - {"K5 (5k86) 75 (P75)", CPU_K5, 75000000, 3/2, 0x500, 0x500, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7,4,4, 9}, - {"K5 (SSA/5) 75 (PR75)", CPU_K5, 75000000, 3/2, 0x501, 0x501, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7,4,4, 9}, - {"K5 (5k86) 90 (P90)", CPU_K5, 90000000, 3/2, 0x500, 0x500, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9,4,4, 21/2}, - {"K5 (SSA/5) 90 (PR90)", CPU_K5, 90000000, 3/2, 0x501, 0x501, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9,4,4, 21/2}, - {"K5 (5k86) 100 (P100)", CPU_K5, 100000000, 3/2, 0x500, 0x500, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9,4,4, 12}, - {"K5 (SSA/5) 100 (PR100)", CPU_K5, 100000000, 3/2, 0x501, 0x501, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9,4,4, 12}, - {"K5 (5k86) 90 (PR120)", CPU_5K86, 120000000, 2, 0x511, 0x511, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6, 14}, - {"K5 (5k86) 100 (PR133)", CPU_5K86, 133333333, 2, 0x514, 0x514, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6, 16}, - {"K5 (5k86) 105 (PR150)", CPU_5K86, 150000000, 5/2, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7, 35/2}, - {"K5 (5k86) 116.5 (PR166)", CPU_5K86, 166666666, 5/2, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7, 20}, - {"K5 (5k86) 133 (PR200)", CPU_5K86, 200000000, 3, 0x534, 0x534, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9, 24}, - {"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} -}; - -CPU cpus_K56[] = { - /*AMD K5 (Socket 7)*/ - {"K5 (5k86) 75 (P75)", CPU_K5, 75000000, 3/2, 0x500, 0x500, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7, 4, 4, 9}, - {"K5 (SSA/5) 75 (PR75)", CPU_K5, 75000000, 3/2, 0x501, 0x501, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7, 4, 4, 9}, - {"K5 (5k86) 90 (P90)", CPU_K5, 90000000, 3/2, 0x500, 0x500, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 4, 4, 21/2}, - {"K5 (SSA/5) 90 (PR90)", CPU_K5, 90000000, 3/2, 0x501, 0x501, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 4, 4, 21/2}, - {"K5 (5k86) 100 (P100)", CPU_K5, 100000000, 3/2, 0x500, 0x500, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 4, 4, 12}, - {"K5 (SSA/5) 100 (PR100)", CPU_K5, 100000000, 3/2, 0x501, 0x501, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 4, 4, 12}, - {"K5 (5k86) 90 (PR120)", CPU_5K86, 120000000, 2, 0x511, 0x511, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 14}, - {"K5 (5k86) 100 (PR133)", CPU_5K86, 133333333, 2, 0x514, 0x514, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16}, - {"K5 (5k86) 105 (PR150)", CPU_5K86, 150000000, 5/2, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 35/2}, - {"K5 (5k86) 116.5 (PR166)", CPU_5K86, 166666666, 5/2, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20}, - {"K5 (5k86) 133 (PR200)", CPU_5K86, 200000000, 3, 0x534, 0x534, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24}, - - /*AMD K6 (Socket 7*/ - {"K6 (Model 6) 166", CPU_K6, 166666666, 5/2, 0x561, 0x561, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20}, - {"K6 (Model 6) 200", CPU_K6, 200000000, 3, 0x561, 0x561, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24}, - {"K6 (Model 6) 233", CPU_K6, 233333333, 7/2, 0x561, 0x561, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21, 10, 10, 28}, - {"K6 (Model 7) 200", CPU_K6, 200000000, 3, 0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24}, - {"K6 (Model 7) 233", CPU_K6, 233333333, 7/2, 0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21, 10, 10, 28}, - {"K6 (Model 7) 266", CPU_K6, 266666666, 4, 0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24, 12, 12, 32}, - {"K6 (Model 7) 300", CPU_K6, 300000000, 9/2, 0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27, 13, 13, 36}, -#ifdef USE_NEW_DYNAREC - {"K6-2/233", CPU_K6_2, 233333333, 7/2, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21, 10, 10, 28}, - {"K6-2/266", CPU_K6_2, 266666666, 4, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24, 12, 12, 32}, - {"K6-2/300 AFR-66", CPU_K6_2, 300000000, 9/2, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27, 13, 13, 36}, - {"K6-2/366", CPU_K6_2, 366666666, 11/2, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 33,33, 17, 17, 44}, -#endif - {"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} -}; -#endif - -#ifdef USE_NEW_DYNAREC -CPU cpus_K56_SS7[] = { - /*AMD K5 (Socket 7)*/ - {"K5 (5k86) 75 (P75)", CPU_K5, 75000000, 3/2, 0x500, 0x500, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7, 4, 4, 9}, - {"K5 (SSA/5) 75 (PR75)", CPU_K5, 75000000, 3/2, 0x501, 0x501, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7, 4, 4, 9}, - {"K5 (5k86) 90 (P90)", CPU_K5, 90000000, 3/2, 0x500, 0x500, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 4, 4, 21/2}, - {"K5 (SSA/5) 90 (PR90)", CPU_K5, 90000000, 3/2, 0x501, 0x501, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 4, 4, 21/2}, - {"K5 (5k86) 100 (P100)", CPU_K5, 100000000, 3/2, 0x500, 0x500, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 4, 4, 12}, - {"K5 (SSA/5) 100 (PR100)", CPU_K5, 100000000, 3/2, 0x501, 0x501, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 4, 4, 12}, - {"K5 (5k86) 90 (PR120)", CPU_5K86, 120000000, 2, 0x511, 0x511, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 14}, - {"K5 (5k86) 100 (PR133)", CPU_5K86, 133333333, 2, 0x514, 0x514, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16}, - {"K5 (5k86) 105 (PR150)", CPU_5K86, 150000000, 5/2, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 35/2}, - {"K5 (5k86) 116.5 (PR166)", CPU_5K86, 166666666, 5/2, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20}, - {"K5 (5k86) 133 (PR200)", CPU_5K86, 200000000, 3, 0x534, 0x534, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24}, - - /*AMD K6 (Socket 7)*/ - {"K6 (Model 6) 166", CPU_K6, 166666666, 5/2, 0x561, 0x561, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20}, - {"K6 (Model 6) 200", CPU_K6, 200000000, 3, 0x561, 0x561, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24}, - {"K6 (Model 6) 233", CPU_K6, 233333333, 7/2, 0x561, 0x561, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,10,10, 28}, - {"K6 (Model 7) 200", CPU_K6, 200000000, 3, 0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24}, - {"K6 (Model 7) 233", CPU_K6, 233333333, 7/2, 0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,10,10, 28}, - {"K6 (Model 7) 266", CPU_K6, 266666666, 4, 0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24,12,12, 32}, - {"K6 (Model 7) 300", CPU_K6, 300000000, 9/2, 0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 36}, - - /*AMD K6-2 (Socket 7/Super Socket 7)*/ - {"K6-2/233", CPU_K6_2, 233333333, 7/2, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21, 21, 10, 10, 28}, - {"K6-2/266", CPU_K6_2, 266666666, 4, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24, 24, 12, 12, 32}, - {"K6-2/300", CPU_K6_2, 300000000, 3, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27, 27, 9, 9, 36}, - {"K6-2/333", CPU_K6_2, 332500000, 7/2, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 30, 30, 11, 11, 40}, - {"K6-2/350", CPU_K6_2C, 350000000, 7/2, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 32, 32, 11, 11, 42}, - {"K6-2/366", CPU_K6_2C, 366666666, 11/2, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 33, 33, 17, 17, 44}, - {"K6-2/380", CPU_K6_2C, 380000000, 4, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 34, 34, 12, 12, 46}, - {"K6-2/400", CPU_K6_2C, 400000000, 4, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 36, 36, 12, 12, 48}, - {"K6-2/450", CPU_K6_2C, 450000000, 9/2, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 41, 41, 14, 14, 54}, - {"K6-2/475", CPU_K6_2C, 475000000, 5, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 43, 43, 15, 15, 57}, - {"K6-2/500", CPU_K6_2C, 500000000, 5, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 45, 45, 15, 15, 60}, - {"K6-2/533", CPU_K6_2C, 533333333, 11/2, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 48, 48, 17, 17, 64}, - {"K6-2/550", CPU_K6_2C, 550000000, 11/2, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 50, 50, 17, 17, 66}, - - /*AMD K6-2+/K6-3/K6-3+ (Super Socket 7)*/ - {"K6-2+/450", CPU_K6_2P, 450000000, 9/2, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 41, 41, 14, 14, 54}, - {"K6-2+/475", CPU_K6_2P, 475000000, 5, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 43, 43, 15, 15, 57}, - {"K6-2+/500", CPU_K6_2P, 500000000, 5, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 45, 45, 15, 15, 60}, - {"K6-2+/533", CPU_K6_2P, 533333333, 11/2, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 48, 48, 17, 17, 64}, - {"K6-2+/550", CPU_K6_2P, 550000000, 11/2, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 50, 50, 17, 17, 66}, - {"K6-III/400", CPU_K6_3, 400000000, 4, 0x591, 0x591, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 36, 36, 12, 12, 48}, - {"K6-III/450", CPU_K6_3, 450000000, 9/2, 0x591, 0x591, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 41, 41, 14, 14, 54}, - {"K6-III+/400", CPU_K6_3P, 400000000, 4, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 36, 36, 12, 12, 48}, - {"K6-III+/450", CPU_K6_3P, 450000000, 9/2, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 41, 41, 14, 14, 54}, - {"K6-III+/475", CPU_K6_3P, 475000000, 5, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 43, 43, 15, 15, 57}, - {"K6-III+/500", CPU_K6_3P, 500000000, 5, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 45, 45, 15, 15, 60}, - {"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} -}; -#endif - -#ifdef DEV_BRANCH -#ifdef USE_I686 -CPU cpus_PentiumPro[] = { - /*Intel Pentium Pro*/ - {"Pentium Pro 50", CPU_PENTIUMPRO, 50000000, 1, 0x612, 0x612, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 4, 4, 3, 3, 6}, - {"Pentium Pro 60" , CPU_PENTIUMPRO, 60000000, 1, 0x612, 0x612, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6, 3, 3, 7}, - {"Pentium Pro 66" , CPU_PENTIUMPRO, 66666666, 1, 0x612, 0x612, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6, 3, 3, 8}, - {"Pentium Pro 75", CPU_PENTIUMPRO, 75000000, 3/2, 0x612, 0x612, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7, 4, 4, 9}, - {"Pentium Pro 150", CPU_PENTIUMPRO, 150000000, 5/2, 0x612, 0x612, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 35/2}, - {"Pentium Pro 166", CPU_PENTIUMPRO, 166666666, 5/2, 0x617, 0x617, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20}, - {"Pentium Pro 180", CPU_PENTIUMPRO, 180000000, 3, 0x617, 0x617, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 21}, - {"Pentium Pro 200", CPU_PENTIUMPRO, 200000000, 3, 0x617, 0x617, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24}, - - /*Intel Pentium II OverDrive*/ - {"Pentium II Overdrive 50", CPU_PENTIUM2D, 50000000, 1, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 4, 4, 3, 3, 6}, - {"Pentium II Overdrive 60", CPU_PENTIUM2D, 60000000, 1, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6, 3, 3, 7}, - {"Pentium II Overdrive 66", CPU_PENTIUM2D, 66666666, 1, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6, 3, 3, 8}, - {"Pentium II Overdrive 75", CPU_PENTIUM2D, 75000000, 3/2, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7, 4, 4, 9}, - {"Pentium II Overdrive 210", CPU_PENTIUM2D, 210000000, 7/2, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 17,17, 7, 7, 25}, - {"Pentium II Overdrive 233", CPU_PENTIUM2D, 233333333, 7/2, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,10,10, 28}, - {"Pentium II Overdrive 240", CPU_PENTIUM2D, 240000000, 4, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24,12,12, 29}, - {"Pentium II Overdrive 266", CPU_PENTIUM2D, 266666666, 4, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24,12,12, 32}, - {"Pentium II Overdrive 270", CPU_PENTIUM2D, 270000000, 9/2, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 25,25,12,12, 33}, - {"Pentium II Overdrive 300/66", CPU_PENTIUM2D, 300000000, 9/2, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 25,25,12,12, 36}, - {"Pentium II Overdrive 300/60", CPU_PENTIUM2D, 300000000, 5, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 36}, - {"Pentium II Overdrive 333", CPU_PENTIUM2D, 333333333, 5, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 40}, - {"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} -}; - -CPU cpus_PentiumII[] = { - /*Intel Pentium II Klamath*/ - {"Pentium II Klamath 50", CPU_PENTIUM2, 50000000, 1, 0x634, 0x634, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 4, 4, 3, 3, 6}, - {"Pentium II Klamath 60", CPU_PENTIUM2, 60000000, 1, 0x634, 0x634, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6, 3, 3, 7}, - {"Pentium II Klamath 66", CPU_PENTIUM2, 66666666, 1, 0x634, 0x634, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6, 3, 3, 8}, - {"Pentium II Klamath 75", CPU_PENTIUM2, 75000000, 3/2, 0x634, 0x634, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7, 4, 4, 9}, - {"Pentium II Klamath 233", CPU_PENTIUM2, 233333333, 7/2, 0x634, 0x634, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,10,10, 28}, - {"Pentium II Klamath 266", CPU_PENTIUM2, 266666666, 4, 0x634, 0x634, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24,12,12, 29}, - {"Pentium II Klamath 300/66", CPU_PENTIUM2, 300000000, 9/2, 0x634, 0x634, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 25,25,12,12, 36}, - - /*Intel Pentium II Deschutes*/ - {"Pentium II Deschutes 50", CPU_PENTIUM2D, 50000000, 1, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 4, 4, 3, 3, 6}, - {"Pentium II Deschutes 60", CPU_PENTIUM2D, 60000000, 1, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6, 3, 3, 7}, - {"Pentium II Deschutes 66", CPU_PENTIUM2D, 66666666, 1, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6, 3, 3, 8}, - {"Pentium II Deschutes 75", CPU_PENTIUM2D, 75000000, 3/2, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7, 4, 4, 9}, - {"Pentium II Deschutes 266", CPU_PENTIUM2D, 266666666, 4, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24,12,12, 29}, - {"Pentium II Deschutes 300/66", CPU_PENTIUM2D, 300000000, 9/2, 0x651, 0x651, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 25,25,12,12, 36}, - {"Pentium II Deschutes 333", CPU_PENTIUM2D, 333333333, 5, 0x651, 0x651, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 40}, - {"Pentium II Deschutes 350", CPU_PENTIUM2D, 350000000, 7/2, 0x651, 0x651, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 32,32,11,11, 42}, - {"Pentium II Deschutes 400", CPU_PENTIUM2D, 400000000, 4, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 36,36,12,12, 48}, - {"Pentium II Deschutes 450", CPU_PENTIUM2D, 450000000, 9/2, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 41,41,14,14, 54}, - {"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} - -}; - -CPU cpus_PGA370[] = { - {"Celeron Mendocino 100", CPU_PENTIUM2D, 100000000, 3/2, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 12}, - {"Celeron Mendocino 333", CPU_PENTIUM2D, 333333333, 5, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 40}, - {"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} -}; -#endif -#endif -CPU cpus_Cyrix3[] = { - /*VIA Cyrix III (Samuel)*/ - {"Cyrix III 66", CPU_CYRIX3S, 66666666, 1, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 8}, /*66 MHz version*/ - {"Cyrix III 233", CPU_CYRIX3S, 233333333, 3.5, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC, 21, 21, 9, 9, 28}, - {"Cyrix III 266", CPU_CYRIX3S, 266666666, 4, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC, 24, 24, 12, 12, 32}, - {"Cyrix III 300", CPU_CYRIX3S, 300000000, 4.5, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC, 27, 27, 13, 13, 36}, - {"Cyrix III 333", CPU_CYRIX3S, 333333333, 5, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC, 30, 30, 15, 15, 40}, - {"Cyrix III 350", CPU_CYRIX3S, 350000000, 3.5, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC, 32, 32, 11, 11, 42}, - {"Cyrix III 400", CPU_CYRIX3S, 400000000, 4, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC, 36, 36, 12, 12, 48}, - {"Cyrix III 450", CPU_CYRIX3S, 450000000, 4.5, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC, 41, 41, 14, 14, 54}, /*^ is lower P2 speeds to allow emulation below 466 mhz*/ - {"Cyrix III 500", CPU_CYRIX3S, 500000000, 5, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC, 45, 45, 15, 15, 60}, - {"Cyrix III 550", CPU_CYRIX3S, 550000000, 5.5, 0x662, 0x662, 0, CPU_SUPPORTS_DYNAREC, 50, 50, 17, 17, 66}, - {"Cyrix III 600", CPU_CYRIX3S, 600000000, 6, 0x662, 0x662, 0, CPU_SUPPORTS_DYNAREC, 54, 54, 18, 18, 72}, - {"Cyrix III 650", CPU_CYRIX3S, 650000000, 6.5, 0x662, 0x662, 0, CPU_SUPPORTS_DYNAREC, 58, 58, 20, 20, 78}, - {"Cyrix III 700", CPU_CYRIX3S, 700000000, 7, 0x662, 0x662, 0, CPU_SUPPORTS_DYNAREC, 62, 62, 21, 21, 84}, - {"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} +/* + * 86Box A hypervisor and IBM PC system emulator that specializes in + * running old operating systems and software designed for IBM + * PC systems and compatibles from 1981 through fairly recent + * system designs based on the PCI bus. + * + * This file is part of the 86Box distribution. + * + * Define all known processor types. + * + * Available cpuspeeds: + * + * 0 = 16 MHz + * 1 = 20 MHz + * 2 = 25 MHz + * 3 = 33 MHz + * 4 = 40 MHz + * 5 = 50 MHz + * 6 = 66 MHz + * 7 = 75 MHz + * 8 = 80 MHz + * 9 = 90 MHz + * 10 = 100 MHz + * 11 = 120 MHz + * 12 = 133 MHz + * 13 = 150 MHz + * 14 = 160 MHz + * 15 = 166 MHz + * 16 = 180 MHz + * 17 = 200 MHz + * + * + * + * Authors: Sarah Walker, + * leilei, + * Miran Grca, + * Fred N. van Kempen, + * + * Copyright 2008-2019 Sarah Walker. + * Copyright 2016-2019 leilei. + * Copyright 2016-2019 Miran Grca. + * Copyright 2017-2019 Fred N. van Kempen. + */ +#include +#include +#include +#include +#include "86box.h" +#include "cpu.h" +#include "machine.h" + + +CPU cpus_8088[] = { + /*8088 standard*/ + {"8088/4.77", CPU_8088, 4772728, 1, 0, 0, 0, 0, 0,0,0,0, 1}, + {"8088/7.16", CPU_8088, 7159092, 1, 0, 0, 0, 0, 0,0,0,0, 1}, + {"8088/8", CPU_8088, 8000000, 1, 0, 0, 0, 0, 0,0,0,0, 1}, + {"8088/10", CPU_8088, 10000000, 1, 0, 0, 0, 0, 0,0,0,0, 1}, + {"8088/12", CPU_8088, 12000000, 1, 0, 0, 0, 0, 0,0,0,0, 1}, + {"8088/16", CPU_8088, 16000000, 1, 0, 0, 0, 0, 0,0,0,0, 1}, + {"", -1, 0, 0, 0, 0, 0, 0, 0,0,0,0, 0} +}; + +CPU cpus_pcjr[] = { + /*8088 PCjr*/ + {"8088/4.77", CPU_8088, 4772728, 1, 0, 0, 0, 0, 0,0,0,0, 1}, + {"", -1, 0, 0, 0, 0, 0, 0, 0,0,0,0, 0} +}; + +CPU cpus_europc[] = { + /*8088 EuroPC*/ + {"8088/4.77", CPU_8088, 4772728, 1, 0, 0, 0, CPU_ALTERNATE_XTAL, 0,0,0,0, 1}, + {"8088/7.16", CPU_8088, 7159092, 1, 0, 0, 0, CPU_ALTERNATE_XTAL, 0,0,0,0, 1}, + {"8088/9.54", CPU_8088, 9545456, 1, 0, 0, 0, 0, 0,0,0,0, 1}, + {"", -1, 0, 0, 0, 0, 0, 0, 0,0,0,0, 0} +}; + +CPU cpus_8086[] = { + /*8086 standard*/ + {"8086/7.16", CPU_8086, 7159092, 1, 0, 0, 0, CPU_ALTERNATE_XTAL, 0,0,0,0, 1}, + {"8086/8", CPU_8086, 8000000, 1, 0, 0, 0, 0, 0,0,0,0, 1}, + {"8086/9.54", CPU_8086, 9545456, 1, 0, 0, 0, CPU_ALTERNATE_XTAL, 0,0,0,0, 1}, + {"8086/10", CPU_8086, 10000000, 1, 0, 0, 0, 0, 0,0,0,0, 1}, + {"8086/12", CPU_8086, 12000000, 1, 0, 0, 0, 0, 0,0,0,0, 1}, + {"8086/16", CPU_8086, 16000000, 1, 0, 0, 0, 0, 0,0,0,0, 2}, + {"", -1, 0, 0, 0, 0, 0, 0, 0,0,0,0, 0} +}; + +CPU cpus_pc1512[] = { + /*8086 Amstrad*/ + {"8086/8", CPU_8086, 8000000, 1, 0, 0, 0, 0, 0,0,0,0, 1}, + {"", -1, 0, 0, 0, 0, 0, 0, 0,0,0,0, 0} +}; + +CPU cpus_286[] = { + /*286*/ + {"286/6", CPU_286, 6000000, 1, 0, 0, 0, 0, 2,2,2,2, 1}, + {"286/8", CPU_286, 8000000, 1, 0, 0, 0, 0, 2,2,2,2, 1}, + {"286/10", CPU_286, 10000000, 1, 0, 0, 0, 0, 2,2,2,2, 1}, + {"286/12", CPU_286, 12500000, 1, 0, 0, 0, 0, 3,3,3,3, 2}, + {"286/16", CPU_286, 16000000, 1, 0, 0, 0, 0, 3,3,3,3, 2}, + {"286/20", CPU_286, 20000000, 1, 0, 0, 0, 0, 4,4,4,4, 3}, + {"286/25", CPU_286, 25000000, 1, 0, 0, 0, 0, 4,4,4,4, 3}, + {"", -1, 0, 0, 0, 0, 0, 0, 0,0,0,0, 0} +}; + +CPU cpus_ibmat[] = { + /*286*/ + {"286/6", CPU_286, 6000000, 1, 0, 0, 0, 0, 3,3,3,3, 1}, + {"286/8", CPU_286, 8000000, 1, 0, 0, 0, 0, 3,3,3,3, 1}, + {"", -1, 0, 0, 0, 0, 0, 0, 0,0,0,0, 0} +}; + +CPU cpus_ibmxt286[] = { + /*286*/ + {"286/6", CPU_286, 6000000, 1, 0, 0, 0, 0, 2,2,2,2, 1}, + {"", -1, 0, 0, 0, 0, 0, 0, 0,0,0,0, 0} +}; + +CPU cpus_ps1_m2011[] = { + /*286*/ + {"286/10", CPU_286, 10000000, 1, 0, 0, 0, 0, 2,2,2,2, 1}, + {"", -1, 0, 0, 0, 0, 0, 0, 0,0,0,0, 9} +}; + +CPU cpus_ps2_m30_286[] = { + /*286*/ + {"286/10", CPU_286, 10000000, 1, 0, 0, 0, 0, 2,2,2,2, 1}, + {"286/12", CPU_286, 12500000, 1, 0, 0, 0, 0, 3,3,3,3, 2}, + {"286/16", CPU_286, 16000000, 1, 0, 0, 0, 0, 3,3,3,3, 2}, + {"286/20", CPU_286, 20000000, 1, 0, 0, 0, 0, 4,4,4,4, 3}, + {"286/25", CPU_286, 25000000, 1, 0, 0, 0, 0, 4,4,4,4, 3}, + {"", -1, 0, 0, 0, 0, 0, 0, 0,0,0,0, 0} +}; + +CPU cpus_i386SX[] = { + /*i386SX*/ + {"i386SX/16", CPU_386SX, 16000000, 1, 0x2308, 0, 0, 0, 3,3,3,3, 2}, + {"i386SX/20", CPU_386SX, 20000000, 1, 0x2308, 0, 0, 0, 4,4,3,3, 3}, + {"i386SX/25", CPU_386SX, 25000000, 1, 0x2308, 0, 0, 0, 4,4,3,3, 3}, + {"i386SX/33", CPU_386SX, 33333333, 1, 0x2308, 0, 0, 0, 6,6,3,3, 4}, + {"i386SX/40", CPU_386SX, 40000000, 1, 0x2308, 0, 0, 0, 7,7,3,3, 5}, + {"", -1, 0, 0, 0, 0, 0, 0, 0,0,0,0, 0} +}; + +CPU cpus_i386DX[] = { + /*i386DX/RapidCAD*/ + {"i386DX/16", CPU_386DX, 16000000, 1, 0x0308, 0, 0, 0, 3,3,3,3, 2}, + {"i386DX/20", CPU_386DX, 20000000, 1, 0x0308, 0, 0, 0, 4,4,3,3, 3}, + {"i386DX/25", CPU_386DX, 25000000, 1, 0x0308, 0, 0, 0, 4,4,3,3, 3}, + {"i386DX/33", CPU_386DX, 33333333, 1, 0x0308, 0, 0, 0, 6,6,3,3, 4}, + {"i386DX/40", CPU_386DX, 40000000, 1, 0x0308, 0, 0, 0, 7,7,3,3, 5}, + {"RapidCAD/25", CPU_RAPIDCAD, 25000000, 1, 0x0430, 0, 0, CPU_SUPPORTS_DYNAREC, 4,4,3,3, 3}, + {"RapidCAD/33", CPU_RAPIDCAD, 33333333, 1, 0x0430, 0, 0, CPU_SUPPORTS_DYNAREC, 6,6,3,3, 4}, + {"RapidCAD/40", CPU_RAPIDCAD, 40000000, 1, 0x0430, 0, 0, CPU_SUPPORTS_DYNAREC, 7,7,3,3, 5}, + {"", -1, 0, 0, 0, 0, 0, 0, 0,0,0,0, 0} +}; + +CPU cpus_Am386SX[] = { + /*Am386SX*/ + {"Am386SX/16", CPU_386SX, 16000000, 1, 0x2308, 0, 0, 0, 3,3,3,3, 2}, + {"Am386SX/20", CPU_386SX, 20000000, 1, 0x2308, 0, 0, 0, 4,4,3,3, 3}, + {"Am386SX/25", CPU_386SX, 25000000, 1, 0x2308, 0, 0, 0, 4,4,3,3, 3}, + {"Am386SX/33", CPU_386SX, 33333333, 1, 0x2308, 0, 0, 0, 6,6,3,3, 4}, + {"Am386SX/40", CPU_386SX, 40000000, 1, 0x2308, 0, 0, 0, 7,7,3,3, 5}, + {"", -1, 0, 0, 0, 0, 0, 0, 0,0,0,0, 0} +}; + +CPU cpus_Am386DX[] = { + /*Am386DX*/ + {"Am386DX/25", CPU_386DX, 25000000, 1, 0x0308, 0, 0, 0, 4,4,3,3, 3}, + {"Am386DX/33", CPU_386DX, 33333333, 1, 0x0308, 0, 0, 0, 6,6,3,3, 4}, + {"Am386DX/40", CPU_386DX, 40000000, 1, 0x0308, 0, 0, 0, 7,7,3,3, 5}, + {"", -1, 0, 0, 0, 0, 0, 0, 0,0,0,0, 0} +}; + +CPU cpus_486SLC[] = { + /*Cx486SLC*/ + {"Cx486SLC/20", CPU_486SLC, 20000000, 1, 0x400, 0, 0x0000, 0, 4,4,3,3, 3}, + {"Cx486SLC/25", CPU_486SLC, 25000000, 1, 0x400, 0, 0x0000, 0, 4,4,3,3, 3}, + {"Cx486SLC/33", CPU_486SLC, 33333333, 1, 0x400, 0, 0x0000, 0, 6,6,3,3, 4}, + {"Cx486SRx2/32", CPU_486SLC, 32000000, 2, 0x406, 0, 0x0006, 0, 6,6,6,6, 4}, + {"Cx486SRx2/40", CPU_486SLC, 40000000, 2, 0x406, 0, 0x0006, 0, 8,8,6,6, 6}, + {"Cx486SRx2/50", CPU_486SLC, 50000000, 2, 0x406, 0, 0x0006, 0, 8,8,6,6, 6}, + {"", -1, 0, 0, 0, 0, 0, 0, 0,0,0,0, 0} +}; + +CPU cpus_IBM386SLC[] = { + /*IBM 386SLC*/ + {"386SLC/16", CPU_IBM386SLC, 16000000, 1, 0x300, 0, 0, 0, 3,3,3,3, 2}, + {"386SLC/20", CPU_IBM386SLC, 20000000, 1, 0x300, 0, 0, 0, 4,4,3,3, 3}, + {"386SLC/25", CPU_IBM386SLC, 25000000, 1, 0x300, 0, 0, 0, 4,4,3,3, 3}, + {"", -1, 0, 0, 0, 0, 0, 0, 0,0,0,0, 0} +}; + +CPU cpus_IBM486SLC[] = { + /*IBM 486SLC*/ + {"486SLC/33", CPU_IBM486SLC, 33333333, 1, 0x400, 0, 0, 0, 6,6,3,3, 4}, + {"486SLC2/40", CPU_IBM486SLC, 40000000, 2, 0x400, 0, 0, 0, 7,7,6,6, 5}, + {"486SLC2/50", CPU_IBM486SLC, 50000000, 2, 0x400, 0, 0, 0, 8,8,6,6, 6}, + {"486SLC2/66", CPU_IBM486SLC, 66666666, 2, 0x400, 0, 0, 0, 12,12,6,6, 8}, + {"486SLC3/60", CPU_IBM486SLC, 60000000, 3, 0x400, 0, 0, 0, 12,12,9,9, 7}, + {"486SLC3/75", CPU_IBM486SLC, 75000000, 3, 0x400, 0, 0, 0, 12,12,9,9, 9}, + {"486SLC3/100", CPU_IBM486SLC, 100000000, 3, 0x400, 0, 0, 0, 18,18,9,9, 12}, + {"", -1, 0, 0, 0, 0, 0, 0, 0,0,0,0, 0} +}; + +CPU cpus_IBM486BL[] = { + /*IBM Blue Lightning*/ + {"486BL2/50", CPU_IBM486BL, 50000000, 2, 0x400, 0, 0, 0, 8,8,6,6, 6}, + {"486BL2/66", CPU_IBM486BL, 66666666, 2, 0x400, 0, 0, 0, 12,12,6,6, 8}, + {"486BL3/75", CPU_IBM486BL, 75000000, 3, 0x400, 0, 0, 0, 12,12,9,9, 9}, + {"486BL3/100", CPU_IBM486BL, 100000000, 3, 0x400, 0, 0, 0, 18,18,9,9, 12}, + {"", -1, 0, 0, 0, 0, 0, 0, 0,0,0,0, 0} +}; + +CPU cpus_486DLC[] = { + /*Cx486DLC*/ + {"Cx486DLC/25", CPU_486DLC, 25000000, 1, 0x401, 0, 0x0001, 0, 4, 4,3,3, 3}, + {"Cx486DLC/33", CPU_486DLC, 33333333, 1, 0x401, 0, 0x0001, 0, 6, 6,3,3, 4}, + {"Cx486DLC/40", CPU_486DLC, 40000000, 1, 0x401, 0, 0x0001, 0, 7, 7,3,3, 5}, + {"Cx486DRx2/32", CPU_486DLC, 32000000, 2, 0x407, 0, 0x0007, 0, 6, 6,6,6, 4}, + {"Cx486DRx2/40", CPU_486DLC, 40000000, 2, 0x407, 0, 0x0007, 0, 8, 8,6,6, 6}, + {"Cx486DRx2/50", CPU_486DLC, 50000000, 2, 0x407, 0, 0x0007, 0, 8, 8,6,6, 6}, + {"Cx486DRx2/66", CPU_486DLC, 66666666, 2, 0x407, 0, 0x0007, 0, 12,12,6,6, 8}, + {"", -1, 0, 0, 0, 0, 0, 0, 0, 0,0,0, 0} +}; + +CPU cpus_i486S1[] = { + /*i486*/ + {"i486SX/16", CPU_i486SX, 16000000, 1, 0x420, 0, 0, CPU_SUPPORTS_DYNAREC, 3, 3,3,3, 2}, + {"i486SX/20", CPU_i486SX, 20000000, 1, 0x420, 0, 0, CPU_SUPPORTS_DYNAREC, 4, 4,3,3, 3}, + {"i486SX/25", CPU_i486SX, 25000000, 1, 0x422, 0, 0, CPU_SUPPORTS_DYNAREC, 4, 4,3,3, 3}, + {"i486SX/33", CPU_i486SX, 33333333, 1, 0x42a, 0, 0, CPU_SUPPORTS_DYNAREC, 6, 6,3,3, 4}, + {"i486SX2/50", CPU_i486SX, 50000000, 2, 0x45b, 0, 0, CPU_SUPPORTS_DYNAREC, 8, 8,6,6, 6}, + {"i486SX2/66 (Q0569)", CPU_i486SX, 66666666, 2, 0x45b, 0, 0, CPU_SUPPORTS_DYNAREC, 8, 8,6,6, 8}, + {"i486DX/25", CPU_i486DX, 25000000, 1, 0x404, 0, 0, CPU_SUPPORTS_DYNAREC, 4, 4,3,3, 3}, + {"i486DX/33", CPU_i486DX, 33333333, 1, 0x414, 0, 0, CPU_SUPPORTS_DYNAREC, 6, 6,3,3, 4}, + {"i486DX/50", CPU_i486DX, 50000000, 1, 0x411, 0, 0, CPU_SUPPORTS_DYNAREC, 8, 8,4,4, 6}, + {"i486DX2/40", CPU_i486DX, 40000000, 2, 0x430, 0x430, 0, CPU_SUPPORTS_DYNAREC, 7, 7,6,6, 5}, + {"i486DX2/50", CPU_i486DX, 50000000, 2, 0x433, 0x433, 0, CPU_SUPPORTS_DYNAREC, 8, 8,6,6, 6}, + {"i486DX2/66", CPU_i486DX, 66666666, 2, 0x435, 0x435, 0, CPU_SUPPORTS_DYNAREC, 12,12,6,6, 8}, + {"iDX4 OverDrive 75", CPU_iDX4, 75000000, 3, 0x1480, 0x1480, 0, CPU_SUPPORTS_DYNAREC, 12,12,9,9, 9}, /*Only added the DX4 OverDrive as the others would be redundant*/ + {"iDX4 OverDrive 100", CPU_iDX4, 100000000, 3, 0x1480, 0x1480, 0, CPU_SUPPORTS_DYNAREC, 18,18,9,9, 12}, + {"", -1, 0, 0, 0, 0, 0, 0, 0, 0,0,0, 0} +}; +CPU cpus_Am486S1[] = { + /*Am486*/ + {"Am486SX/33", CPU_Am486SX, 33333333, 1, 0x42a, 0, 0, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 4}, + {"Am486SX/40", CPU_Am486SX, 40000000, 1, 0x42a, 0, 0, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5}, + {"Am486SX2/50", CPU_Am486SX2, 50000000, 2, 0x45b, 0x45b, 0, CPU_SUPPORTS_DYNAREC, 8, 8, 6, 6, 6}, /*CPUID available on SX2, DX2, DX4, 5x86, >= 50 MHz*/ + {"Am486SX2/66", CPU_Am486SX2, 66666666, 2, 0x45b, 0x45b, 0, CPU_SUPPORTS_DYNAREC, 12,12, 6, 6, 8}, /*Isn't on all real AMD SX2s and DX2s, availability here is pretty arbitary (and distinguishes them from the Intel chips)*/ + {"Am486DX/33", CPU_Am486DX, 33333333, 1, 0x430, 0, 0, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 4}, + {"Am486DX/40", CPU_Am486DX, 40000000, 1, 0x430, 0, 0, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5}, + {"Am486DX2/50", CPU_Am486DX2, 50000000, 2, 0x470, 0x470, 0, CPU_SUPPORTS_DYNAREC, 8, 8, 6, 6, 6}, + {"Am486DX2/66", CPU_Am486DX2, 66666666, 2, 0x470, 0x470, 0, CPU_SUPPORTS_DYNAREC, 12,12, 6, 6, 8}, + {"Am486DX2/80", CPU_Am486DX2, 80000000, 2, 0x470, 0x470, 0, CPU_SUPPORTS_DYNAREC, 14,14, 6, 6, 10}, + {"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} +}; +CPU cpus_Cx486S1[] = { + /*Cyrix 486*/ + {"Cx486S/25", CPU_Cx486S, 25000000, 1, 0x420, 0, 0x0010, CPU_SUPPORTS_DYNAREC, 4, 4, 3, 3, 3}, + {"Cx486S/33", CPU_Cx486S, 33333333, 1, 0x420, 0, 0x0010, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 4}, + {"Cx486S/40", CPU_Cx486S, 40000000, 1, 0x420, 0, 0x0010, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5}, + {"Cx486DX/33", CPU_Cx486DX, 33333333, 1, 0x430, 0, 0x051a, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 4}, + {"Cx486DX/40", CPU_Cx486DX, 40000000, 1, 0x430, 0, 0x051a, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5}, + {"Cx486DX2/50", CPU_Cx486DX2, 50000000, 2, 0x430, 0, 0x081b, CPU_SUPPORTS_DYNAREC, 8, 8, 6, 6, 6}, + {"Cx486DX2/66", CPU_Cx486DX2, 66666666, 2, 0x430, 0, 0x0b1b, CPU_SUPPORTS_DYNAREC, 12,12, 6, 6, 8}, + {"Cx486DX2/80", CPU_Cx486DX2, 80000000, 2, 0x430, 0, 0x311b, CPU_SUPPORTS_DYNAREC, 14,14, 6, 6, 10}, + {"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} +}; + +CPU cpus_i486[] = { + /*i486/P24T*/ + {"i486SX/16", CPU_i486SX, 16000000, 1, 0x420, 0, 0, CPU_SUPPORTS_DYNAREC, 3, 3,3,3, 2}, + {"i486SX/20", CPU_i486SX, 20000000, 1, 0x420, 0, 0, CPU_SUPPORTS_DYNAREC, 4, 4,3,3, 3}, + {"i486SX/25", CPU_i486SX, 25000000, 1, 0x422, 0, 0, CPU_SUPPORTS_DYNAREC, 4, 4,3,3, 3}, + {"i486SX/33", CPU_i486SX, 33333333, 1, 0x42a, 0, 0, CPU_SUPPORTS_DYNAREC, 6, 6,3,3, 4}, + {"i486SX2/50", CPU_i486SX, 50000000, 2, 0x45b, 0, 0, CPU_SUPPORTS_DYNAREC, 8, 8,6,6, 6}, + {"i486SX2/66 (Q0569)", CPU_i486SX, 66666666, 2, 0x45b, 0, 0, CPU_SUPPORTS_DYNAREC, 8, 8,6,6, 8}, + {"i486DX/25", CPU_i486DX, 25000000, 1, 0x404, 0, 0, CPU_SUPPORTS_DYNAREC, 4, 4,3,3, 3}, + {"i486DX/33", CPU_i486DX, 33333333, 1, 0x414, 0, 0, CPU_SUPPORTS_DYNAREC, 6, 6,3,3, 4}, + {"i486DX/50", CPU_i486DX, 50000000, 1, 0x411, 0, 0, CPU_SUPPORTS_DYNAREC, 8, 8,4,4, 6}, + {"i486DX2/40", CPU_i486DX, 40000000, 2, 0x430, 0x430, 0, CPU_SUPPORTS_DYNAREC, 7, 7,6,6, 5}, + {"i486DX2/50", CPU_i486DX, 50000000, 2, 0x433, 0x433, 0, CPU_SUPPORTS_DYNAREC, 8, 8,6,6, 6}, + {"i486DX2/66", CPU_i486DX, 66666666, 2, 0x435, 0x435, 0, CPU_SUPPORTS_DYNAREC, 12,12,6,6, 8}, + {"iDX4/75", CPU_iDX4, 75000000, 3, 0x480, 0x480, 0, CPU_SUPPORTS_DYNAREC, 12,12,9,9, 9}, /*CPUID available on DX4, >= 75 MHz*/ + {"iDX4/100", CPU_iDX4, 100000000, 3, 0x483, 0x483, 0, CPU_SUPPORTS_DYNAREC, 18,18,9,9, 12}, /*Is on some real Intel DX2s, limit here is pretty arbitary*/ + {"iDX4 OverDrive 75", CPU_iDX4, 75000000, 3, 0x1480, 0x1480, 0, CPU_SUPPORTS_DYNAREC, 12,12,9,9, 9}, + {"iDX4 OverDrive 100", CPU_iDX4, 100000000, 3, 0x1480, 0x1480, 0, CPU_SUPPORTS_DYNAREC, 18,18,9,9, 12}, + {"Pentium OverDrive 63", CPU_PENTIUM, 62500000, 5/2, 0x1531, 0x1531, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10,7,7, 15/2}, + {"Pentium OverDrive 83", CPU_PENTIUM, 83333333, 5/2, 0x1532, 0x1532, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,8,8, 10}, + {"", -1, 0, 0, 0, 0, 0, 0, 0, 0,0,0, 0} +}; + +CPU cpus_Am486[] = { + /*Am486/5x86*/ + {"Am486SX/33", CPU_Am486SX, 33333333, 1, 0x42a, 0, 0, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 4}, + {"Am486SX/40", CPU_Am486SX, 40000000, 1, 0x42a, 0, 0, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5}, + {"Am486SX2/50", CPU_Am486SX2, 50000000, 2, 0x45b, 0x45b, 0, CPU_SUPPORTS_DYNAREC, 8, 8, 6, 6, 6}, /*CPUID available on SX2, DX2, DX4, 5x86, >= 50 MHz*/ + {"Am486SX2/66", CPU_Am486SX2, 66666666, 2, 0x45b, 0x45b, 0, CPU_SUPPORTS_DYNAREC, 12,12, 6, 6, 8}, + {"Am486DX/33", CPU_Am486DX, 33333333, 1, 0x430, 0, 0, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 4}, + {"Am486DX/40", CPU_Am486DX, 40000000, 1, 0x430, 0, 0, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5}, + {"Am486DX2/50", CPU_Am486DX2, 50000000, 2, 0x470, 0x470, 0, CPU_SUPPORTS_DYNAREC, 8, 8, 6, 6, 6}, + {"Am486DX2/66", CPU_Am486DX2, 66666666, 2, 0x470, 0x470, 0, CPU_SUPPORTS_DYNAREC, 12,12, 6, 6, 8}, + {"Am486DX2/80", CPU_Am486DX2, 80000000, 2, 0x470, 0x470, 0, CPU_SUPPORTS_DYNAREC, 14,14, 6, 6, 10}, + {"Am486DX4/75", CPU_Am486DX4, 75000000, 3, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC, 12,12, 9, 9, 9}, + {"Am486DX4/90", CPU_Am486DX4, 90000000, 3, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC, 15,15, 9, 9, 12}, + {"Am486DX4/100", CPU_Am486DX4, 100000000, 3, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC, 15,15, 9, 9, 12}, + {"Am486DX4/120", CPU_Am486DX4, 120000000, 3, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC, 21,21, 9, 9, 15}, + {"Am5x86/P75", CPU_Am5x86, 133333333, 4, 0x4e0, 0x4e0, 0, CPU_SUPPORTS_DYNAREC, 24,24,12,12, 16}, + {"Am5x86/P75+", CPU_Am5x86, 150000000, 3, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC, 28,28,12,12, 20},/*The rare P75+ was indeed a triple-clocked 150 MHz according to research*/ + {"Am5x86/P90", CPU_Am5x86, 160000000, 4, 0x4e0, 0x4e0, 0, CPU_SUPPORTS_DYNAREC, 28,28,12,12, 20},/*160 MHz on a 40 MHz bus was a common overclock and "5x86/P90" was used by a number of BIOSes to refer to that configuration*/ + {"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} +}; + +CPU cpus_Cx486[] = { + /*Cyrix 486*/ + {"Cx486S/25", CPU_Cx486S, 25000000, 1, 0x420, 0, 0x0010, CPU_SUPPORTS_DYNAREC, 4, 4, 3, 3, 3}, + {"Cx486S/33", CPU_Cx486S, 33333333, 1, 0x420, 0, 0x0010, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 4}, + {"Cx486S/40", CPU_Cx486S, 40000000, 1, 0x420, 0, 0x0010, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5}, + {"Cx486DX/33", CPU_Cx486DX, 33333333, 1, 0x430, 0, 0x051a, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 4}, + {"Cx486DX/40", CPU_Cx486DX, 40000000, 1, 0x430, 0, 0x051a, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5}, + {"Cx486DX2/50", CPU_Cx486DX2, 50000000, 2, 0x430, 0, 0x081b, CPU_SUPPORTS_DYNAREC, 8, 8, 6, 6, 6}, + {"Cx486DX2/66", CPU_Cx486DX2, 66666666, 2, 0x430, 0, 0x0b1b, CPU_SUPPORTS_DYNAREC, 12,12, 6, 6, 8}, + {"Cx486DX2/80", CPU_Cx486DX2, 80000000, 2, 0x430, 0, 0x311b, CPU_SUPPORTS_DYNAREC, 14,14, 6, 6, 10}, + {"Cx486DX4/75", CPU_Cx486DX4, 75000000, 3, 0x480, 0, 0x361f, CPU_SUPPORTS_DYNAREC, 12,12, 9, 9, 9}, + {"Cx486DX4/100", CPU_Cx486DX4, 100000000, 3, 0x480, 0, 0x361f, CPU_SUPPORTS_DYNAREC, 15,15, 9, 9, 12}, + + /*Cyrix 5x86*/ + {"Cx5x86/80", CPU_Cx5x86, 80000000, 2, 0x480, 0, 0x002f, CPU_SUPPORTS_DYNAREC, 14,14, 6, 6, 10}, /*If we're including the Pentium 50, might as well include this*/ + {"Cx5x86/100", CPU_Cx5x86, 100000000, 3, 0x480, 0, 0x002f, CPU_SUPPORTS_DYNAREC, 15,15, 9, 9, 12}, + {"Cx5x86/120", CPU_Cx5x86, 120000000, 3, 0x480, 0, 0x002f, CPU_SUPPORTS_DYNAREC, 21,21, 9, 9, 15}, + {"Cx5x86/133", CPU_Cx5x86, 133333333, 4, 0x480, 0, 0x002f, CPU_SUPPORTS_DYNAREC, 24,24,12,12, 16}, + {"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} +}; + +#if defined(USE_NEW_DYNAREC) || (defined(DEV_BRANCH) && defined(USE_CYRIX_6X86)) +CPU cpus_6x863V[] = { + /*Cyrix 6x86*/ + {"Cx6x86/P90", CPU_Cx6x86, 80000000, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 8, 8, 6, 6, 10}, + {"Cx6x86/PR120+", CPU_Cx6x86, 100000000, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 12}, + {"Cx6x86/PR133+", CPU_Cx6x86, 110000000, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 14}, + {"Cx6x86/PR150+", CPU_Cx6x86, 120000000, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 14}, + {"Cx6x86/PR166+", CPU_Cx6x86, 133333333, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16}, + {"Cx6x86/PR200+", CPU_Cx6x86, 150000000, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 18}, + {"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} +}; + +CPU cpus_6x86[] = { + /*Cyrix 6x86*/ + {"Cx6x86/P90", CPU_Cx6x86, 80000000, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 8, 8, 6, 6, 10}, + {"Cx6x86/PR120+", CPU_Cx6x86, 100000000, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 12}, + {"Cx6x86/PR133+", CPU_Cx6x86, 110000000, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 14}, + {"Cx6x86/PR150+", CPU_Cx6x86, 120000000, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 14}, + {"Cx6x86/PR166+", CPU_Cx6x86, 133333333, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16}, + {"Cx6x86/PR200+", CPU_Cx6x86, 150000000, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 18}, + + /*Cyrix 6x86L*/ + {"Cx6x86L/PR133+", CPU_Cx6x86L, 110000000, 2, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 14}, + {"Cx6x86L/PR150+", CPU_Cx6x86L, 120000000, 2, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 14}, + {"Cx6x86L/PR166+", CPU_Cx6x86L, 133333333, 2, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16}, + {"Cx6x86L/PR200+", CPU_Cx6x86L, 150000000, 2, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 18}, + + /*Cyrix 6x86MX/MII*/ + {"Cx6x86MX/PR166", CPU_Cx6x86MX, 133333333, 2, 0x600, 0x600, 0x0451, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16}, + {"Cx6x86MX/PR200", CPU_Cx6x86MX, 166666666, 5/2, 0x600, 0x600, 0x0452, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20}, + {"Cx6x86MX/PR233", CPU_Cx6x86MX, 187500000, 5/2, 0x600, 0x600, 0x0452, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 45/2}, + {"Cx6x86MX/PR266", CPU_Cx6x86MX, 208333333, 5/2, 0x600, 0x600, 0x0452, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 17,17, 7, 7, 25}, + {"MII/PR300", CPU_Cx6x86MX, 233333333, 7/2, 0x601, 0x601, 0x0852, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,11,11, 28}, + {"MII/PR333", CPU_Cx6x86MX, 250000000, 3, 0x601, 0x601, 0x0853, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 23,23, 9, 9, 30}, + {"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} + }; +#endif + +#ifdef USE_NEW_DYNAREC + CPU cpus_6x86SS7[] = { + /*Cyrix 6x86*/ + {"Cx6x86/P90", CPU_Cx6x86, 80000000, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 8, 8, 6, 6, 10}, + {"Cx6x86/PR120+", CPU_Cx6x86, 100000000, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 12}, + {"Cx6x86/PR133+", CPU_Cx6x86, 110000000, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 14}, + {"Cx6x86/PR150+", CPU_Cx6x86, 120000000, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 14}, + {"Cx6x86/PR166+", CPU_Cx6x86, 133333333, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16}, + {"Cx6x86/PR200+", CPU_Cx6x86, 150000000, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 18}, + + /*Cyrix 6x86L*/ + {"Cx6x86L/PR133+", CPU_Cx6x86L, 110000000, 2, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 14}, + {"Cx6x86L/PR150+", CPU_Cx6x86L, 120000000, 2, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 14}, + {"Cx6x86L/PR166+", CPU_Cx6x86L, 133333333, 2, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16}, + {"Cx6x86L/PR200+", CPU_Cx6x86L, 150000000, 2, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 18}, + + /*Cyrix 6x86MX/MII*/ + {"Cx6x86MX/PR166", CPU_Cx6x86MX, 133333333, 2, 0x600, 0x600, 0x0451, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16}, + {"Cx6x86MX/PR200", CPU_Cx6x86MX, 166666666, 5/2, 0x600, 0x600, 0x0452, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20}, + {"Cx6x86MX/PR233", CPU_Cx6x86MX, 187500000, 5/2, 0x600, 0x600, 0x0452, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 45/2}, + {"Cx6x86MX/PR266", CPU_Cx6x86MX, 208333333, 5/2, 0x600, 0x600, 0x0452, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 17,17, 7, 7, 25}, + {"MII/PR300", CPU_Cx6x86MX, 233333333, 7/2, 0x601, 0x601, 0x0852, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,11,11, 28}, + {"MII/PR333", CPU_Cx6x86MX, 250000000, 3, 0x601, 0x601, 0x0853, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 23,23, 9, 9, 30}, + {"MII/PR366", CPU_Cx6x86MX, 250000000, 5/2, 0x601, 0x601, 0x0853, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 23,23, 7, 7, 30}, + {"MII/PR400", CPU_Cx6x86MX, 285000000, 3, 0x601, 0x601, 0x0853, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27, 9, 9, 34}, + {"MII/PR433", CPU_Cx6x86MX, 300000000, 3, 0x601, 0x601, 0x0853, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27, 9, 9, 36}, + {"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} + }; +#endif + +CPU cpus_WinChip[] = { + /*IDT WinChip*/ + {"WinChip 75", CPU_WINCHIP, 75000000, 3/2, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 8, 8, 4, 4, 9}, + {"WinChip 90", CPU_WINCHIP, 90000000, 3/2, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 9, 9, 4, 4, 21/2}, + {"WinChip 100", CPU_WINCHIP, 100000000, 3/2, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 9, 9, 4, 4, 12}, + {"WinChip 120", CPU_WINCHIP, 120000000, 2, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 12, 12, 6, 6, 14}, + {"WinChip 133", CPU_WINCHIP, 133333333, 2, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 12, 12, 6, 6, 16}, + {"WinChip 150", CPU_WINCHIP, 150000000, 5/2, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 15, 15, 7, 7, 35/2}, + {"WinChip 166", CPU_WINCHIP, 166666666, 5/2, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 15, 15, 7, 7, 40}, + {"WinChip 180", CPU_WINCHIP, 180000000, 3, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 21}, + {"WinChip 200", CPU_WINCHIP, 200000000, 3, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 24}, + {"WinChip 225", CPU_WINCHIP, 225000000, 3, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 27}, + {"WinChip 240", CPU_WINCHIP, 240000000, 4, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 24, 24, 12, 12, 28}, +#ifdef USE_NEW_DYNAREC + {"WinChip 2/200", CPU_WINCHIP2, 200000000, 3, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 24}, + {"WinChip 2/225", CPU_WINCHIP2, 225000000, 3, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 27}, + {"WinChip 2/240", CPU_WINCHIP2, 240000000, 4, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 24, 24, 12, 12, 30}, + {"WinChip 2/250", CPU_WINCHIP2, 250000000, 3, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 24, 24, 12, 12, 30}, + {"WinChip 2A/200", CPU_WINCHIP2, 200000000, 3, 0x587, 0x587, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 24}, + {"WinChip 2A/233", CPU_WINCHIP2, 233333333, 7/2, 0x587, 0x587, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, (7*8)/2}, +#endif + {"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} +}; + +#ifdef USE_NEW_DYNAREC +CPU cpus_WinChip_SS7[] = { + /*IDT WinChip*/ + {"WinChip 75", CPU_WINCHIP, 75000000, 3/2, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 8, 8, 4, 4, 9}, + {"WinChip 90", CPU_WINCHIP, 90000000, 3/2, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 9, 9, 4, 4, 21/2}, + {"WinChip 100", CPU_WINCHIP, 100000000, 3/2, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 9, 9, 4, 4, 12}, + {"WinChip 120", CPU_WINCHIP, 120000000, 2, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 12, 12, 6, 6, 14}, + {"WinChip 133", CPU_WINCHIP, 133333333, 2, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 12, 12, 6, 6, 16}, + {"WinChip 150", CPU_WINCHIP, 150000000, 5/2, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 15, 15, 7, 7, 35/2}, + {"WinChip 166", CPU_WINCHIP, 166666666, 5/2, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 15, 15, 7, 7, 40}, + {"WinChip 180", CPU_WINCHIP, 180000000, 3, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 21}, + {"WinChip 200", CPU_WINCHIP, 200000000, 3, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 24}, + {"WinChip 225", CPU_WINCHIP, 225000000, 3, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 27}, + {"WinChip 240", CPU_WINCHIP, 240000000, 4, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 24, 24, 12, 12, 28}, + {"WinChip 2/200", CPU_WINCHIP2, 200000000, 3, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 3*8}, + {"WinChip 2/225", CPU_WINCHIP2, 225000000, 3, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 3*9}, + {"WinChip 2/240", CPU_WINCHIP2, 240000000, 4, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 24, 24, 12, 12, 30}, + {"WinChip 2/250", CPU_WINCHIP2, 250000000, 3, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 24, 24, 12, 12, 30}, + {"WinChip 2A/200", CPU_WINCHIP2, 200000000, 3, 0x587, 0x587, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 3*8}, + {"WinChip 2A/233", CPU_WINCHIP2, 233333333, 7/2, 0x587, 0x587, 0, CPU_SUPPORTS_DYNAREC, 21, 21, 9, 9, (7*8)/2}, + {"WinChip 2A/266", CPU_WINCHIP2, 233333333, 7/3, 0x587, 0x587, 0, CPU_SUPPORTS_DYNAREC, 21, 21, 7, 7, 28}, + {"WinChip 2A/300", CPU_WINCHIP2, 250000000, 5/2, 0x587, 0x587, 0, CPU_SUPPORTS_DYNAREC, 24, 24, 8, 8, 30}, + {"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} +}; +#endif + +CPU cpus_Pentium5V[] = { + /*Intel Pentium (5V, socket 4)*/ + {"Pentium 60", CPU_PENTIUM, 60000000, 1, 0x517, 0x517, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6,3,3, 7}, + {"Pentium 66", CPU_PENTIUM, 66666666, 1, 0x517, 0x517, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6,3,3, 8}, + {"Pentium OverDrive 120", CPU_PENTIUM, 120000000, 2, 0x51A, 0x51A, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6, 14}, + {"Pentium OverDrive 133", CPU_PENTIUM, 133333333, 2, 0x51A, 0x51A, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6, 16}, + {"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} +}; + +CPU cpus_Pentium5V50[] = { + /*Intel Pentium (5V, socket 4, including 50 MHz FSB)*/ + {"Pentium 50 (Q0399)", CPU_PENTIUM, 50000000, 1, 0x513, 0x513, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 4, 4,3,3, 6}, + {"Pentium 60", CPU_PENTIUM, 60000000, 1, 0x517, 0x517, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6,3,3, 7}, + {"Pentium 66", CPU_PENTIUM, 66666666, 1, 0x517, 0x517, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6,3,3, 8}, + {"Pentium OverDrive 100", CPU_PENTIUM, 100000000, 2, 0x51A, 0x51A, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 8, 8,6,6, 12}, + {"Pentium OverDrive 120", CPU_PENTIUM, 120000000, 2, 0x51A, 0x51A, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6, 14}, + {"Pentium OverDrive 133", CPU_PENTIUM, 133333333, 2, 0x51A, 0x51A, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6, 16}, + {"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} +}; + +CPU cpus_PentiumS5[] = { + /*Intel Pentium (Socket 5)*/ + {"Pentium 75", CPU_PENTIUM, 75000000, 3/2, 0x522, 0x522, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7,4,4, 9}, + {"Pentium OverDrive MMX 75", CPU_PENTIUMMMX, 75000000, 3/2, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7,4,4, 9}, + {"Pentium 90", CPU_PENTIUM, 90000000, 3/2, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9,4,4, 21/2}, + {"Pentium 100/50", CPU_PENTIUM, 100000000, 2, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10,6,6, 12}, + {"Pentium 100/66", CPU_PENTIUM, 100000000, 3/2, 0x526, 0x526, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9,4,4, 12}, + {"Pentium 120", CPU_PENTIUM, 120000000, 2, 0x526, 0x526, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6, 14}, + + /*Intel Pentium OverDrive*/ + {"Pentium OverDrive 125", CPU_PENTIUM, 125000000, 3, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,7,7, 16}, + {"Pentium OverDrive 150", CPU_PENTIUM, 150000000, 5/2, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7, 35/2}, + {"Pentium OverDrive 166", CPU_PENTIUM, 166666666, 5/2, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7, 40}, + {"Pentium OverDrive MMX 125", CPU_PENTIUMMMX, 125000000, 5/2, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,7,7, 15}, + {"Pentium OverDrive MMX 150/60", CPU_PENTIUMMMX, 150000000, 5/2, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7, 35/2}, + {"Pentium OverDrive MMX 166", CPU_PENTIUMMMX, 166000000, 5/2, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7, 20}, + {"Pentium OverDrive MMX 180", CPU_PENTIUMMMX, 180000000, 3, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9, 21}, + {"Pentium OverDrive MMX 200", CPU_PENTIUMMMX, 200000000, 3, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9, 24}, + {"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} +}; + +CPU cpus_Pentium3V[] = { + /*Intel Pentium*/ + {"Pentium 75", CPU_PENTIUM, 75000000, 3/2, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7, 4, 4, 9}, + {"Pentium OverDrive MMX 75", CPU_PENTIUMMMX, 75000000, 3/2, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7, 4, 4, 9}, + {"Pentium 90", CPU_PENTIUM, 90000000, 3/2, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 4, 4, 21/2}, + {"Pentium 100/50", CPU_PENTIUM, 100000000, 2, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 12}, + {"Pentium 100/66", CPU_PENTIUM, 100000000, 3/2, 0x526, 0x526, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 4, 4, 12}, + {"Pentium 120", CPU_PENTIUM, 120000000, 2, 0x526, 0x526, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 14}, + {"Pentium 133", CPU_PENTIUM, 133333333, 2, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16}, + {"Pentium 150", CPU_PENTIUM, 150000000, 5/2, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 35/2}, + {"Pentium 166", CPU_PENTIUM, 166666666, 5/2, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20}, + {"Pentium 200", CPU_PENTIUM, 200000000, 3, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24}, + + /*Intel Pentium OverDrive*/ + {"Pentium OverDrive 125", CPU_PENTIUM, 125000000, 5/2, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 7, 7, 15}, + {"Pentium OverDrive 150", CPU_PENTIUM, 150000000, 5/2, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 35/2}, + {"Pentium OverDrive 166", CPU_PENTIUM, 166666666, 5/2, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20}, + {"Pentium OverDrive MMX 125", CPU_PENTIUMMMX, 125000000, 5/2, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 7, 7, 15}, + {"Pentium OverDrive MMX 150/60", CPU_PENTIUMMMX, 150000000, 5/2, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 35/2}, + {"Pentium OverDrive MMX 166", CPU_PENTIUMMMX, 166000000, 5/2, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20}, + {"Pentium OverDrive MMX 180", CPU_PENTIUMMMX, 180000000, 3, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 21}, + {"Pentium OverDrive MMX 200", CPU_PENTIUMMMX, 200000000, 3, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24}, + {"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} +}; + +CPU cpus_Pentium[] = { + /*Intel Pentium*/ + {"Pentium 75", CPU_PENTIUM, 75000000, 3/2, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7, 4, 4, 9}, + {"Pentium OverDrive MMX 75", CPU_PENTIUMMMX, 75000000, 3/2, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7, 4, 4, 9}, + {"Pentium 90", CPU_PENTIUM, 90000000, 3/2, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 4, 4, 21/2}, + {"Pentium 100/50", CPU_PENTIUM, 100000000, 2, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 12}, + {"Pentium 100/66", CPU_PENTIUM, 100000000, 3/2, 0x526, 0x526, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 4, 4, 12}, + {"Pentium 120", CPU_PENTIUM, 120000000, 2, 0x526, 0x526, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 14}, + {"Pentium 133", CPU_PENTIUM, 133333333, 2, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16}, + {"Pentium 150", CPU_PENTIUM, 150000000, 5/2, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 35/2}, + {"Pentium 166", CPU_PENTIUM, 166666666, 5/2, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20}, + {"Pentium 200", CPU_PENTIUM, 200000000, 3, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24}, + + /*Intel Pentium MMX*/ + {"Pentium MMX 166", CPU_PENTIUMMMX, 166666666, 5/2, 0x543, 0x543, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20}, + {"Pentium MMX 200", CPU_PENTIUMMMX, 200000000, 3, 0x543, 0x543, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24}, + {"Pentium MMX 233", CPU_PENTIUMMMX, 233333333, 7/2, 0x543, 0x543, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,10,10, 28}, + + /*Mobile Pentium*/ + {"Mobile Pentium MMX 120", CPU_PENTIUMMMX, 120000000, 2, 0x543, 0x543, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 14}, + {"Mobile Pentium MMX 133", CPU_PENTIUMMMX, 133333333, 2, 0x543, 0x543, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16}, + {"Mobile Pentium MMX 150", CPU_PENTIUMMMX, 150000000, 5/2, 0x544, 0x544, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 35/2}, + {"Mobile Pentium MMX 166", CPU_PENTIUMMMX, 166666666, 5/2, 0x544, 0x544, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20}, + {"Mobile Pentium MMX 200", CPU_PENTIUMMMX, 200000000, 3, 0x581, 0x581, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24}, + {"Mobile Pentium MMX 233", CPU_PENTIUMMMX, 233333333, 7/2, 0x581, 0x581, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,10,10, 28}, + {"Mobile Pentium MMX 266", CPU_PENTIUMMMX, 266666666, 4, 0x582, 0x582, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24,12,12, 32}, + {"Mobile Pentium MMX 300", CPU_PENTIUMMMX, 300000000, 9/2, 0x582, 0x582, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 36}, + + /*Intel Pentium OverDrive*/ + {"Pentium OverDrive 125", CPU_PENTIUM, 125000000, 5/2, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 7, 7, 15}, + {"Pentium OverDrive 150", CPU_PENTIUM, 150000000, 5/2, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 35/2}, + {"Pentium OverDrive 166", CPU_PENTIUM, 166666666, 5/2, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20}, + {"Pentium OverDrive MMX 125", CPU_PENTIUMMMX, 125000000, 5/2, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 7, 7, 15}, + {"Pentium OverDrive MMX 150/60", CPU_PENTIUMMMX, 150000000, 5/2, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 35/2}, + {"Pentium OverDrive MMX 166", CPU_PENTIUMMMX, 166000000, 5/2, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20}, + {"Pentium OverDrive MMX 180", CPU_PENTIUMMMX, 180000000, 3, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 21}, + {"Pentium OverDrive MMX 200", CPU_PENTIUMMMX, 200000000, 3, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24}, + {"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} +}; + +#if defined(USE_NEW_DYNAREC) || (defined(DEV_BRANCH) && defined(USE_AMD_K)) +CPU cpus_K5[] = { + /*AMD K5 (Socket 5)*/ + {"K5 (5k86) 75 (P75)", CPU_K5, 75000000, 3/2, 0x500, 0x500, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7,4,4, 9}, + {"K5 (SSA/5) 75 (PR75)", CPU_K5, 75000000, 3/2, 0x501, 0x501, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7,4,4, 9}, + {"K5 (5k86) 90 (P90)", CPU_K5, 90000000, 3/2, 0x500, 0x500, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9,4,4, 21/2}, + {"K5 (SSA/5) 90 (PR90)", CPU_K5, 90000000, 3/2, 0x501, 0x501, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9,4,4, 21/2}, + {"K5 (5k86) 100 (P100)", CPU_K5, 100000000, 3/2, 0x500, 0x500, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9,4,4, 12}, + {"K5 (SSA/5) 100 (PR100)", CPU_K5, 100000000, 3/2, 0x501, 0x501, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9,4,4, 12}, + {"K5 (5k86) 90 (PR120)", CPU_5K86, 120000000, 2, 0x511, 0x511, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6, 14}, + {"K5 (5k86) 100 (PR133)", CPU_5K86, 133333333, 2, 0x514, 0x514, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6, 16}, + {"K5 (5k86) 105 (PR150)", CPU_5K86, 150000000, 5/2, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7, 35/2}, + {"K5 (5k86) 116.5 (PR166)", CPU_5K86, 166666666, 5/2, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7, 20}, + {"K5 (5k86) 133 (PR200)", CPU_5K86, 200000000, 3, 0x534, 0x534, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9, 24}, + {"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} +}; + +CPU cpus_K56[] = { + /*AMD K5 (Socket 7)*/ + {"K5 (5k86) 75 (P75)", CPU_K5, 75000000, 3/2, 0x500, 0x500, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7, 4, 4, 9}, + {"K5 (SSA/5) 75 (PR75)", CPU_K5, 75000000, 3/2, 0x501, 0x501, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7, 4, 4, 9}, + {"K5 (5k86) 90 (P90)", CPU_K5, 90000000, 3/2, 0x500, 0x500, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 4, 4, 21/2}, + {"K5 (SSA/5) 90 (PR90)", CPU_K5, 90000000, 3/2, 0x501, 0x501, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 4, 4, 21/2}, + {"K5 (5k86) 100 (P100)", CPU_K5, 100000000, 3/2, 0x500, 0x500, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 4, 4, 12}, + {"K5 (SSA/5) 100 (PR100)", CPU_K5, 100000000, 3/2, 0x501, 0x501, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 4, 4, 12}, + {"K5 (5k86) 90 (PR120)", CPU_5K86, 120000000, 2, 0x511, 0x511, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 14}, + {"K5 (5k86) 100 (PR133)", CPU_5K86, 133333333, 2, 0x514, 0x514, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16}, + {"K5 (5k86) 105 (PR150)", CPU_5K86, 150000000, 5/2, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 35/2}, + {"K5 (5k86) 116.5 (PR166)", CPU_5K86, 166666666, 5/2, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20}, + {"K5 (5k86) 133 (PR200)", CPU_5K86, 200000000, 3, 0x534, 0x534, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24}, + + /*AMD K6 (Socket 7*/ + {"K6 (Model 6) 166", CPU_K6, 166666666, 5/2, 0x561, 0x561, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20}, + {"K6 (Model 6) 200", CPU_K6, 200000000, 3, 0x561, 0x561, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24}, + {"K6 (Model 6) 233", CPU_K6, 233333333, 7/2, 0x561, 0x561, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21, 10, 10, 28}, + {"K6 (Model 7) 200", CPU_K6, 200000000, 3, 0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24}, + {"K6 (Model 7) 233", CPU_K6, 233333333, 7/2, 0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21, 10, 10, 28}, + {"K6 (Model 7) 266", CPU_K6, 266666666, 4, 0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24, 12, 12, 32}, + {"K6 (Model 7) 300", CPU_K6, 300000000, 9/2, 0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27, 13, 13, 36}, +#ifdef USE_NEW_DYNAREC + {"K6-2/233", CPU_K6_2, 233333333, 7/2, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21, 10, 10, 28}, + {"K6-2/266", CPU_K6_2, 266666666, 4, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24, 12, 12, 32}, + {"K6-2/300 AFR-66", CPU_K6_2, 300000000, 9/2, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27, 13, 13, 36}, + {"K6-2/366", CPU_K6_2, 366666666, 11/2, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 33,33, 17, 17, 44}, +#endif + {"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} +}; +#endif + +#ifdef USE_NEW_DYNAREC +CPU cpus_K56_SS7[] = { + /*AMD K5 (Socket 7)*/ + {"K5 (5k86) 75 (P75)", CPU_K5, 75000000, 3/2, 0x500, 0x500, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7, 4, 4, 9}, + {"K5 (SSA/5) 75 (PR75)", CPU_K5, 75000000, 3/2, 0x501, 0x501, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7, 4, 4, 9}, + {"K5 (5k86) 90 (P90)", CPU_K5, 90000000, 3/2, 0x500, 0x500, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 4, 4, 21/2}, + {"K5 (SSA/5) 90 (PR90)", CPU_K5, 90000000, 3/2, 0x501, 0x501, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 4, 4, 21/2}, + {"K5 (5k86) 100 (P100)", CPU_K5, 100000000, 3/2, 0x500, 0x500, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 4, 4, 12}, + {"K5 (SSA/5) 100 (PR100)", CPU_K5, 100000000, 3/2, 0x501, 0x501, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 4, 4, 12}, + {"K5 (5k86) 90 (PR120)", CPU_5K86, 120000000, 2, 0x511, 0x511, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 14}, + {"K5 (5k86) 100 (PR133)", CPU_5K86, 133333333, 2, 0x514, 0x514, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16}, + {"K5 (5k86) 105 (PR150)", CPU_5K86, 150000000, 5/2, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 35/2}, + {"K5 (5k86) 116.5 (PR166)", CPU_5K86, 166666666, 5/2, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20}, + {"K5 (5k86) 133 (PR200)", CPU_5K86, 200000000, 3, 0x534, 0x534, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24}, + + /*AMD K6 (Socket 7)*/ + {"K6 (Model 6) 166", CPU_K6, 166666666, 5/2, 0x561, 0x561, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20}, + {"K6 (Model 6) 200", CPU_K6, 200000000, 3, 0x561, 0x561, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24}, + {"K6 (Model 6) 233", CPU_K6, 233333333, 7/2, 0x561, 0x561, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,10,10, 28}, + {"K6 (Model 7) 200", CPU_K6, 200000000, 3, 0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24}, + {"K6 (Model 7) 233", CPU_K6, 233333333, 7/2, 0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,10,10, 28}, + {"K6 (Model 7) 266", CPU_K6, 266666666, 4, 0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24,12,12, 32}, + {"K6 (Model 7) 300", CPU_K6, 300000000, 9/2, 0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 36}, + + /*AMD K6-2 (Socket 7/Super Socket 7)*/ + {"K6-2/233", CPU_K6_2, 233333333, 7/2, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21, 21, 10, 10, 28}, + {"K6-2/266", CPU_K6_2, 266666666, 4, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24, 24, 12, 12, 32}, + {"K6-2/300", CPU_K6_2, 300000000, 3, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27, 27, 9, 9, 36}, + {"K6-2/333", CPU_K6_2, 332500000, 7/2, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 30, 30, 11, 11, 40}, + {"K6-2/350", CPU_K6_2C, 350000000, 7/2, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 32, 32, 11, 11, 42}, + {"K6-2/366", CPU_K6_2C, 366666666, 11/2, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 33, 33, 17, 17, 44}, + {"K6-2/380", CPU_K6_2C, 380000000, 4, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 34, 34, 12, 12, 46}, + {"K6-2/400", CPU_K6_2C, 400000000, 4, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 36, 36, 12, 12, 48}, + {"K6-2/450", CPU_K6_2C, 450000000, 9/2, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 41, 41, 14, 14, 54}, + {"K6-2/475", CPU_K6_2C, 475000000, 5, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 43, 43, 15, 15, 57}, + {"K6-2/500", CPU_K6_2C, 500000000, 5, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 45, 45, 15, 15, 60}, + {"K6-2/533", CPU_K6_2C, 533333333, 11/2, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 48, 48, 17, 17, 64}, + {"K6-2/550", CPU_K6_2C, 550000000, 11/2, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 50, 50, 17, 17, 66}, + + /*AMD K6-2+/K6-3/K6-3+ (Super Socket 7)*/ + {"K6-2+/450", CPU_K6_2P, 450000000, 9/2, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 41, 41, 14, 14, 54}, + {"K6-2+/475", CPU_K6_2P, 475000000, 5, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 43, 43, 15, 15, 57}, + {"K6-2+/500", CPU_K6_2P, 500000000, 5, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 45, 45, 15, 15, 60}, + {"K6-2+/533", CPU_K6_2P, 533333333, 11/2, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 48, 48, 17, 17, 64}, + {"K6-2+/550", CPU_K6_2P, 550000000, 11/2, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 50, 50, 17, 17, 66}, + {"K6-III/400", CPU_K6_3, 400000000, 4, 0x591, 0x591, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 36, 36, 12, 12, 48}, + {"K6-III/450", CPU_K6_3, 450000000, 9/2, 0x591, 0x591, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 41, 41, 14, 14, 54}, + {"K6-III+/400", CPU_K6_3P, 400000000, 4, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 36, 36, 12, 12, 48}, + {"K6-III+/450", CPU_K6_3P, 450000000, 9/2, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 41, 41, 14, 14, 54}, + {"K6-III+/475", CPU_K6_3P, 475000000, 5, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 43, 43, 15, 15, 57}, + {"K6-III+/500", CPU_K6_3P, 500000000, 5, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 45, 45, 15, 15, 60}, + {"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} +}; +#endif + +#ifdef DEV_BRANCH +#ifdef USE_I686 +CPU cpus_PentiumPro[] = { + /*Intel Pentium Pro*/ + {"Pentium Pro 50", CPU_PENTIUMPRO, 50000000, 1, 0x612, 0x612, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 4, 4, 3, 3, 6}, + {"Pentium Pro 60" , CPU_PENTIUMPRO, 60000000, 1, 0x612, 0x612, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6, 3, 3, 7}, + {"Pentium Pro 66" , CPU_PENTIUMPRO, 66666666, 1, 0x612, 0x612, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6, 3, 3, 8}, + {"Pentium Pro 75", CPU_PENTIUMPRO, 75000000, 3/2, 0x612, 0x612, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7, 4, 4, 9}, + {"Pentium Pro 150", CPU_PENTIUMPRO, 150000000, 5/2, 0x612, 0x612, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 35/2}, + {"Pentium Pro 166", CPU_PENTIUMPRO, 166666666, 5/2, 0x617, 0x617, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20}, + {"Pentium Pro 180", CPU_PENTIUMPRO, 180000000, 3, 0x617, 0x617, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 21}, + {"Pentium Pro 200", CPU_PENTIUMPRO, 200000000, 3, 0x617, 0x617, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24}, + + /*Intel Pentium II OverDrive*/ + {"Pentium II Overdrive 50", CPU_PENTIUM2D, 50000000, 1, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 4, 4, 3, 3, 6}, + {"Pentium II Overdrive 60", CPU_PENTIUM2D, 60000000, 1, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6, 3, 3, 7}, + {"Pentium II Overdrive 66", CPU_PENTIUM2D, 66666666, 1, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6, 3, 3, 8}, + {"Pentium II Overdrive 75", CPU_PENTIUM2D, 75000000, 3/2, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7, 4, 4, 9}, + {"Pentium II Overdrive 210", CPU_PENTIUM2D, 210000000, 7/2, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 17,17, 7, 7, 25}, + {"Pentium II Overdrive 233", CPU_PENTIUM2D, 233333333, 7/2, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,10,10, 28}, + {"Pentium II Overdrive 240", CPU_PENTIUM2D, 240000000, 4, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24,12,12, 29}, + {"Pentium II Overdrive 266", CPU_PENTIUM2D, 266666666, 4, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24,12,12, 32}, + {"Pentium II Overdrive 270", CPU_PENTIUM2D, 270000000, 9/2, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 25,25,12,12, 33}, + {"Pentium II Overdrive 300/66", CPU_PENTIUM2D, 300000000, 9/2, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 25,25,12,12, 36}, + {"Pentium II Overdrive 300/60", CPU_PENTIUM2D, 300000000, 5, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 36}, + {"Pentium II Overdrive 333", CPU_PENTIUM2D, 333333333, 5, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 40}, + {"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} +}; + +CPU cpus_PentiumII[] = { + /*Intel Pentium II Klamath*/ + {"Pentium II Klamath 50", CPU_PENTIUM2, 50000000, 1, 0x634, 0x634, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 4, 4, 3, 3, 6}, + {"Pentium II Klamath 60", CPU_PENTIUM2, 60000000, 1, 0x634, 0x634, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6, 3, 3, 7}, + {"Pentium II Klamath 66", CPU_PENTIUM2, 66666666, 1, 0x634, 0x634, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6, 3, 3, 8}, + {"Pentium II Klamath 75", CPU_PENTIUM2, 75000000, 3/2, 0x634, 0x634, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7, 4, 4, 9}, + {"Pentium II Klamath 233", CPU_PENTIUM2, 233333333, 7/2, 0x634, 0x634, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,10,10, 28}, + {"Pentium II Klamath 266", CPU_PENTIUM2, 266666666, 4, 0x634, 0x634, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24,12,12, 29}, + {"Pentium II Klamath 300/66", CPU_PENTIUM2, 300000000, 9/2, 0x634, 0x634, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 25,25,12,12, 36}, + + /*Intel Pentium II Deschutes*/ + {"Pentium II Deschutes 50", CPU_PENTIUM2D, 50000000, 1, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 4, 4, 3, 3, 6}, + {"Pentium II Deschutes 60", CPU_PENTIUM2D, 60000000, 1, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6, 3, 3, 7}, + {"Pentium II Deschutes 66", CPU_PENTIUM2D, 66666666, 1, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6, 3, 3, 8}, + {"Pentium II Deschutes 75", CPU_PENTIUM2D, 75000000, 3/2, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7, 4, 4, 9}, + {"Pentium II Deschutes 266", CPU_PENTIUM2D, 266666666, 4, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24,12,12, 29}, + {"Pentium II Deschutes 300/66", CPU_PENTIUM2D, 300000000, 9/2, 0x651, 0x651, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 25,25,12,12, 36}, + {"Pentium II Deschutes 333", CPU_PENTIUM2D, 333333333, 5, 0x651, 0x651, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 40}, + {"Pentium II Deschutes 350", CPU_PENTIUM2D, 350000000, 7/2, 0x651, 0x651, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 32,32,11,11, 42}, + {"Pentium II Deschutes 400", CPU_PENTIUM2D, 400000000, 4, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 36,36,12,12, 48}, + {"Pentium II Deschutes 450", CPU_PENTIUM2D, 450000000, 9/2, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 41,41,14,14, 54}, + {"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} + +}; + +CPU cpus_Celeron[] = { // Mendocino Celerons. Exact architecture as the P2D series. Intended for + // the PGA370 boards but they were capable to fit on a PGA 370 to Slot 1 + // adaptor card so they work on Slot 1 motherboards too!. + + // The 100Mhz Mendocino is only meant to not cause any struggle + // to the recompiler. + {"Celeron Mendocino 100", CPU_PENTIUM2D, 100000000, 3/2, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 12}, + {"Celeron Mendocino 333", CPU_PENTIUM2D, 333333333, 5, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 40}, + {"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} +}; +#endif +#endif +CPU cpus_Cyrix3[] = { + /*VIA Cyrix III (Samuel)*/ + {"Cyrix III 66", CPU_CYRIX3S, 66666666, 1, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 8}, /*66 MHz version*/ + {"Cyrix III 233", CPU_CYRIX3S, 233333333, 3.5, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC, 21, 21, 9, 9, 28}, + {"Cyrix III 266", CPU_CYRIX3S, 266666666, 4, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC, 24, 24, 12, 12, 32}, + {"Cyrix III 300", CPU_CYRIX3S, 300000000, 4.5, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC, 27, 27, 13, 13, 36}, + {"Cyrix III 333", CPU_CYRIX3S, 333333333, 5, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC, 30, 30, 15, 15, 40}, + {"Cyrix III 350", CPU_CYRIX3S, 350000000, 3.5, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC, 32, 32, 11, 11, 42}, + {"Cyrix III 400", CPU_CYRIX3S, 400000000, 4, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC, 36, 36, 12, 12, 48}, + {"Cyrix III 450", CPU_CYRIX3S, 450000000, 4.5, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC, 41, 41, 14, 14, 54}, /*^ is lower P2 speeds to allow emulation below 466 mhz*/ + {"Cyrix III 500", CPU_CYRIX3S, 500000000, 5, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC, 45, 45, 15, 15, 60}, + {"Cyrix III 550", CPU_CYRIX3S, 550000000, 5.5, 0x662, 0x662, 0, CPU_SUPPORTS_DYNAREC, 50, 50, 17, 17, 66}, + {"Cyrix III 600", CPU_CYRIX3S, 600000000, 6, 0x662, 0x662, 0, CPU_SUPPORTS_DYNAREC, 54, 54, 18, 18, 72}, + {"Cyrix III 650", CPU_CYRIX3S, 650000000, 6.5, 0x662, 0x662, 0, CPU_SUPPORTS_DYNAREC, 58, 58, 20, 20, 78}, + {"Cyrix III 700", CPU_CYRIX3S, 700000000, 7, 0x662, 0x662, 0, CPU_SUPPORTS_DYNAREC, 62, 62, 21, 21, 84}, + {"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} }; \ No newline at end of file diff --git a/src/machines/m_at_socket8.c b/src/machines/m_at_socket8.c new file mode 100644 index 000000000..1b662405c --- /dev/null +++ b/src/machines/m_at_socket8.c @@ -0,0 +1,300 @@ +/* + * 86Box A hypervisor and IBM PC system emulator that specializes in + * running old operating systems and software designed for IBM + * PC systems and compatibles from 1981 through fairly recent + * system designs based on the PCI bus. + * + * This file is part of the 86Box distribution. + * + * Implementation of Socket 8 and Slot 1 machines. + * + * + * + * Authors: Miran Grca, + * + * Copyright 2016-2019 Miran Grca. + */ +#include +#include +#include +#include +#include +#include "86box.h" +#include "mem.h" +#include "86box_io.h" +#include "rom.h" +#include "pci.h" +#include "device.h" +#include "chipset.h" +#include "hdc.h" +#include "hdc_ide.h" +#include "keyboard.h" +#include "intel_flash.h" +#include "intel_sio.h" +#include "piix.h" +#include "sio.h" +#include "sst_flash.h" +#include "hwm.h" +#include "video.h" +#include "cpu.h" +#include "machine.h" + + +#if defined(DEV_BRANCH) && defined(USE_I686) + + +int +machine_at_i440fx_init(const machine_t *model) +{ + int ret; + + ret = bios_load_linear(L"roms/machines/440fx/ntmaw501.bin", + 0x000e0000, 131072, 0); + + if (bios_only || !ret) + return ret; + + machine_at_common_init(model); + + pci_init(PCI_CONFIG_TYPE_1); + pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0); + pci_register_slot(0x0E, PCI_CARD_NORMAL, 1, 2, 3, 4); + pci_register_slot(0x0D, PCI_CARD_NORMAL, 2, 3, 4, 1); + pci_register_slot(0x0C, PCI_CARD_NORMAL, 3, 4, 1, 2); + pci_register_slot(0x0B, PCI_CARD_NORMAL, 4, 1, 2, 3); + pci_register_slot(0x0A, PCI_CARD_NORMAL, 1, 2, 3, 4); + pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0); + device_add(&i440fx_device); + device_add(&piix3_device); + device_add(&keyboard_ps2_pci_device); + device_add(&fdc37c665_device); + device_add(&intel_flash_bxt_device); + + return ret; +} + + +int +machine_at_s1668_init(const machine_t *model) +{ + int ret; + + ret = bios_load_linear(L"roms/machines/tpatx/s1668p.rom", + 0x000e0000, 131072, 0); + + if (bios_only || !ret) + return ret; + + machine_at_common_init(model); + + pci_init(PCI_CONFIG_TYPE_1); + pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0); + pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0); + pci_register_slot(0x0E, PCI_CARD_NORMAL, 1, 2, 3, 4); + pci_register_slot(0x0D, PCI_CARD_NORMAL, 2, 3, 4, 1); + pci_register_slot(0x0C, PCI_CARD_NORMAL, 3, 4, 1, 2); + pci_register_slot(0x0B, PCI_CARD_NORMAL, 4, 1, 2, 3); + pci_register_slot(0x0A, PCI_CARD_NORMAL, 1, 2, 3, 4); + device_add(&i440fx_device); + device_add(&piix3_device); + device_add(&keyboard_ps2_ami_pci_device); + device_add(&fdc37c665_device); + device_add(&intel_flash_bxt_device); + + return ret; +} + +#endif +int +machine_at_6abx3_init(const machine_t *model) +{ + int ret; + + ret = bios_load_linear(L"roms/machines/6abx3/6abx3h1.bin", + 0x000c0000, 262144, 0); + + if (bios_only || !ret) + return ret; + + machine_at_common_init_ex(model, 2); + + pci_init(PCI_CONFIG_TYPE_1); + pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0); + pci_register_slot(0x08, PCI_CARD_NORMAL, 1, 2, 3, 4); + pci_register_slot(0x09, PCI_CARD_NORMAL, 2, 3, 4, 1); + pci_register_slot(0x0B, PCI_CARD_NORMAL, 4, 1, 2, 3); + pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2); + pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4); + pci_register_slot(0x01, PCI_CARD_NORMAL, 1, 2, 3, 4); + device_add(&i440bx_device); + device_add(&piix4_device); + device_add(&keyboard_ps2_pci_device); + device_add(&w83877tf_device); + // device_add(&w83977tf_device); + // device_add(&intel_flash_bxt_device); + // device_add(&sst_flash_29ee020_device); + device_add(&intel_flash_bxt_device); + + return ret; +} +#if defined(DEV_BRANCH) && defined(USE_I686) +int +machine_at_p2bls_init(const machine_t *model) +{ + int ret; + + ret = bios_load_linear(L"roms/machines/p2bls/1014ls.003", + 0x000c0000, 262144, 0); + + if (bios_only || !ret) + return ret; + + machine_at_common_init_ex(model, 2); + + pci_init(PCI_CONFIG_TYPE_1); + pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0); + pci_register_slot(0x06, PCI_CARD_NORMAL, 4, 1, 2, 3); + pci_register_slot(0x07, PCI_CARD_NORMAL, 3, 4, 1, 2); + pci_register_slot(0x0B, PCI_CARD_NORMAL, 2, 3, 4, 1); + pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 2, 3, 4); + pci_register_slot(0x09, PCI_CARD_NORMAL, 4, 1, 2, 3); + pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2); + pci_register_slot(0x04, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4); + pci_register_slot(0x01, PCI_CARD_NORMAL, 1, 2, 3, 4); + device_add(&i440bx_device); + device_add(&piix4_device); + device_add(&keyboard_ps2_pci_device); + device_add(&w83977ef_device); + device_add(&sst_flash_39sf020_device); + + hwm_values_t machine_hwm = { + { /* fan speeds */ + 3000, /* Chassis */ + 3000, /* CPU */ + 3000, /* Power */ + 0 + }, { /* temperatures */ + 30, /* MB */ + 0, /* unused */ + 27, /* CPU */ + 0 + }, { /* voltages */ + 2050, /* VCORE (2.05V by default) */ + 0, /* unused */ + 3300, /* +3.3V */ + RESISTOR_DIVIDER(5000, 11, 16), /* +5V (divider values bruteforced) */ + RESISTOR_DIVIDER(12000, 28, 10), /* +12V (28K/10K divider suggested in the W83781D datasheet) */ + RESISTOR_DIVIDER(12000, 853, 347), /* -12V (divider values bruteforced) */ + RESISTOR_DIVIDER(5000, 1, 2), /* -5V (divider values bruteforced) */ + 0 + } + }; + if (model->cpu[cpu_manufacturer].cpus[cpu_effective].cpu_type == CPU_PENTIUM2) + machine_hwm.voltages[0] = 2800; /* set higher VCORE (2.8V) for Klamath */ + hwm_set_values(machine_hwm); + device_add(&as99127f_device); + + return ret; +} + +int +machine_at_borapro_init(const machine_t *model) +{ + //AMI 440ZX Board. Packard Bell OEM of the MSI-6168 + //MIGHT REQUIRE MORE EXCESSIVE TESTING! + //Reports emmersive amounts of RAM like few Intel OEM boards + //we have. + + int ret; + + ret = bios_load_linear(L"roms/machines/borapro/MS6168V2.50", + 0x000c0000, 262144, 0); + + if (bios_only || !ret) + return ret; + + machine_at_common_init_ex(model, 2); + + pci_init(PCI_CONFIG_TYPE_1); + pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0); + pci_register_slot(0x0E, PCI_CARD_NORMAL, 1, 2, 3, 4); + pci_register_slot(0x10, PCI_CARD_NORMAL, 2, 3, 4, 1); + pci_register_slot(0x12, PCI_CARD_NORMAL, 3, 4, 1, 2); + pci_register_slot(0x14, PCI_CARD_NORMAL, 4, 1, 2, 3); + pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4); + pci_register_slot(0x01, PCI_CARD_NORMAL, 1, 2, 3, 4); + device_add(&i440zx_device); + device_add(&piix4e_device); + device_add(&w83977ef_device); + device_add(&keyboard_ps2_ami_pci_device); + device_add(&intel_flash_bxt_device); + + return ret; +} + +int +machine_at_p6bxt_init(const machine_t *model) +{ + int ret; + + ret = bios_load_linear(L"roms/machines/p6bxt/bxt53s.BIN", + 0x000c0000, 262144, 0); + + if (bios_only || !ret) + return ret; + + machine_at_common_init_ex(model, 2); + + pci_init(PCI_CONFIG_TYPE_1); + pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0); + pci_register_slot(0x09, PCI_CARD_NORMAL, 1, 2, 3, 4); + pci_register_slot(0x0A, PCI_CARD_NORMAL, 2, 3, 4, 1); + pci_register_slot(0x0B, PCI_CARD_NORMAL, 3, 4, 1, 2); + pci_register_slot(0x0C, PCI_CARD_NORMAL, 4, 1, 2, 3); + pci_register_slot(0x0D, PCI_CARD_NORMAL, 4, 3, 2, 1); /* Slot 5: Probably the integrated sound chip. */ + pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4); + pci_register_slot(0x01, PCI_CARD_NORMAL, 1, 2, 3, 4); + device_add(&i440bx_device); + device_add(&piix4e_device); + device_add(&w83977tf_device); + device_add(&keyboard_ps2_pci_device); + device_add(&sst_flash_39sf020_device); + + return ret; +} + + +int +machine_at_63a_init(const machine_t *model) +{ + + /* 440ZX Board. 440ZX is basically an underpowered 440BX. There no + difference between to chipsets other than the name. */ + int ret; + + ret = bios_load_linear(L"roms/machines/63a/63a-q3.bin", + 0x000c0000, 262144, 0); + + if (bios_only || !ret) + return ret; + + machine_at_common_init_ex(model, 2); + + pci_init(PCI_CONFIG_TYPE_1); + pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0); + pci_register_slot(0x08, PCI_CARD_NORMAL, 1, 2, 3, 4); + pci_register_slot(0x09, PCI_CARD_NORMAL, 2, 3, 4, 1); + pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2); + pci_register_slot(0x0B, PCI_CARD_NORMAL, 4, 1, 2, 3); + pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 2, 3, 4); // Integrated Sound? + pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4); + pci_register_slot(0x01, PCI_CARD_NORMAL, 1, 2, 3, 4); + device_add(&i440zx_device); + device_add(&piix4e_device); + device_add(&w83977tf_device); + device_add(&keyboard_ps2_pci_device); + device_add(&intel_flash_bxt_device); + + return ret; +} +#endif From 27bb7ad4c855db02b58cdf59308076d15effbf88 Mon Sep 17 00:00:00 2001 From: tiseno100 <58827426+tiseno100@users.noreply.github.com> Date: Wed, 25 Mar 2020 12:27:42 +0200 Subject: [PATCH 26/33] Delete m_at_socket8.c --- src/machines/m_at_socket8.c | 300 ------------------------------------ 1 file changed, 300 deletions(-) delete mode 100644 src/machines/m_at_socket8.c diff --git a/src/machines/m_at_socket8.c b/src/machines/m_at_socket8.c deleted file mode 100644 index 1b662405c..000000000 --- a/src/machines/m_at_socket8.c +++ /dev/null @@ -1,300 +0,0 @@ -/* - * 86Box A hypervisor and IBM PC system emulator that specializes in - * running old operating systems and software designed for IBM - * PC systems and compatibles from 1981 through fairly recent - * system designs based on the PCI bus. - * - * This file is part of the 86Box distribution. - * - * Implementation of Socket 8 and Slot 1 machines. - * - * - * - * Authors: Miran Grca, - * - * Copyright 2016-2019 Miran Grca. - */ -#include -#include -#include -#include -#include -#include "86box.h" -#include "mem.h" -#include "86box_io.h" -#include "rom.h" -#include "pci.h" -#include "device.h" -#include "chipset.h" -#include "hdc.h" -#include "hdc_ide.h" -#include "keyboard.h" -#include "intel_flash.h" -#include "intel_sio.h" -#include "piix.h" -#include "sio.h" -#include "sst_flash.h" -#include "hwm.h" -#include "video.h" -#include "cpu.h" -#include "machine.h" - - -#if defined(DEV_BRANCH) && defined(USE_I686) - - -int -machine_at_i440fx_init(const machine_t *model) -{ - int ret; - - ret = bios_load_linear(L"roms/machines/440fx/ntmaw501.bin", - 0x000e0000, 131072, 0); - - if (bios_only || !ret) - return ret; - - machine_at_common_init(model); - - pci_init(PCI_CONFIG_TYPE_1); - pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0); - pci_register_slot(0x0E, PCI_CARD_NORMAL, 1, 2, 3, 4); - pci_register_slot(0x0D, PCI_CARD_NORMAL, 2, 3, 4, 1); - pci_register_slot(0x0C, PCI_CARD_NORMAL, 3, 4, 1, 2); - pci_register_slot(0x0B, PCI_CARD_NORMAL, 4, 1, 2, 3); - pci_register_slot(0x0A, PCI_CARD_NORMAL, 1, 2, 3, 4); - pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0); - device_add(&i440fx_device); - device_add(&piix3_device); - device_add(&keyboard_ps2_pci_device); - device_add(&fdc37c665_device); - device_add(&intel_flash_bxt_device); - - return ret; -} - - -int -machine_at_s1668_init(const machine_t *model) -{ - int ret; - - ret = bios_load_linear(L"roms/machines/tpatx/s1668p.rom", - 0x000e0000, 131072, 0); - - if (bios_only || !ret) - return ret; - - machine_at_common_init(model); - - pci_init(PCI_CONFIG_TYPE_1); - pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0); - pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0); - pci_register_slot(0x0E, PCI_CARD_NORMAL, 1, 2, 3, 4); - pci_register_slot(0x0D, PCI_CARD_NORMAL, 2, 3, 4, 1); - pci_register_slot(0x0C, PCI_CARD_NORMAL, 3, 4, 1, 2); - pci_register_slot(0x0B, PCI_CARD_NORMAL, 4, 1, 2, 3); - pci_register_slot(0x0A, PCI_CARD_NORMAL, 1, 2, 3, 4); - device_add(&i440fx_device); - device_add(&piix3_device); - device_add(&keyboard_ps2_ami_pci_device); - device_add(&fdc37c665_device); - device_add(&intel_flash_bxt_device); - - return ret; -} - -#endif -int -machine_at_6abx3_init(const machine_t *model) -{ - int ret; - - ret = bios_load_linear(L"roms/machines/6abx3/6abx3h1.bin", - 0x000c0000, 262144, 0); - - if (bios_only || !ret) - return ret; - - machine_at_common_init_ex(model, 2); - - pci_init(PCI_CONFIG_TYPE_1); - pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0); - pci_register_slot(0x08, PCI_CARD_NORMAL, 1, 2, 3, 4); - pci_register_slot(0x09, PCI_CARD_NORMAL, 2, 3, 4, 1); - pci_register_slot(0x0B, PCI_CARD_NORMAL, 4, 1, 2, 3); - pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2); - pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4); - pci_register_slot(0x01, PCI_CARD_NORMAL, 1, 2, 3, 4); - device_add(&i440bx_device); - device_add(&piix4_device); - device_add(&keyboard_ps2_pci_device); - device_add(&w83877tf_device); - // device_add(&w83977tf_device); - // device_add(&intel_flash_bxt_device); - // device_add(&sst_flash_29ee020_device); - device_add(&intel_flash_bxt_device); - - return ret; -} -#if defined(DEV_BRANCH) && defined(USE_I686) -int -machine_at_p2bls_init(const machine_t *model) -{ - int ret; - - ret = bios_load_linear(L"roms/machines/p2bls/1014ls.003", - 0x000c0000, 262144, 0); - - if (bios_only || !ret) - return ret; - - machine_at_common_init_ex(model, 2); - - pci_init(PCI_CONFIG_TYPE_1); - pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0); - pci_register_slot(0x06, PCI_CARD_NORMAL, 4, 1, 2, 3); - pci_register_slot(0x07, PCI_CARD_NORMAL, 3, 4, 1, 2); - pci_register_slot(0x0B, PCI_CARD_NORMAL, 2, 3, 4, 1); - pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 2, 3, 4); - pci_register_slot(0x09, PCI_CARD_NORMAL, 4, 1, 2, 3); - pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2); - pci_register_slot(0x04, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4); - pci_register_slot(0x01, PCI_CARD_NORMAL, 1, 2, 3, 4); - device_add(&i440bx_device); - device_add(&piix4_device); - device_add(&keyboard_ps2_pci_device); - device_add(&w83977ef_device); - device_add(&sst_flash_39sf020_device); - - hwm_values_t machine_hwm = { - { /* fan speeds */ - 3000, /* Chassis */ - 3000, /* CPU */ - 3000, /* Power */ - 0 - }, { /* temperatures */ - 30, /* MB */ - 0, /* unused */ - 27, /* CPU */ - 0 - }, { /* voltages */ - 2050, /* VCORE (2.05V by default) */ - 0, /* unused */ - 3300, /* +3.3V */ - RESISTOR_DIVIDER(5000, 11, 16), /* +5V (divider values bruteforced) */ - RESISTOR_DIVIDER(12000, 28, 10), /* +12V (28K/10K divider suggested in the W83781D datasheet) */ - RESISTOR_DIVIDER(12000, 853, 347), /* -12V (divider values bruteforced) */ - RESISTOR_DIVIDER(5000, 1, 2), /* -5V (divider values bruteforced) */ - 0 - } - }; - if (model->cpu[cpu_manufacturer].cpus[cpu_effective].cpu_type == CPU_PENTIUM2) - machine_hwm.voltages[0] = 2800; /* set higher VCORE (2.8V) for Klamath */ - hwm_set_values(machine_hwm); - device_add(&as99127f_device); - - return ret; -} - -int -machine_at_borapro_init(const machine_t *model) -{ - //AMI 440ZX Board. Packard Bell OEM of the MSI-6168 - //MIGHT REQUIRE MORE EXCESSIVE TESTING! - //Reports emmersive amounts of RAM like few Intel OEM boards - //we have. - - int ret; - - ret = bios_load_linear(L"roms/machines/borapro/MS6168V2.50", - 0x000c0000, 262144, 0); - - if (bios_only || !ret) - return ret; - - machine_at_common_init_ex(model, 2); - - pci_init(PCI_CONFIG_TYPE_1); - pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0); - pci_register_slot(0x0E, PCI_CARD_NORMAL, 1, 2, 3, 4); - pci_register_slot(0x10, PCI_CARD_NORMAL, 2, 3, 4, 1); - pci_register_slot(0x12, PCI_CARD_NORMAL, 3, 4, 1, 2); - pci_register_slot(0x14, PCI_CARD_NORMAL, 4, 1, 2, 3); - pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4); - pci_register_slot(0x01, PCI_CARD_NORMAL, 1, 2, 3, 4); - device_add(&i440zx_device); - device_add(&piix4e_device); - device_add(&w83977ef_device); - device_add(&keyboard_ps2_ami_pci_device); - device_add(&intel_flash_bxt_device); - - return ret; -} - -int -machine_at_p6bxt_init(const machine_t *model) -{ - int ret; - - ret = bios_load_linear(L"roms/machines/p6bxt/bxt53s.BIN", - 0x000c0000, 262144, 0); - - if (bios_only || !ret) - return ret; - - machine_at_common_init_ex(model, 2); - - pci_init(PCI_CONFIG_TYPE_1); - pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0); - pci_register_slot(0x09, PCI_CARD_NORMAL, 1, 2, 3, 4); - pci_register_slot(0x0A, PCI_CARD_NORMAL, 2, 3, 4, 1); - pci_register_slot(0x0B, PCI_CARD_NORMAL, 3, 4, 1, 2); - pci_register_slot(0x0C, PCI_CARD_NORMAL, 4, 1, 2, 3); - pci_register_slot(0x0D, PCI_CARD_NORMAL, 4, 3, 2, 1); /* Slot 5: Probably the integrated sound chip. */ - pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4); - pci_register_slot(0x01, PCI_CARD_NORMAL, 1, 2, 3, 4); - device_add(&i440bx_device); - device_add(&piix4e_device); - device_add(&w83977tf_device); - device_add(&keyboard_ps2_pci_device); - device_add(&sst_flash_39sf020_device); - - return ret; -} - - -int -machine_at_63a_init(const machine_t *model) -{ - - /* 440ZX Board. 440ZX is basically an underpowered 440BX. There no - difference between to chipsets other than the name. */ - int ret; - - ret = bios_load_linear(L"roms/machines/63a/63a-q3.bin", - 0x000c0000, 262144, 0); - - if (bios_only || !ret) - return ret; - - machine_at_common_init_ex(model, 2); - - pci_init(PCI_CONFIG_TYPE_1); - pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0); - pci_register_slot(0x08, PCI_CARD_NORMAL, 1, 2, 3, 4); - pci_register_slot(0x09, PCI_CARD_NORMAL, 2, 3, 4, 1); - pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2); - pci_register_slot(0x0B, PCI_CARD_NORMAL, 4, 1, 2, 3); - pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 2, 3, 4); // Integrated Sound? - pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4); - pci_register_slot(0x01, PCI_CARD_NORMAL, 1, 2, 3, 4); - device_add(&i440zx_device); - device_add(&piix4e_device); - device_add(&w83977tf_device); - device_add(&keyboard_ps2_pci_device); - device_add(&intel_flash_bxt_device); - - return ret; -} -#endif From aee772d773f8ae0f915e75ddfcaa6906a111c24e Mon Sep 17 00:00:00 2001 From: tiseno100 <58827426+tiseno100@users.noreply.github.com> Date: Wed, 25 Mar 2020 12:28:10 +0200 Subject: [PATCH 27/33] mistyped directory --- src/machine/m_at_socket8.c | 566 ++++++++++++++++++++----------------- 1 file changed, 300 insertions(+), 266 deletions(-) diff --git a/src/machine/m_at_socket8.c b/src/machine/m_at_socket8.c index 270c9c178..1b662405c 100644 --- a/src/machine/m_at_socket8.c +++ b/src/machine/m_at_socket8.c @@ -1,266 +1,300 @@ -/* - * 86Box A hypervisor and IBM PC system emulator that specializes in - * running old operating systems and software designed for IBM - * PC systems and compatibles from 1981 through fairly recent - * system designs based on the PCI bus. - * - * This file is part of the 86Box distribution. - * - * Implementation of Socket 8 and Slot 1 machines. - * - * - * - * Authors: Miran Grca, - * - * Copyright 2016-2019 Miran Grca. - */ -#include -#include -#include -#include -#include -#include "86box.h" -#include "mem.h" -#include "86box_io.h" -#include "rom.h" -#include "pci.h" -#include "device.h" -#include "chipset.h" -#include "hdc.h" -#include "hdc_ide.h" -#include "keyboard.h" -#include "intel_flash.h" -#include "intel_sio.h" -#include "piix.h" -#include "sio.h" -#include "sst_flash.h" -#include "hwm.h" -#include "video.h" -#include "cpu.h" -#include "machine.h" - - -#if defined(DEV_BRANCH) && defined(USE_I686) - - -int -machine_at_i440fx_init(const machine_t *model) -{ - int ret; - - ret = bios_load_linear(L"roms/machines/440fx/ntmaw501.bin", - 0x000e0000, 131072, 0); - - if (bios_only || !ret) - return ret; - - machine_at_common_init(model); - - pci_init(PCI_CONFIG_TYPE_1); - pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0); - pci_register_slot(0x0E, PCI_CARD_NORMAL, 1, 2, 3, 4); - pci_register_slot(0x0D, PCI_CARD_NORMAL, 2, 3, 4, 1); - pci_register_slot(0x0C, PCI_CARD_NORMAL, 3, 4, 1, 2); - pci_register_slot(0x0B, PCI_CARD_NORMAL, 4, 1, 2, 3); - pci_register_slot(0x0A, PCI_CARD_NORMAL, 1, 2, 3, 4); - pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0); - device_add(&i440fx_device); - device_add(&piix3_device); - device_add(&keyboard_ps2_pci_device); - device_add(&fdc37c665_device); - device_add(&intel_flash_bxt_device); - - return ret; -} - - -int -machine_at_s1668_init(const machine_t *model) -{ - int ret; - - ret = bios_load_linear(L"roms/machines/tpatx/s1668p.rom", - 0x000e0000, 131072, 0); - - if (bios_only || !ret) - return ret; - - machine_at_common_init(model); - - pci_init(PCI_CONFIG_TYPE_1); - pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0); - pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0); - pci_register_slot(0x0E, PCI_CARD_NORMAL, 1, 2, 3, 4); - pci_register_slot(0x0D, PCI_CARD_NORMAL, 2, 3, 4, 1); - pci_register_slot(0x0C, PCI_CARD_NORMAL, 3, 4, 1, 2); - pci_register_slot(0x0B, PCI_CARD_NORMAL, 4, 1, 2, 3); - pci_register_slot(0x0A, PCI_CARD_NORMAL, 1, 2, 3, 4); - device_add(&i440fx_device); - device_add(&piix3_device); - device_add(&keyboard_ps2_ami_pci_device); - device_add(&fdc37c665_device); - device_add(&intel_flash_bxt_device); - - return ret; -} - -#endif -int -machine_at_6abx3_init(const machine_t *model) -{ - int ret; - - ret = bios_load_linear(L"roms/machines/6abx3/6abx3h1.bin", - 0x000c0000, 262144, 0); - - if (bios_only || !ret) - return ret; - - machine_at_common_init_ex(model, 2); - - pci_init(PCI_CONFIG_TYPE_1); - pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0); - pci_register_slot(0x08, PCI_CARD_NORMAL, 1, 2, 3, 4); - pci_register_slot(0x09, PCI_CARD_NORMAL, 2, 3, 4, 1); - pci_register_slot(0x0B, PCI_CARD_NORMAL, 4, 1, 2, 3); - pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2); - pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4); - pci_register_slot(0x01, PCI_CARD_NORMAL, 1, 2, 3, 4); - device_add(&i440bx_device); - device_add(&piix4_device); - device_add(&keyboard_ps2_pci_device); - device_add(&w83877tf_device); - // device_add(&w83977tf_device); - // device_add(&intel_flash_bxt_device); - // device_add(&sst_flash_29ee020_device); - device_add(&intel_flash_bxt_device); - - return ret; -} -#if defined(DEV_BRANCH) && defined(USE_I686) -int -machine_at_p2bls_init(const machine_t *model) -{ - int ret; - - ret = bios_load_linear(L"roms/machines/p2bls/1014ls.003", - 0x000c0000, 262144, 0); - - if (bios_only || !ret) - return ret; - - machine_at_common_init_ex(model, 2); - - pci_init(PCI_CONFIG_TYPE_1); - pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0); - pci_register_slot(0x06, PCI_CARD_NORMAL, 4, 1, 2, 3); - pci_register_slot(0x07, PCI_CARD_NORMAL, 3, 4, 1, 2); - pci_register_slot(0x0B, PCI_CARD_NORMAL, 2, 3, 4, 1); - pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 2, 3, 4); - pci_register_slot(0x09, PCI_CARD_NORMAL, 4, 1, 2, 3); - pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2); - pci_register_slot(0x04, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4); - pci_register_slot(0x01, PCI_CARD_NORMAL, 1, 2, 3, 4); - device_add(&i440bx_device); - device_add(&piix4_device); - device_add(&keyboard_ps2_pci_device); - device_add(&w83977ef_device); - device_add(&sst_flash_39sf020_device); - - hwm_values_t machine_hwm = { - { /* fan speeds */ - 3000, /* Chassis */ - 3000, /* CPU */ - 3000, /* Power */ - 0 - }, { /* temperatures */ - 30, /* MB */ - 0, /* unused */ - 27, /* CPU */ - 0 - }, { /* voltages */ - 2050, /* VCORE (2.05V by default) */ - 0, /* unused */ - 3300, /* +3.3V */ - RESISTOR_DIVIDER(5000, 11, 16), /* +5V (divider values bruteforced) */ - RESISTOR_DIVIDER(12000, 28, 10), /* +12V (28K/10K divider suggested in the W83781D datasheet) */ - RESISTOR_DIVIDER(12000, 853, 347), /* -12V (divider values bruteforced) */ - RESISTOR_DIVIDER(5000, 1, 2), /* -5V (divider values bruteforced) */ - 0 - } - }; - if (model->cpu[cpu_manufacturer].cpus[cpu_effective].cpu_type == CPU_PENTIUM2) - machine_hwm.voltages[0] = 2800; /* set higher VCORE (2.8V) for Klamath */ - hwm_set_values(machine_hwm); - device_add(&as99127f_device); - - return ret; -} - - -int -machine_at_p6bxt_init(const machine_t *model) -{ - int ret; - - ret = bios_load_linear(L"roms/machines/p6bxt/bxt53s.BIN", - 0x000c0000, 262144, 0); - - if (bios_only || !ret) - return ret; - - machine_at_common_init_ex(model, 2); - - pci_init(PCI_CONFIG_TYPE_1); - pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0); - pci_register_slot(0x09, PCI_CARD_NORMAL, 1, 2, 3, 4); - pci_register_slot(0x0A, PCI_CARD_NORMAL, 2, 3, 4, 1); - pci_register_slot(0x0B, PCI_CARD_NORMAL, 3, 4, 1, 2); - pci_register_slot(0x0C, PCI_CARD_NORMAL, 4, 1, 2, 3); - pci_register_slot(0x0D, PCI_CARD_NORMAL, 4, 3, 2, 1); /* Slot 5: Probably the integrated sound chip. */ - pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4); - pci_register_slot(0x01, PCI_CARD_NORMAL, 1, 2, 3, 4); - device_add(&i440bx_device); - device_add(&piix4e_device); - device_add(&w83977tf_device); - device_add(&keyboard_ps2_pci_device); - device_add(&intel_flash_bxt_device); - - return ret; -} - - -int -machine_at_63a_init(const machine_t *model) -{ - - /* 440ZX Board. 440ZX is basically an underpowered 440BX. There no - difference between to chipsets other than the name. */ - int ret; - - ret = bios_load_linear(L"roms/machines/63a/63a-q3.bin", - 0x000c0000, 262144, 0); - - if (bios_only || !ret) - return ret; - - machine_at_common_init_ex(model, 2); - - pci_init(PCI_CONFIG_TYPE_1); - pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0); - pci_register_slot(0x08, PCI_CARD_NORMAL, 1, 2, 3, 4); - pci_register_slot(0x09, PCI_CARD_NORMAL, 2, 3, 4, 1); - pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2); - pci_register_slot(0x0B, PCI_CARD_NORMAL, 4, 1, 2, 3); - pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 2, 3, 4); // Integrated Sound? - pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4); - pci_register_slot(0x01, PCI_CARD_NORMAL, 1, 2, 3, 4); - device_add(&i440zx_device); - device_add(&piix4e_device); - device_add(&w83977tf_device); - device_add(&keyboard_ps2_pci_device); - device_add(&intel_flash_bxt_device); - - return ret; -} -#endif +/* + * 86Box A hypervisor and IBM PC system emulator that specializes in + * running old operating systems and software designed for IBM + * PC systems and compatibles from 1981 through fairly recent + * system designs based on the PCI bus. + * + * This file is part of the 86Box distribution. + * + * Implementation of Socket 8 and Slot 1 machines. + * + * + * + * Authors: Miran Grca, + * + * Copyright 2016-2019 Miran Grca. + */ +#include +#include +#include +#include +#include +#include "86box.h" +#include "mem.h" +#include "86box_io.h" +#include "rom.h" +#include "pci.h" +#include "device.h" +#include "chipset.h" +#include "hdc.h" +#include "hdc_ide.h" +#include "keyboard.h" +#include "intel_flash.h" +#include "intel_sio.h" +#include "piix.h" +#include "sio.h" +#include "sst_flash.h" +#include "hwm.h" +#include "video.h" +#include "cpu.h" +#include "machine.h" + + +#if defined(DEV_BRANCH) && defined(USE_I686) + + +int +machine_at_i440fx_init(const machine_t *model) +{ + int ret; + + ret = bios_load_linear(L"roms/machines/440fx/ntmaw501.bin", + 0x000e0000, 131072, 0); + + if (bios_only || !ret) + return ret; + + machine_at_common_init(model); + + pci_init(PCI_CONFIG_TYPE_1); + pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0); + pci_register_slot(0x0E, PCI_CARD_NORMAL, 1, 2, 3, 4); + pci_register_slot(0x0D, PCI_CARD_NORMAL, 2, 3, 4, 1); + pci_register_slot(0x0C, PCI_CARD_NORMAL, 3, 4, 1, 2); + pci_register_slot(0x0B, PCI_CARD_NORMAL, 4, 1, 2, 3); + pci_register_slot(0x0A, PCI_CARD_NORMAL, 1, 2, 3, 4); + pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0); + device_add(&i440fx_device); + device_add(&piix3_device); + device_add(&keyboard_ps2_pci_device); + device_add(&fdc37c665_device); + device_add(&intel_flash_bxt_device); + + return ret; +} + + +int +machine_at_s1668_init(const machine_t *model) +{ + int ret; + + ret = bios_load_linear(L"roms/machines/tpatx/s1668p.rom", + 0x000e0000, 131072, 0); + + if (bios_only || !ret) + return ret; + + machine_at_common_init(model); + + pci_init(PCI_CONFIG_TYPE_1); + pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0); + pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0); + pci_register_slot(0x0E, PCI_CARD_NORMAL, 1, 2, 3, 4); + pci_register_slot(0x0D, PCI_CARD_NORMAL, 2, 3, 4, 1); + pci_register_slot(0x0C, PCI_CARD_NORMAL, 3, 4, 1, 2); + pci_register_slot(0x0B, PCI_CARD_NORMAL, 4, 1, 2, 3); + pci_register_slot(0x0A, PCI_CARD_NORMAL, 1, 2, 3, 4); + device_add(&i440fx_device); + device_add(&piix3_device); + device_add(&keyboard_ps2_ami_pci_device); + device_add(&fdc37c665_device); + device_add(&intel_flash_bxt_device); + + return ret; +} + +#endif +int +machine_at_6abx3_init(const machine_t *model) +{ + int ret; + + ret = bios_load_linear(L"roms/machines/6abx3/6abx3h1.bin", + 0x000c0000, 262144, 0); + + if (bios_only || !ret) + return ret; + + machine_at_common_init_ex(model, 2); + + pci_init(PCI_CONFIG_TYPE_1); + pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0); + pci_register_slot(0x08, PCI_CARD_NORMAL, 1, 2, 3, 4); + pci_register_slot(0x09, PCI_CARD_NORMAL, 2, 3, 4, 1); + pci_register_slot(0x0B, PCI_CARD_NORMAL, 4, 1, 2, 3); + pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2); + pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4); + pci_register_slot(0x01, PCI_CARD_NORMAL, 1, 2, 3, 4); + device_add(&i440bx_device); + device_add(&piix4_device); + device_add(&keyboard_ps2_pci_device); + device_add(&w83877tf_device); + // device_add(&w83977tf_device); + // device_add(&intel_flash_bxt_device); + // device_add(&sst_flash_29ee020_device); + device_add(&intel_flash_bxt_device); + + return ret; +} +#if defined(DEV_BRANCH) && defined(USE_I686) +int +machine_at_p2bls_init(const machine_t *model) +{ + int ret; + + ret = bios_load_linear(L"roms/machines/p2bls/1014ls.003", + 0x000c0000, 262144, 0); + + if (bios_only || !ret) + return ret; + + machine_at_common_init_ex(model, 2); + + pci_init(PCI_CONFIG_TYPE_1); + pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0); + pci_register_slot(0x06, PCI_CARD_NORMAL, 4, 1, 2, 3); + pci_register_slot(0x07, PCI_CARD_NORMAL, 3, 4, 1, 2); + pci_register_slot(0x0B, PCI_CARD_NORMAL, 2, 3, 4, 1); + pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 2, 3, 4); + pci_register_slot(0x09, PCI_CARD_NORMAL, 4, 1, 2, 3); + pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2); + pci_register_slot(0x04, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4); + pci_register_slot(0x01, PCI_CARD_NORMAL, 1, 2, 3, 4); + device_add(&i440bx_device); + device_add(&piix4_device); + device_add(&keyboard_ps2_pci_device); + device_add(&w83977ef_device); + device_add(&sst_flash_39sf020_device); + + hwm_values_t machine_hwm = { + { /* fan speeds */ + 3000, /* Chassis */ + 3000, /* CPU */ + 3000, /* Power */ + 0 + }, { /* temperatures */ + 30, /* MB */ + 0, /* unused */ + 27, /* CPU */ + 0 + }, { /* voltages */ + 2050, /* VCORE (2.05V by default) */ + 0, /* unused */ + 3300, /* +3.3V */ + RESISTOR_DIVIDER(5000, 11, 16), /* +5V (divider values bruteforced) */ + RESISTOR_DIVIDER(12000, 28, 10), /* +12V (28K/10K divider suggested in the W83781D datasheet) */ + RESISTOR_DIVIDER(12000, 853, 347), /* -12V (divider values bruteforced) */ + RESISTOR_DIVIDER(5000, 1, 2), /* -5V (divider values bruteforced) */ + 0 + } + }; + if (model->cpu[cpu_manufacturer].cpus[cpu_effective].cpu_type == CPU_PENTIUM2) + machine_hwm.voltages[0] = 2800; /* set higher VCORE (2.8V) for Klamath */ + hwm_set_values(machine_hwm); + device_add(&as99127f_device); + + return ret; +} + +int +machine_at_borapro_init(const machine_t *model) +{ + //AMI 440ZX Board. Packard Bell OEM of the MSI-6168 + //MIGHT REQUIRE MORE EXCESSIVE TESTING! + //Reports emmersive amounts of RAM like few Intel OEM boards + //we have. + + int ret; + + ret = bios_load_linear(L"roms/machines/borapro/MS6168V2.50", + 0x000c0000, 262144, 0); + + if (bios_only || !ret) + return ret; + + machine_at_common_init_ex(model, 2); + + pci_init(PCI_CONFIG_TYPE_1); + pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0); + pci_register_slot(0x0E, PCI_CARD_NORMAL, 1, 2, 3, 4); + pci_register_slot(0x10, PCI_CARD_NORMAL, 2, 3, 4, 1); + pci_register_slot(0x12, PCI_CARD_NORMAL, 3, 4, 1, 2); + pci_register_slot(0x14, PCI_CARD_NORMAL, 4, 1, 2, 3); + pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4); + pci_register_slot(0x01, PCI_CARD_NORMAL, 1, 2, 3, 4); + device_add(&i440zx_device); + device_add(&piix4e_device); + device_add(&w83977ef_device); + device_add(&keyboard_ps2_ami_pci_device); + device_add(&intel_flash_bxt_device); + + return ret; +} + +int +machine_at_p6bxt_init(const machine_t *model) +{ + int ret; + + ret = bios_load_linear(L"roms/machines/p6bxt/bxt53s.BIN", + 0x000c0000, 262144, 0); + + if (bios_only || !ret) + return ret; + + machine_at_common_init_ex(model, 2); + + pci_init(PCI_CONFIG_TYPE_1); + pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0); + pci_register_slot(0x09, PCI_CARD_NORMAL, 1, 2, 3, 4); + pci_register_slot(0x0A, PCI_CARD_NORMAL, 2, 3, 4, 1); + pci_register_slot(0x0B, PCI_CARD_NORMAL, 3, 4, 1, 2); + pci_register_slot(0x0C, PCI_CARD_NORMAL, 4, 1, 2, 3); + pci_register_slot(0x0D, PCI_CARD_NORMAL, 4, 3, 2, 1); /* Slot 5: Probably the integrated sound chip. */ + pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4); + pci_register_slot(0x01, PCI_CARD_NORMAL, 1, 2, 3, 4); + device_add(&i440bx_device); + device_add(&piix4e_device); + device_add(&w83977tf_device); + device_add(&keyboard_ps2_pci_device); + device_add(&sst_flash_39sf020_device); + + return ret; +} + + +int +machine_at_63a_init(const machine_t *model) +{ + + /* 440ZX Board. 440ZX is basically an underpowered 440BX. There no + difference between to chipsets other than the name. */ + int ret; + + ret = bios_load_linear(L"roms/machines/63a/63a-q3.bin", + 0x000c0000, 262144, 0); + + if (bios_only || !ret) + return ret; + + machine_at_common_init_ex(model, 2); + + pci_init(PCI_CONFIG_TYPE_1); + pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0); + pci_register_slot(0x08, PCI_CARD_NORMAL, 1, 2, 3, 4); + pci_register_slot(0x09, PCI_CARD_NORMAL, 2, 3, 4, 1); + pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2); + pci_register_slot(0x0B, PCI_CARD_NORMAL, 4, 1, 2, 3); + pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 2, 3, 4); // Integrated Sound? + pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4); + pci_register_slot(0x01, PCI_CARD_NORMAL, 1, 2, 3, 4); + device_add(&i440zx_device); + device_add(&piix4e_device); + device_add(&w83977tf_device); + device_add(&keyboard_ps2_pci_device); + device_add(&intel_flash_bxt_device); + + return ret; +} +#endif From b1a421a2e98a73680724097b204cfb7b14490937 Mon Sep 17 00:00:00 2001 From: tiseno100 <58827426+tiseno100@users.noreply.github.com> Date: Wed, 25 Mar 2020 12:31:54 +0200 Subject: [PATCH 28/33] Incorrect Encoding. Fixed --- src/cpu_common/cpu.h | 1134 +++++++++++++-------------- src/cpu_common/cpu_table.c | 1494 ++++++++++++++++++------------------ src/machine/m_at_socket8.c | 600 +++++++-------- 3 files changed, 1614 insertions(+), 1614 deletions(-) diff --git a/src/cpu_common/cpu.h b/src/cpu_common/cpu.h index bdba10437..92a0cfe9f 100644 --- a/src/cpu_common/cpu.h +++ b/src/cpu_common/cpu.h @@ -1,567 +1,567 @@ -/* - * 86Box A hypervisor and IBM PC system emulator that specializes in - * running old operating systems and software designed for IBM - * PC systems and compatibles from 1981 through fairly recent - * system designs based on the PCI bus. - * - * This file is part of the 86Box distribution. - * - * CPU type handler. - * - * - * - * Authors: Sarah Walker, - * leilei, - * Miran Grca, - * - * Copyright 2008-2018 Sarah Walker. - * Copyright 2016-2018 leilei. - * Copyright 2016,2018 Miran Grca. - */ -#ifndef EMU_CPU_H -# define EMU_CPU_H -enum { - CPU_8088, /* 808x class CPUs */ - CPU_8086, -#ifdef USE_NEC_808X - CPU_V20, /* NEC 808x class CPUs - future proofing */ - CPU_V30, -#endif - CPU_286, /* 286 class CPUs */ - CPU_386SX, /* 386 class CPUs */ - CPU_386DX, - CPU_IBM386SLC, - CPU_IBM486SLC, - CPU_IBM486BL, - CPU_RAPIDCAD, - CPU_486SLC, - CPU_486DLC, - CPU_i486SX, /* 486 class CPUs */ - CPU_Am486SX, - CPU_Cx486S, - CPU_i486SX2, - CPU_Am486SX2, - CPU_i486DX, - CPU_i486DX2, - CPU_Am486DX, - CPU_Am486DX2, - CPU_Cx486DX, - CPU_Cx486DX2, - CPU_iDX4, - CPU_Am486DX4, - CPU_Cx486DX4, - CPU_Am5x86, - CPU_Cx5x86, - CPU_WINCHIP, /* 586 class CPUs */ -#ifdef USE_NEW_DYNAREC - CPU_WINCHIP2, -#endif - CPU_PENTIUM, - CPU_PENTIUMMMX, -#if (defined(USE_NEW_DYNAREC) || (defined(DEV_BRANCH) && defined(USE_CYRIX_6X86))) - CPU_Cx6x86, - CPU_Cx6x86MX, - CPU_Cx6x86L, - CPU_CxGX1, -#endif -#if (defined(USE_NEW_DYNAREC) || (defined(DEV_BRANCH) && defined(USE_AMD_K))) - CPU_K5, - CPU_5K86, - CPU_K6, -#endif -#ifdef USE_NEW_DYNAREC - CPU_K6_2, - CPU_K6_2C, - CPU_K6_3, - CPU_K6_2P, - CPU_K6_3P, -#endif - CPU_CYRIX3S, -#if defined(DEV_BRANCH) && defined(USE_I686) - CPU_PENTIUMPRO, /* 686 class CPUs */ - CPU_PENTIUM2, - CPU_PENTIUM2D, -#endif - CPU_MAX /* Only really needed to close the enum in a way independent of the #ifdef's. */ -}; - - -#define MANU_INTEL 0 -#define MANU_AMD 1 -#define MANU_CYRIX 2 -#define MANU_IDT 3 -#define MANU_NEC 4 - -#define CPU_SUPPORTS_DYNAREC 1 -#define CPU_REQUIRES_DYNAREC 2 -#define CPU_ALTERNATE_XTAL 4 - - -typedef struct { - const char *name; - int cpu_type; - int rspeed; - double multi; - uint32_t edx_reset; - uint32_t cpuid_model; - uint16_t cyrix_id; - uint8_t cpu_flags; - int8_t mem_read_cycles, mem_write_cycles; - int8_t cache_read_cycles, cache_write_cycles; - int8_t atclk_div; -} CPU; - - -extern CPU cpus_8088[]; -extern CPU cpus_8086[]; -extern CPU cpus_286[]; -extern CPU cpus_i386SX[]; -extern CPU cpus_i386DX[]; -extern CPU cpus_Am386SX[]; -extern CPU cpus_Am386DX[]; -extern CPU cpus_486SLC[]; -extern CPU cpus_486DLC[]; -extern CPU cpus_IBM386SLC[]; -extern CPU cpus_IBM486SLC[]; -extern CPU cpus_IBM486BL[]; -extern CPU cpus_i486S1[]; -extern CPU cpus_Am486S1[]; -extern CPU cpus_Cx486S1[]; -extern CPU cpus_i486[]; -extern CPU cpus_Am486[]; -extern CPU cpus_Cx486[]; -extern CPU cpus_WinChip[]; -#ifdef USE_NEW_DYNAREC -extern CPU cpus_WinChip_SS7[]; -#endif -extern CPU cpus_Pentium5V[]; -extern CPU cpus_Pentium5V50[]; -extern CPU cpus_PentiumS5[]; -extern CPU cpus_Pentium3V[]; -extern CPU cpus_Pentium[]; -#if (defined(USE_NEW_DYNAREC) || (defined(DEV_BRANCH) && defined(USE_AMD_K))) -extern CPU cpus_K5[]; -extern CPU cpus_K56[]; -#endif -#ifdef USE_NEW_DYNAREC -extern CPU cpus_K56_SS7[]; -#endif -#if (defined(USE_NEW_DYNAREC) || (defined(DEV_BRANCH) && defined(USE_CYRIX_6X86))) -extern CPU cpus_6x863V[]; -extern CPU cpus_6x86[]; -#endif -#ifdef USE_NEW_DYNAREC -extern CPU cpus_6x86SS7[]; -#endif -extern CPU cpus_Cyrix3[]; -#if defined(DEV_BRANCH) && defined(USE_I686) -extern CPU cpus_PentiumPro[]; -extern CPU cpus_PentiumII[]; -extern CPU cpus_Celeron[]; -#endif - - -#define C_FLAG 0x0001 -#define P_FLAG 0x0004 -#define A_FLAG 0x0010 -#define Z_FLAG 0x0040 -#define N_FLAG 0x0080 -#define T_FLAG 0x0100 -#define I_FLAG 0x0200 -#define D_FLAG 0x0400 -#define V_FLAG 0x0800 -#define NT_FLAG 0x4000 - -#define VM_FLAG 0x0002 /* in EFLAGS */ -#define VIF_FLAG 0x0008 /* in EFLAGS */ -#define VIP_FLAG 0x0010 /* in EFLAGS */ - -#define WP_FLAG 0x10000 /* in CR0 */ -#define CR4_VME (1 << 0) -#define CR4_PVI (1 << 1) -#define CR4_PSE (1 << 4) - -#define CPL ((cpu_state.seg_cs.access>>5)&3) - -#define IOPL ((cpu_state.flags>>12)&3) - -#define IOPLp ((!(msw&1)) || (CPL<=IOPL)) - - -typedef union { - uint32_t l; - uint16_t w; - struct { - uint8_t l, - h; - } b; -} x86reg; - -typedef struct { - uint32_t base; - uint32_t limit; - uint8_t access; - uint16_t seg; - uint32_t limit_low, - limit_high; - int checked; /*Non-zero if selector is known to be valid*/ -} x86seg; - -typedef union { - uint64_t q; - int64_t sq; - uint32_t l[2]; - int32_t sl[2]; - uint16_t w[4]; - int16_t sw[4]; - uint8_t b[8]; - int8_t sb[8]; - float f[2]; -} MMX_REG; - -typedef struct { - uint32_t tr1, tr12; - uint32_t cesr; - uint32_t fcr; - uint64_t fcr2, fcr3; -} msr_t; - -typedef union { - uint32_t l; - uint16_t w; -} cr0_t; - - -struct _cpustate_ { - x86reg regs[8]; - - uint8_t tag[8]; - - x86seg *ea_seg; - uint32_t eaaddr; - - int flags_op; - uint32_t flags_res; - uint32_t flags_op1, - flags_op2; - - uint32_t pc; - uint32_t oldpc; - uint32_t op32; - - int TOP; - - union { - struct { - int8_t rm, - mod, - reg; - } rm_mod_reg; - int32_t rm_mod_reg_data; - } rm_data; - - int8_t ssegs; - int8_t ismmx; - int8_t abrt; - - int _cycles; - int cpu_recomp_ins; - - uint16_t npxs, - npxc; - - double ST[8]; - - uint16_t MM_w4[8]; - - MMX_REG MM[8]; - - uint16_t old_npxc, - new_npxc; - uint32_t last_ea; - -#ifdef USE_NEW_DYNAREC - uint32_t old_fp_control, new_fp_control; -#if defined i386 || defined __i386 || defined __i386__ || defined _X86_ - uint16_t old_fp_control2, new_fp_control2; -#endif -#if defined i386 || defined __i386 || defined __i386__ || defined _X86_ || defined __amd64__ - uint32_t trunc_fp_control; -#endif -#endif - - x86seg seg_cs, - seg_ds, - seg_es, - seg_ss, - seg_fs, - seg_gs; - - uint16_t flags, eflags; -} cpu_state; - -/*The cpu_state.flags below must match in both cpu_cur_status and block->status for a block - to be valid*/ -#define CPU_STATUS_USE32 (1 << 0) -#define CPU_STATUS_STACK32 (1 << 1) -#define CPU_STATUS_PMODE (1 << 2) -#define CPU_STATUS_V86 (1 << 3) -#define CPU_STATUS_FLAGS 0xffff - -/*If the cpu_state.flags below are set in cpu_cur_status, they must be set in block->status. - Otherwise they are ignored*/ -#ifdef USE_NEW_DYNAREC -#define CPU_STATUS_NOTFLATDS (1 << 8) -#define CPU_STATUS_NOTFLATSS (1 << 9) -#define CPU_STATUS_MASK 0xff00 -#else -#define CPU_STATUS_NOTFLATDS (1 << 16) -#define CPU_STATUS_NOTFLATSS (1 << 17) -#define CPU_STATUS_MASK 0xffff0000 -#endif - -#ifdef __MSC__ -# define COMPILE_TIME_ASSERT(expr) /*nada*/ -#else -# ifdef EXTREME_DEBUG -# define COMPILE_TIME_ASSERT(expr) typedef char COMP_TIME_ASSERT[(expr) ? 1 : 0]; -# else -# define COMPILE_TIME_ASSERT(expr) /*nada*/ -# endif -#endif - -COMPILE_TIME_ASSERT(sizeof(cpu_state) <= 128) - -#define cpu_state_offset(MEMBER) ((uint8_t)((uintptr_t)&cpu_state.MEMBER - (uintptr_t)&cpu_state - 128)) - -#define EAX cpu_state.regs[0].l -#define AX cpu_state.regs[0].w -#define AL cpu_state.regs[0].b.l -#define AH cpu_state.regs[0].b.h -#define ECX cpu_state.regs[1].l -#define CX cpu_state.regs[1].w -#define CL cpu_state.regs[1].b.l -#define CH cpu_state.regs[1].b.h -#define EDX cpu_state.regs[2].l -#define DX cpu_state.regs[2].w -#define DL cpu_state.regs[2].b.l -#define DH cpu_state.regs[2].b.h -#define EBX cpu_state.regs[3].l -#define BX cpu_state.regs[3].w -#define BL cpu_state.regs[3].b.l -#define BH cpu_state.regs[3].b.h -#define ESP cpu_state.regs[4].l -#define EBP cpu_state.regs[5].l -#define ESI cpu_state.regs[6].l -#define EDI cpu_state.regs[7].l -#define SP cpu_state.regs[4].w -#define BP cpu_state.regs[5].w -#define SI cpu_state.regs[6].w -#define DI cpu_state.regs[7].w - -#define cycles cpu_state._cycles - -#define cpu_rm cpu_state.rm_data.rm_mod_reg.rm -#define cpu_mod cpu_state.rm_data.rm_mod_reg.mod -#define cpu_reg cpu_state.rm_data.rm_mod_reg.reg - -#define CR4_TSD (1 << 2) -#define CR4_DE (1 << 3) -#define CR4_MCE (1 << 6) -#define CR4_PCE (1 << 8) -#define CR4_OSFXSR (1 << 9) - - -/* Global variables. */ -extern int cpu_iscyrix; -extern int cpu_16bitbus; -extern int cpu_busspeed, cpu_pci_speed; -extern int cpu_multi; -extern double cpu_dmulti; -extern int cpu_cyrix_alignment; /*Cyrix 5x86/6x86 only has data misalignment - penalties when crossing 8-byte boundaries*/ - -extern int is8086, is286, is386, is486, is486sx, is486dx, is486sx2, is486dx2, isdx4; -extern int isibmcpu; -extern int is_rapidcad; -extern int hasfpu; -#define CPU_FEATURE_RDTSC (1 << 0) -#define CPU_FEATURE_MSR (1 << 1) -#define CPU_FEATURE_MMX (1 << 2) -#define CPU_FEATURE_CR4 (1 << 3) -#define CPU_FEATURE_VME (1 << 4) -#define CPU_FEATURE_CX8 (1 << 5) -#define CPU_FEATURE_3DNOW (1 << 6) - -extern uint32_t cpu_features; - -extern int in_smm, smi_line, smi_latched; -extern uint32_t smbase; - -#ifdef USE_NEW_DYNAREC -extern uint16_t cpu_cur_status; -#else -extern uint32_t cpu_cur_status; -#endif -extern uint64_t cpu_CR4_mask; -extern uint64_t tsc; -extern msr_t msr; -extern uint8_t opcode; -extern int insc; -extern int fpucount; -extern float mips,flops; -extern int clockrate; -extern int cgate16; -extern int cpl_override; -extern int CPUID; -extern uint64_t xt_cpu_multi; -extern int isa_cycles; -extern uint32_t oldds,oldss,olddslimit,oldsslimit,olddslimitw,oldsslimitw; -extern int ins,output; -extern uint32_t pccache; -extern uint8_t *pccache2; - -extern double bus_timing, pci_timing; -extern uint64_t pmc[2]; -extern uint16_t temp_seg_data[4]; -extern uint16_t cs_msr; -extern uint32_t esp_msr; -extern uint32_t eip_msr; - -/* For the AMD K6. */ -extern uint64_t star; - -#define FPU_CW_Reserved_Bits (0xe0c0) - -extern cr0_t CR0; -#define cr0 CR0.l -#define msw CR0.w -extern uint32_t cr2, cr3, cr4; -extern uint32_t dr[8]; - - -/*Segments - - _cs,_ds,_es,_ss are the segment structures - CS,DS,ES,SS is the 16-bit data - cs,ds,es,ss are defines to the bases*/ -extern x86seg gdt,ldt,idt,tr; -extern x86seg _oldds; -#define CS cpu_state.seg_cs.seg -#define DS cpu_state.seg_ds.seg -#define ES cpu_state.seg_es.seg -#define SS cpu_state.seg_ss.seg -#define FS cpu_state.seg_fs.seg -#define GS cpu_state.seg_gs.seg -#define cs cpu_state.seg_cs.base -#define ds cpu_state.seg_ds.base -#define es cpu_state.seg_es.base -#define ss cpu_state.seg_ss.base -#define fs_seg cpu_state.seg_fs.base -#define gs cpu_state.seg_gs.base - - -#define ISA_CYCLES(x) (x * isa_cycles) - -extern int cpu_cycles_read, cpu_cycles_read_l, cpu_cycles_write, cpu_cycles_write_l; -extern int cpu_prefetch_cycles, cpu_prefetch_width, cpu_mem_prefetch_cycles, cpu_rom_prefetch_cycles; -extern int cpu_waitstates; -extern int cpu_cache_int_enabled, cpu_cache_ext_enabled; -extern int cpu_pci_speed; - -extern int timing_rr; -extern int timing_mr, timing_mrl; -extern int timing_rm, timing_rml; -extern int timing_mm, timing_mml; -extern int timing_bt, timing_bnt; -extern int timing_int, timing_int_rm, timing_int_v86, timing_int_pm; -extern int timing_int_pm_outer, timing_iret_rm, timing_iret_v86, timing_iret_pm; -extern int timing_iret_pm_outer, timing_call_rm, timing_call_pm; -extern int timing_call_pm_gate, timing_call_pm_gate_inner; -extern int timing_retf_rm, timing_retf_pm, timing_retf_pm_outer; -extern int timing_jmp_rm, timing_jmp_pm, timing_jmp_pm_gate; -extern int timing_misaligned; - - -extern CPU cpus_pcjr[]; // FIXME: should be in machine file! -extern CPU cpus_europc[]; // FIXME: should be in machine file! -extern CPU cpus_pc1512[]; // FIXME: should be in machine file! -extern CPU cpus_ibmat[]; // FIXME: should be in machine file! -extern CPU cpus_ibmxt286[]; // FIXME: should be in machine file! -extern CPU cpus_ps1_m2011[]; // FIXME: should be in machine file! -extern CPU cpus_ps2_m30_286[]; // FIXME: should be in machine file! -#if 0 -extern CPU cpus_acer[]; // FIXME: should be in machine file! -#endif - - -/* Functions. */ -extern int cpu_has_feature(int feature); - -#ifdef USE_NEW_DYNAREC -extern void loadseg_dynarec(uint16_t seg, x86seg *s); -extern int loadseg(uint16_t seg, x86seg *s); -extern void loadcs(uint16_t seg); -#else -extern void loadseg(uint16_t seg, x86seg *s); -extern void loadcs(uint16_t seg); -#endif - -extern char *cpu_current_pc(char *bufp); - -extern void cpu_update_waitstates(void); -extern void cpu_set(void); - -extern void cpu_CPUID(void); -extern void cpu_RDMSR(void); -extern void cpu_WRMSR(void); - -extern int checkio(int port); -extern void codegen_block_end(void); -extern void codegen_reset(void); -extern void cpu_set_edx(void); -extern int divl(uint32_t val); -extern void execx86(int cycs); -extern void enter_smm(); -extern void leave_smm(); -extern void exec386(int cycs); -extern void exec386_dynarec(int cycs); -extern int idivl(int32_t val); -#ifdef USE_NEW_DYNAREC -extern void loadcscall(uint16_t seg, uint32_t old_pc); -extern void loadcsjmp(uint16_t seg, uint32_t old_pc); -extern void pmodeint(int num, int soft); -extern void pmoderetf(int is32, uint16_t off); -extern void pmodeiret(int is32); -#else -extern void loadcscall(uint16_t seg); -extern void loadcsjmp(uint16_t seg, uint32_t old_pc); -extern void pmodeint(int num, int soft); -extern void pmoderetf(int is32, uint16_t off); -extern void pmodeiret(int is32); -#endif -extern void resetmcr(void); -extern void resetx86(void); -extern void refreshread(void); -extern void resetreadlookup(void); -extern void softresetx86(void); -extern void x86_int(int num); -extern void x86_int_sw(int num); -extern int x86_int_sw_rm(int num); -extern void x86gpf(char *s, uint16_t error); -extern void x86np(char *s, uint16_t error); -extern void x86ss(char *s, uint16_t error); -extern void x86ts(char *s, uint16_t error); - -#ifdef ENABLE_808X_LOG -extern void dumpregs(int __force); -extern void x87_dumpregs(void); -extern void x87_reset(void); -#endif - -extern int cpu_effective, cpu_alt_reset; -extern void cpu_dynamic_switch(int new_cpu); - -extern void cpu_ven_reset(void); - - -#endif /*EMU_CPU_H*/ +/* + * 86Box A hypervisor and IBM PC system emulator that specializes in + * running old operating systems and software designed for IBM + * PC systems and compatibles from 1981 through fairly recent + * system designs based on the PCI bus. + * + * This file is part of the 86Box distribution. + * + * CPU type handler. + * + * + * + * Authors: Sarah Walker, + * leilei, + * Miran Grca, + * + * Copyright 2008-2018 Sarah Walker. + * Copyright 2016-2018 leilei. + * Copyright 2016,2018 Miran Grca. + */ +#ifndef EMU_CPU_H +# define EMU_CPU_H +enum { + CPU_8088, /* 808x class CPUs */ + CPU_8086, +#ifdef USE_NEC_808X + CPU_V20, /* NEC 808x class CPUs - future proofing */ + CPU_V30, +#endif + CPU_286, /* 286 class CPUs */ + CPU_386SX, /* 386 class CPUs */ + CPU_386DX, + CPU_IBM386SLC, + CPU_IBM486SLC, + CPU_IBM486BL, + CPU_RAPIDCAD, + CPU_486SLC, + CPU_486DLC, + CPU_i486SX, /* 486 class CPUs */ + CPU_Am486SX, + CPU_Cx486S, + CPU_i486SX2, + CPU_Am486SX2, + CPU_i486DX, + CPU_i486DX2, + CPU_Am486DX, + CPU_Am486DX2, + CPU_Cx486DX, + CPU_Cx486DX2, + CPU_iDX4, + CPU_Am486DX4, + CPU_Cx486DX4, + CPU_Am5x86, + CPU_Cx5x86, + CPU_WINCHIP, /* 586 class CPUs */ +#ifdef USE_NEW_DYNAREC + CPU_WINCHIP2, +#endif + CPU_PENTIUM, + CPU_PENTIUMMMX, +#if (defined(USE_NEW_DYNAREC) || (defined(DEV_BRANCH) && defined(USE_CYRIX_6X86))) + CPU_Cx6x86, + CPU_Cx6x86MX, + CPU_Cx6x86L, + CPU_CxGX1, +#endif +#if (defined(USE_NEW_DYNAREC) || (defined(DEV_BRANCH) && defined(USE_AMD_K))) + CPU_K5, + CPU_5K86, + CPU_K6, +#endif +#ifdef USE_NEW_DYNAREC + CPU_K6_2, + CPU_K6_2C, + CPU_K6_3, + CPU_K6_2P, + CPU_K6_3P, +#endif + CPU_CYRIX3S, +#if defined(DEV_BRANCH) && defined(USE_I686) + CPU_PENTIUMPRO, /* 686 class CPUs */ + CPU_PENTIUM2, + CPU_PENTIUM2D, +#endif + CPU_MAX /* Only really needed to close the enum in a way independent of the #ifdef's. */ +}; + + +#define MANU_INTEL 0 +#define MANU_AMD 1 +#define MANU_CYRIX 2 +#define MANU_IDT 3 +#define MANU_NEC 4 + +#define CPU_SUPPORTS_DYNAREC 1 +#define CPU_REQUIRES_DYNAREC 2 +#define CPU_ALTERNATE_XTAL 4 + + +typedef struct { + const char *name; + int cpu_type; + int rspeed; + double multi; + uint32_t edx_reset; + uint32_t cpuid_model; + uint16_t cyrix_id; + uint8_t cpu_flags; + int8_t mem_read_cycles, mem_write_cycles; + int8_t cache_read_cycles, cache_write_cycles; + int8_t atclk_div; +} CPU; + + +extern CPU cpus_8088[]; +extern CPU cpus_8086[]; +extern CPU cpus_286[]; +extern CPU cpus_i386SX[]; +extern CPU cpus_i386DX[]; +extern CPU cpus_Am386SX[]; +extern CPU cpus_Am386DX[]; +extern CPU cpus_486SLC[]; +extern CPU cpus_486DLC[]; +extern CPU cpus_IBM386SLC[]; +extern CPU cpus_IBM486SLC[]; +extern CPU cpus_IBM486BL[]; +extern CPU cpus_i486S1[]; +extern CPU cpus_Am486S1[]; +extern CPU cpus_Cx486S1[]; +extern CPU cpus_i486[]; +extern CPU cpus_Am486[]; +extern CPU cpus_Cx486[]; +extern CPU cpus_WinChip[]; +#ifdef USE_NEW_DYNAREC +extern CPU cpus_WinChip_SS7[]; +#endif +extern CPU cpus_Pentium5V[]; +extern CPU cpus_Pentium5V50[]; +extern CPU cpus_PentiumS5[]; +extern CPU cpus_Pentium3V[]; +extern CPU cpus_Pentium[]; +#if (defined(USE_NEW_DYNAREC) || (defined(DEV_BRANCH) && defined(USE_AMD_K))) +extern CPU cpus_K5[]; +extern CPU cpus_K56[]; +#endif +#ifdef USE_NEW_DYNAREC +extern CPU cpus_K56_SS7[]; +#endif +#if (defined(USE_NEW_DYNAREC) || (defined(DEV_BRANCH) && defined(USE_CYRIX_6X86))) +extern CPU cpus_6x863V[]; +extern CPU cpus_6x86[]; +#endif +#ifdef USE_NEW_DYNAREC +extern CPU cpus_6x86SS7[]; +#endif +extern CPU cpus_Cyrix3[]; +#if defined(DEV_BRANCH) && defined(USE_I686) +extern CPU cpus_PentiumPro[]; +extern CPU cpus_PentiumII[]; +extern CPU cpus_Celeron[]; +#endif + + +#define C_FLAG 0x0001 +#define P_FLAG 0x0004 +#define A_FLAG 0x0010 +#define Z_FLAG 0x0040 +#define N_FLAG 0x0080 +#define T_FLAG 0x0100 +#define I_FLAG 0x0200 +#define D_FLAG 0x0400 +#define V_FLAG 0x0800 +#define NT_FLAG 0x4000 + +#define VM_FLAG 0x0002 /* in EFLAGS */ +#define VIF_FLAG 0x0008 /* in EFLAGS */ +#define VIP_FLAG 0x0010 /* in EFLAGS */ + +#define WP_FLAG 0x10000 /* in CR0 */ +#define CR4_VME (1 << 0) +#define CR4_PVI (1 << 1) +#define CR4_PSE (1 << 4) + +#define CPL ((cpu_state.seg_cs.access>>5)&3) + +#define IOPL ((cpu_state.flags>>12)&3) + +#define IOPLp ((!(msw&1)) || (CPL<=IOPL)) + + +typedef union { + uint32_t l; + uint16_t w; + struct { + uint8_t l, + h; + } b; +} x86reg; + +typedef struct { + uint32_t base; + uint32_t limit; + uint8_t access; + uint16_t seg; + uint32_t limit_low, + limit_high; + int checked; /*Non-zero if selector is known to be valid*/ +} x86seg; + +typedef union { + uint64_t q; + int64_t sq; + uint32_t l[2]; + int32_t sl[2]; + uint16_t w[4]; + int16_t sw[4]; + uint8_t b[8]; + int8_t sb[8]; + float f[2]; +} MMX_REG; + +typedef struct { + uint32_t tr1, tr12; + uint32_t cesr; + uint32_t fcr; + uint64_t fcr2, fcr3; +} msr_t; + +typedef union { + uint32_t l; + uint16_t w; +} cr0_t; + + +struct _cpustate_ { + x86reg regs[8]; + + uint8_t tag[8]; + + x86seg *ea_seg; + uint32_t eaaddr; + + int flags_op; + uint32_t flags_res; + uint32_t flags_op1, + flags_op2; + + uint32_t pc; + uint32_t oldpc; + uint32_t op32; + + int TOP; + + union { + struct { + int8_t rm, + mod, + reg; + } rm_mod_reg; + int32_t rm_mod_reg_data; + } rm_data; + + int8_t ssegs; + int8_t ismmx; + int8_t abrt; + + int _cycles; + int cpu_recomp_ins; + + uint16_t npxs, + npxc; + + double ST[8]; + + uint16_t MM_w4[8]; + + MMX_REG MM[8]; + + uint16_t old_npxc, + new_npxc; + uint32_t last_ea; + +#ifdef USE_NEW_DYNAREC + uint32_t old_fp_control, new_fp_control; +#if defined i386 || defined __i386 || defined __i386__ || defined _X86_ + uint16_t old_fp_control2, new_fp_control2; +#endif +#if defined i386 || defined __i386 || defined __i386__ || defined _X86_ || defined __amd64__ + uint32_t trunc_fp_control; +#endif +#endif + + x86seg seg_cs, + seg_ds, + seg_es, + seg_ss, + seg_fs, + seg_gs; + + uint16_t flags, eflags; +} cpu_state; + +/*The cpu_state.flags below must match in both cpu_cur_status and block->status for a block + to be valid*/ +#define CPU_STATUS_USE32 (1 << 0) +#define CPU_STATUS_STACK32 (1 << 1) +#define CPU_STATUS_PMODE (1 << 2) +#define CPU_STATUS_V86 (1 << 3) +#define CPU_STATUS_FLAGS 0xffff + +/*If the cpu_state.flags below are set in cpu_cur_status, they must be set in block->status. + Otherwise they are ignored*/ +#ifdef USE_NEW_DYNAREC +#define CPU_STATUS_NOTFLATDS (1 << 8) +#define CPU_STATUS_NOTFLATSS (1 << 9) +#define CPU_STATUS_MASK 0xff00 +#else +#define CPU_STATUS_NOTFLATDS (1 << 16) +#define CPU_STATUS_NOTFLATSS (1 << 17) +#define CPU_STATUS_MASK 0xffff0000 +#endif + +#ifdef __MSC__ +# define COMPILE_TIME_ASSERT(expr) /*nada*/ +#else +# ifdef EXTREME_DEBUG +# define COMPILE_TIME_ASSERT(expr) typedef char COMP_TIME_ASSERT[(expr) ? 1 : 0]; +# else +# define COMPILE_TIME_ASSERT(expr) /*nada*/ +# endif +#endif + +COMPILE_TIME_ASSERT(sizeof(cpu_state) <= 128) + +#define cpu_state_offset(MEMBER) ((uint8_t)((uintptr_t)&cpu_state.MEMBER - (uintptr_t)&cpu_state - 128)) + +#define EAX cpu_state.regs[0].l +#define AX cpu_state.regs[0].w +#define AL cpu_state.regs[0].b.l +#define AH cpu_state.regs[0].b.h +#define ECX cpu_state.regs[1].l +#define CX cpu_state.regs[1].w +#define CL cpu_state.regs[1].b.l +#define CH cpu_state.regs[1].b.h +#define EDX cpu_state.regs[2].l +#define DX cpu_state.regs[2].w +#define DL cpu_state.regs[2].b.l +#define DH cpu_state.regs[2].b.h +#define EBX cpu_state.regs[3].l +#define BX cpu_state.regs[3].w +#define BL cpu_state.regs[3].b.l +#define BH cpu_state.regs[3].b.h +#define ESP cpu_state.regs[4].l +#define EBP cpu_state.regs[5].l +#define ESI cpu_state.regs[6].l +#define EDI cpu_state.regs[7].l +#define SP cpu_state.regs[4].w +#define BP cpu_state.regs[5].w +#define SI cpu_state.regs[6].w +#define DI cpu_state.regs[7].w + +#define cycles cpu_state._cycles + +#define cpu_rm cpu_state.rm_data.rm_mod_reg.rm +#define cpu_mod cpu_state.rm_data.rm_mod_reg.mod +#define cpu_reg cpu_state.rm_data.rm_mod_reg.reg + +#define CR4_TSD (1 << 2) +#define CR4_DE (1 << 3) +#define CR4_MCE (1 << 6) +#define CR4_PCE (1 << 8) +#define CR4_OSFXSR (1 << 9) + + +/* Global variables. */ +extern int cpu_iscyrix; +extern int cpu_16bitbus; +extern int cpu_busspeed, cpu_pci_speed; +extern int cpu_multi; +extern double cpu_dmulti; +extern int cpu_cyrix_alignment; /*Cyrix 5x86/6x86 only has data misalignment + penalties when crossing 8-byte boundaries*/ + +extern int is8086, is286, is386, is486, is486sx, is486dx, is486sx2, is486dx2, isdx4; +extern int isibmcpu; +extern int is_rapidcad; +extern int hasfpu; +#define CPU_FEATURE_RDTSC (1 << 0) +#define CPU_FEATURE_MSR (1 << 1) +#define CPU_FEATURE_MMX (1 << 2) +#define CPU_FEATURE_CR4 (1 << 3) +#define CPU_FEATURE_VME (1 << 4) +#define CPU_FEATURE_CX8 (1 << 5) +#define CPU_FEATURE_3DNOW (1 << 6) + +extern uint32_t cpu_features; + +extern int in_smm, smi_line, smi_latched; +extern uint32_t smbase; + +#ifdef USE_NEW_DYNAREC +extern uint16_t cpu_cur_status; +#else +extern uint32_t cpu_cur_status; +#endif +extern uint64_t cpu_CR4_mask; +extern uint64_t tsc; +extern msr_t msr; +extern uint8_t opcode; +extern int insc; +extern int fpucount; +extern float mips,flops; +extern int clockrate; +extern int cgate16; +extern int cpl_override; +extern int CPUID; +extern uint64_t xt_cpu_multi; +extern int isa_cycles; +extern uint32_t oldds,oldss,olddslimit,oldsslimit,olddslimitw,oldsslimitw; +extern int ins,output; +extern uint32_t pccache; +extern uint8_t *pccache2; + +extern double bus_timing, pci_timing; +extern uint64_t pmc[2]; +extern uint16_t temp_seg_data[4]; +extern uint16_t cs_msr; +extern uint32_t esp_msr; +extern uint32_t eip_msr; + +/* For the AMD K6. */ +extern uint64_t star; + +#define FPU_CW_Reserved_Bits (0xe0c0) + +extern cr0_t CR0; +#define cr0 CR0.l +#define msw CR0.w +extern uint32_t cr2, cr3, cr4; +extern uint32_t dr[8]; + + +/*Segments - + _cs,_ds,_es,_ss are the segment structures + CS,DS,ES,SS is the 16-bit data + cs,ds,es,ss are defines to the bases*/ +extern x86seg gdt,ldt,idt,tr; +extern x86seg _oldds; +#define CS cpu_state.seg_cs.seg +#define DS cpu_state.seg_ds.seg +#define ES cpu_state.seg_es.seg +#define SS cpu_state.seg_ss.seg +#define FS cpu_state.seg_fs.seg +#define GS cpu_state.seg_gs.seg +#define cs cpu_state.seg_cs.base +#define ds cpu_state.seg_ds.base +#define es cpu_state.seg_es.base +#define ss cpu_state.seg_ss.base +#define fs_seg cpu_state.seg_fs.base +#define gs cpu_state.seg_gs.base + + +#define ISA_CYCLES(x) (x * isa_cycles) + +extern int cpu_cycles_read, cpu_cycles_read_l, cpu_cycles_write, cpu_cycles_write_l; +extern int cpu_prefetch_cycles, cpu_prefetch_width, cpu_mem_prefetch_cycles, cpu_rom_prefetch_cycles; +extern int cpu_waitstates; +extern int cpu_cache_int_enabled, cpu_cache_ext_enabled; +extern int cpu_pci_speed; + +extern int timing_rr; +extern int timing_mr, timing_mrl; +extern int timing_rm, timing_rml; +extern int timing_mm, timing_mml; +extern int timing_bt, timing_bnt; +extern int timing_int, timing_int_rm, timing_int_v86, timing_int_pm; +extern int timing_int_pm_outer, timing_iret_rm, timing_iret_v86, timing_iret_pm; +extern int timing_iret_pm_outer, timing_call_rm, timing_call_pm; +extern int timing_call_pm_gate, timing_call_pm_gate_inner; +extern int timing_retf_rm, timing_retf_pm, timing_retf_pm_outer; +extern int timing_jmp_rm, timing_jmp_pm, timing_jmp_pm_gate; +extern int timing_misaligned; + + +extern CPU cpus_pcjr[]; // FIXME: should be in machine file! +extern CPU cpus_europc[]; // FIXME: should be in machine file! +extern CPU cpus_pc1512[]; // FIXME: should be in machine file! +extern CPU cpus_ibmat[]; // FIXME: should be in machine file! +extern CPU cpus_ibmxt286[]; // FIXME: should be in machine file! +extern CPU cpus_ps1_m2011[]; // FIXME: should be in machine file! +extern CPU cpus_ps2_m30_286[]; // FIXME: should be in machine file! +#if 0 +extern CPU cpus_acer[]; // FIXME: should be in machine file! +#endif + + +/* Functions. */ +extern int cpu_has_feature(int feature); + +#ifdef USE_NEW_DYNAREC +extern void loadseg_dynarec(uint16_t seg, x86seg *s); +extern int loadseg(uint16_t seg, x86seg *s); +extern void loadcs(uint16_t seg); +#else +extern void loadseg(uint16_t seg, x86seg *s); +extern void loadcs(uint16_t seg); +#endif + +extern char *cpu_current_pc(char *bufp); + +extern void cpu_update_waitstates(void); +extern void cpu_set(void); + +extern void cpu_CPUID(void); +extern void cpu_RDMSR(void); +extern void cpu_WRMSR(void); + +extern int checkio(int port); +extern void codegen_block_end(void); +extern void codegen_reset(void); +extern void cpu_set_edx(void); +extern int divl(uint32_t val); +extern void execx86(int cycs); +extern void enter_smm(); +extern void leave_smm(); +extern void exec386(int cycs); +extern void exec386_dynarec(int cycs); +extern int idivl(int32_t val); +#ifdef USE_NEW_DYNAREC +extern void loadcscall(uint16_t seg, uint32_t old_pc); +extern void loadcsjmp(uint16_t seg, uint32_t old_pc); +extern void pmodeint(int num, int soft); +extern void pmoderetf(int is32, uint16_t off); +extern void pmodeiret(int is32); +#else +extern void loadcscall(uint16_t seg); +extern void loadcsjmp(uint16_t seg, uint32_t old_pc); +extern void pmodeint(int num, int soft); +extern void pmoderetf(int is32, uint16_t off); +extern void pmodeiret(int is32); +#endif +extern void resetmcr(void); +extern void resetx86(void); +extern void refreshread(void); +extern void resetreadlookup(void); +extern void softresetx86(void); +extern void x86_int(int num); +extern void x86_int_sw(int num); +extern int x86_int_sw_rm(int num); +extern void x86gpf(char *s, uint16_t error); +extern void x86np(char *s, uint16_t error); +extern void x86ss(char *s, uint16_t error); +extern void x86ts(char *s, uint16_t error); + +#ifdef ENABLE_808X_LOG +extern void dumpregs(int __force); +extern void x87_dumpregs(void); +extern void x87_reset(void); +#endif + +extern int cpu_effective, cpu_alt_reset; +extern void cpu_dynamic_switch(int new_cpu); + +extern void cpu_ven_reset(void); + + +#endif /*EMU_CPU_H*/ diff --git a/src/cpu_common/cpu_table.c b/src/cpu_common/cpu_table.c index c1c73f4c4..f5f1dca4c 100644 --- a/src/cpu_common/cpu_table.c +++ b/src/cpu_common/cpu_table.c @@ -1,748 +1,748 @@ -/* - * 86Box A hypervisor and IBM PC system emulator that specializes in - * running old operating systems and software designed for IBM - * PC systems and compatibles from 1981 through fairly recent - * system designs based on the PCI bus. - * - * This file is part of the 86Box distribution. - * - * Define all known processor types. - * - * Available cpuspeeds: - * - * 0 = 16 MHz - * 1 = 20 MHz - * 2 = 25 MHz - * 3 = 33 MHz - * 4 = 40 MHz - * 5 = 50 MHz - * 6 = 66 MHz - * 7 = 75 MHz - * 8 = 80 MHz - * 9 = 90 MHz - * 10 = 100 MHz - * 11 = 120 MHz - * 12 = 133 MHz - * 13 = 150 MHz - * 14 = 160 MHz - * 15 = 166 MHz - * 16 = 180 MHz - * 17 = 200 MHz - * - * - * - * Authors: Sarah Walker, - * leilei, - * Miran Grca, - * Fred N. van Kempen, - * - * Copyright 2008-2019 Sarah Walker. - * Copyright 2016-2019 leilei. - * Copyright 2016-2019 Miran Grca. - * Copyright 2017-2019 Fred N. van Kempen. - */ -#include -#include -#include -#include -#include "86box.h" -#include "cpu.h" -#include "machine.h" - - -CPU cpus_8088[] = { - /*8088 standard*/ - {"8088/4.77", CPU_8088, 4772728, 1, 0, 0, 0, 0, 0,0,0,0, 1}, - {"8088/7.16", CPU_8088, 7159092, 1, 0, 0, 0, 0, 0,0,0,0, 1}, - {"8088/8", CPU_8088, 8000000, 1, 0, 0, 0, 0, 0,0,0,0, 1}, - {"8088/10", CPU_8088, 10000000, 1, 0, 0, 0, 0, 0,0,0,0, 1}, - {"8088/12", CPU_8088, 12000000, 1, 0, 0, 0, 0, 0,0,0,0, 1}, - {"8088/16", CPU_8088, 16000000, 1, 0, 0, 0, 0, 0,0,0,0, 1}, - {"", -1, 0, 0, 0, 0, 0, 0, 0,0,0,0, 0} -}; - -CPU cpus_pcjr[] = { - /*8088 PCjr*/ - {"8088/4.77", CPU_8088, 4772728, 1, 0, 0, 0, 0, 0,0,0,0, 1}, - {"", -1, 0, 0, 0, 0, 0, 0, 0,0,0,0, 0} -}; - -CPU cpus_europc[] = { - /*8088 EuroPC*/ - {"8088/4.77", CPU_8088, 4772728, 1, 0, 0, 0, CPU_ALTERNATE_XTAL, 0,0,0,0, 1}, - {"8088/7.16", CPU_8088, 7159092, 1, 0, 0, 0, CPU_ALTERNATE_XTAL, 0,0,0,0, 1}, - {"8088/9.54", CPU_8088, 9545456, 1, 0, 0, 0, 0, 0,0,0,0, 1}, - {"", -1, 0, 0, 0, 0, 0, 0, 0,0,0,0, 0} -}; - -CPU cpus_8086[] = { - /*8086 standard*/ - {"8086/7.16", CPU_8086, 7159092, 1, 0, 0, 0, CPU_ALTERNATE_XTAL, 0,0,0,0, 1}, - {"8086/8", CPU_8086, 8000000, 1, 0, 0, 0, 0, 0,0,0,0, 1}, - {"8086/9.54", CPU_8086, 9545456, 1, 0, 0, 0, CPU_ALTERNATE_XTAL, 0,0,0,0, 1}, - {"8086/10", CPU_8086, 10000000, 1, 0, 0, 0, 0, 0,0,0,0, 1}, - {"8086/12", CPU_8086, 12000000, 1, 0, 0, 0, 0, 0,0,0,0, 1}, - {"8086/16", CPU_8086, 16000000, 1, 0, 0, 0, 0, 0,0,0,0, 2}, - {"", -1, 0, 0, 0, 0, 0, 0, 0,0,0,0, 0} -}; - -CPU cpus_pc1512[] = { - /*8086 Amstrad*/ - {"8086/8", CPU_8086, 8000000, 1, 0, 0, 0, 0, 0,0,0,0, 1}, - {"", -1, 0, 0, 0, 0, 0, 0, 0,0,0,0, 0} -}; - -CPU cpus_286[] = { - /*286*/ - {"286/6", CPU_286, 6000000, 1, 0, 0, 0, 0, 2,2,2,2, 1}, - {"286/8", CPU_286, 8000000, 1, 0, 0, 0, 0, 2,2,2,2, 1}, - {"286/10", CPU_286, 10000000, 1, 0, 0, 0, 0, 2,2,2,2, 1}, - {"286/12", CPU_286, 12500000, 1, 0, 0, 0, 0, 3,3,3,3, 2}, - {"286/16", CPU_286, 16000000, 1, 0, 0, 0, 0, 3,3,3,3, 2}, - {"286/20", CPU_286, 20000000, 1, 0, 0, 0, 0, 4,4,4,4, 3}, - {"286/25", CPU_286, 25000000, 1, 0, 0, 0, 0, 4,4,4,4, 3}, - {"", -1, 0, 0, 0, 0, 0, 0, 0,0,0,0, 0} -}; - -CPU cpus_ibmat[] = { - /*286*/ - {"286/6", CPU_286, 6000000, 1, 0, 0, 0, 0, 3,3,3,3, 1}, - {"286/8", CPU_286, 8000000, 1, 0, 0, 0, 0, 3,3,3,3, 1}, - {"", -1, 0, 0, 0, 0, 0, 0, 0,0,0,0, 0} -}; - -CPU cpus_ibmxt286[] = { - /*286*/ - {"286/6", CPU_286, 6000000, 1, 0, 0, 0, 0, 2,2,2,2, 1}, - {"", -1, 0, 0, 0, 0, 0, 0, 0,0,0,0, 0} -}; - -CPU cpus_ps1_m2011[] = { - /*286*/ - {"286/10", CPU_286, 10000000, 1, 0, 0, 0, 0, 2,2,2,2, 1}, - {"", -1, 0, 0, 0, 0, 0, 0, 0,0,0,0, 9} -}; - -CPU cpus_ps2_m30_286[] = { - /*286*/ - {"286/10", CPU_286, 10000000, 1, 0, 0, 0, 0, 2,2,2,2, 1}, - {"286/12", CPU_286, 12500000, 1, 0, 0, 0, 0, 3,3,3,3, 2}, - {"286/16", CPU_286, 16000000, 1, 0, 0, 0, 0, 3,3,3,3, 2}, - {"286/20", CPU_286, 20000000, 1, 0, 0, 0, 0, 4,4,4,4, 3}, - {"286/25", CPU_286, 25000000, 1, 0, 0, 0, 0, 4,4,4,4, 3}, - {"", -1, 0, 0, 0, 0, 0, 0, 0,0,0,0, 0} -}; - -CPU cpus_i386SX[] = { - /*i386SX*/ - {"i386SX/16", CPU_386SX, 16000000, 1, 0x2308, 0, 0, 0, 3,3,3,3, 2}, - {"i386SX/20", CPU_386SX, 20000000, 1, 0x2308, 0, 0, 0, 4,4,3,3, 3}, - {"i386SX/25", CPU_386SX, 25000000, 1, 0x2308, 0, 0, 0, 4,4,3,3, 3}, - {"i386SX/33", CPU_386SX, 33333333, 1, 0x2308, 0, 0, 0, 6,6,3,3, 4}, - {"i386SX/40", CPU_386SX, 40000000, 1, 0x2308, 0, 0, 0, 7,7,3,3, 5}, - {"", -1, 0, 0, 0, 0, 0, 0, 0,0,0,0, 0} -}; - -CPU cpus_i386DX[] = { - /*i386DX/RapidCAD*/ - {"i386DX/16", CPU_386DX, 16000000, 1, 0x0308, 0, 0, 0, 3,3,3,3, 2}, - {"i386DX/20", CPU_386DX, 20000000, 1, 0x0308, 0, 0, 0, 4,4,3,3, 3}, - {"i386DX/25", CPU_386DX, 25000000, 1, 0x0308, 0, 0, 0, 4,4,3,3, 3}, - {"i386DX/33", CPU_386DX, 33333333, 1, 0x0308, 0, 0, 0, 6,6,3,3, 4}, - {"i386DX/40", CPU_386DX, 40000000, 1, 0x0308, 0, 0, 0, 7,7,3,3, 5}, - {"RapidCAD/25", CPU_RAPIDCAD, 25000000, 1, 0x0430, 0, 0, CPU_SUPPORTS_DYNAREC, 4,4,3,3, 3}, - {"RapidCAD/33", CPU_RAPIDCAD, 33333333, 1, 0x0430, 0, 0, CPU_SUPPORTS_DYNAREC, 6,6,3,3, 4}, - {"RapidCAD/40", CPU_RAPIDCAD, 40000000, 1, 0x0430, 0, 0, CPU_SUPPORTS_DYNAREC, 7,7,3,3, 5}, - {"", -1, 0, 0, 0, 0, 0, 0, 0,0,0,0, 0} -}; - -CPU cpus_Am386SX[] = { - /*Am386SX*/ - {"Am386SX/16", CPU_386SX, 16000000, 1, 0x2308, 0, 0, 0, 3,3,3,3, 2}, - {"Am386SX/20", CPU_386SX, 20000000, 1, 0x2308, 0, 0, 0, 4,4,3,3, 3}, - {"Am386SX/25", CPU_386SX, 25000000, 1, 0x2308, 0, 0, 0, 4,4,3,3, 3}, - {"Am386SX/33", CPU_386SX, 33333333, 1, 0x2308, 0, 0, 0, 6,6,3,3, 4}, - {"Am386SX/40", CPU_386SX, 40000000, 1, 0x2308, 0, 0, 0, 7,7,3,3, 5}, - {"", -1, 0, 0, 0, 0, 0, 0, 0,0,0,0, 0} -}; - -CPU cpus_Am386DX[] = { - /*Am386DX*/ - {"Am386DX/25", CPU_386DX, 25000000, 1, 0x0308, 0, 0, 0, 4,4,3,3, 3}, - {"Am386DX/33", CPU_386DX, 33333333, 1, 0x0308, 0, 0, 0, 6,6,3,3, 4}, - {"Am386DX/40", CPU_386DX, 40000000, 1, 0x0308, 0, 0, 0, 7,7,3,3, 5}, - {"", -1, 0, 0, 0, 0, 0, 0, 0,0,0,0, 0} -}; - -CPU cpus_486SLC[] = { - /*Cx486SLC*/ - {"Cx486SLC/20", CPU_486SLC, 20000000, 1, 0x400, 0, 0x0000, 0, 4,4,3,3, 3}, - {"Cx486SLC/25", CPU_486SLC, 25000000, 1, 0x400, 0, 0x0000, 0, 4,4,3,3, 3}, - {"Cx486SLC/33", CPU_486SLC, 33333333, 1, 0x400, 0, 0x0000, 0, 6,6,3,3, 4}, - {"Cx486SRx2/32", CPU_486SLC, 32000000, 2, 0x406, 0, 0x0006, 0, 6,6,6,6, 4}, - {"Cx486SRx2/40", CPU_486SLC, 40000000, 2, 0x406, 0, 0x0006, 0, 8,8,6,6, 6}, - {"Cx486SRx2/50", CPU_486SLC, 50000000, 2, 0x406, 0, 0x0006, 0, 8,8,6,6, 6}, - {"", -1, 0, 0, 0, 0, 0, 0, 0,0,0,0, 0} -}; - -CPU cpus_IBM386SLC[] = { - /*IBM 386SLC*/ - {"386SLC/16", CPU_IBM386SLC, 16000000, 1, 0x300, 0, 0, 0, 3,3,3,3, 2}, - {"386SLC/20", CPU_IBM386SLC, 20000000, 1, 0x300, 0, 0, 0, 4,4,3,3, 3}, - {"386SLC/25", CPU_IBM386SLC, 25000000, 1, 0x300, 0, 0, 0, 4,4,3,3, 3}, - {"", -1, 0, 0, 0, 0, 0, 0, 0,0,0,0, 0} -}; - -CPU cpus_IBM486SLC[] = { - /*IBM 486SLC*/ - {"486SLC/33", CPU_IBM486SLC, 33333333, 1, 0x400, 0, 0, 0, 6,6,3,3, 4}, - {"486SLC2/40", CPU_IBM486SLC, 40000000, 2, 0x400, 0, 0, 0, 7,7,6,6, 5}, - {"486SLC2/50", CPU_IBM486SLC, 50000000, 2, 0x400, 0, 0, 0, 8,8,6,6, 6}, - {"486SLC2/66", CPU_IBM486SLC, 66666666, 2, 0x400, 0, 0, 0, 12,12,6,6, 8}, - {"486SLC3/60", CPU_IBM486SLC, 60000000, 3, 0x400, 0, 0, 0, 12,12,9,9, 7}, - {"486SLC3/75", CPU_IBM486SLC, 75000000, 3, 0x400, 0, 0, 0, 12,12,9,9, 9}, - {"486SLC3/100", CPU_IBM486SLC, 100000000, 3, 0x400, 0, 0, 0, 18,18,9,9, 12}, - {"", -1, 0, 0, 0, 0, 0, 0, 0,0,0,0, 0} -}; - -CPU cpus_IBM486BL[] = { - /*IBM Blue Lightning*/ - {"486BL2/50", CPU_IBM486BL, 50000000, 2, 0x400, 0, 0, 0, 8,8,6,6, 6}, - {"486BL2/66", CPU_IBM486BL, 66666666, 2, 0x400, 0, 0, 0, 12,12,6,6, 8}, - {"486BL3/75", CPU_IBM486BL, 75000000, 3, 0x400, 0, 0, 0, 12,12,9,9, 9}, - {"486BL3/100", CPU_IBM486BL, 100000000, 3, 0x400, 0, 0, 0, 18,18,9,9, 12}, - {"", -1, 0, 0, 0, 0, 0, 0, 0,0,0,0, 0} -}; - -CPU cpus_486DLC[] = { - /*Cx486DLC*/ - {"Cx486DLC/25", CPU_486DLC, 25000000, 1, 0x401, 0, 0x0001, 0, 4, 4,3,3, 3}, - {"Cx486DLC/33", CPU_486DLC, 33333333, 1, 0x401, 0, 0x0001, 0, 6, 6,3,3, 4}, - {"Cx486DLC/40", CPU_486DLC, 40000000, 1, 0x401, 0, 0x0001, 0, 7, 7,3,3, 5}, - {"Cx486DRx2/32", CPU_486DLC, 32000000, 2, 0x407, 0, 0x0007, 0, 6, 6,6,6, 4}, - {"Cx486DRx2/40", CPU_486DLC, 40000000, 2, 0x407, 0, 0x0007, 0, 8, 8,6,6, 6}, - {"Cx486DRx2/50", CPU_486DLC, 50000000, 2, 0x407, 0, 0x0007, 0, 8, 8,6,6, 6}, - {"Cx486DRx2/66", CPU_486DLC, 66666666, 2, 0x407, 0, 0x0007, 0, 12,12,6,6, 8}, - {"", -1, 0, 0, 0, 0, 0, 0, 0, 0,0,0, 0} -}; - -CPU cpus_i486S1[] = { - /*i486*/ - {"i486SX/16", CPU_i486SX, 16000000, 1, 0x420, 0, 0, CPU_SUPPORTS_DYNAREC, 3, 3,3,3, 2}, - {"i486SX/20", CPU_i486SX, 20000000, 1, 0x420, 0, 0, CPU_SUPPORTS_DYNAREC, 4, 4,3,3, 3}, - {"i486SX/25", CPU_i486SX, 25000000, 1, 0x422, 0, 0, CPU_SUPPORTS_DYNAREC, 4, 4,3,3, 3}, - {"i486SX/33", CPU_i486SX, 33333333, 1, 0x42a, 0, 0, CPU_SUPPORTS_DYNAREC, 6, 6,3,3, 4}, - {"i486SX2/50", CPU_i486SX, 50000000, 2, 0x45b, 0, 0, CPU_SUPPORTS_DYNAREC, 8, 8,6,6, 6}, - {"i486SX2/66 (Q0569)", CPU_i486SX, 66666666, 2, 0x45b, 0, 0, CPU_SUPPORTS_DYNAREC, 8, 8,6,6, 8}, - {"i486DX/25", CPU_i486DX, 25000000, 1, 0x404, 0, 0, CPU_SUPPORTS_DYNAREC, 4, 4,3,3, 3}, - {"i486DX/33", CPU_i486DX, 33333333, 1, 0x414, 0, 0, CPU_SUPPORTS_DYNAREC, 6, 6,3,3, 4}, - {"i486DX/50", CPU_i486DX, 50000000, 1, 0x411, 0, 0, CPU_SUPPORTS_DYNAREC, 8, 8,4,4, 6}, - {"i486DX2/40", CPU_i486DX, 40000000, 2, 0x430, 0x430, 0, CPU_SUPPORTS_DYNAREC, 7, 7,6,6, 5}, - {"i486DX2/50", CPU_i486DX, 50000000, 2, 0x433, 0x433, 0, CPU_SUPPORTS_DYNAREC, 8, 8,6,6, 6}, - {"i486DX2/66", CPU_i486DX, 66666666, 2, 0x435, 0x435, 0, CPU_SUPPORTS_DYNAREC, 12,12,6,6, 8}, - {"iDX4 OverDrive 75", CPU_iDX4, 75000000, 3, 0x1480, 0x1480, 0, CPU_SUPPORTS_DYNAREC, 12,12,9,9, 9}, /*Only added the DX4 OverDrive as the others would be redundant*/ - {"iDX4 OverDrive 100", CPU_iDX4, 100000000, 3, 0x1480, 0x1480, 0, CPU_SUPPORTS_DYNAREC, 18,18,9,9, 12}, - {"", -1, 0, 0, 0, 0, 0, 0, 0, 0,0,0, 0} -}; -CPU cpus_Am486S1[] = { - /*Am486*/ - {"Am486SX/33", CPU_Am486SX, 33333333, 1, 0x42a, 0, 0, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 4}, - {"Am486SX/40", CPU_Am486SX, 40000000, 1, 0x42a, 0, 0, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5}, - {"Am486SX2/50", CPU_Am486SX2, 50000000, 2, 0x45b, 0x45b, 0, CPU_SUPPORTS_DYNAREC, 8, 8, 6, 6, 6}, /*CPUID available on SX2, DX2, DX4, 5x86, >= 50 MHz*/ - {"Am486SX2/66", CPU_Am486SX2, 66666666, 2, 0x45b, 0x45b, 0, CPU_SUPPORTS_DYNAREC, 12,12, 6, 6, 8}, /*Isn't on all real AMD SX2s and DX2s, availability here is pretty arbitary (and distinguishes them from the Intel chips)*/ - {"Am486DX/33", CPU_Am486DX, 33333333, 1, 0x430, 0, 0, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 4}, - {"Am486DX/40", CPU_Am486DX, 40000000, 1, 0x430, 0, 0, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5}, - {"Am486DX2/50", CPU_Am486DX2, 50000000, 2, 0x470, 0x470, 0, CPU_SUPPORTS_DYNAREC, 8, 8, 6, 6, 6}, - {"Am486DX2/66", CPU_Am486DX2, 66666666, 2, 0x470, 0x470, 0, CPU_SUPPORTS_DYNAREC, 12,12, 6, 6, 8}, - {"Am486DX2/80", CPU_Am486DX2, 80000000, 2, 0x470, 0x470, 0, CPU_SUPPORTS_DYNAREC, 14,14, 6, 6, 10}, - {"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} -}; -CPU cpus_Cx486S1[] = { - /*Cyrix 486*/ - {"Cx486S/25", CPU_Cx486S, 25000000, 1, 0x420, 0, 0x0010, CPU_SUPPORTS_DYNAREC, 4, 4, 3, 3, 3}, - {"Cx486S/33", CPU_Cx486S, 33333333, 1, 0x420, 0, 0x0010, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 4}, - {"Cx486S/40", CPU_Cx486S, 40000000, 1, 0x420, 0, 0x0010, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5}, - {"Cx486DX/33", CPU_Cx486DX, 33333333, 1, 0x430, 0, 0x051a, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 4}, - {"Cx486DX/40", CPU_Cx486DX, 40000000, 1, 0x430, 0, 0x051a, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5}, - {"Cx486DX2/50", CPU_Cx486DX2, 50000000, 2, 0x430, 0, 0x081b, CPU_SUPPORTS_DYNAREC, 8, 8, 6, 6, 6}, - {"Cx486DX2/66", CPU_Cx486DX2, 66666666, 2, 0x430, 0, 0x0b1b, CPU_SUPPORTS_DYNAREC, 12,12, 6, 6, 8}, - {"Cx486DX2/80", CPU_Cx486DX2, 80000000, 2, 0x430, 0, 0x311b, CPU_SUPPORTS_DYNAREC, 14,14, 6, 6, 10}, - {"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} -}; - -CPU cpus_i486[] = { - /*i486/P24T*/ - {"i486SX/16", CPU_i486SX, 16000000, 1, 0x420, 0, 0, CPU_SUPPORTS_DYNAREC, 3, 3,3,3, 2}, - {"i486SX/20", CPU_i486SX, 20000000, 1, 0x420, 0, 0, CPU_SUPPORTS_DYNAREC, 4, 4,3,3, 3}, - {"i486SX/25", CPU_i486SX, 25000000, 1, 0x422, 0, 0, CPU_SUPPORTS_DYNAREC, 4, 4,3,3, 3}, - {"i486SX/33", CPU_i486SX, 33333333, 1, 0x42a, 0, 0, CPU_SUPPORTS_DYNAREC, 6, 6,3,3, 4}, - {"i486SX2/50", CPU_i486SX, 50000000, 2, 0x45b, 0, 0, CPU_SUPPORTS_DYNAREC, 8, 8,6,6, 6}, - {"i486SX2/66 (Q0569)", CPU_i486SX, 66666666, 2, 0x45b, 0, 0, CPU_SUPPORTS_DYNAREC, 8, 8,6,6, 8}, - {"i486DX/25", CPU_i486DX, 25000000, 1, 0x404, 0, 0, CPU_SUPPORTS_DYNAREC, 4, 4,3,3, 3}, - {"i486DX/33", CPU_i486DX, 33333333, 1, 0x414, 0, 0, CPU_SUPPORTS_DYNAREC, 6, 6,3,3, 4}, - {"i486DX/50", CPU_i486DX, 50000000, 1, 0x411, 0, 0, CPU_SUPPORTS_DYNAREC, 8, 8,4,4, 6}, - {"i486DX2/40", CPU_i486DX, 40000000, 2, 0x430, 0x430, 0, CPU_SUPPORTS_DYNAREC, 7, 7,6,6, 5}, - {"i486DX2/50", CPU_i486DX, 50000000, 2, 0x433, 0x433, 0, CPU_SUPPORTS_DYNAREC, 8, 8,6,6, 6}, - {"i486DX2/66", CPU_i486DX, 66666666, 2, 0x435, 0x435, 0, CPU_SUPPORTS_DYNAREC, 12,12,6,6, 8}, - {"iDX4/75", CPU_iDX4, 75000000, 3, 0x480, 0x480, 0, CPU_SUPPORTS_DYNAREC, 12,12,9,9, 9}, /*CPUID available on DX4, >= 75 MHz*/ - {"iDX4/100", CPU_iDX4, 100000000, 3, 0x483, 0x483, 0, CPU_SUPPORTS_DYNAREC, 18,18,9,9, 12}, /*Is on some real Intel DX2s, limit here is pretty arbitary*/ - {"iDX4 OverDrive 75", CPU_iDX4, 75000000, 3, 0x1480, 0x1480, 0, CPU_SUPPORTS_DYNAREC, 12,12,9,9, 9}, - {"iDX4 OverDrive 100", CPU_iDX4, 100000000, 3, 0x1480, 0x1480, 0, CPU_SUPPORTS_DYNAREC, 18,18,9,9, 12}, - {"Pentium OverDrive 63", CPU_PENTIUM, 62500000, 5/2, 0x1531, 0x1531, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10,7,7, 15/2}, - {"Pentium OverDrive 83", CPU_PENTIUM, 83333333, 5/2, 0x1532, 0x1532, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,8,8, 10}, - {"", -1, 0, 0, 0, 0, 0, 0, 0, 0,0,0, 0} -}; - -CPU cpus_Am486[] = { - /*Am486/5x86*/ - {"Am486SX/33", CPU_Am486SX, 33333333, 1, 0x42a, 0, 0, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 4}, - {"Am486SX/40", CPU_Am486SX, 40000000, 1, 0x42a, 0, 0, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5}, - {"Am486SX2/50", CPU_Am486SX2, 50000000, 2, 0x45b, 0x45b, 0, CPU_SUPPORTS_DYNAREC, 8, 8, 6, 6, 6}, /*CPUID available on SX2, DX2, DX4, 5x86, >= 50 MHz*/ - {"Am486SX2/66", CPU_Am486SX2, 66666666, 2, 0x45b, 0x45b, 0, CPU_SUPPORTS_DYNAREC, 12,12, 6, 6, 8}, - {"Am486DX/33", CPU_Am486DX, 33333333, 1, 0x430, 0, 0, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 4}, - {"Am486DX/40", CPU_Am486DX, 40000000, 1, 0x430, 0, 0, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5}, - {"Am486DX2/50", CPU_Am486DX2, 50000000, 2, 0x470, 0x470, 0, CPU_SUPPORTS_DYNAREC, 8, 8, 6, 6, 6}, - {"Am486DX2/66", CPU_Am486DX2, 66666666, 2, 0x470, 0x470, 0, CPU_SUPPORTS_DYNAREC, 12,12, 6, 6, 8}, - {"Am486DX2/80", CPU_Am486DX2, 80000000, 2, 0x470, 0x470, 0, CPU_SUPPORTS_DYNAREC, 14,14, 6, 6, 10}, - {"Am486DX4/75", CPU_Am486DX4, 75000000, 3, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC, 12,12, 9, 9, 9}, - {"Am486DX4/90", CPU_Am486DX4, 90000000, 3, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC, 15,15, 9, 9, 12}, - {"Am486DX4/100", CPU_Am486DX4, 100000000, 3, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC, 15,15, 9, 9, 12}, - {"Am486DX4/120", CPU_Am486DX4, 120000000, 3, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC, 21,21, 9, 9, 15}, - {"Am5x86/P75", CPU_Am5x86, 133333333, 4, 0x4e0, 0x4e0, 0, CPU_SUPPORTS_DYNAREC, 24,24,12,12, 16}, - {"Am5x86/P75+", CPU_Am5x86, 150000000, 3, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC, 28,28,12,12, 20},/*The rare P75+ was indeed a triple-clocked 150 MHz according to research*/ - {"Am5x86/P90", CPU_Am5x86, 160000000, 4, 0x4e0, 0x4e0, 0, CPU_SUPPORTS_DYNAREC, 28,28,12,12, 20},/*160 MHz on a 40 MHz bus was a common overclock and "5x86/P90" was used by a number of BIOSes to refer to that configuration*/ - {"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} -}; - -CPU cpus_Cx486[] = { - /*Cyrix 486*/ - {"Cx486S/25", CPU_Cx486S, 25000000, 1, 0x420, 0, 0x0010, CPU_SUPPORTS_DYNAREC, 4, 4, 3, 3, 3}, - {"Cx486S/33", CPU_Cx486S, 33333333, 1, 0x420, 0, 0x0010, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 4}, - {"Cx486S/40", CPU_Cx486S, 40000000, 1, 0x420, 0, 0x0010, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5}, - {"Cx486DX/33", CPU_Cx486DX, 33333333, 1, 0x430, 0, 0x051a, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 4}, - {"Cx486DX/40", CPU_Cx486DX, 40000000, 1, 0x430, 0, 0x051a, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5}, - {"Cx486DX2/50", CPU_Cx486DX2, 50000000, 2, 0x430, 0, 0x081b, CPU_SUPPORTS_DYNAREC, 8, 8, 6, 6, 6}, - {"Cx486DX2/66", CPU_Cx486DX2, 66666666, 2, 0x430, 0, 0x0b1b, CPU_SUPPORTS_DYNAREC, 12,12, 6, 6, 8}, - {"Cx486DX2/80", CPU_Cx486DX2, 80000000, 2, 0x430, 0, 0x311b, CPU_SUPPORTS_DYNAREC, 14,14, 6, 6, 10}, - {"Cx486DX4/75", CPU_Cx486DX4, 75000000, 3, 0x480, 0, 0x361f, CPU_SUPPORTS_DYNAREC, 12,12, 9, 9, 9}, - {"Cx486DX4/100", CPU_Cx486DX4, 100000000, 3, 0x480, 0, 0x361f, CPU_SUPPORTS_DYNAREC, 15,15, 9, 9, 12}, - - /*Cyrix 5x86*/ - {"Cx5x86/80", CPU_Cx5x86, 80000000, 2, 0x480, 0, 0x002f, CPU_SUPPORTS_DYNAREC, 14,14, 6, 6, 10}, /*If we're including the Pentium 50, might as well include this*/ - {"Cx5x86/100", CPU_Cx5x86, 100000000, 3, 0x480, 0, 0x002f, CPU_SUPPORTS_DYNAREC, 15,15, 9, 9, 12}, - {"Cx5x86/120", CPU_Cx5x86, 120000000, 3, 0x480, 0, 0x002f, CPU_SUPPORTS_DYNAREC, 21,21, 9, 9, 15}, - {"Cx5x86/133", CPU_Cx5x86, 133333333, 4, 0x480, 0, 0x002f, CPU_SUPPORTS_DYNAREC, 24,24,12,12, 16}, - {"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} -}; - -#if defined(USE_NEW_DYNAREC) || (defined(DEV_BRANCH) && defined(USE_CYRIX_6X86)) -CPU cpus_6x863V[] = { - /*Cyrix 6x86*/ - {"Cx6x86/P90", CPU_Cx6x86, 80000000, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 8, 8, 6, 6, 10}, - {"Cx6x86/PR120+", CPU_Cx6x86, 100000000, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 12}, - {"Cx6x86/PR133+", CPU_Cx6x86, 110000000, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 14}, - {"Cx6x86/PR150+", CPU_Cx6x86, 120000000, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 14}, - {"Cx6x86/PR166+", CPU_Cx6x86, 133333333, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16}, - {"Cx6x86/PR200+", CPU_Cx6x86, 150000000, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 18}, - {"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} -}; - -CPU cpus_6x86[] = { - /*Cyrix 6x86*/ - {"Cx6x86/P90", CPU_Cx6x86, 80000000, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 8, 8, 6, 6, 10}, - {"Cx6x86/PR120+", CPU_Cx6x86, 100000000, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 12}, - {"Cx6x86/PR133+", CPU_Cx6x86, 110000000, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 14}, - {"Cx6x86/PR150+", CPU_Cx6x86, 120000000, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 14}, - {"Cx6x86/PR166+", CPU_Cx6x86, 133333333, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16}, - {"Cx6x86/PR200+", CPU_Cx6x86, 150000000, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 18}, - - /*Cyrix 6x86L*/ - {"Cx6x86L/PR133+", CPU_Cx6x86L, 110000000, 2, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 14}, - {"Cx6x86L/PR150+", CPU_Cx6x86L, 120000000, 2, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 14}, - {"Cx6x86L/PR166+", CPU_Cx6x86L, 133333333, 2, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16}, - {"Cx6x86L/PR200+", CPU_Cx6x86L, 150000000, 2, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 18}, - - /*Cyrix 6x86MX/MII*/ - {"Cx6x86MX/PR166", CPU_Cx6x86MX, 133333333, 2, 0x600, 0x600, 0x0451, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16}, - {"Cx6x86MX/PR200", CPU_Cx6x86MX, 166666666, 5/2, 0x600, 0x600, 0x0452, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20}, - {"Cx6x86MX/PR233", CPU_Cx6x86MX, 187500000, 5/2, 0x600, 0x600, 0x0452, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 45/2}, - {"Cx6x86MX/PR266", CPU_Cx6x86MX, 208333333, 5/2, 0x600, 0x600, 0x0452, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 17,17, 7, 7, 25}, - {"MII/PR300", CPU_Cx6x86MX, 233333333, 7/2, 0x601, 0x601, 0x0852, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,11,11, 28}, - {"MII/PR333", CPU_Cx6x86MX, 250000000, 3, 0x601, 0x601, 0x0853, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 23,23, 9, 9, 30}, - {"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} - }; -#endif - -#ifdef USE_NEW_DYNAREC - CPU cpus_6x86SS7[] = { - /*Cyrix 6x86*/ - {"Cx6x86/P90", CPU_Cx6x86, 80000000, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 8, 8, 6, 6, 10}, - {"Cx6x86/PR120+", CPU_Cx6x86, 100000000, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 12}, - {"Cx6x86/PR133+", CPU_Cx6x86, 110000000, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 14}, - {"Cx6x86/PR150+", CPU_Cx6x86, 120000000, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 14}, - {"Cx6x86/PR166+", CPU_Cx6x86, 133333333, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16}, - {"Cx6x86/PR200+", CPU_Cx6x86, 150000000, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 18}, - - /*Cyrix 6x86L*/ - {"Cx6x86L/PR133+", CPU_Cx6x86L, 110000000, 2, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 14}, - {"Cx6x86L/PR150+", CPU_Cx6x86L, 120000000, 2, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 14}, - {"Cx6x86L/PR166+", CPU_Cx6x86L, 133333333, 2, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16}, - {"Cx6x86L/PR200+", CPU_Cx6x86L, 150000000, 2, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 18}, - - /*Cyrix 6x86MX/MII*/ - {"Cx6x86MX/PR166", CPU_Cx6x86MX, 133333333, 2, 0x600, 0x600, 0x0451, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16}, - {"Cx6x86MX/PR200", CPU_Cx6x86MX, 166666666, 5/2, 0x600, 0x600, 0x0452, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20}, - {"Cx6x86MX/PR233", CPU_Cx6x86MX, 187500000, 5/2, 0x600, 0x600, 0x0452, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 45/2}, - {"Cx6x86MX/PR266", CPU_Cx6x86MX, 208333333, 5/2, 0x600, 0x600, 0x0452, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 17,17, 7, 7, 25}, - {"MII/PR300", CPU_Cx6x86MX, 233333333, 7/2, 0x601, 0x601, 0x0852, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,11,11, 28}, - {"MII/PR333", CPU_Cx6x86MX, 250000000, 3, 0x601, 0x601, 0x0853, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 23,23, 9, 9, 30}, - {"MII/PR366", CPU_Cx6x86MX, 250000000, 5/2, 0x601, 0x601, 0x0853, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 23,23, 7, 7, 30}, - {"MII/PR400", CPU_Cx6x86MX, 285000000, 3, 0x601, 0x601, 0x0853, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27, 9, 9, 34}, - {"MII/PR433", CPU_Cx6x86MX, 300000000, 3, 0x601, 0x601, 0x0853, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27, 9, 9, 36}, - {"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} - }; -#endif - -CPU cpus_WinChip[] = { - /*IDT WinChip*/ - {"WinChip 75", CPU_WINCHIP, 75000000, 3/2, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 8, 8, 4, 4, 9}, - {"WinChip 90", CPU_WINCHIP, 90000000, 3/2, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 9, 9, 4, 4, 21/2}, - {"WinChip 100", CPU_WINCHIP, 100000000, 3/2, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 9, 9, 4, 4, 12}, - {"WinChip 120", CPU_WINCHIP, 120000000, 2, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 12, 12, 6, 6, 14}, - {"WinChip 133", CPU_WINCHIP, 133333333, 2, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 12, 12, 6, 6, 16}, - {"WinChip 150", CPU_WINCHIP, 150000000, 5/2, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 15, 15, 7, 7, 35/2}, - {"WinChip 166", CPU_WINCHIP, 166666666, 5/2, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 15, 15, 7, 7, 40}, - {"WinChip 180", CPU_WINCHIP, 180000000, 3, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 21}, - {"WinChip 200", CPU_WINCHIP, 200000000, 3, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 24}, - {"WinChip 225", CPU_WINCHIP, 225000000, 3, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 27}, - {"WinChip 240", CPU_WINCHIP, 240000000, 4, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 24, 24, 12, 12, 28}, -#ifdef USE_NEW_DYNAREC - {"WinChip 2/200", CPU_WINCHIP2, 200000000, 3, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 24}, - {"WinChip 2/225", CPU_WINCHIP2, 225000000, 3, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 27}, - {"WinChip 2/240", CPU_WINCHIP2, 240000000, 4, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 24, 24, 12, 12, 30}, - {"WinChip 2/250", CPU_WINCHIP2, 250000000, 3, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 24, 24, 12, 12, 30}, - {"WinChip 2A/200", CPU_WINCHIP2, 200000000, 3, 0x587, 0x587, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 24}, - {"WinChip 2A/233", CPU_WINCHIP2, 233333333, 7/2, 0x587, 0x587, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, (7*8)/2}, -#endif - {"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} -}; - -#ifdef USE_NEW_DYNAREC -CPU cpus_WinChip_SS7[] = { - /*IDT WinChip*/ - {"WinChip 75", CPU_WINCHIP, 75000000, 3/2, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 8, 8, 4, 4, 9}, - {"WinChip 90", CPU_WINCHIP, 90000000, 3/2, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 9, 9, 4, 4, 21/2}, - {"WinChip 100", CPU_WINCHIP, 100000000, 3/2, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 9, 9, 4, 4, 12}, - {"WinChip 120", CPU_WINCHIP, 120000000, 2, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 12, 12, 6, 6, 14}, - {"WinChip 133", CPU_WINCHIP, 133333333, 2, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 12, 12, 6, 6, 16}, - {"WinChip 150", CPU_WINCHIP, 150000000, 5/2, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 15, 15, 7, 7, 35/2}, - {"WinChip 166", CPU_WINCHIP, 166666666, 5/2, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 15, 15, 7, 7, 40}, - {"WinChip 180", CPU_WINCHIP, 180000000, 3, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 21}, - {"WinChip 200", CPU_WINCHIP, 200000000, 3, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 24}, - {"WinChip 225", CPU_WINCHIP, 225000000, 3, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 27}, - {"WinChip 240", CPU_WINCHIP, 240000000, 4, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 24, 24, 12, 12, 28}, - {"WinChip 2/200", CPU_WINCHIP2, 200000000, 3, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 3*8}, - {"WinChip 2/225", CPU_WINCHIP2, 225000000, 3, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 3*9}, - {"WinChip 2/240", CPU_WINCHIP2, 240000000, 4, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 24, 24, 12, 12, 30}, - {"WinChip 2/250", CPU_WINCHIP2, 250000000, 3, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 24, 24, 12, 12, 30}, - {"WinChip 2A/200", CPU_WINCHIP2, 200000000, 3, 0x587, 0x587, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 3*8}, - {"WinChip 2A/233", CPU_WINCHIP2, 233333333, 7/2, 0x587, 0x587, 0, CPU_SUPPORTS_DYNAREC, 21, 21, 9, 9, (7*8)/2}, - {"WinChip 2A/266", CPU_WINCHIP2, 233333333, 7/3, 0x587, 0x587, 0, CPU_SUPPORTS_DYNAREC, 21, 21, 7, 7, 28}, - {"WinChip 2A/300", CPU_WINCHIP2, 250000000, 5/2, 0x587, 0x587, 0, CPU_SUPPORTS_DYNAREC, 24, 24, 8, 8, 30}, - {"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} -}; -#endif - -CPU cpus_Pentium5V[] = { - /*Intel Pentium (5V, socket 4)*/ - {"Pentium 60", CPU_PENTIUM, 60000000, 1, 0x517, 0x517, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6,3,3, 7}, - {"Pentium 66", CPU_PENTIUM, 66666666, 1, 0x517, 0x517, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6,3,3, 8}, - {"Pentium OverDrive 120", CPU_PENTIUM, 120000000, 2, 0x51A, 0x51A, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6, 14}, - {"Pentium OverDrive 133", CPU_PENTIUM, 133333333, 2, 0x51A, 0x51A, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6, 16}, - {"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} -}; - -CPU cpus_Pentium5V50[] = { - /*Intel Pentium (5V, socket 4, including 50 MHz FSB)*/ - {"Pentium 50 (Q0399)", CPU_PENTIUM, 50000000, 1, 0x513, 0x513, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 4, 4,3,3, 6}, - {"Pentium 60", CPU_PENTIUM, 60000000, 1, 0x517, 0x517, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6,3,3, 7}, - {"Pentium 66", CPU_PENTIUM, 66666666, 1, 0x517, 0x517, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6,3,3, 8}, - {"Pentium OverDrive 100", CPU_PENTIUM, 100000000, 2, 0x51A, 0x51A, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 8, 8,6,6, 12}, - {"Pentium OverDrive 120", CPU_PENTIUM, 120000000, 2, 0x51A, 0x51A, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6, 14}, - {"Pentium OverDrive 133", CPU_PENTIUM, 133333333, 2, 0x51A, 0x51A, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6, 16}, - {"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} -}; - -CPU cpus_PentiumS5[] = { - /*Intel Pentium (Socket 5)*/ - {"Pentium 75", CPU_PENTIUM, 75000000, 3/2, 0x522, 0x522, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7,4,4, 9}, - {"Pentium OverDrive MMX 75", CPU_PENTIUMMMX, 75000000, 3/2, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7,4,4, 9}, - {"Pentium 90", CPU_PENTIUM, 90000000, 3/2, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9,4,4, 21/2}, - {"Pentium 100/50", CPU_PENTIUM, 100000000, 2, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10,6,6, 12}, - {"Pentium 100/66", CPU_PENTIUM, 100000000, 3/2, 0x526, 0x526, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9,4,4, 12}, - {"Pentium 120", CPU_PENTIUM, 120000000, 2, 0x526, 0x526, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6, 14}, - - /*Intel Pentium OverDrive*/ - {"Pentium OverDrive 125", CPU_PENTIUM, 125000000, 3, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,7,7, 16}, - {"Pentium OverDrive 150", CPU_PENTIUM, 150000000, 5/2, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7, 35/2}, - {"Pentium OverDrive 166", CPU_PENTIUM, 166666666, 5/2, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7, 40}, - {"Pentium OverDrive MMX 125", CPU_PENTIUMMMX, 125000000, 5/2, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,7,7, 15}, - {"Pentium OverDrive MMX 150/60", CPU_PENTIUMMMX, 150000000, 5/2, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7, 35/2}, - {"Pentium OverDrive MMX 166", CPU_PENTIUMMMX, 166000000, 5/2, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7, 20}, - {"Pentium OverDrive MMX 180", CPU_PENTIUMMMX, 180000000, 3, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9, 21}, - {"Pentium OverDrive MMX 200", CPU_PENTIUMMMX, 200000000, 3, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9, 24}, - {"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} -}; - -CPU cpus_Pentium3V[] = { - /*Intel Pentium*/ - {"Pentium 75", CPU_PENTIUM, 75000000, 3/2, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7, 4, 4, 9}, - {"Pentium OverDrive MMX 75", CPU_PENTIUMMMX, 75000000, 3/2, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7, 4, 4, 9}, - {"Pentium 90", CPU_PENTIUM, 90000000, 3/2, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 4, 4, 21/2}, - {"Pentium 100/50", CPU_PENTIUM, 100000000, 2, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 12}, - {"Pentium 100/66", CPU_PENTIUM, 100000000, 3/2, 0x526, 0x526, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 4, 4, 12}, - {"Pentium 120", CPU_PENTIUM, 120000000, 2, 0x526, 0x526, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 14}, - {"Pentium 133", CPU_PENTIUM, 133333333, 2, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16}, - {"Pentium 150", CPU_PENTIUM, 150000000, 5/2, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 35/2}, - {"Pentium 166", CPU_PENTIUM, 166666666, 5/2, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20}, - {"Pentium 200", CPU_PENTIUM, 200000000, 3, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24}, - - /*Intel Pentium OverDrive*/ - {"Pentium OverDrive 125", CPU_PENTIUM, 125000000, 5/2, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 7, 7, 15}, - {"Pentium OverDrive 150", CPU_PENTIUM, 150000000, 5/2, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 35/2}, - {"Pentium OverDrive 166", CPU_PENTIUM, 166666666, 5/2, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20}, - {"Pentium OverDrive MMX 125", CPU_PENTIUMMMX, 125000000, 5/2, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 7, 7, 15}, - {"Pentium OverDrive MMX 150/60", CPU_PENTIUMMMX, 150000000, 5/2, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 35/2}, - {"Pentium OverDrive MMX 166", CPU_PENTIUMMMX, 166000000, 5/2, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20}, - {"Pentium OverDrive MMX 180", CPU_PENTIUMMMX, 180000000, 3, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 21}, - {"Pentium OverDrive MMX 200", CPU_PENTIUMMMX, 200000000, 3, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24}, - {"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} -}; - -CPU cpus_Pentium[] = { - /*Intel Pentium*/ - {"Pentium 75", CPU_PENTIUM, 75000000, 3/2, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7, 4, 4, 9}, - {"Pentium OverDrive MMX 75", CPU_PENTIUMMMX, 75000000, 3/2, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7, 4, 4, 9}, - {"Pentium 90", CPU_PENTIUM, 90000000, 3/2, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 4, 4, 21/2}, - {"Pentium 100/50", CPU_PENTIUM, 100000000, 2, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 12}, - {"Pentium 100/66", CPU_PENTIUM, 100000000, 3/2, 0x526, 0x526, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 4, 4, 12}, - {"Pentium 120", CPU_PENTIUM, 120000000, 2, 0x526, 0x526, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 14}, - {"Pentium 133", CPU_PENTIUM, 133333333, 2, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16}, - {"Pentium 150", CPU_PENTIUM, 150000000, 5/2, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 35/2}, - {"Pentium 166", CPU_PENTIUM, 166666666, 5/2, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20}, - {"Pentium 200", CPU_PENTIUM, 200000000, 3, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24}, - - /*Intel Pentium MMX*/ - {"Pentium MMX 166", CPU_PENTIUMMMX, 166666666, 5/2, 0x543, 0x543, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20}, - {"Pentium MMX 200", CPU_PENTIUMMMX, 200000000, 3, 0x543, 0x543, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24}, - {"Pentium MMX 233", CPU_PENTIUMMMX, 233333333, 7/2, 0x543, 0x543, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,10,10, 28}, - - /*Mobile Pentium*/ - {"Mobile Pentium MMX 120", CPU_PENTIUMMMX, 120000000, 2, 0x543, 0x543, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 14}, - {"Mobile Pentium MMX 133", CPU_PENTIUMMMX, 133333333, 2, 0x543, 0x543, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16}, - {"Mobile Pentium MMX 150", CPU_PENTIUMMMX, 150000000, 5/2, 0x544, 0x544, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 35/2}, - {"Mobile Pentium MMX 166", CPU_PENTIUMMMX, 166666666, 5/2, 0x544, 0x544, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20}, - {"Mobile Pentium MMX 200", CPU_PENTIUMMMX, 200000000, 3, 0x581, 0x581, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24}, - {"Mobile Pentium MMX 233", CPU_PENTIUMMMX, 233333333, 7/2, 0x581, 0x581, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,10,10, 28}, - {"Mobile Pentium MMX 266", CPU_PENTIUMMMX, 266666666, 4, 0x582, 0x582, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24,12,12, 32}, - {"Mobile Pentium MMX 300", CPU_PENTIUMMMX, 300000000, 9/2, 0x582, 0x582, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 36}, - - /*Intel Pentium OverDrive*/ - {"Pentium OverDrive 125", CPU_PENTIUM, 125000000, 5/2, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 7, 7, 15}, - {"Pentium OverDrive 150", CPU_PENTIUM, 150000000, 5/2, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 35/2}, - {"Pentium OverDrive 166", CPU_PENTIUM, 166666666, 5/2, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20}, - {"Pentium OverDrive MMX 125", CPU_PENTIUMMMX, 125000000, 5/2, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 7, 7, 15}, - {"Pentium OverDrive MMX 150/60", CPU_PENTIUMMMX, 150000000, 5/2, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 35/2}, - {"Pentium OverDrive MMX 166", CPU_PENTIUMMMX, 166000000, 5/2, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20}, - {"Pentium OverDrive MMX 180", CPU_PENTIUMMMX, 180000000, 3, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 21}, - {"Pentium OverDrive MMX 200", CPU_PENTIUMMMX, 200000000, 3, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24}, - {"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} -}; - -#if defined(USE_NEW_DYNAREC) || (defined(DEV_BRANCH) && defined(USE_AMD_K)) -CPU cpus_K5[] = { - /*AMD K5 (Socket 5)*/ - {"K5 (5k86) 75 (P75)", CPU_K5, 75000000, 3/2, 0x500, 0x500, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7,4,4, 9}, - {"K5 (SSA/5) 75 (PR75)", CPU_K5, 75000000, 3/2, 0x501, 0x501, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7,4,4, 9}, - {"K5 (5k86) 90 (P90)", CPU_K5, 90000000, 3/2, 0x500, 0x500, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9,4,4, 21/2}, - {"K5 (SSA/5) 90 (PR90)", CPU_K5, 90000000, 3/2, 0x501, 0x501, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9,4,4, 21/2}, - {"K5 (5k86) 100 (P100)", CPU_K5, 100000000, 3/2, 0x500, 0x500, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9,4,4, 12}, - {"K5 (SSA/5) 100 (PR100)", CPU_K5, 100000000, 3/2, 0x501, 0x501, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9,4,4, 12}, - {"K5 (5k86) 90 (PR120)", CPU_5K86, 120000000, 2, 0x511, 0x511, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6, 14}, - {"K5 (5k86) 100 (PR133)", CPU_5K86, 133333333, 2, 0x514, 0x514, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6, 16}, - {"K5 (5k86) 105 (PR150)", CPU_5K86, 150000000, 5/2, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7, 35/2}, - {"K5 (5k86) 116.5 (PR166)", CPU_5K86, 166666666, 5/2, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7, 20}, - {"K5 (5k86) 133 (PR200)", CPU_5K86, 200000000, 3, 0x534, 0x534, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9, 24}, - {"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} -}; - -CPU cpus_K56[] = { - /*AMD K5 (Socket 7)*/ - {"K5 (5k86) 75 (P75)", CPU_K5, 75000000, 3/2, 0x500, 0x500, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7, 4, 4, 9}, - {"K5 (SSA/5) 75 (PR75)", CPU_K5, 75000000, 3/2, 0x501, 0x501, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7, 4, 4, 9}, - {"K5 (5k86) 90 (P90)", CPU_K5, 90000000, 3/2, 0x500, 0x500, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 4, 4, 21/2}, - {"K5 (SSA/5) 90 (PR90)", CPU_K5, 90000000, 3/2, 0x501, 0x501, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 4, 4, 21/2}, - {"K5 (5k86) 100 (P100)", CPU_K5, 100000000, 3/2, 0x500, 0x500, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 4, 4, 12}, - {"K5 (SSA/5) 100 (PR100)", CPU_K5, 100000000, 3/2, 0x501, 0x501, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 4, 4, 12}, - {"K5 (5k86) 90 (PR120)", CPU_5K86, 120000000, 2, 0x511, 0x511, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 14}, - {"K5 (5k86) 100 (PR133)", CPU_5K86, 133333333, 2, 0x514, 0x514, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16}, - {"K5 (5k86) 105 (PR150)", CPU_5K86, 150000000, 5/2, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 35/2}, - {"K5 (5k86) 116.5 (PR166)", CPU_5K86, 166666666, 5/2, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20}, - {"K5 (5k86) 133 (PR200)", CPU_5K86, 200000000, 3, 0x534, 0x534, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24}, - - /*AMD K6 (Socket 7*/ - {"K6 (Model 6) 166", CPU_K6, 166666666, 5/2, 0x561, 0x561, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20}, - {"K6 (Model 6) 200", CPU_K6, 200000000, 3, 0x561, 0x561, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24}, - {"K6 (Model 6) 233", CPU_K6, 233333333, 7/2, 0x561, 0x561, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21, 10, 10, 28}, - {"K6 (Model 7) 200", CPU_K6, 200000000, 3, 0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24}, - {"K6 (Model 7) 233", CPU_K6, 233333333, 7/2, 0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21, 10, 10, 28}, - {"K6 (Model 7) 266", CPU_K6, 266666666, 4, 0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24, 12, 12, 32}, - {"K6 (Model 7) 300", CPU_K6, 300000000, 9/2, 0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27, 13, 13, 36}, -#ifdef USE_NEW_DYNAREC - {"K6-2/233", CPU_K6_2, 233333333, 7/2, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21, 10, 10, 28}, - {"K6-2/266", CPU_K6_2, 266666666, 4, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24, 12, 12, 32}, - {"K6-2/300 AFR-66", CPU_K6_2, 300000000, 9/2, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27, 13, 13, 36}, - {"K6-2/366", CPU_K6_2, 366666666, 11/2, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 33,33, 17, 17, 44}, -#endif - {"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} -}; -#endif - -#ifdef USE_NEW_DYNAREC -CPU cpus_K56_SS7[] = { - /*AMD K5 (Socket 7)*/ - {"K5 (5k86) 75 (P75)", CPU_K5, 75000000, 3/2, 0x500, 0x500, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7, 4, 4, 9}, - {"K5 (SSA/5) 75 (PR75)", CPU_K5, 75000000, 3/2, 0x501, 0x501, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7, 4, 4, 9}, - {"K5 (5k86) 90 (P90)", CPU_K5, 90000000, 3/2, 0x500, 0x500, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 4, 4, 21/2}, - {"K5 (SSA/5) 90 (PR90)", CPU_K5, 90000000, 3/2, 0x501, 0x501, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 4, 4, 21/2}, - {"K5 (5k86) 100 (P100)", CPU_K5, 100000000, 3/2, 0x500, 0x500, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 4, 4, 12}, - {"K5 (SSA/5) 100 (PR100)", CPU_K5, 100000000, 3/2, 0x501, 0x501, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 4, 4, 12}, - {"K5 (5k86) 90 (PR120)", CPU_5K86, 120000000, 2, 0x511, 0x511, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 14}, - {"K5 (5k86) 100 (PR133)", CPU_5K86, 133333333, 2, 0x514, 0x514, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16}, - {"K5 (5k86) 105 (PR150)", CPU_5K86, 150000000, 5/2, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 35/2}, - {"K5 (5k86) 116.5 (PR166)", CPU_5K86, 166666666, 5/2, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20}, - {"K5 (5k86) 133 (PR200)", CPU_5K86, 200000000, 3, 0x534, 0x534, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24}, - - /*AMD K6 (Socket 7)*/ - {"K6 (Model 6) 166", CPU_K6, 166666666, 5/2, 0x561, 0x561, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20}, - {"K6 (Model 6) 200", CPU_K6, 200000000, 3, 0x561, 0x561, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24}, - {"K6 (Model 6) 233", CPU_K6, 233333333, 7/2, 0x561, 0x561, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,10,10, 28}, - {"K6 (Model 7) 200", CPU_K6, 200000000, 3, 0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24}, - {"K6 (Model 7) 233", CPU_K6, 233333333, 7/2, 0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,10,10, 28}, - {"K6 (Model 7) 266", CPU_K6, 266666666, 4, 0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24,12,12, 32}, - {"K6 (Model 7) 300", CPU_K6, 300000000, 9/2, 0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 36}, - - /*AMD K6-2 (Socket 7/Super Socket 7)*/ - {"K6-2/233", CPU_K6_2, 233333333, 7/2, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21, 21, 10, 10, 28}, - {"K6-2/266", CPU_K6_2, 266666666, 4, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24, 24, 12, 12, 32}, - {"K6-2/300", CPU_K6_2, 300000000, 3, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27, 27, 9, 9, 36}, - {"K6-2/333", CPU_K6_2, 332500000, 7/2, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 30, 30, 11, 11, 40}, - {"K6-2/350", CPU_K6_2C, 350000000, 7/2, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 32, 32, 11, 11, 42}, - {"K6-2/366", CPU_K6_2C, 366666666, 11/2, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 33, 33, 17, 17, 44}, - {"K6-2/380", CPU_K6_2C, 380000000, 4, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 34, 34, 12, 12, 46}, - {"K6-2/400", CPU_K6_2C, 400000000, 4, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 36, 36, 12, 12, 48}, - {"K6-2/450", CPU_K6_2C, 450000000, 9/2, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 41, 41, 14, 14, 54}, - {"K6-2/475", CPU_K6_2C, 475000000, 5, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 43, 43, 15, 15, 57}, - {"K6-2/500", CPU_K6_2C, 500000000, 5, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 45, 45, 15, 15, 60}, - {"K6-2/533", CPU_K6_2C, 533333333, 11/2, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 48, 48, 17, 17, 64}, - {"K6-2/550", CPU_K6_2C, 550000000, 11/2, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 50, 50, 17, 17, 66}, - - /*AMD K6-2+/K6-3/K6-3+ (Super Socket 7)*/ - {"K6-2+/450", CPU_K6_2P, 450000000, 9/2, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 41, 41, 14, 14, 54}, - {"K6-2+/475", CPU_K6_2P, 475000000, 5, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 43, 43, 15, 15, 57}, - {"K6-2+/500", CPU_K6_2P, 500000000, 5, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 45, 45, 15, 15, 60}, - {"K6-2+/533", CPU_K6_2P, 533333333, 11/2, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 48, 48, 17, 17, 64}, - {"K6-2+/550", CPU_K6_2P, 550000000, 11/2, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 50, 50, 17, 17, 66}, - {"K6-III/400", CPU_K6_3, 400000000, 4, 0x591, 0x591, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 36, 36, 12, 12, 48}, - {"K6-III/450", CPU_K6_3, 450000000, 9/2, 0x591, 0x591, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 41, 41, 14, 14, 54}, - {"K6-III+/400", CPU_K6_3P, 400000000, 4, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 36, 36, 12, 12, 48}, - {"K6-III+/450", CPU_K6_3P, 450000000, 9/2, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 41, 41, 14, 14, 54}, - {"K6-III+/475", CPU_K6_3P, 475000000, 5, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 43, 43, 15, 15, 57}, - {"K6-III+/500", CPU_K6_3P, 500000000, 5, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 45, 45, 15, 15, 60}, - {"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} -}; -#endif - -#ifdef DEV_BRANCH -#ifdef USE_I686 -CPU cpus_PentiumPro[] = { - /*Intel Pentium Pro*/ - {"Pentium Pro 50", CPU_PENTIUMPRO, 50000000, 1, 0x612, 0x612, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 4, 4, 3, 3, 6}, - {"Pentium Pro 60" , CPU_PENTIUMPRO, 60000000, 1, 0x612, 0x612, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6, 3, 3, 7}, - {"Pentium Pro 66" , CPU_PENTIUMPRO, 66666666, 1, 0x612, 0x612, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6, 3, 3, 8}, - {"Pentium Pro 75", CPU_PENTIUMPRO, 75000000, 3/2, 0x612, 0x612, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7, 4, 4, 9}, - {"Pentium Pro 150", CPU_PENTIUMPRO, 150000000, 5/2, 0x612, 0x612, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 35/2}, - {"Pentium Pro 166", CPU_PENTIUMPRO, 166666666, 5/2, 0x617, 0x617, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20}, - {"Pentium Pro 180", CPU_PENTIUMPRO, 180000000, 3, 0x617, 0x617, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 21}, - {"Pentium Pro 200", CPU_PENTIUMPRO, 200000000, 3, 0x617, 0x617, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24}, - - /*Intel Pentium II OverDrive*/ - {"Pentium II Overdrive 50", CPU_PENTIUM2D, 50000000, 1, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 4, 4, 3, 3, 6}, - {"Pentium II Overdrive 60", CPU_PENTIUM2D, 60000000, 1, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6, 3, 3, 7}, - {"Pentium II Overdrive 66", CPU_PENTIUM2D, 66666666, 1, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6, 3, 3, 8}, - {"Pentium II Overdrive 75", CPU_PENTIUM2D, 75000000, 3/2, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7, 4, 4, 9}, - {"Pentium II Overdrive 210", CPU_PENTIUM2D, 210000000, 7/2, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 17,17, 7, 7, 25}, - {"Pentium II Overdrive 233", CPU_PENTIUM2D, 233333333, 7/2, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,10,10, 28}, - {"Pentium II Overdrive 240", CPU_PENTIUM2D, 240000000, 4, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24,12,12, 29}, - {"Pentium II Overdrive 266", CPU_PENTIUM2D, 266666666, 4, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24,12,12, 32}, - {"Pentium II Overdrive 270", CPU_PENTIUM2D, 270000000, 9/2, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 25,25,12,12, 33}, - {"Pentium II Overdrive 300/66", CPU_PENTIUM2D, 300000000, 9/2, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 25,25,12,12, 36}, - {"Pentium II Overdrive 300/60", CPU_PENTIUM2D, 300000000, 5, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 36}, - {"Pentium II Overdrive 333", CPU_PENTIUM2D, 333333333, 5, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 40}, - {"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} -}; - -CPU cpus_PentiumII[] = { - /*Intel Pentium II Klamath*/ - {"Pentium II Klamath 50", CPU_PENTIUM2, 50000000, 1, 0x634, 0x634, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 4, 4, 3, 3, 6}, - {"Pentium II Klamath 60", CPU_PENTIUM2, 60000000, 1, 0x634, 0x634, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6, 3, 3, 7}, - {"Pentium II Klamath 66", CPU_PENTIUM2, 66666666, 1, 0x634, 0x634, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6, 3, 3, 8}, - {"Pentium II Klamath 75", CPU_PENTIUM2, 75000000, 3/2, 0x634, 0x634, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7, 4, 4, 9}, - {"Pentium II Klamath 233", CPU_PENTIUM2, 233333333, 7/2, 0x634, 0x634, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,10,10, 28}, - {"Pentium II Klamath 266", CPU_PENTIUM2, 266666666, 4, 0x634, 0x634, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24,12,12, 29}, - {"Pentium II Klamath 300/66", CPU_PENTIUM2, 300000000, 9/2, 0x634, 0x634, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 25,25,12,12, 36}, - - /*Intel Pentium II Deschutes*/ - {"Pentium II Deschutes 50", CPU_PENTIUM2D, 50000000, 1, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 4, 4, 3, 3, 6}, - {"Pentium II Deschutes 60", CPU_PENTIUM2D, 60000000, 1, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6, 3, 3, 7}, - {"Pentium II Deschutes 66", CPU_PENTIUM2D, 66666666, 1, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6, 3, 3, 8}, - {"Pentium II Deschutes 75", CPU_PENTIUM2D, 75000000, 3/2, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7, 4, 4, 9}, - {"Pentium II Deschutes 266", CPU_PENTIUM2D, 266666666, 4, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24,12,12, 29}, - {"Pentium II Deschutes 300/66", CPU_PENTIUM2D, 300000000, 9/2, 0x651, 0x651, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 25,25,12,12, 36}, - {"Pentium II Deschutes 333", CPU_PENTIUM2D, 333333333, 5, 0x651, 0x651, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 40}, - {"Pentium II Deschutes 350", CPU_PENTIUM2D, 350000000, 7/2, 0x651, 0x651, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 32,32,11,11, 42}, - {"Pentium II Deschutes 400", CPU_PENTIUM2D, 400000000, 4, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 36,36,12,12, 48}, - {"Pentium II Deschutes 450", CPU_PENTIUM2D, 450000000, 9/2, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 41,41,14,14, 54}, - {"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} - -}; - -CPU cpus_Celeron[] = { // Mendocino Celerons. Exact architecture as the P2D series. Intended for - // the PGA370 boards but they were capable to fit on a PGA 370 to Slot 1 - // adaptor card so they work on Slot 1 motherboards too!. - - // The 100Mhz Mendocino is only meant to not cause any struggle - // to the recompiler. - {"Celeron Mendocino 100", CPU_PENTIUM2D, 100000000, 3/2, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 12}, - {"Celeron Mendocino 333", CPU_PENTIUM2D, 333333333, 5, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 40}, - {"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} -}; -#endif -#endif -CPU cpus_Cyrix3[] = { - /*VIA Cyrix III (Samuel)*/ - {"Cyrix III 66", CPU_CYRIX3S, 66666666, 1, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 8}, /*66 MHz version*/ - {"Cyrix III 233", CPU_CYRIX3S, 233333333, 3.5, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC, 21, 21, 9, 9, 28}, - {"Cyrix III 266", CPU_CYRIX3S, 266666666, 4, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC, 24, 24, 12, 12, 32}, - {"Cyrix III 300", CPU_CYRIX3S, 300000000, 4.5, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC, 27, 27, 13, 13, 36}, - {"Cyrix III 333", CPU_CYRIX3S, 333333333, 5, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC, 30, 30, 15, 15, 40}, - {"Cyrix III 350", CPU_CYRIX3S, 350000000, 3.5, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC, 32, 32, 11, 11, 42}, - {"Cyrix III 400", CPU_CYRIX3S, 400000000, 4, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC, 36, 36, 12, 12, 48}, - {"Cyrix III 450", CPU_CYRIX3S, 450000000, 4.5, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC, 41, 41, 14, 14, 54}, /*^ is lower P2 speeds to allow emulation below 466 mhz*/ - {"Cyrix III 500", CPU_CYRIX3S, 500000000, 5, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC, 45, 45, 15, 15, 60}, - {"Cyrix III 550", CPU_CYRIX3S, 550000000, 5.5, 0x662, 0x662, 0, CPU_SUPPORTS_DYNAREC, 50, 50, 17, 17, 66}, - {"Cyrix III 600", CPU_CYRIX3S, 600000000, 6, 0x662, 0x662, 0, CPU_SUPPORTS_DYNAREC, 54, 54, 18, 18, 72}, - {"Cyrix III 650", CPU_CYRIX3S, 650000000, 6.5, 0x662, 0x662, 0, CPU_SUPPORTS_DYNAREC, 58, 58, 20, 20, 78}, - {"Cyrix III 700", CPU_CYRIX3S, 700000000, 7, 0x662, 0x662, 0, CPU_SUPPORTS_DYNAREC, 62, 62, 21, 21, 84}, - {"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} +/* + * 86Box A hypervisor and IBM PC system emulator that specializes in + * running old operating systems and software designed for IBM + * PC systems and compatibles from 1981 through fairly recent + * system designs based on the PCI bus. + * + * This file is part of the 86Box distribution. + * + * Define all known processor types. + * + * Available cpuspeeds: + * + * 0 = 16 MHz + * 1 = 20 MHz + * 2 = 25 MHz + * 3 = 33 MHz + * 4 = 40 MHz + * 5 = 50 MHz + * 6 = 66 MHz + * 7 = 75 MHz + * 8 = 80 MHz + * 9 = 90 MHz + * 10 = 100 MHz + * 11 = 120 MHz + * 12 = 133 MHz + * 13 = 150 MHz + * 14 = 160 MHz + * 15 = 166 MHz + * 16 = 180 MHz + * 17 = 200 MHz + * + * + * + * Authors: Sarah Walker, + * leilei, + * Miran Grca, + * Fred N. van Kempen, + * + * Copyright 2008-2019 Sarah Walker. + * Copyright 2016-2019 leilei. + * Copyright 2016-2019 Miran Grca. + * Copyright 2017-2019 Fred N. van Kempen. + */ +#include +#include +#include +#include +#include "86box.h" +#include "cpu.h" +#include "machine.h" + + +CPU cpus_8088[] = { + /*8088 standard*/ + {"8088/4.77", CPU_8088, 4772728, 1, 0, 0, 0, 0, 0,0,0,0, 1}, + {"8088/7.16", CPU_8088, 7159092, 1, 0, 0, 0, 0, 0,0,0,0, 1}, + {"8088/8", CPU_8088, 8000000, 1, 0, 0, 0, 0, 0,0,0,0, 1}, + {"8088/10", CPU_8088, 10000000, 1, 0, 0, 0, 0, 0,0,0,0, 1}, + {"8088/12", CPU_8088, 12000000, 1, 0, 0, 0, 0, 0,0,0,0, 1}, + {"8088/16", CPU_8088, 16000000, 1, 0, 0, 0, 0, 0,0,0,0, 1}, + {"", -1, 0, 0, 0, 0, 0, 0, 0,0,0,0, 0} +}; + +CPU cpus_pcjr[] = { + /*8088 PCjr*/ + {"8088/4.77", CPU_8088, 4772728, 1, 0, 0, 0, 0, 0,0,0,0, 1}, + {"", -1, 0, 0, 0, 0, 0, 0, 0,0,0,0, 0} +}; + +CPU cpus_europc[] = { + /*8088 EuroPC*/ + {"8088/4.77", CPU_8088, 4772728, 1, 0, 0, 0, CPU_ALTERNATE_XTAL, 0,0,0,0, 1}, + {"8088/7.16", CPU_8088, 7159092, 1, 0, 0, 0, CPU_ALTERNATE_XTAL, 0,0,0,0, 1}, + {"8088/9.54", CPU_8088, 9545456, 1, 0, 0, 0, 0, 0,0,0,0, 1}, + {"", -1, 0, 0, 0, 0, 0, 0, 0,0,0,0, 0} +}; + +CPU cpus_8086[] = { + /*8086 standard*/ + {"8086/7.16", CPU_8086, 7159092, 1, 0, 0, 0, CPU_ALTERNATE_XTAL, 0,0,0,0, 1}, + {"8086/8", CPU_8086, 8000000, 1, 0, 0, 0, 0, 0,0,0,0, 1}, + {"8086/9.54", CPU_8086, 9545456, 1, 0, 0, 0, CPU_ALTERNATE_XTAL, 0,0,0,0, 1}, + {"8086/10", CPU_8086, 10000000, 1, 0, 0, 0, 0, 0,0,0,0, 1}, + {"8086/12", CPU_8086, 12000000, 1, 0, 0, 0, 0, 0,0,0,0, 1}, + {"8086/16", CPU_8086, 16000000, 1, 0, 0, 0, 0, 0,0,0,0, 2}, + {"", -1, 0, 0, 0, 0, 0, 0, 0,0,0,0, 0} +}; + +CPU cpus_pc1512[] = { + /*8086 Amstrad*/ + {"8086/8", CPU_8086, 8000000, 1, 0, 0, 0, 0, 0,0,0,0, 1}, + {"", -1, 0, 0, 0, 0, 0, 0, 0,0,0,0, 0} +}; + +CPU cpus_286[] = { + /*286*/ + {"286/6", CPU_286, 6000000, 1, 0, 0, 0, 0, 2,2,2,2, 1}, + {"286/8", CPU_286, 8000000, 1, 0, 0, 0, 0, 2,2,2,2, 1}, + {"286/10", CPU_286, 10000000, 1, 0, 0, 0, 0, 2,2,2,2, 1}, + {"286/12", CPU_286, 12500000, 1, 0, 0, 0, 0, 3,3,3,3, 2}, + {"286/16", CPU_286, 16000000, 1, 0, 0, 0, 0, 3,3,3,3, 2}, + {"286/20", CPU_286, 20000000, 1, 0, 0, 0, 0, 4,4,4,4, 3}, + {"286/25", CPU_286, 25000000, 1, 0, 0, 0, 0, 4,4,4,4, 3}, + {"", -1, 0, 0, 0, 0, 0, 0, 0,0,0,0, 0} +}; + +CPU cpus_ibmat[] = { + /*286*/ + {"286/6", CPU_286, 6000000, 1, 0, 0, 0, 0, 3,3,3,3, 1}, + {"286/8", CPU_286, 8000000, 1, 0, 0, 0, 0, 3,3,3,3, 1}, + {"", -1, 0, 0, 0, 0, 0, 0, 0,0,0,0, 0} +}; + +CPU cpus_ibmxt286[] = { + /*286*/ + {"286/6", CPU_286, 6000000, 1, 0, 0, 0, 0, 2,2,2,2, 1}, + {"", -1, 0, 0, 0, 0, 0, 0, 0,0,0,0, 0} +}; + +CPU cpus_ps1_m2011[] = { + /*286*/ + {"286/10", CPU_286, 10000000, 1, 0, 0, 0, 0, 2,2,2,2, 1}, + {"", -1, 0, 0, 0, 0, 0, 0, 0,0,0,0, 9} +}; + +CPU cpus_ps2_m30_286[] = { + /*286*/ + {"286/10", CPU_286, 10000000, 1, 0, 0, 0, 0, 2,2,2,2, 1}, + {"286/12", CPU_286, 12500000, 1, 0, 0, 0, 0, 3,3,3,3, 2}, + {"286/16", CPU_286, 16000000, 1, 0, 0, 0, 0, 3,3,3,3, 2}, + {"286/20", CPU_286, 20000000, 1, 0, 0, 0, 0, 4,4,4,4, 3}, + {"286/25", CPU_286, 25000000, 1, 0, 0, 0, 0, 4,4,4,4, 3}, + {"", -1, 0, 0, 0, 0, 0, 0, 0,0,0,0, 0} +}; + +CPU cpus_i386SX[] = { + /*i386SX*/ + {"i386SX/16", CPU_386SX, 16000000, 1, 0x2308, 0, 0, 0, 3,3,3,3, 2}, + {"i386SX/20", CPU_386SX, 20000000, 1, 0x2308, 0, 0, 0, 4,4,3,3, 3}, + {"i386SX/25", CPU_386SX, 25000000, 1, 0x2308, 0, 0, 0, 4,4,3,3, 3}, + {"i386SX/33", CPU_386SX, 33333333, 1, 0x2308, 0, 0, 0, 6,6,3,3, 4}, + {"i386SX/40", CPU_386SX, 40000000, 1, 0x2308, 0, 0, 0, 7,7,3,3, 5}, + {"", -1, 0, 0, 0, 0, 0, 0, 0,0,0,0, 0} +}; + +CPU cpus_i386DX[] = { + /*i386DX/RapidCAD*/ + {"i386DX/16", CPU_386DX, 16000000, 1, 0x0308, 0, 0, 0, 3,3,3,3, 2}, + {"i386DX/20", CPU_386DX, 20000000, 1, 0x0308, 0, 0, 0, 4,4,3,3, 3}, + {"i386DX/25", CPU_386DX, 25000000, 1, 0x0308, 0, 0, 0, 4,4,3,3, 3}, + {"i386DX/33", CPU_386DX, 33333333, 1, 0x0308, 0, 0, 0, 6,6,3,3, 4}, + {"i386DX/40", CPU_386DX, 40000000, 1, 0x0308, 0, 0, 0, 7,7,3,3, 5}, + {"RapidCAD/25", CPU_RAPIDCAD, 25000000, 1, 0x0430, 0, 0, CPU_SUPPORTS_DYNAREC, 4,4,3,3, 3}, + {"RapidCAD/33", CPU_RAPIDCAD, 33333333, 1, 0x0430, 0, 0, CPU_SUPPORTS_DYNAREC, 6,6,3,3, 4}, + {"RapidCAD/40", CPU_RAPIDCAD, 40000000, 1, 0x0430, 0, 0, CPU_SUPPORTS_DYNAREC, 7,7,3,3, 5}, + {"", -1, 0, 0, 0, 0, 0, 0, 0,0,0,0, 0} +}; + +CPU cpus_Am386SX[] = { + /*Am386SX*/ + {"Am386SX/16", CPU_386SX, 16000000, 1, 0x2308, 0, 0, 0, 3,3,3,3, 2}, + {"Am386SX/20", CPU_386SX, 20000000, 1, 0x2308, 0, 0, 0, 4,4,3,3, 3}, + {"Am386SX/25", CPU_386SX, 25000000, 1, 0x2308, 0, 0, 0, 4,4,3,3, 3}, + {"Am386SX/33", CPU_386SX, 33333333, 1, 0x2308, 0, 0, 0, 6,6,3,3, 4}, + {"Am386SX/40", CPU_386SX, 40000000, 1, 0x2308, 0, 0, 0, 7,7,3,3, 5}, + {"", -1, 0, 0, 0, 0, 0, 0, 0,0,0,0, 0} +}; + +CPU cpus_Am386DX[] = { + /*Am386DX*/ + {"Am386DX/25", CPU_386DX, 25000000, 1, 0x0308, 0, 0, 0, 4,4,3,3, 3}, + {"Am386DX/33", CPU_386DX, 33333333, 1, 0x0308, 0, 0, 0, 6,6,3,3, 4}, + {"Am386DX/40", CPU_386DX, 40000000, 1, 0x0308, 0, 0, 0, 7,7,3,3, 5}, + {"", -1, 0, 0, 0, 0, 0, 0, 0,0,0,0, 0} +}; + +CPU cpus_486SLC[] = { + /*Cx486SLC*/ + {"Cx486SLC/20", CPU_486SLC, 20000000, 1, 0x400, 0, 0x0000, 0, 4,4,3,3, 3}, + {"Cx486SLC/25", CPU_486SLC, 25000000, 1, 0x400, 0, 0x0000, 0, 4,4,3,3, 3}, + {"Cx486SLC/33", CPU_486SLC, 33333333, 1, 0x400, 0, 0x0000, 0, 6,6,3,3, 4}, + {"Cx486SRx2/32", CPU_486SLC, 32000000, 2, 0x406, 0, 0x0006, 0, 6,6,6,6, 4}, + {"Cx486SRx2/40", CPU_486SLC, 40000000, 2, 0x406, 0, 0x0006, 0, 8,8,6,6, 6}, + {"Cx486SRx2/50", CPU_486SLC, 50000000, 2, 0x406, 0, 0x0006, 0, 8,8,6,6, 6}, + {"", -1, 0, 0, 0, 0, 0, 0, 0,0,0,0, 0} +}; + +CPU cpus_IBM386SLC[] = { + /*IBM 386SLC*/ + {"386SLC/16", CPU_IBM386SLC, 16000000, 1, 0x300, 0, 0, 0, 3,3,3,3, 2}, + {"386SLC/20", CPU_IBM386SLC, 20000000, 1, 0x300, 0, 0, 0, 4,4,3,3, 3}, + {"386SLC/25", CPU_IBM386SLC, 25000000, 1, 0x300, 0, 0, 0, 4,4,3,3, 3}, + {"", -1, 0, 0, 0, 0, 0, 0, 0,0,0,0, 0} +}; + +CPU cpus_IBM486SLC[] = { + /*IBM 486SLC*/ + {"486SLC/33", CPU_IBM486SLC, 33333333, 1, 0x400, 0, 0, 0, 6,6,3,3, 4}, + {"486SLC2/40", CPU_IBM486SLC, 40000000, 2, 0x400, 0, 0, 0, 7,7,6,6, 5}, + {"486SLC2/50", CPU_IBM486SLC, 50000000, 2, 0x400, 0, 0, 0, 8,8,6,6, 6}, + {"486SLC2/66", CPU_IBM486SLC, 66666666, 2, 0x400, 0, 0, 0, 12,12,6,6, 8}, + {"486SLC3/60", CPU_IBM486SLC, 60000000, 3, 0x400, 0, 0, 0, 12,12,9,9, 7}, + {"486SLC3/75", CPU_IBM486SLC, 75000000, 3, 0x400, 0, 0, 0, 12,12,9,9, 9}, + {"486SLC3/100", CPU_IBM486SLC, 100000000, 3, 0x400, 0, 0, 0, 18,18,9,9, 12}, + {"", -1, 0, 0, 0, 0, 0, 0, 0,0,0,0, 0} +}; + +CPU cpus_IBM486BL[] = { + /*IBM Blue Lightning*/ + {"486BL2/50", CPU_IBM486BL, 50000000, 2, 0x400, 0, 0, 0, 8,8,6,6, 6}, + {"486BL2/66", CPU_IBM486BL, 66666666, 2, 0x400, 0, 0, 0, 12,12,6,6, 8}, + {"486BL3/75", CPU_IBM486BL, 75000000, 3, 0x400, 0, 0, 0, 12,12,9,9, 9}, + {"486BL3/100", CPU_IBM486BL, 100000000, 3, 0x400, 0, 0, 0, 18,18,9,9, 12}, + {"", -1, 0, 0, 0, 0, 0, 0, 0,0,0,0, 0} +}; + +CPU cpus_486DLC[] = { + /*Cx486DLC*/ + {"Cx486DLC/25", CPU_486DLC, 25000000, 1, 0x401, 0, 0x0001, 0, 4, 4,3,3, 3}, + {"Cx486DLC/33", CPU_486DLC, 33333333, 1, 0x401, 0, 0x0001, 0, 6, 6,3,3, 4}, + {"Cx486DLC/40", CPU_486DLC, 40000000, 1, 0x401, 0, 0x0001, 0, 7, 7,3,3, 5}, + {"Cx486DRx2/32", CPU_486DLC, 32000000, 2, 0x407, 0, 0x0007, 0, 6, 6,6,6, 4}, + {"Cx486DRx2/40", CPU_486DLC, 40000000, 2, 0x407, 0, 0x0007, 0, 8, 8,6,6, 6}, + {"Cx486DRx2/50", CPU_486DLC, 50000000, 2, 0x407, 0, 0x0007, 0, 8, 8,6,6, 6}, + {"Cx486DRx2/66", CPU_486DLC, 66666666, 2, 0x407, 0, 0x0007, 0, 12,12,6,6, 8}, + {"", -1, 0, 0, 0, 0, 0, 0, 0, 0,0,0, 0} +}; + +CPU cpus_i486S1[] = { + /*i486*/ + {"i486SX/16", CPU_i486SX, 16000000, 1, 0x420, 0, 0, CPU_SUPPORTS_DYNAREC, 3, 3,3,3, 2}, + {"i486SX/20", CPU_i486SX, 20000000, 1, 0x420, 0, 0, CPU_SUPPORTS_DYNAREC, 4, 4,3,3, 3}, + {"i486SX/25", CPU_i486SX, 25000000, 1, 0x422, 0, 0, CPU_SUPPORTS_DYNAREC, 4, 4,3,3, 3}, + {"i486SX/33", CPU_i486SX, 33333333, 1, 0x42a, 0, 0, CPU_SUPPORTS_DYNAREC, 6, 6,3,3, 4}, + {"i486SX2/50", CPU_i486SX, 50000000, 2, 0x45b, 0, 0, CPU_SUPPORTS_DYNAREC, 8, 8,6,6, 6}, + {"i486SX2/66 (Q0569)", CPU_i486SX, 66666666, 2, 0x45b, 0, 0, CPU_SUPPORTS_DYNAREC, 8, 8,6,6, 8}, + {"i486DX/25", CPU_i486DX, 25000000, 1, 0x404, 0, 0, CPU_SUPPORTS_DYNAREC, 4, 4,3,3, 3}, + {"i486DX/33", CPU_i486DX, 33333333, 1, 0x414, 0, 0, CPU_SUPPORTS_DYNAREC, 6, 6,3,3, 4}, + {"i486DX/50", CPU_i486DX, 50000000, 1, 0x411, 0, 0, CPU_SUPPORTS_DYNAREC, 8, 8,4,4, 6}, + {"i486DX2/40", CPU_i486DX, 40000000, 2, 0x430, 0x430, 0, CPU_SUPPORTS_DYNAREC, 7, 7,6,6, 5}, + {"i486DX2/50", CPU_i486DX, 50000000, 2, 0x433, 0x433, 0, CPU_SUPPORTS_DYNAREC, 8, 8,6,6, 6}, + {"i486DX2/66", CPU_i486DX, 66666666, 2, 0x435, 0x435, 0, CPU_SUPPORTS_DYNAREC, 12,12,6,6, 8}, + {"iDX4 OverDrive 75", CPU_iDX4, 75000000, 3, 0x1480, 0x1480, 0, CPU_SUPPORTS_DYNAREC, 12,12,9,9, 9}, /*Only added the DX4 OverDrive as the others would be redundant*/ + {"iDX4 OverDrive 100", CPU_iDX4, 100000000, 3, 0x1480, 0x1480, 0, CPU_SUPPORTS_DYNAREC, 18,18,9,9, 12}, + {"", -1, 0, 0, 0, 0, 0, 0, 0, 0,0,0, 0} +}; +CPU cpus_Am486S1[] = { + /*Am486*/ + {"Am486SX/33", CPU_Am486SX, 33333333, 1, 0x42a, 0, 0, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 4}, + {"Am486SX/40", CPU_Am486SX, 40000000, 1, 0x42a, 0, 0, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5}, + {"Am486SX2/50", CPU_Am486SX2, 50000000, 2, 0x45b, 0x45b, 0, CPU_SUPPORTS_DYNAREC, 8, 8, 6, 6, 6}, /*CPUID available on SX2, DX2, DX4, 5x86, >= 50 MHz*/ + {"Am486SX2/66", CPU_Am486SX2, 66666666, 2, 0x45b, 0x45b, 0, CPU_SUPPORTS_DYNAREC, 12,12, 6, 6, 8}, /*Isn't on all real AMD SX2s and DX2s, availability here is pretty arbitary (and distinguishes them from the Intel chips)*/ + {"Am486DX/33", CPU_Am486DX, 33333333, 1, 0x430, 0, 0, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 4}, + {"Am486DX/40", CPU_Am486DX, 40000000, 1, 0x430, 0, 0, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5}, + {"Am486DX2/50", CPU_Am486DX2, 50000000, 2, 0x470, 0x470, 0, CPU_SUPPORTS_DYNAREC, 8, 8, 6, 6, 6}, + {"Am486DX2/66", CPU_Am486DX2, 66666666, 2, 0x470, 0x470, 0, CPU_SUPPORTS_DYNAREC, 12,12, 6, 6, 8}, + {"Am486DX2/80", CPU_Am486DX2, 80000000, 2, 0x470, 0x470, 0, CPU_SUPPORTS_DYNAREC, 14,14, 6, 6, 10}, + {"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} +}; +CPU cpus_Cx486S1[] = { + /*Cyrix 486*/ + {"Cx486S/25", CPU_Cx486S, 25000000, 1, 0x420, 0, 0x0010, CPU_SUPPORTS_DYNAREC, 4, 4, 3, 3, 3}, + {"Cx486S/33", CPU_Cx486S, 33333333, 1, 0x420, 0, 0x0010, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 4}, + {"Cx486S/40", CPU_Cx486S, 40000000, 1, 0x420, 0, 0x0010, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5}, + {"Cx486DX/33", CPU_Cx486DX, 33333333, 1, 0x430, 0, 0x051a, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 4}, + {"Cx486DX/40", CPU_Cx486DX, 40000000, 1, 0x430, 0, 0x051a, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5}, + {"Cx486DX2/50", CPU_Cx486DX2, 50000000, 2, 0x430, 0, 0x081b, CPU_SUPPORTS_DYNAREC, 8, 8, 6, 6, 6}, + {"Cx486DX2/66", CPU_Cx486DX2, 66666666, 2, 0x430, 0, 0x0b1b, CPU_SUPPORTS_DYNAREC, 12,12, 6, 6, 8}, + {"Cx486DX2/80", CPU_Cx486DX2, 80000000, 2, 0x430, 0, 0x311b, CPU_SUPPORTS_DYNAREC, 14,14, 6, 6, 10}, + {"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} +}; + +CPU cpus_i486[] = { + /*i486/P24T*/ + {"i486SX/16", CPU_i486SX, 16000000, 1, 0x420, 0, 0, CPU_SUPPORTS_DYNAREC, 3, 3,3,3, 2}, + {"i486SX/20", CPU_i486SX, 20000000, 1, 0x420, 0, 0, CPU_SUPPORTS_DYNAREC, 4, 4,3,3, 3}, + {"i486SX/25", CPU_i486SX, 25000000, 1, 0x422, 0, 0, CPU_SUPPORTS_DYNAREC, 4, 4,3,3, 3}, + {"i486SX/33", CPU_i486SX, 33333333, 1, 0x42a, 0, 0, CPU_SUPPORTS_DYNAREC, 6, 6,3,3, 4}, + {"i486SX2/50", CPU_i486SX, 50000000, 2, 0x45b, 0, 0, CPU_SUPPORTS_DYNAREC, 8, 8,6,6, 6}, + {"i486SX2/66 (Q0569)", CPU_i486SX, 66666666, 2, 0x45b, 0, 0, CPU_SUPPORTS_DYNAREC, 8, 8,6,6, 8}, + {"i486DX/25", CPU_i486DX, 25000000, 1, 0x404, 0, 0, CPU_SUPPORTS_DYNAREC, 4, 4,3,3, 3}, + {"i486DX/33", CPU_i486DX, 33333333, 1, 0x414, 0, 0, CPU_SUPPORTS_DYNAREC, 6, 6,3,3, 4}, + {"i486DX/50", CPU_i486DX, 50000000, 1, 0x411, 0, 0, CPU_SUPPORTS_DYNAREC, 8, 8,4,4, 6}, + {"i486DX2/40", CPU_i486DX, 40000000, 2, 0x430, 0x430, 0, CPU_SUPPORTS_DYNAREC, 7, 7,6,6, 5}, + {"i486DX2/50", CPU_i486DX, 50000000, 2, 0x433, 0x433, 0, CPU_SUPPORTS_DYNAREC, 8, 8,6,6, 6}, + {"i486DX2/66", CPU_i486DX, 66666666, 2, 0x435, 0x435, 0, CPU_SUPPORTS_DYNAREC, 12,12,6,6, 8}, + {"iDX4/75", CPU_iDX4, 75000000, 3, 0x480, 0x480, 0, CPU_SUPPORTS_DYNAREC, 12,12,9,9, 9}, /*CPUID available on DX4, >= 75 MHz*/ + {"iDX4/100", CPU_iDX4, 100000000, 3, 0x483, 0x483, 0, CPU_SUPPORTS_DYNAREC, 18,18,9,9, 12}, /*Is on some real Intel DX2s, limit here is pretty arbitary*/ + {"iDX4 OverDrive 75", CPU_iDX4, 75000000, 3, 0x1480, 0x1480, 0, CPU_SUPPORTS_DYNAREC, 12,12,9,9, 9}, + {"iDX4 OverDrive 100", CPU_iDX4, 100000000, 3, 0x1480, 0x1480, 0, CPU_SUPPORTS_DYNAREC, 18,18,9,9, 12}, + {"Pentium OverDrive 63", CPU_PENTIUM, 62500000, 5/2, 0x1531, 0x1531, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10,7,7, 15/2}, + {"Pentium OverDrive 83", CPU_PENTIUM, 83333333, 5/2, 0x1532, 0x1532, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,8,8, 10}, + {"", -1, 0, 0, 0, 0, 0, 0, 0, 0,0,0, 0} +}; + +CPU cpus_Am486[] = { + /*Am486/5x86*/ + {"Am486SX/33", CPU_Am486SX, 33333333, 1, 0x42a, 0, 0, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 4}, + {"Am486SX/40", CPU_Am486SX, 40000000, 1, 0x42a, 0, 0, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5}, + {"Am486SX2/50", CPU_Am486SX2, 50000000, 2, 0x45b, 0x45b, 0, CPU_SUPPORTS_DYNAREC, 8, 8, 6, 6, 6}, /*CPUID available on SX2, DX2, DX4, 5x86, >= 50 MHz*/ + {"Am486SX2/66", CPU_Am486SX2, 66666666, 2, 0x45b, 0x45b, 0, CPU_SUPPORTS_DYNAREC, 12,12, 6, 6, 8}, + {"Am486DX/33", CPU_Am486DX, 33333333, 1, 0x430, 0, 0, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 4}, + {"Am486DX/40", CPU_Am486DX, 40000000, 1, 0x430, 0, 0, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5}, + {"Am486DX2/50", CPU_Am486DX2, 50000000, 2, 0x470, 0x470, 0, CPU_SUPPORTS_DYNAREC, 8, 8, 6, 6, 6}, + {"Am486DX2/66", CPU_Am486DX2, 66666666, 2, 0x470, 0x470, 0, CPU_SUPPORTS_DYNAREC, 12,12, 6, 6, 8}, + {"Am486DX2/80", CPU_Am486DX2, 80000000, 2, 0x470, 0x470, 0, CPU_SUPPORTS_DYNAREC, 14,14, 6, 6, 10}, + {"Am486DX4/75", CPU_Am486DX4, 75000000, 3, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC, 12,12, 9, 9, 9}, + {"Am486DX4/90", CPU_Am486DX4, 90000000, 3, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC, 15,15, 9, 9, 12}, + {"Am486DX4/100", CPU_Am486DX4, 100000000, 3, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC, 15,15, 9, 9, 12}, + {"Am486DX4/120", CPU_Am486DX4, 120000000, 3, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC, 21,21, 9, 9, 15}, + {"Am5x86/P75", CPU_Am5x86, 133333333, 4, 0x4e0, 0x4e0, 0, CPU_SUPPORTS_DYNAREC, 24,24,12,12, 16}, + {"Am5x86/P75+", CPU_Am5x86, 150000000, 3, 0x482, 0x482, 0, CPU_SUPPORTS_DYNAREC, 28,28,12,12, 20},/*The rare P75+ was indeed a triple-clocked 150 MHz according to research*/ + {"Am5x86/P90", CPU_Am5x86, 160000000, 4, 0x4e0, 0x4e0, 0, CPU_SUPPORTS_DYNAREC, 28,28,12,12, 20},/*160 MHz on a 40 MHz bus was a common overclock and "5x86/P90" was used by a number of BIOSes to refer to that configuration*/ + {"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} +}; + +CPU cpus_Cx486[] = { + /*Cyrix 486*/ + {"Cx486S/25", CPU_Cx486S, 25000000, 1, 0x420, 0, 0x0010, CPU_SUPPORTS_DYNAREC, 4, 4, 3, 3, 3}, + {"Cx486S/33", CPU_Cx486S, 33333333, 1, 0x420, 0, 0x0010, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 4}, + {"Cx486S/40", CPU_Cx486S, 40000000, 1, 0x420, 0, 0x0010, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5}, + {"Cx486DX/33", CPU_Cx486DX, 33333333, 1, 0x430, 0, 0x051a, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 4}, + {"Cx486DX/40", CPU_Cx486DX, 40000000, 1, 0x430, 0, 0x051a, CPU_SUPPORTS_DYNAREC, 7, 7, 3, 3, 5}, + {"Cx486DX2/50", CPU_Cx486DX2, 50000000, 2, 0x430, 0, 0x081b, CPU_SUPPORTS_DYNAREC, 8, 8, 6, 6, 6}, + {"Cx486DX2/66", CPU_Cx486DX2, 66666666, 2, 0x430, 0, 0x0b1b, CPU_SUPPORTS_DYNAREC, 12,12, 6, 6, 8}, + {"Cx486DX2/80", CPU_Cx486DX2, 80000000, 2, 0x430, 0, 0x311b, CPU_SUPPORTS_DYNAREC, 14,14, 6, 6, 10}, + {"Cx486DX4/75", CPU_Cx486DX4, 75000000, 3, 0x480, 0, 0x361f, CPU_SUPPORTS_DYNAREC, 12,12, 9, 9, 9}, + {"Cx486DX4/100", CPU_Cx486DX4, 100000000, 3, 0x480, 0, 0x361f, CPU_SUPPORTS_DYNAREC, 15,15, 9, 9, 12}, + + /*Cyrix 5x86*/ + {"Cx5x86/80", CPU_Cx5x86, 80000000, 2, 0x480, 0, 0x002f, CPU_SUPPORTS_DYNAREC, 14,14, 6, 6, 10}, /*If we're including the Pentium 50, might as well include this*/ + {"Cx5x86/100", CPU_Cx5x86, 100000000, 3, 0x480, 0, 0x002f, CPU_SUPPORTS_DYNAREC, 15,15, 9, 9, 12}, + {"Cx5x86/120", CPU_Cx5x86, 120000000, 3, 0x480, 0, 0x002f, CPU_SUPPORTS_DYNAREC, 21,21, 9, 9, 15}, + {"Cx5x86/133", CPU_Cx5x86, 133333333, 4, 0x480, 0, 0x002f, CPU_SUPPORTS_DYNAREC, 24,24,12,12, 16}, + {"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} +}; + +#if defined(USE_NEW_DYNAREC) || (defined(DEV_BRANCH) && defined(USE_CYRIX_6X86)) +CPU cpus_6x863V[] = { + /*Cyrix 6x86*/ + {"Cx6x86/P90", CPU_Cx6x86, 80000000, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 8, 8, 6, 6, 10}, + {"Cx6x86/PR120+", CPU_Cx6x86, 100000000, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 12}, + {"Cx6x86/PR133+", CPU_Cx6x86, 110000000, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 14}, + {"Cx6x86/PR150+", CPU_Cx6x86, 120000000, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 14}, + {"Cx6x86/PR166+", CPU_Cx6x86, 133333333, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16}, + {"Cx6x86/PR200+", CPU_Cx6x86, 150000000, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 18}, + {"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} +}; + +CPU cpus_6x86[] = { + /*Cyrix 6x86*/ + {"Cx6x86/P90", CPU_Cx6x86, 80000000, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 8, 8, 6, 6, 10}, + {"Cx6x86/PR120+", CPU_Cx6x86, 100000000, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 12}, + {"Cx6x86/PR133+", CPU_Cx6x86, 110000000, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 14}, + {"Cx6x86/PR150+", CPU_Cx6x86, 120000000, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 14}, + {"Cx6x86/PR166+", CPU_Cx6x86, 133333333, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16}, + {"Cx6x86/PR200+", CPU_Cx6x86, 150000000, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 18}, + + /*Cyrix 6x86L*/ + {"Cx6x86L/PR133+", CPU_Cx6x86L, 110000000, 2, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 14}, + {"Cx6x86L/PR150+", CPU_Cx6x86L, 120000000, 2, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 14}, + {"Cx6x86L/PR166+", CPU_Cx6x86L, 133333333, 2, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16}, + {"Cx6x86L/PR200+", CPU_Cx6x86L, 150000000, 2, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 18}, + + /*Cyrix 6x86MX/MII*/ + {"Cx6x86MX/PR166", CPU_Cx6x86MX, 133333333, 2, 0x600, 0x600, 0x0451, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16}, + {"Cx6x86MX/PR200", CPU_Cx6x86MX, 166666666, 5/2, 0x600, 0x600, 0x0452, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20}, + {"Cx6x86MX/PR233", CPU_Cx6x86MX, 187500000, 5/2, 0x600, 0x600, 0x0452, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 45/2}, + {"Cx6x86MX/PR266", CPU_Cx6x86MX, 208333333, 5/2, 0x600, 0x600, 0x0452, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 17,17, 7, 7, 25}, + {"MII/PR300", CPU_Cx6x86MX, 233333333, 7/2, 0x601, 0x601, 0x0852, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,11,11, 28}, + {"MII/PR333", CPU_Cx6x86MX, 250000000, 3, 0x601, 0x601, 0x0853, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 23,23, 9, 9, 30}, + {"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} + }; +#endif + +#ifdef USE_NEW_DYNAREC + CPU cpus_6x86SS7[] = { + /*Cyrix 6x86*/ + {"Cx6x86/P90", CPU_Cx6x86, 80000000, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 8, 8, 6, 6, 10}, + {"Cx6x86/PR120+", CPU_Cx6x86, 100000000, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 12}, + {"Cx6x86/PR133+", CPU_Cx6x86, 110000000, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 14}, + {"Cx6x86/PR150+", CPU_Cx6x86, 120000000, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 14}, + {"Cx6x86/PR166+", CPU_Cx6x86, 133333333, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16}, + {"Cx6x86/PR200+", CPU_Cx6x86, 150000000, 2, 0x520, 0x520, 0x1731, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 18}, + + /*Cyrix 6x86L*/ + {"Cx6x86L/PR133+", CPU_Cx6x86L, 110000000, 2, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 14}, + {"Cx6x86L/PR150+", CPU_Cx6x86L, 120000000, 2, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 14}, + {"Cx6x86L/PR166+", CPU_Cx6x86L, 133333333, 2, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16}, + {"Cx6x86L/PR200+", CPU_Cx6x86L, 150000000, 2, 0x540, 0x540, 0x2231, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 18}, + + /*Cyrix 6x86MX/MII*/ + {"Cx6x86MX/PR166", CPU_Cx6x86MX, 133333333, 2, 0x600, 0x600, 0x0451, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16}, + {"Cx6x86MX/PR200", CPU_Cx6x86MX, 166666666, 5/2, 0x600, 0x600, 0x0452, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20}, + {"Cx6x86MX/PR233", CPU_Cx6x86MX, 187500000, 5/2, 0x600, 0x600, 0x0452, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 45/2}, + {"Cx6x86MX/PR266", CPU_Cx6x86MX, 208333333, 5/2, 0x600, 0x600, 0x0452, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 17,17, 7, 7, 25}, + {"MII/PR300", CPU_Cx6x86MX, 233333333, 7/2, 0x601, 0x601, 0x0852, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,11,11, 28}, + {"MII/PR333", CPU_Cx6x86MX, 250000000, 3, 0x601, 0x601, 0x0853, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 23,23, 9, 9, 30}, + {"MII/PR366", CPU_Cx6x86MX, 250000000, 5/2, 0x601, 0x601, 0x0853, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 23,23, 7, 7, 30}, + {"MII/PR400", CPU_Cx6x86MX, 285000000, 3, 0x601, 0x601, 0x0853, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27, 9, 9, 34}, + {"MII/PR433", CPU_Cx6x86MX, 300000000, 3, 0x601, 0x601, 0x0853, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27, 9, 9, 36}, + {"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} + }; +#endif + +CPU cpus_WinChip[] = { + /*IDT WinChip*/ + {"WinChip 75", CPU_WINCHIP, 75000000, 3/2, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 8, 8, 4, 4, 9}, + {"WinChip 90", CPU_WINCHIP, 90000000, 3/2, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 9, 9, 4, 4, 21/2}, + {"WinChip 100", CPU_WINCHIP, 100000000, 3/2, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 9, 9, 4, 4, 12}, + {"WinChip 120", CPU_WINCHIP, 120000000, 2, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 12, 12, 6, 6, 14}, + {"WinChip 133", CPU_WINCHIP, 133333333, 2, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 12, 12, 6, 6, 16}, + {"WinChip 150", CPU_WINCHIP, 150000000, 5/2, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 15, 15, 7, 7, 35/2}, + {"WinChip 166", CPU_WINCHIP, 166666666, 5/2, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 15, 15, 7, 7, 40}, + {"WinChip 180", CPU_WINCHIP, 180000000, 3, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 21}, + {"WinChip 200", CPU_WINCHIP, 200000000, 3, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 24}, + {"WinChip 225", CPU_WINCHIP, 225000000, 3, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 27}, + {"WinChip 240", CPU_WINCHIP, 240000000, 4, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 24, 24, 12, 12, 28}, +#ifdef USE_NEW_DYNAREC + {"WinChip 2/200", CPU_WINCHIP2, 200000000, 3, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 24}, + {"WinChip 2/225", CPU_WINCHIP2, 225000000, 3, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 27}, + {"WinChip 2/240", CPU_WINCHIP2, 240000000, 4, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 24, 24, 12, 12, 30}, + {"WinChip 2/250", CPU_WINCHIP2, 250000000, 3, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 24, 24, 12, 12, 30}, + {"WinChip 2A/200", CPU_WINCHIP2, 200000000, 3, 0x587, 0x587, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 24}, + {"WinChip 2A/233", CPU_WINCHIP2, 233333333, 7/2, 0x587, 0x587, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, (7*8)/2}, +#endif + {"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} +}; + +#ifdef USE_NEW_DYNAREC +CPU cpus_WinChip_SS7[] = { + /*IDT WinChip*/ + {"WinChip 75", CPU_WINCHIP, 75000000, 3/2, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 8, 8, 4, 4, 9}, + {"WinChip 90", CPU_WINCHIP, 90000000, 3/2, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 9, 9, 4, 4, 21/2}, + {"WinChip 100", CPU_WINCHIP, 100000000, 3/2, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 9, 9, 4, 4, 12}, + {"WinChip 120", CPU_WINCHIP, 120000000, 2, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 12, 12, 6, 6, 14}, + {"WinChip 133", CPU_WINCHIP, 133333333, 2, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 12, 12, 6, 6, 16}, + {"WinChip 150", CPU_WINCHIP, 150000000, 5/2, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 15, 15, 7, 7, 35/2}, + {"WinChip 166", CPU_WINCHIP, 166666666, 5/2, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 15, 15, 7, 7, 40}, + {"WinChip 180", CPU_WINCHIP, 180000000, 3, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 21}, + {"WinChip 200", CPU_WINCHIP, 200000000, 3, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 24}, + {"WinChip 225", CPU_WINCHIP, 225000000, 3, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 27}, + {"WinChip 240", CPU_WINCHIP, 240000000, 4, 0x540, 0x540, 0, CPU_SUPPORTS_DYNAREC, 24, 24, 12, 12, 28}, + {"WinChip 2/200", CPU_WINCHIP2, 200000000, 3, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 3*8}, + {"WinChip 2/225", CPU_WINCHIP2, 225000000, 3, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 3*9}, + {"WinChip 2/240", CPU_WINCHIP2, 240000000, 4, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 24, 24, 12, 12, 30}, + {"WinChip 2/250", CPU_WINCHIP2, 250000000, 3, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC, 24, 24, 12, 12, 30}, + {"WinChip 2A/200", CPU_WINCHIP2, 200000000, 3, 0x587, 0x587, 0, CPU_SUPPORTS_DYNAREC, 18, 18, 9, 9, 3*8}, + {"WinChip 2A/233", CPU_WINCHIP2, 233333333, 7/2, 0x587, 0x587, 0, CPU_SUPPORTS_DYNAREC, 21, 21, 9, 9, (7*8)/2}, + {"WinChip 2A/266", CPU_WINCHIP2, 233333333, 7/3, 0x587, 0x587, 0, CPU_SUPPORTS_DYNAREC, 21, 21, 7, 7, 28}, + {"WinChip 2A/300", CPU_WINCHIP2, 250000000, 5/2, 0x587, 0x587, 0, CPU_SUPPORTS_DYNAREC, 24, 24, 8, 8, 30}, + {"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} +}; +#endif + +CPU cpus_Pentium5V[] = { + /*Intel Pentium (5V, socket 4)*/ + {"Pentium 60", CPU_PENTIUM, 60000000, 1, 0x517, 0x517, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6,3,3, 7}, + {"Pentium 66", CPU_PENTIUM, 66666666, 1, 0x517, 0x517, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6,3,3, 8}, + {"Pentium OverDrive 120", CPU_PENTIUM, 120000000, 2, 0x51A, 0x51A, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6, 14}, + {"Pentium OverDrive 133", CPU_PENTIUM, 133333333, 2, 0x51A, 0x51A, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6, 16}, + {"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} +}; + +CPU cpus_Pentium5V50[] = { + /*Intel Pentium (5V, socket 4, including 50 MHz FSB)*/ + {"Pentium 50 (Q0399)", CPU_PENTIUM, 50000000, 1, 0x513, 0x513, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 4, 4,3,3, 6}, + {"Pentium 60", CPU_PENTIUM, 60000000, 1, 0x517, 0x517, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6,3,3, 7}, + {"Pentium 66", CPU_PENTIUM, 66666666, 1, 0x517, 0x517, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6,3,3, 8}, + {"Pentium OverDrive 100", CPU_PENTIUM, 100000000, 2, 0x51A, 0x51A, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 8, 8,6,6, 12}, + {"Pentium OverDrive 120", CPU_PENTIUM, 120000000, 2, 0x51A, 0x51A, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6, 14}, + {"Pentium OverDrive 133", CPU_PENTIUM, 133333333, 2, 0x51A, 0x51A, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6, 16}, + {"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} +}; + +CPU cpus_PentiumS5[] = { + /*Intel Pentium (Socket 5)*/ + {"Pentium 75", CPU_PENTIUM, 75000000, 3/2, 0x522, 0x522, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7,4,4, 9}, + {"Pentium OverDrive MMX 75", CPU_PENTIUMMMX, 75000000, 3/2, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7,4,4, 9}, + {"Pentium 90", CPU_PENTIUM, 90000000, 3/2, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9,4,4, 21/2}, + {"Pentium 100/50", CPU_PENTIUM, 100000000, 2, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10,6,6, 12}, + {"Pentium 100/66", CPU_PENTIUM, 100000000, 3/2, 0x526, 0x526, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9,4,4, 12}, + {"Pentium 120", CPU_PENTIUM, 120000000, 2, 0x526, 0x526, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6, 14}, + + /*Intel Pentium OverDrive*/ + {"Pentium OverDrive 125", CPU_PENTIUM, 125000000, 3, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,7,7, 16}, + {"Pentium OverDrive 150", CPU_PENTIUM, 150000000, 5/2, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7, 35/2}, + {"Pentium OverDrive 166", CPU_PENTIUM, 166666666, 5/2, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7, 40}, + {"Pentium OverDrive MMX 125", CPU_PENTIUMMMX, 125000000, 5/2, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,7,7, 15}, + {"Pentium OverDrive MMX 150/60", CPU_PENTIUMMMX, 150000000, 5/2, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7, 35/2}, + {"Pentium OverDrive MMX 166", CPU_PENTIUMMMX, 166000000, 5/2, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7, 20}, + {"Pentium OverDrive MMX 180", CPU_PENTIUMMMX, 180000000, 3, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9, 21}, + {"Pentium OverDrive MMX 200", CPU_PENTIUMMMX, 200000000, 3, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9, 24}, + {"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} +}; + +CPU cpus_Pentium3V[] = { + /*Intel Pentium*/ + {"Pentium 75", CPU_PENTIUM, 75000000, 3/2, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7, 4, 4, 9}, + {"Pentium OverDrive MMX 75", CPU_PENTIUMMMX, 75000000, 3/2, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7, 4, 4, 9}, + {"Pentium 90", CPU_PENTIUM, 90000000, 3/2, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 4, 4, 21/2}, + {"Pentium 100/50", CPU_PENTIUM, 100000000, 2, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 12}, + {"Pentium 100/66", CPU_PENTIUM, 100000000, 3/2, 0x526, 0x526, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 4, 4, 12}, + {"Pentium 120", CPU_PENTIUM, 120000000, 2, 0x526, 0x526, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 14}, + {"Pentium 133", CPU_PENTIUM, 133333333, 2, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16}, + {"Pentium 150", CPU_PENTIUM, 150000000, 5/2, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 35/2}, + {"Pentium 166", CPU_PENTIUM, 166666666, 5/2, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20}, + {"Pentium 200", CPU_PENTIUM, 200000000, 3, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24}, + + /*Intel Pentium OverDrive*/ + {"Pentium OverDrive 125", CPU_PENTIUM, 125000000, 5/2, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 7, 7, 15}, + {"Pentium OverDrive 150", CPU_PENTIUM, 150000000, 5/2, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 35/2}, + {"Pentium OverDrive 166", CPU_PENTIUM, 166666666, 5/2, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20}, + {"Pentium OverDrive MMX 125", CPU_PENTIUMMMX, 125000000, 5/2, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 7, 7, 15}, + {"Pentium OverDrive MMX 150/60", CPU_PENTIUMMMX, 150000000, 5/2, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 35/2}, + {"Pentium OverDrive MMX 166", CPU_PENTIUMMMX, 166000000, 5/2, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20}, + {"Pentium OverDrive MMX 180", CPU_PENTIUMMMX, 180000000, 3, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 21}, + {"Pentium OverDrive MMX 200", CPU_PENTIUMMMX, 200000000, 3, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24}, + {"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} +}; + +CPU cpus_Pentium[] = { + /*Intel Pentium*/ + {"Pentium 75", CPU_PENTIUM, 75000000, 3/2, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7, 4, 4, 9}, + {"Pentium OverDrive MMX 75", CPU_PENTIUMMMX, 75000000, 3/2, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7, 4, 4, 9}, + {"Pentium 90", CPU_PENTIUM, 90000000, 3/2, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 4, 4, 21/2}, + {"Pentium 100/50", CPU_PENTIUM, 100000000, 2, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 12}, + {"Pentium 100/66", CPU_PENTIUM, 100000000, 3/2, 0x526, 0x526, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 4, 4, 12}, + {"Pentium 120", CPU_PENTIUM, 120000000, 2, 0x526, 0x526, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 14}, + {"Pentium 133", CPU_PENTIUM, 133333333, 2, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16}, + {"Pentium 150", CPU_PENTIUM, 150000000, 5/2, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 35/2}, + {"Pentium 166", CPU_PENTIUM, 166666666, 5/2, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20}, + {"Pentium 200", CPU_PENTIUM, 200000000, 3, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24}, + + /*Intel Pentium MMX*/ + {"Pentium MMX 166", CPU_PENTIUMMMX, 166666666, 5/2, 0x543, 0x543, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20}, + {"Pentium MMX 200", CPU_PENTIUMMMX, 200000000, 3, 0x543, 0x543, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24}, + {"Pentium MMX 233", CPU_PENTIUMMMX, 233333333, 7/2, 0x543, 0x543, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,10,10, 28}, + + /*Mobile Pentium*/ + {"Mobile Pentium MMX 120", CPU_PENTIUMMMX, 120000000, 2, 0x543, 0x543, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 14}, + {"Mobile Pentium MMX 133", CPU_PENTIUMMMX, 133333333, 2, 0x543, 0x543, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16}, + {"Mobile Pentium MMX 150", CPU_PENTIUMMMX, 150000000, 5/2, 0x544, 0x544, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 35/2}, + {"Mobile Pentium MMX 166", CPU_PENTIUMMMX, 166666666, 5/2, 0x544, 0x544, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20}, + {"Mobile Pentium MMX 200", CPU_PENTIUMMMX, 200000000, 3, 0x581, 0x581, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24}, + {"Mobile Pentium MMX 233", CPU_PENTIUMMMX, 233333333, 7/2, 0x581, 0x581, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,10,10, 28}, + {"Mobile Pentium MMX 266", CPU_PENTIUMMMX, 266666666, 4, 0x582, 0x582, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24,12,12, 32}, + {"Mobile Pentium MMX 300", CPU_PENTIUMMMX, 300000000, 9/2, 0x582, 0x582, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 36}, + + /*Intel Pentium OverDrive*/ + {"Pentium OverDrive 125", CPU_PENTIUM, 125000000, 5/2, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 7, 7, 15}, + {"Pentium OverDrive 150", CPU_PENTIUM, 150000000, 5/2, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 35/2}, + {"Pentium OverDrive 166", CPU_PENTIUM, 166666666, 5/2, 0x52c, 0x52c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20}, + {"Pentium OverDrive MMX 125", CPU_PENTIUMMMX, 125000000, 5/2, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 7, 7, 15}, + {"Pentium OverDrive MMX 150/60", CPU_PENTIUMMMX, 150000000, 5/2, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 35/2}, + {"Pentium OverDrive MMX 166", CPU_PENTIUMMMX, 166000000, 5/2, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20}, + {"Pentium OverDrive MMX 180", CPU_PENTIUMMMX, 180000000, 3, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 21}, + {"Pentium OverDrive MMX 200", CPU_PENTIUMMMX, 200000000, 3, 0x1542, 0x1542, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24}, + {"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} +}; + +#if defined(USE_NEW_DYNAREC) || (defined(DEV_BRANCH) && defined(USE_AMD_K)) +CPU cpus_K5[] = { + /*AMD K5 (Socket 5)*/ + {"K5 (5k86) 75 (P75)", CPU_K5, 75000000, 3/2, 0x500, 0x500, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7,4,4, 9}, + {"K5 (SSA/5) 75 (PR75)", CPU_K5, 75000000, 3/2, 0x501, 0x501, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7,4,4, 9}, + {"K5 (5k86) 90 (P90)", CPU_K5, 90000000, 3/2, 0x500, 0x500, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9,4,4, 21/2}, + {"K5 (SSA/5) 90 (PR90)", CPU_K5, 90000000, 3/2, 0x501, 0x501, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9,4,4, 21/2}, + {"K5 (5k86) 100 (P100)", CPU_K5, 100000000, 3/2, 0x500, 0x500, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9,4,4, 12}, + {"K5 (SSA/5) 100 (PR100)", CPU_K5, 100000000, 3/2, 0x501, 0x501, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9,4,4, 12}, + {"K5 (5k86) 90 (PR120)", CPU_5K86, 120000000, 2, 0x511, 0x511, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6, 14}, + {"K5 (5k86) 100 (PR133)", CPU_5K86, 133333333, 2, 0x514, 0x514, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12,6,6, 16}, + {"K5 (5k86) 105 (PR150)", CPU_5K86, 150000000, 5/2, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7, 35/2}, + {"K5 (5k86) 116.5 (PR166)", CPU_5K86, 166666666, 5/2, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,7,7, 20}, + {"K5 (5k86) 133 (PR200)", CPU_5K86, 200000000, 3, 0x534, 0x534, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18,9,9, 24}, + {"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} +}; + +CPU cpus_K56[] = { + /*AMD K5 (Socket 7)*/ + {"K5 (5k86) 75 (P75)", CPU_K5, 75000000, 3/2, 0x500, 0x500, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7, 4, 4, 9}, + {"K5 (SSA/5) 75 (PR75)", CPU_K5, 75000000, 3/2, 0x501, 0x501, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7, 4, 4, 9}, + {"K5 (5k86) 90 (P90)", CPU_K5, 90000000, 3/2, 0x500, 0x500, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 4, 4, 21/2}, + {"K5 (SSA/5) 90 (PR90)", CPU_K5, 90000000, 3/2, 0x501, 0x501, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 4, 4, 21/2}, + {"K5 (5k86) 100 (P100)", CPU_K5, 100000000, 3/2, 0x500, 0x500, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 4, 4, 12}, + {"K5 (SSA/5) 100 (PR100)", CPU_K5, 100000000, 3/2, 0x501, 0x501, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 4, 4, 12}, + {"K5 (5k86) 90 (PR120)", CPU_5K86, 120000000, 2, 0x511, 0x511, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 14}, + {"K5 (5k86) 100 (PR133)", CPU_5K86, 133333333, 2, 0x514, 0x514, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16}, + {"K5 (5k86) 105 (PR150)", CPU_5K86, 150000000, 5/2, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 35/2}, + {"K5 (5k86) 116.5 (PR166)", CPU_5K86, 166666666, 5/2, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20}, + {"K5 (5k86) 133 (PR200)", CPU_5K86, 200000000, 3, 0x534, 0x534, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24}, + + /*AMD K6 (Socket 7*/ + {"K6 (Model 6) 166", CPU_K6, 166666666, 5/2, 0x561, 0x561, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20}, + {"K6 (Model 6) 200", CPU_K6, 200000000, 3, 0x561, 0x561, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24}, + {"K6 (Model 6) 233", CPU_K6, 233333333, 7/2, 0x561, 0x561, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21, 10, 10, 28}, + {"K6 (Model 7) 200", CPU_K6, 200000000, 3, 0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24}, + {"K6 (Model 7) 233", CPU_K6, 233333333, 7/2, 0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21, 10, 10, 28}, + {"K6 (Model 7) 266", CPU_K6, 266666666, 4, 0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24, 12, 12, 32}, + {"K6 (Model 7) 300", CPU_K6, 300000000, 9/2, 0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27, 13, 13, 36}, +#ifdef USE_NEW_DYNAREC + {"K6-2/233", CPU_K6_2, 233333333, 7/2, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21, 10, 10, 28}, + {"K6-2/266", CPU_K6_2, 266666666, 4, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24, 12, 12, 32}, + {"K6-2/300 AFR-66", CPU_K6_2, 300000000, 9/2, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27, 13, 13, 36}, + {"K6-2/366", CPU_K6_2, 366666666, 11/2, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 33,33, 17, 17, 44}, +#endif + {"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} +}; +#endif + +#ifdef USE_NEW_DYNAREC +CPU cpus_K56_SS7[] = { + /*AMD K5 (Socket 7)*/ + {"K5 (5k86) 75 (P75)", CPU_K5, 75000000, 3/2, 0x500, 0x500, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7, 4, 4, 9}, + {"K5 (SSA/5) 75 (PR75)", CPU_K5, 75000000, 3/2, 0x501, 0x501, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7, 4, 4, 9}, + {"K5 (5k86) 90 (P90)", CPU_K5, 90000000, 3/2, 0x500, 0x500, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 4, 4, 21/2}, + {"K5 (SSA/5) 90 (PR90)", CPU_K5, 90000000, 3/2, 0x501, 0x501, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 4, 4, 21/2}, + {"K5 (5k86) 100 (P100)", CPU_K5, 100000000, 3/2, 0x500, 0x500, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 4, 4, 12}, + {"K5 (SSA/5) 100 (PR100)", CPU_K5, 100000000, 3/2, 0x501, 0x501, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 9, 9, 4, 4, 12}, + {"K5 (5k86) 90 (PR120)", CPU_5K86, 120000000, 2, 0x511, 0x511, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 14}, + {"K5 (5k86) 100 (PR133)", CPU_5K86, 133333333, 2, 0x514, 0x514, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 12,12, 6, 6, 16}, + {"K5 (5k86) 105 (PR150)", CPU_5K86, 150000000, 5/2, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 35/2}, + {"K5 (5k86) 116.5 (PR166)", CPU_5K86, 166666666, 5/2, 0x524, 0x524, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20}, + {"K5 (5k86) 133 (PR200)", CPU_5K86, 200000000, 3, 0x534, 0x534, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24}, + + /*AMD K6 (Socket 7)*/ + {"K6 (Model 6) 166", CPU_K6, 166666666, 5/2, 0x561, 0x561, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20}, + {"K6 (Model 6) 200", CPU_K6, 200000000, 3, 0x561, 0x561, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24}, + {"K6 (Model 6) 233", CPU_K6, 233333333, 7/2, 0x561, 0x561, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,10,10, 28}, + {"K6 (Model 7) 200", CPU_K6, 200000000, 3, 0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24}, + {"K6 (Model 7) 233", CPU_K6, 233333333, 7/2, 0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,10,10, 28}, + {"K6 (Model 7) 266", CPU_K6, 266666666, 4, 0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24,12,12, 32}, + {"K6 (Model 7) 300", CPU_K6, 300000000, 9/2, 0x570, 0x570, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 36}, + + /*AMD K6-2 (Socket 7/Super Socket 7)*/ + {"K6-2/233", CPU_K6_2, 233333333, 7/2, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21, 21, 10, 10, 28}, + {"K6-2/266", CPU_K6_2, 266666666, 4, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24, 24, 12, 12, 32}, + {"K6-2/300", CPU_K6_2, 300000000, 3, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27, 27, 9, 9, 36}, + {"K6-2/333", CPU_K6_2, 332500000, 7/2, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 30, 30, 11, 11, 40}, + {"K6-2/350", CPU_K6_2C, 350000000, 7/2, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 32, 32, 11, 11, 42}, + {"K6-2/366", CPU_K6_2C, 366666666, 11/2, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 33, 33, 17, 17, 44}, + {"K6-2/380", CPU_K6_2C, 380000000, 4, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 34, 34, 12, 12, 46}, + {"K6-2/400", CPU_K6_2C, 400000000, 4, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 36, 36, 12, 12, 48}, + {"K6-2/450", CPU_K6_2C, 450000000, 9/2, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 41, 41, 14, 14, 54}, + {"K6-2/475", CPU_K6_2C, 475000000, 5, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 43, 43, 15, 15, 57}, + {"K6-2/500", CPU_K6_2C, 500000000, 5, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 45, 45, 15, 15, 60}, + {"K6-2/533", CPU_K6_2C, 533333333, 11/2, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 48, 48, 17, 17, 64}, + {"K6-2/550", CPU_K6_2C, 550000000, 11/2, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 50, 50, 17, 17, 66}, + + /*AMD K6-2+/K6-3/K6-3+ (Super Socket 7)*/ + {"K6-2+/450", CPU_K6_2P, 450000000, 9/2, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 41, 41, 14, 14, 54}, + {"K6-2+/475", CPU_K6_2P, 475000000, 5, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 43, 43, 15, 15, 57}, + {"K6-2+/500", CPU_K6_2P, 500000000, 5, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 45, 45, 15, 15, 60}, + {"K6-2+/533", CPU_K6_2P, 533333333, 11/2, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 48, 48, 17, 17, 64}, + {"K6-2+/550", CPU_K6_2P, 550000000, 11/2, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 50, 50, 17, 17, 66}, + {"K6-III/400", CPU_K6_3, 400000000, 4, 0x591, 0x591, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 36, 36, 12, 12, 48}, + {"K6-III/450", CPU_K6_3, 450000000, 9/2, 0x591, 0x591, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 41, 41, 14, 14, 54}, + {"K6-III+/400", CPU_K6_3P, 400000000, 4, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 36, 36, 12, 12, 48}, + {"K6-III+/450", CPU_K6_3P, 450000000, 9/2, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 41, 41, 14, 14, 54}, + {"K6-III+/475", CPU_K6_3P, 475000000, 5, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 43, 43, 15, 15, 57}, + {"K6-III+/500", CPU_K6_3P, 500000000, 5, 0x5d0, 0x5d0, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 45, 45, 15, 15, 60}, + {"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} +}; +#endif + +#ifdef DEV_BRANCH +#ifdef USE_I686 +CPU cpus_PentiumPro[] = { + /*Intel Pentium Pro*/ + {"Pentium Pro 50", CPU_PENTIUMPRO, 50000000, 1, 0x612, 0x612, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 4, 4, 3, 3, 6}, + {"Pentium Pro 60" , CPU_PENTIUMPRO, 60000000, 1, 0x612, 0x612, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6, 3, 3, 7}, + {"Pentium Pro 66" , CPU_PENTIUMPRO, 66666666, 1, 0x612, 0x612, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6, 3, 3, 8}, + {"Pentium Pro 75", CPU_PENTIUMPRO, 75000000, 3/2, 0x612, 0x612, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7, 4, 4, 9}, + {"Pentium Pro 150", CPU_PENTIUMPRO, 150000000, 5/2, 0x612, 0x612, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 35/2}, + {"Pentium Pro 166", CPU_PENTIUMPRO, 166666666, 5/2, 0x617, 0x617, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15, 7, 7, 20}, + {"Pentium Pro 180", CPU_PENTIUMPRO, 180000000, 3, 0x617, 0x617, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 21}, + {"Pentium Pro 200", CPU_PENTIUMPRO, 200000000, 3, 0x617, 0x617, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 18,18, 9, 9, 24}, + + /*Intel Pentium II OverDrive*/ + {"Pentium II Overdrive 50", CPU_PENTIUM2D, 50000000, 1, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 4, 4, 3, 3, 6}, + {"Pentium II Overdrive 60", CPU_PENTIUM2D, 60000000, 1, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6, 3, 3, 7}, + {"Pentium II Overdrive 66", CPU_PENTIUM2D, 66666666, 1, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6, 3, 3, 8}, + {"Pentium II Overdrive 75", CPU_PENTIUM2D, 75000000, 3/2, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7, 4, 4, 9}, + {"Pentium II Overdrive 210", CPU_PENTIUM2D, 210000000, 7/2, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 17,17, 7, 7, 25}, + {"Pentium II Overdrive 233", CPU_PENTIUM2D, 233333333, 7/2, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,10,10, 28}, + {"Pentium II Overdrive 240", CPU_PENTIUM2D, 240000000, 4, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24,12,12, 29}, + {"Pentium II Overdrive 266", CPU_PENTIUM2D, 266666666, 4, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24,12,12, 32}, + {"Pentium II Overdrive 270", CPU_PENTIUM2D, 270000000, 9/2, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 25,25,12,12, 33}, + {"Pentium II Overdrive 300/66", CPU_PENTIUM2D, 300000000, 9/2, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 25,25,12,12, 36}, + {"Pentium II Overdrive 300/60", CPU_PENTIUM2D, 300000000, 5, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 36}, + {"Pentium II Overdrive 333", CPU_PENTIUM2D, 333333333, 5, 0x1632, 0x1632, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 40}, + {"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} +}; + +CPU cpus_PentiumII[] = { + /*Intel Pentium II Klamath*/ + {"Pentium II Klamath 50", CPU_PENTIUM2, 50000000, 1, 0x634, 0x634, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 4, 4, 3, 3, 6}, + {"Pentium II Klamath 60", CPU_PENTIUM2, 60000000, 1, 0x634, 0x634, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6, 3, 3, 7}, + {"Pentium II Klamath 66", CPU_PENTIUM2, 66666666, 1, 0x634, 0x634, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6, 3, 3, 8}, + {"Pentium II Klamath 75", CPU_PENTIUM2, 75000000, 3/2, 0x634, 0x634, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7, 4, 4, 9}, + {"Pentium II Klamath 233", CPU_PENTIUM2, 233333333, 7/2, 0x634, 0x634, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 21,21,10,10, 28}, + {"Pentium II Klamath 266", CPU_PENTIUM2, 266666666, 4, 0x634, 0x634, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24,12,12, 29}, + {"Pentium II Klamath 300/66", CPU_PENTIUM2, 300000000, 9/2, 0x634, 0x634, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 25,25,12,12, 36}, + + /*Intel Pentium II Deschutes*/ + {"Pentium II Deschutes 50", CPU_PENTIUM2D, 50000000, 1, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 4, 4, 3, 3, 6}, + {"Pentium II Deschutes 60", CPU_PENTIUM2D, 60000000, 1, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6, 3, 3, 7}, + {"Pentium II Deschutes 66", CPU_PENTIUM2D, 66666666, 1, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 6, 6, 3, 3, 8}, + {"Pentium II Deschutes 75", CPU_PENTIUM2D, 75000000, 3/2, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 7, 7, 4, 4, 9}, + {"Pentium II Deschutes 266", CPU_PENTIUM2D, 266666666, 4, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24,24,12,12, 29}, + {"Pentium II Deschutes 300/66", CPU_PENTIUM2D, 300000000, 9/2, 0x651, 0x651, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 25,25,12,12, 36}, + {"Pentium II Deschutes 333", CPU_PENTIUM2D, 333333333, 5, 0x651, 0x651, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 40}, + {"Pentium II Deschutes 350", CPU_PENTIUM2D, 350000000, 7/2, 0x651, 0x651, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 32,32,11,11, 42}, + {"Pentium II Deschutes 400", CPU_PENTIUM2D, 400000000, 4, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 36,36,12,12, 48}, + {"Pentium II Deschutes 450", CPU_PENTIUM2D, 450000000, 9/2, 0x652, 0x652, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 41,41,14,14, 54}, + {"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} + +}; + +CPU cpus_Celeron[] = { // Mendocino Celerons. Exact architecture as the P2D series. Intended for + // the PGA370 boards but they were capable to fit on a PGA 370 to Slot 1 + // adaptor card so they work on Slot 1 motherboards too!. + + // The 100Mhz Mendocino is only meant to not cause any struggle + // to the recompiler. + {"Celeron Mendocino 100", CPU_PENTIUM2D, 100000000, 3/2, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10, 6, 6, 12}, + {"Celeron Mendocino 333", CPU_PENTIUM2D, 333333333, 5, 0x665, 0x665, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27,27,13,13, 40}, + {"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} +}; +#endif +#endif +CPU cpus_Cyrix3[] = { + /*VIA Cyrix III (Samuel)*/ + {"Cyrix III 66", CPU_CYRIX3S, 66666666, 1, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC, 6, 6, 3, 3, 8}, /*66 MHz version*/ + {"Cyrix III 233", CPU_CYRIX3S, 233333333, 3.5, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC, 21, 21, 9, 9, 28}, + {"Cyrix III 266", CPU_CYRIX3S, 266666666, 4, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC, 24, 24, 12, 12, 32}, + {"Cyrix III 300", CPU_CYRIX3S, 300000000, 4.5, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC, 27, 27, 13, 13, 36}, + {"Cyrix III 333", CPU_CYRIX3S, 333333333, 5, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC, 30, 30, 15, 15, 40}, + {"Cyrix III 350", CPU_CYRIX3S, 350000000, 3.5, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC, 32, 32, 11, 11, 42}, + {"Cyrix III 400", CPU_CYRIX3S, 400000000, 4, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC, 36, 36, 12, 12, 48}, + {"Cyrix III 450", CPU_CYRIX3S, 450000000, 4.5, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC, 41, 41, 14, 14, 54}, /*^ is lower P2 speeds to allow emulation below 466 mhz*/ + {"Cyrix III 500", CPU_CYRIX3S, 500000000, 5, 0x660, 0x660, 0, CPU_SUPPORTS_DYNAREC, 45, 45, 15, 15, 60}, + {"Cyrix III 550", CPU_CYRIX3S, 550000000, 5.5, 0x662, 0x662, 0, CPU_SUPPORTS_DYNAREC, 50, 50, 17, 17, 66}, + {"Cyrix III 600", CPU_CYRIX3S, 600000000, 6, 0x662, 0x662, 0, CPU_SUPPORTS_DYNAREC, 54, 54, 18, 18, 72}, + {"Cyrix III 650", CPU_CYRIX3S, 650000000, 6.5, 0x662, 0x662, 0, CPU_SUPPORTS_DYNAREC, 58, 58, 20, 20, 78}, + {"Cyrix III 700", CPU_CYRIX3S, 700000000, 7, 0x662, 0x662, 0, CPU_SUPPORTS_DYNAREC, 62, 62, 21, 21, 84}, + {"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} }; \ No newline at end of file diff --git a/src/machine/m_at_socket8.c b/src/machine/m_at_socket8.c index 1b662405c..3e0348e4f 100644 --- a/src/machine/m_at_socket8.c +++ b/src/machine/m_at_socket8.c @@ -1,300 +1,300 @@ -/* - * 86Box A hypervisor and IBM PC system emulator that specializes in - * running old operating systems and software designed for IBM - * PC systems and compatibles from 1981 through fairly recent - * system designs based on the PCI bus. - * - * This file is part of the 86Box distribution. - * - * Implementation of Socket 8 and Slot 1 machines. - * - * - * - * Authors: Miran Grca, - * - * Copyright 2016-2019 Miran Grca. - */ -#include -#include -#include -#include -#include -#include "86box.h" -#include "mem.h" -#include "86box_io.h" -#include "rom.h" -#include "pci.h" -#include "device.h" -#include "chipset.h" -#include "hdc.h" -#include "hdc_ide.h" -#include "keyboard.h" -#include "intel_flash.h" -#include "intel_sio.h" -#include "piix.h" -#include "sio.h" -#include "sst_flash.h" -#include "hwm.h" -#include "video.h" -#include "cpu.h" -#include "machine.h" - - -#if defined(DEV_BRANCH) && defined(USE_I686) - - -int -machine_at_i440fx_init(const machine_t *model) -{ - int ret; - - ret = bios_load_linear(L"roms/machines/440fx/ntmaw501.bin", - 0x000e0000, 131072, 0); - - if (bios_only || !ret) - return ret; - - machine_at_common_init(model); - - pci_init(PCI_CONFIG_TYPE_1); - pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0); - pci_register_slot(0x0E, PCI_CARD_NORMAL, 1, 2, 3, 4); - pci_register_slot(0x0D, PCI_CARD_NORMAL, 2, 3, 4, 1); - pci_register_slot(0x0C, PCI_CARD_NORMAL, 3, 4, 1, 2); - pci_register_slot(0x0B, PCI_CARD_NORMAL, 4, 1, 2, 3); - pci_register_slot(0x0A, PCI_CARD_NORMAL, 1, 2, 3, 4); - pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0); - device_add(&i440fx_device); - device_add(&piix3_device); - device_add(&keyboard_ps2_pci_device); - device_add(&fdc37c665_device); - device_add(&intel_flash_bxt_device); - - return ret; -} - - -int -machine_at_s1668_init(const machine_t *model) -{ - int ret; - - ret = bios_load_linear(L"roms/machines/tpatx/s1668p.rom", - 0x000e0000, 131072, 0); - - if (bios_only || !ret) - return ret; - - machine_at_common_init(model); - - pci_init(PCI_CONFIG_TYPE_1); - pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0); - pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0); - pci_register_slot(0x0E, PCI_CARD_NORMAL, 1, 2, 3, 4); - pci_register_slot(0x0D, PCI_CARD_NORMAL, 2, 3, 4, 1); - pci_register_slot(0x0C, PCI_CARD_NORMAL, 3, 4, 1, 2); - pci_register_slot(0x0B, PCI_CARD_NORMAL, 4, 1, 2, 3); - pci_register_slot(0x0A, PCI_CARD_NORMAL, 1, 2, 3, 4); - device_add(&i440fx_device); - device_add(&piix3_device); - device_add(&keyboard_ps2_ami_pci_device); - device_add(&fdc37c665_device); - device_add(&intel_flash_bxt_device); - - return ret; -} - -#endif -int -machine_at_6abx3_init(const machine_t *model) -{ - int ret; - - ret = bios_load_linear(L"roms/machines/6abx3/6abx3h1.bin", - 0x000c0000, 262144, 0); - - if (bios_only || !ret) - return ret; - - machine_at_common_init_ex(model, 2); - - pci_init(PCI_CONFIG_TYPE_1); - pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0); - pci_register_slot(0x08, PCI_CARD_NORMAL, 1, 2, 3, 4); - pci_register_slot(0x09, PCI_CARD_NORMAL, 2, 3, 4, 1); - pci_register_slot(0x0B, PCI_CARD_NORMAL, 4, 1, 2, 3); - pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2); - pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4); - pci_register_slot(0x01, PCI_CARD_NORMAL, 1, 2, 3, 4); - device_add(&i440bx_device); - device_add(&piix4_device); - device_add(&keyboard_ps2_pci_device); - device_add(&w83877tf_device); - // device_add(&w83977tf_device); - // device_add(&intel_flash_bxt_device); - // device_add(&sst_flash_29ee020_device); - device_add(&intel_flash_bxt_device); - - return ret; -} -#if defined(DEV_BRANCH) && defined(USE_I686) -int -machine_at_p2bls_init(const machine_t *model) -{ - int ret; - - ret = bios_load_linear(L"roms/machines/p2bls/1014ls.003", - 0x000c0000, 262144, 0); - - if (bios_only || !ret) - return ret; - - machine_at_common_init_ex(model, 2); - - pci_init(PCI_CONFIG_TYPE_1); - pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0); - pci_register_slot(0x06, PCI_CARD_NORMAL, 4, 1, 2, 3); - pci_register_slot(0x07, PCI_CARD_NORMAL, 3, 4, 1, 2); - pci_register_slot(0x0B, PCI_CARD_NORMAL, 2, 3, 4, 1); - pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 2, 3, 4); - pci_register_slot(0x09, PCI_CARD_NORMAL, 4, 1, 2, 3); - pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2); - pci_register_slot(0x04, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4); - pci_register_slot(0x01, PCI_CARD_NORMAL, 1, 2, 3, 4); - device_add(&i440bx_device); - device_add(&piix4_device); - device_add(&keyboard_ps2_pci_device); - device_add(&w83977ef_device); - device_add(&sst_flash_39sf020_device); - - hwm_values_t machine_hwm = { - { /* fan speeds */ - 3000, /* Chassis */ - 3000, /* CPU */ - 3000, /* Power */ - 0 - }, { /* temperatures */ - 30, /* MB */ - 0, /* unused */ - 27, /* CPU */ - 0 - }, { /* voltages */ - 2050, /* VCORE (2.05V by default) */ - 0, /* unused */ - 3300, /* +3.3V */ - RESISTOR_DIVIDER(5000, 11, 16), /* +5V (divider values bruteforced) */ - RESISTOR_DIVIDER(12000, 28, 10), /* +12V (28K/10K divider suggested in the W83781D datasheet) */ - RESISTOR_DIVIDER(12000, 853, 347), /* -12V (divider values bruteforced) */ - RESISTOR_DIVIDER(5000, 1, 2), /* -5V (divider values bruteforced) */ - 0 - } - }; - if (model->cpu[cpu_manufacturer].cpus[cpu_effective].cpu_type == CPU_PENTIUM2) - machine_hwm.voltages[0] = 2800; /* set higher VCORE (2.8V) for Klamath */ - hwm_set_values(machine_hwm); - device_add(&as99127f_device); - - return ret; -} - -int -machine_at_borapro_init(const machine_t *model) -{ - //AMI 440ZX Board. Packard Bell OEM of the MSI-6168 - //MIGHT REQUIRE MORE EXCESSIVE TESTING! - //Reports emmersive amounts of RAM like few Intel OEM boards - //we have. - - int ret; - - ret = bios_load_linear(L"roms/machines/borapro/MS6168V2.50", - 0x000c0000, 262144, 0); - - if (bios_only || !ret) - return ret; - - machine_at_common_init_ex(model, 2); - - pci_init(PCI_CONFIG_TYPE_1); - pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0); - pci_register_slot(0x0E, PCI_CARD_NORMAL, 1, 2, 3, 4); - pci_register_slot(0x10, PCI_CARD_NORMAL, 2, 3, 4, 1); - pci_register_slot(0x12, PCI_CARD_NORMAL, 3, 4, 1, 2); - pci_register_slot(0x14, PCI_CARD_NORMAL, 4, 1, 2, 3); - pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4); - pci_register_slot(0x01, PCI_CARD_NORMAL, 1, 2, 3, 4); - device_add(&i440zx_device); - device_add(&piix4e_device); - device_add(&w83977ef_device); - device_add(&keyboard_ps2_ami_pci_device); - device_add(&intel_flash_bxt_device); - - return ret; -} - -int -machine_at_p6bxt_init(const machine_t *model) -{ - int ret; - - ret = bios_load_linear(L"roms/machines/p6bxt/bxt53s.BIN", - 0x000c0000, 262144, 0); - - if (bios_only || !ret) - return ret; - - machine_at_common_init_ex(model, 2); - - pci_init(PCI_CONFIG_TYPE_1); - pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0); - pci_register_slot(0x09, PCI_CARD_NORMAL, 1, 2, 3, 4); - pci_register_slot(0x0A, PCI_CARD_NORMAL, 2, 3, 4, 1); - pci_register_slot(0x0B, PCI_CARD_NORMAL, 3, 4, 1, 2); - pci_register_slot(0x0C, PCI_CARD_NORMAL, 4, 1, 2, 3); - pci_register_slot(0x0D, PCI_CARD_NORMAL, 4, 3, 2, 1); /* Slot 5: Probably the integrated sound chip. */ - pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4); - pci_register_slot(0x01, PCI_CARD_NORMAL, 1, 2, 3, 4); - device_add(&i440bx_device); - device_add(&piix4e_device); - device_add(&w83977tf_device); - device_add(&keyboard_ps2_pci_device); - device_add(&sst_flash_39sf020_device); - - return ret; -} - - -int -machine_at_63a_init(const machine_t *model) -{ - - /* 440ZX Board. 440ZX is basically an underpowered 440BX. There no - difference between to chipsets other than the name. */ - int ret; - - ret = bios_load_linear(L"roms/machines/63a/63a-q3.bin", - 0x000c0000, 262144, 0); - - if (bios_only || !ret) - return ret; - - machine_at_common_init_ex(model, 2); - - pci_init(PCI_CONFIG_TYPE_1); - pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0); - pci_register_slot(0x08, PCI_CARD_NORMAL, 1, 2, 3, 4); - pci_register_slot(0x09, PCI_CARD_NORMAL, 2, 3, 4, 1); - pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2); - pci_register_slot(0x0B, PCI_CARD_NORMAL, 4, 1, 2, 3); - pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 2, 3, 4); // Integrated Sound? - pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4); - pci_register_slot(0x01, PCI_CARD_NORMAL, 1, 2, 3, 4); - device_add(&i440zx_device); - device_add(&piix4e_device); - device_add(&w83977tf_device); - device_add(&keyboard_ps2_pci_device); - device_add(&intel_flash_bxt_device); - - return ret; -} -#endif +/* + * 86Box A hypervisor and IBM PC system emulator that specializes in + * running old operating systems and software designed for IBM + * PC systems and compatibles from 1981 through fairly recent + * system designs based on the PCI bus. + * + * This file is part of the 86Box distribution. + * + * Implementation of Socket 8 and Slot 1 machines. + * + * + * + * Authors: Miran Grca, + * + * Copyright 2016-2019 Miran Grca. + */ +#include +#include +#include +#include +#include +#include "86box.h" +#include "mem.h" +#include "86box_io.h" +#include "rom.h" +#include "pci.h" +#include "device.h" +#include "chipset.h" +#include "hdc.h" +#include "hdc_ide.h" +#include "keyboard.h" +#include "intel_flash.h" +#include "intel_sio.h" +#include "piix.h" +#include "sio.h" +#include "sst_flash.h" +#include "hwm.h" +#include "video.h" +#include "cpu.h" +#include "machine.h" + + +#if defined(DEV_BRANCH) && defined(USE_I686) + + +int +machine_at_i440fx_init(const machine_t *model) +{ + int ret; + + ret = bios_load_linear(L"roms/machines/440fx/ntmaw501.bin", + 0x000e0000, 131072, 0); + + if (bios_only || !ret) + return ret; + + machine_at_common_init(model); + + pci_init(PCI_CONFIG_TYPE_1); + pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0); + pci_register_slot(0x0E, PCI_CARD_NORMAL, 1, 2, 3, 4); + pci_register_slot(0x0D, PCI_CARD_NORMAL, 2, 3, 4, 1); + pci_register_slot(0x0C, PCI_CARD_NORMAL, 3, 4, 1, 2); + pci_register_slot(0x0B, PCI_CARD_NORMAL, 4, 1, 2, 3); + pci_register_slot(0x0A, PCI_CARD_NORMAL, 1, 2, 3, 4); + pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0); + device_add(&i440fx_device); + device_add(&piix3_device); + device_add(&keyboard_ps2_pci_device); + device_add(&fdc37c665_device); + device_add(&intel_flash_bxt_device); + + return ret; +} + + +int +machine_at_s1668_init(const machine_t *model) +{ + int ret; + + ret = bios_load_linear(L"roms/machines/tpatx/s1668p.rom", + 0x000e0000, 131072, 0); + + if (bios_only || !ret) + return ret; + + machine_at_common_init(model); + + pci_init(PCI_CONFIG_TYPE_1); + pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0); + pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0); + pci_register_slot(0x0E, PCI_CARD_NORMAL, 1, 2, 3, 4); + pci_register_slot(0x0D, PCI_CARD_NORMAL, 2, 3, 4, 1); + pci_register_slot(0x0C, PCI_CARD_NORMAL, 3, 4, 1, 2); + pci_register_slot(0x0B, PCI_CARD_NORMAL, 4, 1, 2, 3); + pci_register_slot(0x0A, PCI_CARD_NORMAL, 1, 2, 3, 4); + device_add(&i440fx_device); + device_add(&piix3_device); + device_add(&keyboard_ps2_ami_pci_device); + device_add(&fdc37c665_device); + device_add(&intel_flash_bxt_device); + + return ret; +} + +#endif +int +machine_at_6abx3_init(const machine_t *model) +{ + int ret; + + ret = bios_load_linear(L"roms/machines/6abx3/6abx3h1.bin", + 0x000c0000, 262144, 0); + + if (bios_only || !ret) + return ret; + + machine_at_common_init_ex(model, 2); + + pci_init(PCI_CONFIG_TYPE_1); + pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0); + pci_register_slot(0x08, PCI_CARD_NORMAL, 1, 2, 3, 4); + pci_register_slot(0x09, PCI_CARD_NORMAL, 2, 3, 4, 1); + pci_register_slot(0x0B, PCI_CARD_NORMAL, 4, 1, 2, 3); + pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2); + pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4); + pci_register_slot(0x01, PCI_CARD_NORMAL, 1, 2, 3, 4); + device_add(&i440bx_device); + device_add(&piix4_device); + device_add(&keyboard_ps2_pci_device); + device_add(&w83877tf_device); + // device_add(&w83977tf_device); + // device_add(&intel_flash_bxt_device); + // device_add(&sst_flash_29ee020_device); + device_add(&intel_flash_bxt_device); + + return ret; +} +#if defined(DEV_BRANCH) && defined(USE_I686) +int +machine_at_p2bls_init(const machine_t *model) +{ + int ret; + + ret = bios_load_linear(L"roms/machines/p2bls/1014ls.003", + 0x000c0000, 262144, 0); + + if (bios_only || !ret) + return ret; + + machine_at_common_init_ex(model, 2); + + pci_init(PCI_CONFIG_TYPE_1); + pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0); + pci_register_slot(0x06, PCI_CARD_NORMAL, 4, 1, 2, 3); + pci_register_slot(0x07, PCI_CARD_NORMAL, 3, 4, 1, 2); + pci_register_slot(0x0B, PCI_CARD_NORMAL, 2, 3, 4, 1); + pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 2, 3, 4); + pci_register_slot(0x09, PCI_CARD_NORMAL, 4, 1, 2, 3); + pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2); + pci_register_slot(0x04, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4); + pci_register_slot(0x01, PCI_CARD_NORMAL, 1, 2, 3, 4); + device_add(&i440bx_device); + device_add(&piix4_device); + device_add(&keyboard_ps2_pci_device); + device_add(&w83977ef_device); + device_add(&sst_flash_39sf020_device); + + hwm_values_t machine_hwm = { + { /* fan speeds */ + 3000, /* Chassis */ + 3000, /* CPU */ + 3000, /* Power */ + 0 + }, { /* temperatures */ + 30, /* MB */ + 0, /* unused */ + 27, /* CPU */ + 0 + }, { /* voltages */ + 2050, /* VCORE (2.05V by default) */ + 0, /* unused */ + 3300, /* +3.3V */ + RESISTOR_DIVIDER(5000, 11, 16), /* +5V (divider values bruteforced) */ + RESISTOR_DIVIDER(12000, 28, 10), /* +12V (28K/10K divider suggested in the W83781D datasheet) */ + RESISTOR_DIVIDER(12000, 853, 347), /* -12V (divider values bruteforced) */ + RESISTOR_DIVIDER(5000, 1, 2), /* -5V (divider values bruteforced) */ + 0 + } + }; + if (model->cpu[cpu_manufacturer].cpus[cpu_effective].cpu_type == CPU_PENTIUM2) + machine_hwm.voltages[0] = 2800; /* set higher VCORE (2.8V) for Klamath */ + hwm_set_values(machine_hwm); + device_add(&as99127f_device); + + return ret; +} + +int +machine_at_borapro_init(const machine_t *model) +{ + //AMI 440ZX Board. Packard Bell OEM of the MSI-6168 + //MIGHT REQUIRE MORE EXCESSIVE TESTING! + //Reports emmersive amounts of RAM like few Intel OEM boards + //we have. + + int ret; + + ret = bios_load_linear(L"roms/machines/borapro/MS6168V2.50", + 0x000c0000, 262144, 0); + + if (bios_only || !ret) + return ret; + + machine_at_common_init_ex(model, 2); + + pci_init(PCI_CONFIG_TYPE_1); + pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0); + pci_register_slot(0x0E, PCI_CARD_NORMAL, 1, 2, 3, 4); + pci_register_slot(0x10, PCI_CARD_NORMAL, 2, 3, 4, 1); + pci_register_slot(0x12, PCI_CARD_NORMAL, 3, 4, 1, 2); + pci_register_slot(0x14, PCI_CARD_NORMAL, 4, 1, 2, 3); + pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4); + pci_register_slot(0x01, PCI_CARD_NORMAL, 1, 2, 3, 4); + device_add(&i440zx_device); + device_add(&piix4e_device); + device_add(&w83977ef_device); + device_add(&keyboard_ps2_ami_pci_device); + device_add(&intel_flash_bxt_device); + + return ret; +} + +int +machine_at_p6bxt_init(const machine_t *model) +{ + int ret; + + ret = bios_load_linear(L"roms/machines/p6bxt/bxt53s.BIN", + 0x000c0000, 262144, 0); + + if (bios_only || !ret) + return ret; + + machine_at_common_init_ex(model, 2); + + pci_init(PCI_CONFIG_TYPE_1); + pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0); + pci_register_slot(0x09, PCI_CARD_NORMAL, 1, 2, 3, 4); + pci_register_slot(0x0A, PCI_CARD_NORMAL, 2, 3, 4, 1); + pci_register_slot(0x0B, PCI_CARD_NORMAL, 3, 4, 1, 2); + pci_register_slot(0x0C, PCI_CARD_NORMAL, 4, 1, 2, 3); + pci_register_slot(0x0D, PCI_CARD_NORMAL, 4, 3, 2, 1); /* Slot 5: Probably the integrated sound chip. */ + pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4); + pci_register_slot(0x01, PCI_CARD_NORMAL, 1, 2, 3, 4); + device_add(&i440bx_device); + device_add(&piix4e_device); + device_add(&w83977tf_device); + device_add(&keyboard_ps2_pci_device); + device_add(&sst_flash_39sf020_device); + + return ret; +} + + +int +machine_at_63a_init(const machine_t *model) +{ + + /* 440ZX Board. 440ZX is basically an underpowered 440BX. There no + difference between to chipsets other than the name. */ + int ret; + + ret = bios_load_linear(L"roms/machines/63a/63a-q3.bin", + 0x000c0000, 262144, 0); + + if (bios_only || !ret) + return ret; + + machine_at_common_init_ex(model, 2); + + pci_init(PCI_CONFIG_TYPE_1); + pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0); + pci_register_slot(0x08, PCI_CARD_NORMAL, 1, 2, 3, 4); + pci_register_slot(0x09, PCI_CARD_NORMAL, 2, 3, 4, 1); + pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2); + pci_register_slot(0x0B, PCI_CARD_NORMAL, 4, 1, 2, 3); + pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 2, 3, 4); // Integrated Sound? + pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4); + pci_register_slot(0x01, PCI_CARD_NORMAL, 1, 2, 3, 4); + device_add(&i440zx_device); + device_add(&piix4e_device); + device_add(&w83977tf_device); + device_add(&keyboard_ps2_pci_device); + device_add(&intel_flash_bxt_device); + + return ret; +} +#endif From 8f728eb11ebf4bb1776c733caa82985ccfb881f8 Mon Sep 17 00:00:00 2001 From: tiseno100 <58827426+tiseno100@users.noreply.github.com> Date: Wed, 25 Mar 2020 12:35:18 +0200 Subject: [PATCH 29/33] fixed a few stuff around machines. Eh stupid PR it may be --- src/machine/machine.h | 2 ++ src/machine/machine_table.c | 10 ++++++---- 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/src/machine/machine.h b/src/machine/machine.h index 61cac0923..b9c28a908 100644 --- a/src/machine/machine.h +++ b/src/machine/machine.h @@ -313,6 +313,8 @@ extern int machine_at_s1668_init(const machine_t *); extern int machine_at_6abx3_init(const machine_t *); #if defined(DEV_BRANCH) && defined(USE_I686) /*P2B-LS has no VIA C3 BIOS support, so further investigation may be needed*/ extern int machine_at_p2bls_init(const machine_t *); +extern int machine_at_borapro_init(const machine_t *); + extern int machine_at_p6bxt_init(const machine_t *); extern int machine_at_63a_init(const machine_t *); #endif diff --git a/src/machine/machine_table.c b/src/machine/machine_table.c index cca655def..1cecfce3c 100644 --- a/src/machine/machine_table.c +++ b/src/machine/machine_table.c @@ -233,14 +233,16 @@ const machine_t machines[] = { { "[Socket 8 FX] Tyan Titan-Pro AT", "440fx", {{"Intel", cpus_PentiumPro}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 1024, 8, 127, machine_at_i440fx_init, NULL }, { "[Socket 8 FX] Tyan Titan-Pro ATX", "tpatx", {{"Intel", cpus_PentiumPro}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 1024, 8, 127, machine_at_s1668_init, NULL }, - { "[Slot 1 BX] Lucky Star 6ABX3", "6abx3", {{"Intel", cpus_PentiumII}, {"VIA", cpus_Cyrix3},{"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 768, 8, 255, machine_at_6abx3_init, NULL }, + { "[Slot 1 BX] Lucky Star 6ABX3", "6abx3", {{"Intel", cpus_PentiumII}, {"Intel/PGA370", cpus_Celeron}, {"VIA", cpus_Cyrix3}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 768, 8, 255, machine_at_6abx3_init, NULL }, #else { "[Slot 1 BX] Lucky Star 6ABX3", "6abx3", {{"VIA", cpus_Cyrix3}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 768, 8, 255, machine_at_6abx3_init, NULL }, #endif #if defined(DEV_BRANCH) && defined(USE_I686) - { "[Slot 1 BX] ASUS P2B-LS", "p2bls", {{"Intel", cpus_PentiumII}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 1024, 8, 255, machine_at_p2bls_init, NULL }, - { "[Socket 370 BX] ECS P6BXT-A+", "p6bxt", {{"Intel", cpus_PGA370}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 1024, 8, 255, machine_at_p6bxt_init, NULL }, - { "[Socket 370 ZX] Soltek SL-63A1", "63a", {{"Intel", cpus_PGA370}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 256, 8, 255, machine_at_63a_init, NULL }, + { "[Slot 1 BX] ASUS P2B-LS", "p2bls", {{"Intel", cpus_PentiumII}, {"Intel/PGA370", cpus_Celeron}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 1024, 8, 255, machine_at_p2bls_init, NULL }, + { "[Slot 1 ZX] Packard Bell Bora Pro", "borapro", {{"Intel", cpus_PentiumII}, {"Intel/PGA370", cpus_Celeron}, {"VIA", cpus_Cyrix3}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 256, 8, 255, machine_at_borapro_init, NULL }, + + { "[Socket 370 BX] ECS P6BXT-A+", "p6bxt", {{"Intel", cpus_Celeron}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 1024, 8, 255, machine_at_p6bxt_init, NULL }, + { "[Socket 370 ZX] Soltek SL-63A1", "63a", {{"Intel", cpus_Celeron}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 256, 8, 255, machine_at_63a_init, NULL }, #endif { NULL, NULL, {{"", 0}, {"", 0}, {"", 0}, {"", 0}, {"", 0}}, 0, 0, 0, 0, 0, NULL, NULL } }; From 01f307de0c54fb7468ba74c4ddc1f76ffdd2d89a Mon Sep 17 00:00:00 2001 From: TC1995 Date: Wed, 25 Mar 2020 13:43:16 +0100 Subject: [PATCH 30/33] Changed Compaq Portable III/386 bios to a more working one. --- src/machine/m_at_compaq.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/machine/m_at_compaq.c b/src/machine/m_at_compaq.c index f29a55842..abd29ba54 100644 --- a/src/machine/m_at_compaq.c +++ b/src/machine/m_at_compaq.c @@ -860,9 +860,9 @@ machine_at_portableiii_init(const machine_t *model) { int ret; - ret = bios_load_interleaved(L"roms/machines/portableiii/109738-002.bin", - L"roms/machines/portableiii/109737-002.bin", - 0x000f0000, 65536, 0); + ret = bios_load_interleaved(L"roms/machines/portableiii/Compaq Portable III - BIOS - 106779-002 - Even.bin", + L"roms/machines/portableiii/Compaq Portable III - BIOS - 106778-002 - Odd.bin", + 0x000f8000, 32768, 0); if (bios_only || !ret) return ret; @@ -878,9 +878,9 @@ machine_at_portableiii386_init(const machine_t *model) { int ret; - ret = bios_load_interleaved(L"roms/machines/portableiii/109738-002.bin", - L"roms/machines/portableiii/109737-002.bin", - 0x000f0000, 65536, 0); + ret = bios_load_interleaved(L"roms/machines/portableiii/Compaq Portable III - BIOS - 106779-002 - Even.bin", + L"roms/machines/portableiii/Compaq Portable III - BIOS - 106778-002 - Odd.bin", + 0x000f8000, 32768, 0); if (bios_only || !ret) return ret; From 081aecef559435657a5bd7b5f3dd09c72476a10a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?David=20Hrdli=C4=8Dka?= Date: Wed, 25 Mar 2020 16:38:35 +0100 Subject: [PATCH 31/33] fix vmpath when invoked with a path to config file --- src/pc.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/pc.c b/src/pc.c index f778b7e23..018f2744d 100644 --- a/src/pc.c +++ b/src/pc.c @@ -440,9 +440,6 @@ usage: plat_dir_create(usr_path); } - /* Make sure we have a trailing backslash. */ - plat_path_slash(usr_path); - /* Grab the name of the configuration file. */ if (cfg == NULL) cfg = CONFIG_FILE; @@ -476,6 +473,9 @@ usage: wcscat(usr_path, cfg); } + /* Make sure we have a trailing backslash. */ + plat_path_slash(usr_path); + /* At this point, we can safely create the full path name. */ plat_append_filename(cfg_path, usr_path, p); From 9686311b256bbdd00dda8912848bdea284d52c2f Mon Sep 17 00:00:00 2001 From: TC1995 Date: Wed, 25 Mar 2020 19:06:15 +0100 Subject: [PATCH 32/33] Slight rom load fix for the Compaq Portable II/III/386 (but I wonder if they use the same approach as the Amstrad PC2086/3086). --- src/machine/m_at_compaq.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/machine/m_at_compaq.c b/src/machine/m_at_compaq.c index abd29ba54..6ba8e4f54 100644 --- a/src/machine/m_at_compaq.c +++ b/src/machine/m_at_compaq.c @@ -842,9 +842,9 @@ machine_at_portableii_init(const machine_t *model) { int ret; - ret = bios_load_interleaved(L"roms/machines/portableii/109740-001.rom", + ret = bios_load_interleavedr(L"roms/machines/portableii/109740-001.rom", L"roms/machines/portableii/109739-001.rom", - 0x000f8000, 32768, 0); + 0x000f8000, 65536, 0); if (bios_only || !ret) return ret; @@ -860,9 +860,9 @@ machine_at_portableiii_init(const machine_t *model) { int ret; - ret = bios_load_interleaved(L"roms/machines/portableiii/Compaq Portable III - BIOS - 106779-002 - Even.bin", + ret = bios_load_interleavedr(L"roms/machines/portableiii/Compaq Portable III - BIOS - 106779-002 - Even.bin", L"roms/machines/portableiii/Compaq Portable III - BIOS - 106778-002 - Odd.bin", - 0x000f8000, 32768, 0); + 0x000f8000, 65536, 0); if (bios_only || !ret) return ret; @@ -878,9 +878,9 @@ machine_at_portableiii386_init(const machine_t *model) { int ret; - ret = bios_load_interleaved(L"roms/machines/portableiii/Compaq Portable III - BIOS - 106779-002 - Even.bin", + ret = bios_load_interleavedr(L"roms/machines/portableiii/Compaq Portable III - BIOS - 106779-002 - Even.bin", L"roms/machines/portableiii/Compaq Portable III - BIOS - 106778-002 - Odd.bin", - 0x000f8000, 32768, 0); + 0x000f8000, 65536, 0); if (bios_only || !ret) return ret; From 51bbebbfa3edb6eed73554110c46e12873a5a23f Mon Sep 17 00:00:00 2001 From: nerd73 Date: Wed, 25 Mar 2020 18:02:25 -0600 Subject: [PATCH 33/33] Changes to the IBM 386/486 and RapidCAD CPUs - Disabled the 'is486' flag and moved them to 386 timings - Disabled cache on startup, enable-able later - RapidCAD fixes (permanently disable L1, correct EDX reset) --- src/cpu_common/808x.c | 7 +- src/cpu_common/cpu.c | 103 +++++++----------------------- src/cpu_common/cpu.h | 3 +- src/cpu_common/cpu_table.c | 34 +++++----- src/cpu_common/x86_ops_atomic.h | 84 ------------------------ src/cpu_common/x86_ops_flag.h | 4 +- src/cpu_common/x86_ops_misc.h | 10 --- src/cpu_common/x86_ops_mov_ctrl.h | 14 ++-- src/cpu_common/x86_ops_pmode.h | 4 +- 9 files changed, 53 insertions(+), 210 deletions(-) diff --git a/src/cpu_common/808x.c b/src/cpu_common/808x.c index abee70e26..28a96a73b 100644 --- a/src/cpu_common/808x.c +++ b/src/cpu_common/808x.c @@ -918,14 +918,11 @@ reset_common(int hard) stack32 = 0; msr.fcr = (1 << 8) | (1 << 9) | (1 << 12) | (1 << 16) | (1 << 19) | (1 << 21); msw = 0; - if (is486) + if (hascache) cr0 = 1 << 30; else cr0 = 0; - if (isibmcpu) - cpu_cache_int_enabled = 1; - else - cpu_cache_int_enabled = 0; + cpu_cache_int_enabled = 0; cpu_update_waitstates(); cr4 = 0; cpu_state.eflags = 0; diff --git a/src/cpu_common/cpu.c b/src/cpu_common/cpu.c index 1cd856236..3727fa857 100644 --- a/src/cpu_common/cpu.c +++ b/src/cpu_common/cpu.c @@ -159,7 +159,8 @@ int is286, is486 = 1, is486sx, is486dx, is486sx2, is486dx2, isdx4, cpu_iscyrix, - isibmcpu, + hascache, + isibm486, israpidcad, is_pentium; @@ -281,16 +282,17 @@ cpu_set(void) is8086 = (cpu_s->cpu_type > CPU_8088); is286 = (cpu_s->cpu_type >= CPU_286); is386 = (cpu_s->cpu_type >= CPU_386SX); - isibmcpu = (cpu_s->cpu_type == CPU_IBM386SLC || cpu_s->cpu_type == CPU_IBM486SLC || cpu_s->cpu_type == CPU_IBM486BL); israpidcad = (cpu_s->cpu_type == CPU_RAPIDCAD); - is486 = (cpu_s->cpu_type >= CPU_i486SX) || (cpu_s->cpu_type == CPU_486SLC || cpu_s->cpu_type == CPU_486DLC || cpu_s->cpu_type == CPU_RAPIDCAD || cpu_s->cpu_type == CPU_IBM486SLC || cpu_s->cpu_type == CPU_IBM486BL ); + isibm486 = (cpu_s->cpu_type == CPU_IBM486SLC || cpu_s->cpu_type == CPU_IBM486BL); + is486 = (cpu_s->cpu_type >= CPU_i486SX) || (cpu_s->cpu_type == CPU_486SLC || cpu_s->cpu_type == CPU_486DLC || cpu_s->cpu_type == CPU_RAPIDCAD); is486sx = (cpu_s->cpu_type >= CPU_i486SX) && (cpu_s->cpu_type < CPU_i486SX2); is486sx2 = (cpu_s->cpu_type >= CPU_i486SX2) && (cpu_s->cpu_type < CPU_i486DX); is486dx = (cpu_s->cpu_type >= CPU_i486DX) && (cpu_s->cpu_type < CPU_i486DX2); - is486dx2 = (cpu_s->cpu_type >= CPU_iDX4) && (cpu_s->cpu_type < CPU_WINCHIP); - isdx4 = (cpu_s->cpu_type >= CPU_i486DX2) && (cpu_s->cpu_type < CPU_iDX4); + is486dx2 = (cpu_s->cpu_type >= CPU_i486DX2) && (cpu_s->cpu_type < CPU_iDX4); + isdx4 = (cpu_s->cpu_type >= CPU_iDX4) && (cpu_s->cpu_type < CPU_WINCHIP); is_pentium = (cpu_s->cpu_type >= CPU_WINCHIP); hasfpu = (cpu_s->cpu_type >= CPU_i486DX) || (cpu_s->cpu_type == CPU_RAPIDCAD); + hascache = (cpu_s->cpu_type >= CPU_486SLC) || (cpu_s->cpu_type == CPU_IBM386SLC || cpu_s->cpu_type == CPU_IBM486SLC || cpu_s->cpu_type == CPU_IBM486BL); #if defined(USE_NEW_DYNAREC) || (defined(DEV_BRANCH) && defined(USE_CYRIX_6X86)) cpu_iscyrix = (cpu_s->cpu_type == CPU_486SLC || cpu_s->cpu_type == CPU_486DLC || cpu_s->cpu_type == CPU_Cx486S || cpu_s->cpu_type == CPU_Cx486DX || cpu_s->cpu_type == CPU_Cx5x86 || cpu_s->cpu_type == CPU_Cx6x86 || cpu_s->cpu_type == CPU_Cx6x86MX || cpu_s->cpu_type == CPU_Cx6x86L || cpu_s->cpu_type == CPU_CxGX1); #else @@ -518,7 +520,13 @@ cpu_set(void) timing_jmp_pm = 23; timing_jmp_pm_gate = 38; break; - + + case CPU_IBM486SLC: +#ifdef USE_DYNAREC + x86_setopcodes(ops_386, ops_486_0f, dynarec_ops_386, dynarec_ops_486_0f); +#else + x86_setopcodes(ops_386, ops_486_0f); +#endif case CPU_IBM386SLC: case CPU_386SX: timing_rr = 2; /*register dest - register src*/ @@ -550,7 +558,13 @@ cpu_set(void) timing_jmp_pm = 27; timing_jmp_pm_gate = 45; break; - + + case CPU_IBM486BL: +#ifdef USE_DYNAREC + x86_setopcodes(ops_386, ops_486_0f, dynarec_ops_386, dynarec_ops_486_0f); +#else + x86_setopcodes(ops_386, ops_486_0f); +#endif case CPU_386DX: timing_rr = 2; /*register dest - register src*/ timing_rm = 6; /*register dest - memory src*/ @@ -582,80 +596,7 @@ cpu_set(void) timing_jmp_pm_gate = 45; break; - case CPU_IBM486SLC: -#ifdef USE_DYNAREC - x86_setopcodes(ops_386, ops_486_0f, dynarec_ops_386, dynarec_ops_486_0f); -#else - x86_setopcodes(ops_386, ops_486_0f); -#endif - timing_rr = 1; /*register dest - register src*/ - timing_rm = 2; /*register dest - memory src*/ - timing_mr = 5; /*memory dest - register src*/ - timing_mm = 3; - timing_rml = 4; /*register dest - memory src long*/ - timing_mrl = 5; /*memory dest - register src long*/ - timing_mml = 5; - timing_bt = 3-1; /*branch taken*/ - timing_bnt = 1; /*branch not taken*/ - timing_int = 4; - timing_int_rm = 26; - timing_int_v86 = 82; - timing_int_pm = 44; - timing_int_pm_outer = 71; - timing_iret_rm = 15; - timing_iret_v86 = 36; /*unknown*/ - timing_iret_pm = 20; - timing_iret_pm_outer = 36; - timing_call_rm = 18; - timing_call_pm = 20; - timing_call_pm_gate = 35; - timing_call_pm_gate_inner = 69; - timing_retf_rm = 13; - timing_retf_pm = 17; - timing_retf_pm_outer = 35; - timing_jmp_rm = 17; - timing_jmp_pm = 19; - timing_jmp_pm_gate = 32; - timing_misaligned = 3; - break; - - case CPU_IBM486BL: -#ifdef USE_DYNAREC - x86_setopcodes(ops_386, ops_486_0f, dynarec_ops_386, dynarec_ops_486_0f); -#else - x86_setopcodes(ops_386, ops_486_0f); -#endif - timing_rr = 1; /*register dest - register src*/ - timing_rm = 2; /*register dest - memory src*/ - timing_mr = 3; /*memory dest - register src*/ - timing_mm = 3; - timing_rml = 2; /*register dest - memory src long*/ - timing_mrl = 3; /*memory dest - register src long*/ - timing_mml = 3; - timing_bt = 3-1; /*branch taken*/ - timing_bnt = 1; /*branch not taken*/ - timing_int = 4; - timing_int_rm = 26; - timing_int_v86 = 82; - timing_int_pm = 44; - timing_int_pm_outer = 71; - timing_iret_rm = 15; - timing_iret_v86 = 36; /*unknown*/ - timing_iret_pm = 20; - timing_iret_pm_outer = 36; - timing_call_rm = 18; - timing_call_pm = 20; - timing_call_pm_gate = 35; - timing_call_pm_gate_inner = 69; - timing_retf_rm = 13; - timing_retf_pm = 17; - timing_retf_pm_outer = 35; - timing_jmp_rm = 17; - timing_jmp_pm = 19; - timing_jmp_pm_gate = 32; - timing_misaligned = 3; - break; - + case CPU_RAPIDCAD: #ifdef USE_DYNAREC x86_setopcodes(ops_386, ops_486_0f, dynarec_ops_386, dynarec_ops_486_0f); diff --git a/src/cpu_common/cpu.h b/src/cpu_common/cpu.h index 92a0cfe9f..636273b75 100644 --- a/src/cpu_common/cpu.h +++ b/src/cpu_common/cpu.h @@ -382,7 +382,8 @@ extern int cpu_cyrix_alignment; /*Cyrix 5x86/6x86 only has data misalignment penalties when crossing 8-byte boundaries*/ extern int is8086, is286, is386, is486, is486sx, is486dx, is486sx2, is486dx2, isdx4; -extern int isibmcpu; +extern int hascache; +extern int isibm486; extern int is_rapidcad; extern int hasfpu; #define CPU_FEATURE_RDTSC (1 << 0) diff --git a/src/cpu_common/cpu_table.c b/src/cpu_common/cpu_table.c index f5f1dca4c..d13877db7 100644 --- a/src/cpu_common/cpu_table.c +++ b/src/cpu_common/cpu_table.c @@ -150,9 +150,9 @@ CPU cpus_i386DX[] = { {"i386DX/25", CPU_386DX, 25000000, 1, 0x0308, 0, 0, 0, 4,4,3,3, 3}, {"i386DX/33", CPU_386DX, 33333333, 1, 0x0308, 0, 0, 0, 6,6,3,3, 4}, {"i386DX/40", CPU_386DX, 40000000, 1, 0x0308, 0, 0, 0, 7,7,3,3, 5}, - {"RapidCAD/25", CPU_RAPIDCAD, 25000000, 1, 0x0430, 0, 0, CPU_SUPPORTS_DYNAREC, 4,4,3,3, 3}, - {"RapidCAD/33", CPU_RAPIDCAD, 33333333, 1, 0x0430, 0, 0, CPU_SUPPORTS_DYNAREC, 6,6,3,3, 4}, - {"RapidCAD/40", CPU_RAPIDCAD, 40000000, 1, 0x0430, 0, 0, CPU_SUPPORTS_DYNAREC, 7,7,3,3, 5}, + {"RapidCAD/25", CPU_RAPIDCAD, 25000000, 1, 0x0340, 0, 0, CPU_SUPPORTS_DYNAREC, 4,4,3,3, 3}, + {"RapidCAD/33", CPU_RAPIDCAD, 33333333, 1, 0x0340, 0, 0, CPU_SUPPORTS_DYNAREC, 6,6,3,3, 4}, + {"RapidCAD/40", CPU_RAPIDCAD, 40000000, 1, 0x0340, 0, 0, CPU_SUPPORTS_DYNAREC, 7,7,3,3, 5}, {"", -1, 0, 0, 0, 0, 0, 0, 0,0,0,0, 0} }; @@ -187,30 +187,30 @@ CPU cpus_486SLC[] = { CPU cpus_IBM386SLC[] = { /*IBM 386SLC*/ - {"386SLC/16", CPU_IBM386SLC, 16000000, 1, 0x300, 0, 0, 0, 3,3,3,3, 2}, - {"386SLC/20", CPU_IBM386SLC, 20000000, 1, 0x300, 0, 0, 0, 4,4,3,3, 3}, - {"386SLC/25", CPU_IBM386SLC, 25000000, 1, 0x300, 0, 0, 0, 4,4,3,3, 3}, + {"386SLC/16", CPU_IBM386SLC, 16000000, 1, 0xA301, 0, 0, 0, 3,3,3,3, 2}, + {"386SLC/20", CPU_IBM386SLC, 20000000, 1, 0xA301, 0, 0, 0, 4,4,3,3, 3}, + {"386SLC/25", CPU_IBM386SLC, 25000000, 1, 0xA301, 0, 0, 0, 4,4,3,3, 3}, {"", -1, 0, 0, 0, 0, 0, 0, 0,0,0,0, 0} }; CPU cpus_IBM486SLC[] = { /*IBM 486SLC*/ - {"486SLC/33", CPU_IBM486SLC, 33333333, 1, 0x400, 0, 0, 0, 6,6,3,3, 4}, - {"486SLC2/40", CPU_IBM486SLC, 40000000, 2, 0x400, 0, 0, 0, 7,7,6,6, 5}, - {"486SLC2/50", CPU_IBM486SLC, 50000000, 2, 0x400, 0, 0, 0, 8,8,6,6, 6}, - {"486SLC2/66", CPU_IBM486SLC, 66666666, 2, 0x400, 0, 0, 0, 12,12,6,6, 8}, - {"486SLC3/60", CPU_IBM486SLC, 60000000, 3, 0x400, 0, 0, 0, 12,12,9,9, 7}, - {"486SLC3/75", CPU_IBM486SLC, 75000000, 3, 0x400, 0, 0, 0, 12,12,9,9, 9}, - {"486SLC3/100", CPU_IBM486SLC, 100000000, 3, 0x400, 0, 0, 0, 18,18,9,9, 12}, + {"486SLC/33", CPU_IBM486SLC, 33333333, 1, 0xA401, 0, 0, 0, 6,6,3,3, 4}, + {"486SLC2/40", CPU_IBM486SLC, 40000000, 2, 0xA421, 0, 0, 0, 7,7,6,6, 5}, + {"486SLC2/50", CPU_IBM486SLC, 50000000, 2, 0xA421, 0, 0, 0, 8,8,6,6, 6}, + {"486SLC2/66", CPU_IBM486SLC, 66666666, 2, 0xA421, 0, 0, 0, 12,12,6,6, 8}, + {"486SLC3/60", CPU_IBM486SLC, 60000000, 3, 0xA439, 0, 0, 0, 12,12,9,9, 7}, + {"486SLC3/75", CPU_IBM486SLC, 75000000, 3, 0xA439, 0, 0, 0, 12,12,9,9, 9}, + {"486SLC3/100", CPU_IBM486SLC, 100000000, 3, 0xA439, 0, 0, 0, 18,18,9,9, 12}, {"", -1, 0, 0, 0, 0, 0, 0, 0,0,0,0, 0} }; CPU cpus_IBM486BL[] = { /*IBM Blue Lightning*/ - {"486BL2/50", CPU_IBM486BL, 50000000, 2, 0x400, 0, 0, 0, 8,8,6,6, 6}, - {"486BL2/66", CPU_IBM486BL, 66666666, 2, 0x400, 0, 0, 0, 12,12,6,6, 8}, - {"486BL3/75", CPU_IBM486BL, 75000000, 3, 0x400, 0, 0, 0, 12,12,9,9, 9}, - {"486BL3/100", CPU_IBM486BL, 100000000, 3, 0x400, 0, 0, 0, 18,18,9,9, 12}, + {"486BL2/50", CPU_IBM486BL, 50000000, 2, 0xA439, 0, 0, 0, 8,8,6,6, 6}, + {"486BL2/66", CPU_IBM486BL, 66666666, 2, 0xA439, 0, 0, 0, 12,12,6,6, 8}, + {"486BL3/75", CPU_IBM486BL, 75000000, 3, 0xA439, 0, 0, 0, 12,12,9,9, 9}, + {"486BL3/100", CPU_IBM486BL, 100000000, 3, 0xA439, 0, 0, 0, 18,18,9,9, 12}, {"", -1, 0, 0, 0, 0, 0, 0, 0,0,0,0, 0} }; diff --git a/src/cpu_common/x86_ops_atomic.h b/src/cpu_common/x86_ops_atomic.h index 4011a0aa4..fca1c244a 100644 --- a/src/cpu_common/x86_ops_atomic.h +++ b/src/cpu_common/x86_ops_atomic.h @@ -1,12 +1,6 @@ static int opCMPXCHG_b_a16(uint32_t fetchdat) { uint8_t temp, temp2 = AL; - if (!is486) - { - cpu_state.pc = cpu_state.oldpc; - x86illegal(); - return 1; - } fetch_ea_16(fetchdat); SEG_CHECK_WRITE(cpu_state.ea_seg); temp = geteab(); if (cpu_state.abrt) return 1; @@ -20,12 +14,6 @@ static int opCMPXCHG_b_a16(uint32_t fetchdat) static int opCMPXCHG_b_a32(uint32_t fetchdat) { uint8_t temp, temp2 = AL; - if (!is486) - { - cpu_state.pc = cpu_state.oldpc; - x86illegal(); - return 1; - } fetch_ea_32(fetchdat); SEG_CHECK_WRITE(cpu_state.ea_seg); temp = geteab(); if (cpu_state.abrt) return 1; @@ -40,12 +28,6 @@ static int opCMPXCHG_b_a32(uint32_t fetchdat) static int opCMPXCHG_w_a16(uint32_t fetchdat) { uint16_t temp, temp2 = AX; - if (!is486) - { - cpu_state.pc = cpu_state.oldpc; - x86illegal(); - return 1; - } fetch_ea_16(fetchdat); SEG_CHECK_WRITE(cpu_state.ea_seg); temp = geteaw(); if (cpu_state.abrt) return 1; @@ -59,12 +41,6 @@ static int opCMPXCHG_w_a16(uint32_t fetchdat) static int opCMPXCHG_w_a32(uint32_t fetchdat) { uint16_t temp, temp2 = AX; - if (!is486) - { - cpu_state.pc = cpu_state.oldpc; - x86illegal(); - return 1; - } fetch_ea_32(fetchdat); SEG_CHECK_WRITE(cpu_state.ea_seg); temp = geteaw(); if (cpu_state.abrt) return 1; @@ -79,12 +55,6 @@ static int opCMPXCHG_w_a32(uint32_t fetchdat) static int opCMPXCHG_l_a16(uint32_t fetchdat) { uint32_t temp, temp2 = EAX; - if (!is486) - { - cpu_state.pc = cpu_state.oldpc; - x86illegal(); - return 1; - } fetch_ea_16(fetchdat); SEG_CHECK_WRITE(cpu_state.ea_seg); temp = geteal(); if (cpu_state.abrt) return 1; @@ -98,12 +68,6 @@ static int opCMPXCHG_l_a16(uint32_t fetchdat) static int opCMPXCHG_l_a32(uint32_t fetchdat) { uint32_t temp, temp2 = EAX; - if (!is486) - { - cpu_state.pc = cpu_state.oldpc; - x86illegal(); - return 1; - } fetch_ea_32(fetchdat); SEG_CHECK_WRITE(cpu_state.ea_seg); temp = geteal(); if (cpu_state.abrt) return 1; @@ -118,12 +82,6 @@ static int opCMPXCHG_l_a32(uint32_t fetchdat) static int opCMPXCHG8B_a16(uint32_t fetchdat) { uint32_t temp, temp_hi, temp2 = EAX, temp2_hi = EDX; - if (!is486) - { - cpu_state.pc = cpu_state.oldpc; - x86illegal(); - return 0; - } fetch_ea_16(fetchdat); SEG_CHECK_WRITE(cpu_state.ea_seg); temp = geteal(); @@ -150,12 +108,6 @@ static int opCMPXCHG8B_a16(uint32_t fetchdat) static int opCMPXCHG8B_a32(uint32_t fetchdat) { uint32_t temp, temp_hi, temp2 = EAX, temp2_hi = EDX; - if (!is486) - { - cpu_state.pc = cpu_state.oldpc; - x86illegal(); - return 0; - } fetch_ea_32(fetchdat); SEG_CHECK_WRITE(cpu_state.ea_seg); temp = geteal(); @@ -183,12 +135,6 @@ static int opCMPXCHG8B_a32(uint32_t fetchdat) static int opXADD_b_a16(uint32_t fetchdat) { uint8_t temp; - if (!is486) - { - cpu_state.pc = cpu_state.oldpc; - x86illegal(); - return 1; - } fetch_ea_16(fetchdat); SEG_CHECK_WRITE(cpu_state.ea_seg); temp = geteab(); if (cpu_state.abrt) return 1; @@ -201,12 +147,6 @@ static int opXADD_b_a16(uint32_t fetchdat) static int opXADD_b_a32(uint32_t fetchdat) { uint8_t temp; - if (!is486) - { - cpu_state.pc = cpu_state.oldpc; - x86illegal(); - return 1; - } fetch_ea_32(fetchdat); SEG_CHECK_WRITE(cpu_state.ea_seg); temp = geteab(); if (cpu_state.abrt) return 1; @@ -220,12 +160,6 @@ static int opXADD_b_a32(uint32_t fetchdat) static int opXADD_w_a16(uint32_t fetchdat) { uint16_t temp; - if (!is486) - { - cpu_state.pc = cpu_state.oldpc; - x86illegal(); - return 1; - } fetch_ea_16(fetchdat); SEG_CHECK_WRITE(cpu_state.ea_seg); temp = geteaw(); if (cpu_state.abrt) return 1; @@ -238,12 +172,6 @@ static int opXADD_w_a16(uint32_t fetchdat) static int opXADD_w_a32(uint32_t fetchdat) { uint16_t temp; - if (!is486) - { - cpu_state.pc = cpu_state.oldpc; - x86illegal(); - return 1; - } fetch_ea_32(fetchdat); SEG_CHECK_WRITE(cpu_state.ea_seg); temp = geteaw(); if (cpu_state.abrt) return 1; @@ -257,12 +185,6 @@ static int opXADD_w_a32(uint32_t fetchdat) static int opXADD_l_a16(uint32_t fetchdat) { uint32_t temp; - if (!is486) - { - cpu_state.pc = cpu_state.oldpc; - x86illegal(); - return 1; - } fetch_ea_16(fetchdat); SEG_CHECK_WRITE(cpu_state.ea_seg); temp = geteal(); if (cpu_state.abrt) return 1; @@ -275,12 +197,6 @@ static int opXADD_l_a16(uint32_t fetchdat) static int opXADD_l_a32(uint32_t fetchdat) { uint32_t temp; - if (!is486) - { - cpu_state.pc = cpu_state.oldpc; - x86illegal(); - return 1; - } fetch_ea_32(fetchdat); SEG_CHECK_WRITE(cpu_state.ea_seg); temp = geteal(); if (cpu_state.abrt) return 1; diff --git a/src/cpu_common/x86_ops_flag.h b/src/cpu_common/x86_ops_flag.h index 099f2e35f..0d9db70a7 100644 --- a/src/cpu_common/x86_ops_flag.h +++ b/src/cpu_common/x86_ops_flag.h @@ -264,11 +264,11 @@ static int opPOPFD(uint32_t fetchdat) else if (IOPLp) cpu_state.flags = (cpu_state.flags & 0x3000) | (templ & 0x4fd5) | 2; else cpu_state.flags = (cpu_state.flags & 0x3200) | (templ & 0x4dd5) | 2; - templ &= is486 ? 0x3c0000 : 0; + templ &= (is486 || isibm486) ? 0x3c0000 : 0; templ |= ((cpu_state.eflags&3) << 16); if (cpu_CR4_mask & CR4_VME) cpu_state.eflags = (templ >> 16) & 0x3f; else if (CPUID) cpu_state.eflags = (templ >> 16) & 0x27; - else if (is486) cpu_state.eflags = (templ >> 16) & 7; + else if (is486 || isibm486) cpu_state.eflags = (templ >> 16) & 7; else cpu_state.eflags = (templ >> 16) & 3; flags_extract(); diff --git a/src/cpu_common/x86_ops_misc.h b/src/cpu_common/x86_ops_misc.h index 91118211b..91994785e 100644 --- a/src/cpu_common/x86_ops_misc.h +++ b/src/cpu_common/x86_ops_misc.h @@ -741,22 +741,12 @@ static int opCLTS(uint32_t fetchdat) static int opINVD(uint32_t fetchdat) { - if (!is486) - { - x86illegal(); - return 1; - } CLOCK_CYCLES(1000); CPU_BLOCK_END(); return 0; } static int opWBINVD(uint32_t fetchdat) { - if (!is486) - { - x86illegal(); - return 1; - } CLOCK_CYCLES(10000); CPU_BLOCK_END(); return 0; diff --git a/src/cpu_common/x86_ops_mov_ctrl.h b/src/cpu_common/x86_ops_mov_ctrl.h index 06a89884b..569fb4dce 100644 --- a/src/cpu_common/x86_ops_mov_ctrl.h +++ b/src/cpu_common/x86_ops_mov_ctrl.h @@ -10,7 +10,7 @@ static int opMOV_r_CRx_a16(uint32_t fetchdat) { case 0: cpu_state.regs[cpu_rm].l = cr0; - if (is486) + if (is486 || isibm486) cpu_state.regs[cpu_rm].l |= 0x10; /*ET hardwired on 486*/ break; case 2: @@ -46,7 +46,7 @@ static int opMOV_r_CRx_a32(uint32_t fetchdat) { case 0: cpu_state.regs[cpu_rm].l = cr0; - if (is486) + if (is486 || isibm486) cpu_state.regs[cpu_rm].l |= 0x10; /*ET hardwired on 486*/ break; case 2: @@ -118,13 +118,11 @@ static int opMOV_CRx_r_a16(uint32_t fetchdat) cr0 |= 0x10; if (!(cr0 & 0x80000000)) mmu_perm=4; - if (is486 && !(cr0 & (1 << 30))) + if (hascache && !(cr0 & (1 << 30))) cpu_cache_int_enabled = 1; - else if (isibmcpu) - cpu_cache_int_enabled = 1; else cpu_cache_int_enabled = 0; - if (is486 && ((cr0 ^ old_cr0) & (1 << 30))) + if (hascache && ((cr0 ^ old_cr0) & (1 << 30))) cpu_update_waitstates(); if (cr0 & 1) cpu_cur_status |= CPU_STATUS_PMODE; @@ -174,11 +172,11 @@ static int opMOV_CRx_r_a32(uint32_t fetchdat) cr0 |= 0x10; if (!(cr0 & 0x80000000)) mmu_perm=4; - if (is486 && !(cr0 & (1 << 30))) + if (hascache && !(cr0 & (1 << 30))) cpu_cache_int_enabled = 1; else cpu_cache_int_enabled = 0; - if (is486 && ((cr0 ^ old_cr0) & (1 << 30))) + if (hascache && ((cr0 ^ old_cr0) & (1 << 30))) cpu_update_waitstates(); if (cr0 & 1) cpu_cur_status |= CPU_STATUS_PMODE; diff --git a/src/cpu_common/x86_ops_pmode.h b/src/cpu_common/x86_ops_pmode.h index 7fe5d4938..26bdc3a11 100644 --- a/src/cpu_common/x86_ops_pmode.h +++ b/src/cpu_common/x86_ops_pmode.h @@ -370,7 +370,7 @@ static int op0F01_common(uint32_t fetchdat, int is32, int is286, int ea32) case 0x20: /*SMSW*/ if (cpu_mod != 3) SEG_CHECK_WRITE(cpu_state.ea_seg); - if (is486) seteaw(msw); + if (is486 || isibm486) seteaw(msw); else if (is386) seteaw(msw | 0xFF00); else seteaw(msw | 0xFFF0); CLOCK_CYCLES(2); @@ -401,7 +401,7 @@ static int op0F01_common(uint32_t fetchdat, int is32, int is286, int ea32) break; case 0x38: /*INVLPG*/ - if (is486) + if (is486 || isibm486) { if ((CPL || cpu_state.eflags&VM_FLAG) && (cr0&1)) {