diff --git a/src/chipset/intel_4x0.c b/src/chipset/intel_4x0.c index d402145d2..48e639ec4 100644 --- a/src/chipset/intel_4x0.c +++ b/src/chipset/intel_4x0.c @@ -60,8 +60,6 @@ typedef struct static void i4x0_map(uint32_t addr, uint32_t size, int state) { - // pclog("i4x0_map(%08X, %08X, %02X)\n", addr, size, state); - switch (state & 3) { case 0: mem_set_mem_state(addr, size, MEM_READ_EXTANY | MEM_WRITE_EXTANY); @@ -97,7 +95,6 @@ pm2_cntrl_read(uint16_t addr, void *p) { i4x0_t *dev = (i4x0_t *) p; - // pclog("PM2_CTL read: %02X\n", dev->pm2_cntrl & 0x01); return dev->pm2_cntrl & 0x01; } @@ -107,7 +104,6 @@ pm2_cntrl_write(uint16_t addr, uint8_t val, void *p) { i4x0_t *dev = (i4x0_t *) p; - // pclog("PM2_CTL write: %02X\n", val); dev->pm2_cntrl = val & 0x01; } @@ -120,13 +116,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv) uint8_t *regs_l = (uint8_t *) dev->regs_locked[func]; int i; - if (func > dev->max_func) { - - // pclog("invalid write %02X to %02X:%02X\n", val, func, addr); - return; - } - - // pclog("write %02X to %02X:%02X\n", val, func, addr); + if (func > dev->max_func) + return; if ((addr >= 0x10) && (addr < 0x4f)) return; @@ -668,7 +659,6 @@ i4x0_write(int func, int addr, uint8_t val, void *priv) io_removehandler(0x0022, 0x01, pm2_cntrl_read, NULL, NULL, pm2_cntrl_write, NULL, NULL, dev); if (val & 0x40) io_sethandler(0x0022, 0x01, pm2_cntrl_read, NULL, NULL, pm2_cntrl_write, NULL, NULL, dev); - // pclog("430TX: PM2_CTL now %sabled\n", (val & 0x40) ? "en" : "dis"); break; case INTEL_440BX: regs[0x79] = val; @@ -682,7 +672,6 @@ i4x0_write(int func, int addr, uint8_t val, void *priv) io_removehandler(0x0022, 0x01, pm2_cntrl_read, NULL, NULL, pm2_cntrl_write, NULL, NULL, dev); if (val & 0x40) io_sethandler(0x0022, 0x01, pm2_cntrl_read, NULL, NULL, pm2_cntrl_write, NULL, NULL, dev); - // pclog("440BX: PM2_CTL now %sabled\n", (val & 0x40) ? "en" : "dis"); break; } break; @@ -918,10 +907,9 @@ i4x0_read(int func, int addr, void *priv) uint8_t ret = 0xff; uint8_t *regs = (uint8_t *) dev->regs[func]; - if (func > dev->max_func) { - ret = 0xff; - // pclog("invalid read %02X from %02X:%02X\n", ret, func, addr); - } else { + if (func > dev->max_func) + ret = 0xff; + else { ret = regs[addr]; #if defined(DEV_BRANCH) && defined(USE_I686) /* Special behavior for 440FX register 0x93 which is basically TRC in PCI space @@ -929,7 +917,6 @@ i4x0_read(int func, int addr, void *priv) if ((func == 0) && (addr == 0x93) && (dev->type == INTEL_440FX)) ret = (ret & 0xf9) | (trc_read(0x0093, NULL) & 0x06); #endif - // pclog("read %02X from %02X:%02X\n", ret, func, addr); } return ret; diff --git a/src/chipset/intel_4x0.c.old b/src/chipset/intel_4x0.c.old deleted file mode 100644 index 3addcff70..000000000 --- a/src/chipset/intel_4x0.c.old +++ /dev/null @@ -1,529 +0,0 @@ -/* - * 86Box A hypervisor and IBM PC system emulator that specializes in - * running old operating systems and software designed for IBM - * PC systems and compatibles from 1981 through fairly recent - * system designs based on the PCI bus. - * - * This file is part of the 86Box distribution. - * - * Implementation of the Intel PCISet chips from 420TX to 440FX. - * - * Version: @(#)intel_4x0.c 1.0.3 2020/01/24 - * - * Authors: Sarah Walker, - * Miran Grca, - * - * Copyright 2019,2020 Miran Grca. - */ -#include -#include -#include -#include -#include -#include "86box.h" -#include "cpu.h" -#include "mem.h" -#include "86box_io.h" -#include "rom.h" -#include "pci.h" -#include "device.h" -#include "keyboard.h" -#include "chipset.h" - - -enum -{ - INTEL_420TX, - INTEL_430LX, - INTEL_430NX, - INTEL_430FX, - INTEL_430FX_PB640, - INTEL_430HX, - INTEL_430VX, - INTEL_430TX -#if defined(DEV_BRANCH) && defined(USE_I686) - ,INTEL_440FX -#endif -}; - -typedef struct -{ - uint8_t pm2_cntrl; - uint8_t regs[256]; - int type; -} i4x0_t; -static void -i4x0_map(uint32_t addr, uint32_t size, int state) -{ - // pclog("i4x0_map(%08X, %08X, %02X)\n", addr, size, state); - - switch (state & 3) { - case 0: - mem_set_mem_state(addr, size, MEM_READ_EXTANY | MEM_WRITE_EXTANY); - break; - case 1: - mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_EXTANY); - break; - case 2: - mem_set_mem_state(addr, size, MEM_READ_EXTANY | MEM_WRITE_INTERNAL); - break; - case 3: - mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); - break; - } - flushmmucache_nopc(); -} - - -static void -i4x0_write(int func, int addr, uint8_t val, void *priv) -{ - i4x0_t *dev = (i4x0_t *) priv; - - if (func) - return; - - pclog("write %02X to %08X\n", val, addr); - - if ((addr >= 0x10) && (addr < 0x4f)) - return; - - switch (addr) { - case 0x00: case 0x01: case 0x02: case 0x03: - case 0x08: case 0x09: case 0x0a: case 0x0b: - case 0x0c: case 0x0e: - return; - - case 0x04: /*Command register*/ - if (dev->type >= INTEL_430FX) { - if (dev->type == INTEL_430FX_PB640) - val &= 0x06; - else - val &= 0x02; - } else - val &= 0x42; - val |= 0x04; - break; - case 0x05: - if (dev->type >= INTEL_430FX) - val = 0; - else - val &= 0x01; - break; - - case 0x06: /*Status*/ - val = 0; - break; - case 0x07: - if (dev->type >= INTEL_430HX) { - val &= 0x80; - val |= 0x02; - } else { - val = 0x02; - if (dev->type == INTEL_430FX_PB640) - val |= 0x20; - } - break; - - case 0x52: /*Cache Control Register*/ -#if defined(DEV_BRANCH) && defined(USE_I686) - if (dev->type < INTEL_440FX) { -#endif - cpu_cache_ext_enabled = (val & 0x01); - cpu_update_waitstates(); -#if defined(DEV_BRANCH) && defined(USE_I686) - } -#endif - break; - - case 0x59: /*PAM0*/ - if ((dev->regs[0x59] ^ val) & 0xf0) { - i4x0_map(0xf0000, 0x10000, val >> 4); - shadowbios = (val & 0x10); - } - break; - case 0x5a: /*PAM1*/ - if ((dev->regs[0x5a] ^ val) & 0x0f) - i4x0_map(0xc0000, 0x04000, val & 0xf); - if ((dev->regs[0x5a] ^ val) & 0xf0) - i4x0_map(0xc4000, 0x04000, val >> 4); - break; - case 0x5b: /*PAM2*/ - if ((dev->regs[0x5b] ^ val) & 0x0f) - i4x0_map(0xc8000, 0x04000, val & 0xf); - if ((dev->regs[0x5b] ^ val) & 0xf0) - i4x0_map(0xcc000, 0x04000, val >> 4); - break; - case 0x5c: /*PAM3*/ - if ((dev->regs[0x5c] ^ val) & 0x0f) - i4x0_map(0xd0000, 0x04000, val & 0xf); - if ((dev->regs[0x5c] ^ val) & 0xf0) - i4x0_map(0xd4000, 0x04000, val >> 4); - break; - case 0x5d: /*PAM4*/ - if ((dev->regs[0x5d] ^ val) & 0x0f) - i4x0_map(0xd8000, 0x04000, val & 0xf); - if ((dev->regs[0x5d] ^ val) & 0xf0) - i4x0_map(0xdc000, 0x04000, val >> 4); - break; - case 0x5e: /*PAM5*/ - if ((dev->regs[0x5e] ^ val) & 0x0f) - i4x0_map(0xe0000, 0x04000, val & 0xf); - if ((dev->regs[0x5e] ^ val) & 0xf0) - i4x0_map(0xe4000, 0x04000, val >> 4); - break; - case 0x5f: /*PAM6*/ - if ((dev->regs[0x5f] ^ val) & 0x0f) - i4x0_map(0xe8000, 0x04000, val & 0xf); - if ((dev->regs[0x5f] ^ val) & 0xf0) - i4x0_map(0xec000, 0x04000, val >> 4); - break; - case 0x72: /*SMRAM*/ - if ((dev->type >= INTEL_430FX) && ((dev->regs[0x72] ^ val) & 0x48)) - i4x0_map(0xa0000, 0x20000, ((val & 0x48) == 0x48) ? 3 : 0); - else if ((dev->type < INTEL_430FX) && ((dev->regs[0x72] ^ val) & 0x20)) - i4x0_map(0xa0000, 0x20000, ((val & 0x20) == 0x20) ? 3 : 0); - break; - - case 0x73: case 0x74: - // pclog("Access %i at %08X\n", dev->regs[0x73] & 3, dev->regs[0x74] << 19); - break; - } - - dev->regs[addr] = val; -} - - -static uint8_t -i4x0_read(int func, int addr, void *priv) -{ - i4x0_t *dev = (i4x0_t *) priv; - uint8_t ret = 0xff; - - if (!func) { - ret = dev->regs[addr]; - pclog("read %02X from %08X\n", ret, addr); - - // if (addr == 0x50) - // pclog("read %02X from %08X\n", ret, addr); - } - - return ret; -} - - -static void -i4x0_reset(void *priv) -{ - i4x0_t *i4x0 = (i4x0_t *)priv; - - i4x0_write(0, 0x59, 0x00, priv); - i4x0_write(0, 0x5e, 0x00, priv); - i4x0_write(0, 0x5f, 0x00, priv); - if (i4x0->type >= INTEL_430FX) - i4x0_write(0, 0x72, 0x02, priv); - - smbase = 0xa0000; -} - - -static void -i4x0_close(void *p) -{ - i4x0_t *i4x0 = (i4x0_t *)p; - - free(i4x0); -} - - -static uint8_t -pm2_cntrl_read(uint16_t addr, void *p) -{ - i4x0_t *dev = (i4x0_t *) p; - - return dev->pm2_cntrl & 0x01; -} - - -static void -pm2_cntrl_write(uint16_t addr, uint8_t val, void *p) -{ - i4x0_t *dev = (i4x0_t *) p; - - dev->pm2_cntrl = val & 0x01; -} - - -static void -*i4x0_init(const device_t *info) -{ - i4x0_t *i4x0 = (i4x0_t *) malloc(sizeof(i4x0_t)); - memset(i4x0, 0, sizeof(i4x0_t)); - - i4x0->type = info->local; - - i4x0->regs[0x00] = 0x86; i4x0->regs[0x01] = 0x80; /*Intel*/ - switch(i4x0->type) { - case INTEL_420TX: - i4x0->regs[0x02] = 0x83; i4x0->regs[0x03] = 0x04; /*82424TX/ZX*/ - i4x0->regs[0x08] = 0x03; /*A3 stepping*/ - i4x0->regs[0x50] = 0x80; - // i4x0->regs[0x50] = 0x23; - i4x0->regs[0x52] = 0x40; /*256kb PLB cache*/ - break; - case INTEL_430LX: - i4x0->regs[0x02] = 0xa3; i4x0->regs[0x03] = 0x04; /*82434LX/NX*/ - i4x0->regs[0x08] = 0x03; /*A3 stepping*/ - i4x0->regs[0x50] = 0x80; - i4x0->regs[0x52] = 0x40; /*256kb PLB cache*/ - break; - case INTEL_430NX: - i4x0->regs[0x02] = 0xa3; i4x0->regs[0x03] = 0x04; /*82434LX/NX*/ - i4x0->regs[0x08] = 0x10; /*A0 stepping*/ - i4x0->regs[0x50] = 0xA0; - i4x0->regs[0x52] = 0x44; /*256kb PLB cache*/ - i4x0->regs[0x66] = i4x0->regs[0x67] = 0x02; - break; - case INTEL_430FX: - case INTEL_430FX_PB640: - i4x0->regs[0x02] = 0x2d; i4x0->regs[0x03] = 0x12; /*SB82437FX-66*/ - if (i4x0->type == INTEL_430FX_PB640) - i4x0->regs[0x08] = 0x02; /*???? stepping*/ - else - i4x0->regs[0x08] = 0x00; /*A0 stepping*/ - i4x0->regs[0x52] = 0x40; /*256kb PLB cache*/ - break; - case INTEL_430HX: - i4x0->regs[0x02] = 0x50; i4x0->regs[0x03] = 0x12; /*82439HX*/ - i4x0->regs[0x08] = 0x00; /*A0 stepping*/ - i4x0->regs[0x51] = 0x20; - i4x0->regs[0x52] = 0xB5; /*512kb cache*/ - i4x0->regs[0x56] = 0x52; /*DRAM control*/ - // i4x0->regs[0x59] = 0x40; - // i4x0->regs[0x5A] = i4x0->regs[0x5B] = i4x0->regs[0x5C] = i4x0->regs[0x5D] = 0x44; - // i4x0->regs[0x5E] = i4x0->regs[0x5F] = 0x44; - i4x0->regs[0x65] = i4x0->regs[0x66] = i4x0->regs[0x67] = 0x02; - i4x0->regs[0x68] = 0x11; - break; - case INTEL_430VX: - i4x0->regs[0x02] = 0x30; i4x0->regs[0x03] = 0x70; /*82437VX*/ - // i4x0->regs[0x02] = 0x2d; i4x0->regs[0x03] = 0x12; /*SB82437FX-66*/ - i4x0->regs[0x08] = 0x00; /*A0 stepping*/ - i4x0->regs[0x52] = 0x42; /*256kb PLB cache*/ - i4x0->regs[0x53] = 0x14; - i4x0->regs[0x56] = 0x52; /*DRAM control*/ - i4x0->regs[0x67] = 0x11; - i4x0->regs[0x69] = 0x03; - i4x0->regs[0x70] = 0x20; - i4x0->regs[0x74] = 0x0e; - i4x0->regs[0x78] = 0x23; - break; - case INTEL_430TX: - io_sethandler(0x0022, 0x01, pm2_cntrl_read, NULL, NULL, pm2_cntrl_write, NULL, NULL, i4x0); - i4x0->regs[0x02] = 0x00; i4x0->regs[0x03] = 0x71; /*82439TX*/ - i4x0->regs[0x08] = 0x01; /*A0 stepping*/ - i4x0->regs[0x52] = 0x42; /*256kb PLB cache*/ - i4x0->regs[0x53] = 0x14; - i4x0->regs[0x56] = 0x52; /*DRAM control*/ - i4x0->regs[0x65] = 0x02; - i4x0->regs[0x67] = 0x80; - i4x0->regs[0x69] = 0x03; - i4x0->regs[0x70] = 0x20; - break; -#if defined(DEV_BRANCH) && defined(USE_I686) - case INTEL_440FX: - i4x0->regs[0x02] = 0x37; i4x0->regs[0x03] = 0x12; /*82441FX*/ - i4x0->regs[0x08] = 0x02; /*A0 stepping*/ - i4x0->regs[0x2c] = 0xf4; - i4x0->regs[0x2d] = 0x1a; - i4x0->regs[0x2f] = 0x11; - i4x0->regs[0x51] = 0x01; - i4x0->regs[0x53] = 0x80; - i4x0->regs[0x58] = 0x10; - i4x0->regs[0x5a] = i4x0->regs[0x5b] = i4x0->regs[0x5c] = i4x0->regs[0x5d] = 0x11; - i4x0->regs[0x5e] = 0x11; - i4x0->regs[0x5f] = 0x31; - break; -#endif - } - i4x0->regs[0x04] = 0x06; i4x0->regs[0x05] = 0x00; -#if defined(DEV_BRANCH) && defined(USE_I686) - if (i4x0->type == INTEL_440FX) - i4x0->regs[0x06] = 0x80; -#endif - if (i4x0->type == INTEL_430FX) - i4x0->regs[0x07] = 0x82; -#if defined(DEV_BRANCH) && defined(USE_I686) - else if (i4x0->type != INTEL_440FX) -#else - else -#endif - i4x0->regs[0x07] = 0x02; - i4x0->regs[0x0b] = 0x06; - if (i4x0->type >= INTEL_430FX) - i4x0->regs[0x57] = 0x01; - else - i4x0->regs[0x57] = 0x31; - i4x0->regs[0x60] = i4x0->regs[0x61] = i4x0->regs[0x62] = i4x0->regs[0x63] = 0x02; - i4x0->regs[0x64] = 0x02; - if (i4x0->type >= INTEL_430FX) - i4x0->regs[0x72] = 0x02; - -#if defined(DEV_BRANCH) && defined(USE_I686) - if (i4x0->type == INTEL_440FX) { - cpu_cache_ext_enabled = 1; - cpu_update_waitstates(); - } -#endif - - pci_add_card(PCI_ADD_NORTHBRIDGE, i4x0_read, i4x0_write, i4x0); - - i4x0_write(0, 0x59, 0x00, i4x0); - i4x0_write(0, 0x5a, 0x00, i4x0); - i4x0_write(0, 0x5b, 0x00, i4x0); - i4x0_write(0, 0x5c, 0x00, i4x0); - i4x0_write(0, 0x5d, 0x00, i4x0); - i4x0_write(0, 0x5e, 0x00, i4x0); - i4x0_write(0, 0x5f, 0x00, i4x0); - - smbase = 0xa0000; - - return i4x0; -} - - -const device_t i420tx_device = -{ - "Intel 82424TX", - DEVICE_PCI, - INTEL_420TX, - i4x0_init, - i4x0_close, - i4x0_reset, - NULL, - NULL, - NULL, - NULL -}; - - -const device_t i430lx_device = -{ - "Intel 82434LX", - DEVICE_PCI, - INTEL_430LX, - i4x0_init, - i4x0_close, - i4x0_reset, - NULL, - NULL, - NULL, - NULL -}; - - -const device_t i430nx_device = -{ - "Intel 82434NX", - DEVICE_PCI, - INTEL_430NX, - i4x0_init, - i4x0_close, - i4x0_reset, - NULL, - NULL, - NULL, - NULL -}; - - -const device_t i430fx_device = -{ - "Intel SB82437FX-66", - DEVICE_PCI, - INTEL_430FX, - i4x0_init, - i4x0_close, - i4x0_reset, - NULL, - NULL, - NULL, - NULL -}; - - -const device_t i430fx_pb640_device = -{ - "Intel SB82437FX-66 (PB640)", - DEVICE_PCI, - INTEL_430FX_PB640, - i4x0_init, - i4x0_close, - i4x0_reset, - NULL, - NULL, - NULL, - NULL -}; - - -const device_t i430hx_device = -{ - "Intel 82439HX", - DEVICE_PCI, - INTEL_430HX, - i4x0_init, - i4x0_close, - i4x0_reset, - NULL, - NULL, - NULL, - NULL -}; - - -const device_t i430vx_device = -{ - "Intel 82437VX", - DEVICE_PCI, - INTEL_430VX, - i4x0_init, - i4x0_close, - i4x0_reset, - NULL, - NULL, - NULL, - NULL -}; - - -const device_t i430tx_device = -{ - "Intel 82439TX", - DEVICE_PCI, - INTEL_430TX, - i4x0_init, - i4x0_close, - i4x0_reset, - NULL, - NULL, - NULL, - NULL -}; - - -#if defined(DEV_BRANCH) && defined(USE_I686) -const device_t i440fx_device = -{ - "Intel 82441FX", - DEVICE_PCI, - INTEL_440FX, - i4x0_init, - i4x0_close, - i4x0_reset, - NULL, - NULL, - NULL, - NULL -}; -#endif diff --git a/src/chipset/sis_85c496.c b/src/chipset/sis_85c496.c index 51888f23f..607178fb9 100644 --- a/src/chipset/sis_85c496.c +++ b/src/chipset/sis_85c496.c @@ -120,8 +120,6 @@ sis_85c496_write(int func, int addr, uint8_t val, void *priv) if ((addr >= 4 && addr < 8) || addr >= 0x40) dev->pci_conf[addr] = val; - pclog("SiS 496 Write: %02X %02X %02X\n", func, addr, val); - valxor = old ^ val; switch (addr) { @@ -144,7 +142,6 @@ sis_85c496_write(int func, int addr, uint8_t val, void *priv) port_92_remove(dev->port_92); if (val & 0x02) port_92_add(dev->port_92); - pclog("Port 92: %sabled\n", (val & 0x02) ? "En" : "Dis"); } break; @@ -199,10 +196,8 @@ sis_85c496_write(int func, int addr, uint8_t val, void *priv) break; case 0x67: - if (valxor & 0x60) { + if (valxor & 0x60) port_92_set_features(dev->port_92, !!(val & 0x20), !!(val & 0x40)); - pclog("[Port 92] Set features: %sreset, %sA20\n", !!(val & 0x20) ? "" : "no ", !!(val & 0x40) ? "" : "no "); - } break; case 0x82: @@ -252,8 +247,6 @@ sis_85c496_read(int func, int addr, void *priv) break; } - pclog("SiS 496 Read: %02X %02X %02X\n", func, addr, ret); - return ret; } diff --git a/src/cpu_new/codegen_ops_misc.c b/src/cpu_new/codegen_ops_misc.c index d4c243f96..eb73a4f81 100644 --- a/src/cpu_new/codegen_ops_misc.c +++ b/src/cpu_new/codegen_ops_misc.c @@ -359,11 +359,11 @@ uint32_t ropFF_16(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fe return -1; case 0x28: /*JMP far*/ + uop_MOVZX(ir, IREG_pc, src_reg); uop_MEM_LOAD_REG_OFFSET(ir, IREG_temp1_W, ireg_seg_base(target_seg), IREG_eaaddr, 2); uop_LOAD_FUNC_ARG_REG(ir, 0, IREG_temp1_W); - uop_LOAD_FUNC_ARG_IMM(ir, 1, cpu_state.oldpc); + uop_LOAD_FUNC_ARG_IMM(ir, 1, op_pc + 1); uop_CALL_FUNC(ir, loadcsjmp); - uop_MOVZX(ir, IREG_pc, src_reg); return -1; case 0x30: /*PUSH*/ @@ -466,11 +466,11 @@ uint32_t ropFF_32(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fe return -1; case 0x28: /*JMP far*/ + uop_MOV(ir, IREG_pc, src_reg); uop_MEM_LOAD_REG_OFFSET(ir, IREG_temp1_W, ireg_seg_base(target_seg), IREG_eaaddr, 4); uop_LOAD_FUNC_ARG_REG(ir, 0, IREG_temp1_W); - uop_LOAD_FUNC_ARG_IMM(ir, 1, cpu_state.oldpc); + uop_LOAD_FUNC_ARG_IMM(ir, 1, op_pc + 1); uop_CALL_FUNC(ir, loadcsjmp); - uop_MOV(ir, IREG_pc, src_reg); return -1; case 0x30: /*PUSH*/ diff --git a/src/disk/hdc_ide.c b/src/disk/hdc_ide.c index 5ec684bc7..78f612460 100644 --- a/src/disk/hdc_ide.c +++ b/src/disk/hdc_ide.c @@ -278,6 +278,8 @@ ide_irq_raise(ide_t *ide) /* ide_log("Raising IRQ %i (board %i)\n", ide_boards[ide->board]->irq, ide->board); */ + ide_log("IDE %i: IRQ raise\n", ide->board); + if (!(ide->fdisk & 2)) { if (ide_bm[ide->board] && ide_bm[ide->board]->set_irq) ide_bm[ide->board]->set_irq(ide->board | 0x40, ide_bm[ide->board]->priv); @@ -298,6 +300,8 @@ ide_irq_lower(ide_t *ide) /* ide_log("Lowering IRQ %i (board %i)\n", ide_boards[ide->board]->irq, ide->board); */ + ide_log("IDE %i: IRQ lower\n", ide->board); + if (ide->irqstat) { if (ide_bm[ide->board] && ide_bm[ide->board]->set_irq) ide_bm[ide->board]->set_irq(ide->board, ide_bm[ide->board]->priv); @@ -318,6 +322,7 @@ ide_irq_update(ide_t *ide) /* ide_log("Raising IRQ %i (board %i)\n", ide_boards[ide->board]->irq, ide->board); */ if (!(ide->fdisk & 2) && ide->irqstat) { + ide_log("IDE %i: IRQ update raise\n", ide->board); if (ide_bm[ide->board] && ide_bm[ide->board]->set_irq) { ide_bm[ide->board]->set_irq(ide->board, ide_bm[ide->board]->priv); ide_bm[ide->board]->set_irq(ide->board | 0x40, ide_bm[ide->board]->priv); @@ -326,6 +331,7 @@ ide_irq_update(ide_t *ide) picint(1 << ide_boards[ide->board]->irq); } } else if (ide->fdisk & 2) { + ide_log("IDE %i: IRQ update lower\n", ide->board); if (ide_bm[ide->board] && ide_bm[ide->board]->set_irq) ide_bm[ide->board]->set_irq(ide->board, ide_bm[ide->board]->priv); else if (ide_boards[ide->board]->irq != -1) @@ -877,11 +883,17 @@ ide_atapi_callback(ide_t *ide) switch(ide->sc->packet_status) { case PHASE_IDLE: +#ifdef ENABLE_IDE_LOG + ide_log("PHASE_IDLE\n"); +#endif ide->sc->pos = 0; ide->sc->phase = 1; ide->sc->status = READY_STAT | DRQ_STAT | (ide->sc->status & ERR_STAT); return; case PHASE_COMMAND: +#ifdef ENABLE_IDE_LOG + ide_log("PHASE_COMMAND\n"); +#endif ide->sc->status = BUSY_STAT | (ide->sc->status & ERR_STAT); if (ide->packet_command) { ide->packet_command(ide->sc, ide->sc->atapi_cdb); @@ -890,6 +902,9 @@ ide_atapi_callback(ide_t *ide) } return; case PHASE_COMPLETE: +#ifdef ENABLE_IDE_LOG + ide_log("PHASE_COMPLETE\n"); +#endif ide->sc->status = READY_STAT; ide->sc->phase = 3; ide->sc->packet_status = PHASE_NONE; @@ -897,12 +912,18 @@ ide_atapi_callback(ide_t *ide) return; case PHASE_DATA_IN: case PHASE_DATA_OUT: +#ifdef ENABLE_IDE_LOG + ide_log("PHASE_DATA_IN or PHASE_DATA_OUT\n"); +#endif ide->sc->status = READY_STAT | DRQ_STAT | (ide->sc->status & ERR_STAT); ide->sc->phase = !(ide->sc->packet_status & 0x01) << 1; ide_irq_raise(ide); return; case PHASE_DATA_IN_DMA: case PHASE_DATA_OUT_DMA: +#ifdef ENABLE_IDE_LOG + ide_log("PHASE_DATA_IN_DMA or PHASE_DATA_OUT_DMA\n"); +#endif out = (ide->sc->packet_status & 0x01); if (ide_bm[ide->board] && ide_bm[ide->board]->dma) { @@ -932,11 +953,17 @@ ide_atapi_callback(ide_t *ide) return; case PHASE_ERROR: +#ifdef ENABLE_IDE_LOG + ide_log("PHASE_ERROR\n"); +#endif ide->sc->status = READY_STAT | ERR_STAT; ide->sc->phase = 3; ide->sc->packet_status = PHASE_NONE; ide_irq_raise(ide); return; + default: + ide_log("PHASE_UNKNOWN %02X\n", ide->sc->packet_status); + return; } } @@ -1001,6 +1028,9 @@ ide_atapi_packet_read(ide_t *ide, int length) if (!dev || !dev->temp_buffer || (dev->packet_status != PHASE_DATA_IN)) return 0; + if (dev->packet_status == PHASE_DATA_IN) + ide_log("PHASE_DATA_IN read: %i, %i< %i, %i\n", dev->request_pos, dev->max_transfer_len, dev->pos, dev->packet_len); + bufferw = (uint16_t *) dev->temp_buffer; bufferl = (uint32_t *) dev->temp_buffer; @@ -1689,7 +1719,7 @@ ide_read_data(ide_t *ide, int length) ide->secount = (ide->secount - 1) & 0xff; if (ide->secount) { ide_next_sector(ide); - ide->atastat = BSY_STAT; + ide->atastat = BSY_STAT | READY_STAT | DSC_STAT; if (ide->command == WIN_READ_MULTIPLE) ide_callback(ide_boards[ide->board]); else diff --git a/src/disk/hdc_ide_sff8038i.c b/src/disk/hdc_ide_sff8038i.c index 2c58042ae..5e2b19e8d 100644 --- a/src/disk/hdc_ide_sff8038i.c +++ b/src/disk/hdc_ide_sff8038i.c @@ -373,14 +373,16 @@ sff_bus_master_set_irq(int channel, void *priv) channel &= 0x01; if (dev->status & 0x04) { - if ((dev->irq_mode == 2) && (channel & 1) && pci_use_mirq(0)) + sff_log("SFF8038i: Channel %i IRQ raise\n", channel); + if ((dev->irq_mode == 2) && channel && pci_use_mirq(0)) pci_set_mirq(0, 0); else if (dev->irq_mode == 1) pci_set_irq(dev->slot, dev->irq_pin); else picint(1 << (14 + channel)); } else { - if ((dev->irq_mode == 2) && (channel & 1) && pci_use_mirq(0)) + sff_log("SFF8038i: Channel %i IRQ lower\n", channel); + if ((dev->irq_mode == 2) && channel && pci_use_mirq(0)) pci_clear_mirq(0, 0); else if (dev->irq_mode == 1) pci_clear_irq(dev->slot, dev->irq_pin); @@ -419,6 +421,10 @@ sff_reset(void *p) { int i = 0; +#ifdef ENABLE_SFF_LOG + sff_log("SFF8038i: Reset\n"); +#endif + for (i = 0; i < CDROM_NUM; i++) { if ((cdrom[i].bus_type == CDROM_BUS_ATAPI) && (cdrom[i].ide_channel < 4) && cdrom[i].priv) @@ -429,6 +435,9 @@ sff_reset(void *p) (zip_drives[i].ide_channel < 4) && zip_drives[i].priv) zip_reset((scsi_common_t *) zip_drives[i].priv); } + + sff_bus_master_set_irq(0x00, p); + sff_bus_master_set_irq(0x01, p); } diff --git a/src/disk/hdc_st506_at.c b/src/disk/hdc_st506_at.c index a6da77d30..8f29d4fa4 100644 --- a/src/disk/hdc_st506_at.c +++ b/src/disk/hdc_st506_at.c @@ -463,7 +463,7 @@ mfm_readw(uint16_t port, void *priv) mfm->secount = (mfm->secount - 1) & 0xff; if (mfm->secount) { next_sector(mfm); - mfm->status = STAT_BUSY; + mfm->status = STAT_BUSY | STAT_READY | STAT_DSC; timer_set_delay_u64(&mfm->callback_timer, SECTOR_TIME); } else ui_sb_update_icon(SB_HDD|HDD_BUS_MFM, 0); diff --git a/src/floppy/fdc.c b/src/floppy/fdc.c index 81274199c..d4eebc796 100644 --- a/src/floppy/fdc.c +++ b/src/floppy/fdc.c @@ -702,10 +702,6 @@ fdc_write(uint16_t addr, uint8_t val, void *priv) fdc->stat = 0x00; fdc->pnum = fdc->ptot = 0; } - if (val&4) { - fdc->stat = 0x80; - fdc->pnum = fdc->ptot = 0; - } if ((val&4) && !(fdc->dor&4)) { timer_set_delay_u64(&fdc->timer, 8 * TIMER_USEC); fdc->interrupt = -1; @@ -775,7 +771,16 @@ fdc_write(uint16_t addr, uint8_t val, void *priv) fdc->stat |= 0x10; fdc_log("Starting FDC command %02X\n",fdc->command); - switch (fdc->command & 0x1f) { + if (((fdc->command & 0x1f) == 0x02) || ((fdc->command & 0x1f) == 0x05) || + ((fdc->command & 0x1f) == 0x06) || ((fdc->command & 0x1f) == 0x0a) || + ((fdc->command & 0x1f) == 0x0c) || ((fdc->command & 0x1f) == 0x0d) || + ((fdc->command & 0x1f) == 0x11) || ((fdc->command & 0x1f) == 0x16) || + ((fdc->command & 0x1f) == 0x19) || ((fdc->command & 0x1f) == 0x1d)) + fdc->processed_cmd = fdc->command & 0x1f; + else + fdc->processed_cmd = fdc->command; + + switch (fdc->processed_cmd) { case 0x01: /*Mode*/ if (fdc->flags & FDC_FLAG_NSC) { fdc->pnum = 0; @@ -921,7 +926,7 @@ fdc_write(uint16_t addr, uint8_t val, void *priv) } if (fdc->pnum == fdc->ptot) { fdc_log("Got all params %02X\n", fdc->command); - fdc->interrupt = fdc->command & 0x1F; + fdc->interrupt = fdc->processed_cmd; fdc->reset_stat = 0; /* Disable timer if enabled. */ timer_disable(&fdc->timer); @@ -950,7 +955,7 @@ fdc_write(uint16_t addr, uint8_t val, void *priv) break; } /* Process the firt phase of the command. */ - switch (fdc->interrupt & 0x1F) { + switch (fdc->processed_cmd) { case 0x02: /* Read a track */ fdc_io_command_phase1(fdc, 0); fdc->read_track_sector.id.c = fdc->params[1]; @@ -1072,7 +1077,8 @@ fdc_write(uint16_t addr, uint8_t val, void *priv) fdc->stat = (1 << fdc->drive); if (!(fdc->flags & FDC_FLAG_PCJR)) fdc->stat |= 0x80; - fdc->head = (fdc->params[0] & 4) ? 1 : 0; + /* fdc->head = (fdc->params[0] & 4) ? 1 : 0; */ + fdc->head = 0; /* TODO: See if this is correct. */ fdc->st0 = fdc->params[0] & 0x03; fdc->st0 |= (fdc->params[0] & 4); fdc->st0 |= 0x80; @@ -1210,21 +1216,22 @@ fdc_read(uint16_t addr, void *priv) } } else { if (is486 || !fdc->enable_3f1) - return 0xff; + ret = 0xff; + else { + ret = 0x70; - ret = 0x70; + drive = real_drive(fdc, fdc->dor & 3); - drive = real_drive(fdc, fdc->dor & 3); + if (drive) + ret &= ~0x40; + else + ret &= ~0x20; - if (drive) - ret &= ~0x40; - else - ret &= ~0x20; - - if (fdc->dor & 0x10) - ret |= 1; - if (fdc->dor & 0x20) - ret |= 2; + if (fdc->dor & 0x10) + ret |= 1; + if (fdc->dor & 0x20) + ret |= 2; + } } break; case 2: diff --git a/src/floppy/fdc.h b/src/floppy/fdc.h index 786d1bfe5..4fae14c62 100644 --- a/src/floppy/fdc.h +++ b/src/floppy/fdc.h @@ -36,7 +36,7 @@ typedef struct { - uint8_t dor, stat, command, dat, st0, swap; + uint8_t dor, stat, command, processed_cmd, dat, st0, swap; uint8_t swwp, disable_write; uint8_t params[256], res[256]; uint8_t specify[256], format_dat[256]; diff --git a/src/floppy/fdd_86f.c b/src/floppy/fdd_86f.c index d55f86734..8eb4d0f42 100644 --- a/src/floppy/fdd_86f.c +++ b/src/floppy/fdd_86f.c @@ -826,7 +826,7 @@ d86f_byteperiod(int drive) int d86f_is_mfm(int drive) { - return (d86f_track_flags(drive) & 8) ? 1 : 0; + return ((d86f_track_flags(drive) & 0x18) == 0x08) ? 1 : 0; } diff --git a/src/hwm.c b/src/hwm.c index 7f3ac49d6..b3142c7a4 100644 --- a/src/hwm.c +++ b/src/hwm.c @@ -14,6 +14,7 @@ * Copyright 2020 RichardG. */ +#include #include "device.h" #include "hwm.h" diff --git a/src/intel_piix.c b/src/intel_piix.c index 96ecb5c80..3ad177051 100644 --- a/src/intel_piix.c +++ b/src/intel_piix.c @@ -35,6 +35,7 @@ #include "device.h" #include "apm.h" #include "keyboard.h" +#include "machine.h" #include "mem.h" #include "timer.h" #include "nvr.h" @@ -1209,6 +1210,7 @@ static void *piix_init(const device_t *info) { int i; + CPU *cpu_s = &machines[machine].cpu[cpu_manufacturer].cpus[cpu]; piix_t *dev = (piix_t *) malloc(sizeof(piix_t)); memset(dev, 0, sizeof(piix_t)); diff --git a/src/keyboard_at.c b/src/keyboard_at.c index dfaf1d9ca..c81f07bfa 100644 --- a/src/keyboard_at.c +++ b/src/keyboard_at.c @@ -2210,7 +2210,8 @@ kbd_read(uint16_t port, void *priv) atkbd_t *dev = (atkbd_t *)priv; uint8_t ret = 0xff; - sub_cycles(ISA_CYCLES(8)); + if ((dev->flags & KBC_TYPE_MASK) >= KBC_TYPE_PS2_NOREF) + sub_cycles(ISA_CYCLES(8)); if (((dev->flags & KBC_VEN_MASK) == KBC_VEN_XI8088) && (port == 0x63)) port = 0x61; diff --git a/src/machine/m_at_socket7_s7.c b/src/machine/m_at_socket7_s7.c index 9db6c31cc..685dcb7a5 100644 --- a/src/machine/m_at_socket7_s7.c +++ b/src/machine/m_at_socket7_s7.c @@ -315,7 +315,7 @@ machine_at_tc430hx_init(const machine_t *model) if (bios_only || !ret) return ret; - machine_at_common_init_ex(model, 2); + machine_at_common_init(model); pci_init(PCI_CONFIG_TYPE_1); pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0); @@ -526,13 +526,8 @@ machine_at_txp4_init(const machine_t *model) { int ret; -#if 0 - ret = bios_load_linear(L"roms/machines/txp4/5itw003.bin", + ret = bios_load_linear(L"roms/machines/txp4/0112L.001", 0x000e0000, 131072, 0); -#else - ret = bios_load_linear(L"roms/machines/txp4/TX5I0108.AWD", - 0x000e0000, 131072, 0); -#endif if (bios_only || !ret) return ret; @@ -605,13 +600,11 @@ machine_at_sp586tx_init(const machine_t *model) pci_init(PCI_CONFIG_TYPE_1); pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0); - pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 2, 3, 4); - pci_register_slot(0x0B, PCI_CARD_NORMAL, 2, 3, 4, 1); - pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2); - pci_register_slot(0x09, PCI_CARD_NORMAL, 4, 1, 2, 3); + pci_register_slot(0x09, PCI_CARD_NORMAL, 1, 2, 3, 4); + pci_register_slot(0x0A, PCI_CARD_NORMAL, 2, 3, 4, 1); + pci_register_slot(0x0B, PCI_CARD_NORMAL, 3, 4, 1, 2); + pci_register_slot(0x0C, PCI_CARD_NORMAL, 4, 1, 2, 3); pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4); /* PIIX4 */ - pci_register_slot(0x0D, PCI_CARD_NORMAL, 1, 2, 3, 4); - pci_register_slot(0x08, PCI_CARD_NORMAL, 1, 2, 3, 4); device_add(&i430tx_device); device_add(&piix4_device); device_add(&keyboard_ps2_pci_device); diff --git a/src/mouse_ps2.c b/src/mouse_ps2.c index cb7653664..cbd3e5695 100644 --- a/src/mouse_ps2.c +++ b/src/mouse_ps2.c @@ -143,6 +143,27 @@ ps2_write(uint8_t val, void *priv) keyboard_at_adddata_mouse(dev->sample_rate); break; + case 0xeb: /* Get mouse data */ + keyboard_at_adddata_mouse(0xfa); + + temp = 0; + if (dev->x < 0) + temp |= 0x10; + if (dev->y < 0) + temp |= 0x20; + if (mouse_buttons & 1) + temp |= 1; + if (mouse_buttons & 2) + temp |= 2; + if ((mouse_buttons & 4) && (dev->flags & FLAG_INTELLI)) + temp |= 4; + keyboard_at_adddata_mouse(temp); + keyboard_at_adddata_mouse(dev->x & 0xff); + keyboard_at_adddata_mouse(dev->y & 0xff); + if (dev->flags & FLAG_INTMODE) + keyboard_at_adddata_mouse(dev->z); + break; + case 0xf2: /* read ID */ keyboard_at_adddata_mouse(0xfa); if (dev->flags & FLAG_INTMODE) @@ -169,6 +190,7 @@ ps2_write(uint8_t val, void *priv) case 0xff: /* reset */ dev->mode = MODE_STREAM; dev->flags &= 0x88; + mouse_queue_start = mouse_queue_end = 0; keyboard_at_adddata_mouse(0xfa); keyboard_at_adddata_mouse(0xaa); keyboard_at_adddata_mouse(0x00); diff --git a/src/pic.c b/src/pic.c index ac13841e6..ad8cc00d5 100644 --- a/src/pic.c +++ b/src/pic.c @@ -345,6 +345,35 @@ pic2_write(uint16_t addr, uint8_t val, void *priv) pic.pend &= ~4; pic_updatepending(); } else if (!(val & 8)) { /*OCW2*/ +#ifdef ENABLE_PIC_LOG + switch ((val >> 5) & 0x07) { + case 0x00: + pic_log("Rotate in automatic EOI mode (clear)\n"); + break; + case 0x01: + pic_log("Non-specific EOI command\n"); + break; + case 0x02: + pic_log("No operation\n"); + break; + case 0x03: + pic_log("Specific EOI command\n"); + break; + case 0x04: + pic_log("Rotate in automatic EOI mode (set)\n"); + break; + case 0x05: + pic_log("Rotate on on-specific EOI command\n"); + break; + case 0x06: + pic_log("Set priority command\n"); + break; + case 0x07: + pic_log("Rotate on specific EOI command\n"); + break; + } +#endif + pic2.ocw2 = val; if ((val & 0xE0) == 0x60) { pic2.ins &= ~(1 << (val & 7)); @@ -512,21 +541,32 @@ pic_process_interrupt(PIC* target_pic, int c) { uint8_t pending = target_pic->pend & ~target_pic->mask; int ret = -1; + /* TODO: On init, a PIC need to get a pointer to one of these, and rotate as needed + if in rotate mode. */ + /* 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 */ + int priority_xt[16] = { 7, 6, 5, 4, 3, 2, 1, 0, -1, -1, -1, -1, -1, -1, -1, -1 }; + int priority_at[16] = { 14, 13, -1, 4, 3, 2, 1, 0, 12, 11, 10, 9, 8, 7, 6, 5 }; + int i; int pic_int = c & 7; int pic_int_num = 1 << pic_int; int in_service = 0; - in_service = (target_pic->ins & (pic_int_num - 1)); /* Is anything of higher priority already in service? */ - in_service |= (target_pic->ins & pic_int_num); /* Is the current IRQ already in service? */ if (AT) { - /* AT-specific stuff. */ - if (c >= 8) - in_service |= (pic.ins & 0x03); /* IRQ 8 to 15, are IRQ's with higher priorities than the - cascade IRQ already in service? */ - /* For IRQ 0 to 7, the cascade IRQ's in service bit indicates that one or - more IRQ's between 8 and 15 are already in service. */ + for (i = 0; i < 16; i++) { + if ((priority_at[i] != -1) && (priority_at[i] >= priority_at[c])) { + if (i < 8) + in_service |= (pic.ins & (1 << i)); + else + in_service |= (pic2.ins & (1 << i)); + } + } + } else { + for (i = 0; i < 16; i++) { + if ((priority_xt[i] != -1) && (priority_xt[i] >= priority_xt[c])) + in_service |= (pic.ins & (1 << i)); + } } if ((pending & pic_int_num) && !in_service) { diff --git a/src/scsi/scsi.c b/src/scsi/scsi.c index faa7f108d..fb1bdec79 100644 --- a/src/scsi/scsi.c +++ b/src/scsi/scsi.c @@ -74,7 +74,8 @@ static SCSI_CARD scsi_cards[] = { { "[MCA] BusLogic BT-640A", "bt640a", &buslogic_640a_device, }, { "[PCI] BusLogic BT-958D", "bt958d", &buslogic_pci_device, }, { "[PCI] NCR 53C810", "ncr53c810", &ncr53c810_pci_device, }, - //{ "[PCI] NCR 53C825A", "ncr53c825a", &ncr53c825a_pci_device, }, + { "[PCI] NCR 53C825A", "ncr53c825a", &ncr53c825a_pci_device, }, + { "[PCI] NCR 53C860", "ncr53c860", &ncr53c860_pci_device, }, { "[PCI] NCR 53C875", "ncr53c875", &ncr53c875_pci_device, }, { "[VLB] BusLogic BT-445S", "bt445s", &buslogic_445s_device, }, { "", "", NULL, }, diff --git a/src/scsi/scsi_ncr53c8xx.c b/src/scsi/scsi_ncr53c8xx.c index 3161e8f7f..77c9d0143 100644 --- a/src/scsi/scsi_ncr53c8xx.c +++ b/src/scsi/scsi_ncr53c8xx.c @@ -49,8 +49,11 @@ #define NCR53C8XX_ROM L"roms/scsi/ncr53c8xx/NCR307.BIN" +#define HA_ID 7 + #define CHIP_810 0x01 #define CHIP_825 0x03 +#define CHIP_860 0x06 #define CHIP_875 0x0f #define NCR_SCNTL0_TRG 0x01 @@ -302,6 +305,10 @@ typedef struct { uint32_t adder; pc_timer_t timer; + +#ifdef USE_WDTR + uint8_t tr_set[16]; +#endif } ncr53c8xx_t; @@ -401,7 +408,7 @@ ncr53c8xx_soft_reset(ncr53c8xx_t *dev) dev->scntl3 = 0; dev->sstat0 = 0; dev->sstat1 = 0; - dev->scid = 7; + dev->scid = HA_ID; dev->sxfer = 0; dev->socl = 0; dev->sdid = 0; @@ -428,13 +435,21 @@ ncr53c8xx_soft_reset(ncr53c8xx_t *dev) if (dev->chip >= CHIP_825) { /* This *IS* a wide SCSI controller, so reset all SCSI devices. */ - for (i = 0; i < 16; i++) + for (i = 0; i < 16; i++) { +#ifdef USE_WDTR + dev->tr_set[i] = 0; +#endif scsi_device_reset(&scsi_devices[i]); + } } else { /* This is *NOT* a wide SCSI controller, so do not touch SCSI devices with ID's >= 8. */ - for (i = 0; i < 8; i++) + for (i = 0; i < 8; i++) { +#ifdef USE_WDTR + dev->tr_set[i] = 0; +#endif scsi_device_reset(&scsi_devices[i]); + } } } @@ -802,9 +817,9 @@ ncr53c8xx_do_wdtr(ncr53c8xx_t *dev, int exponent) ncr53c8xx_log("Target-initiated WDTR (%08X)\n", dev); ncr53c8xx_set_phase(dev, PHASE_MI); dev->msg_action = 4; - ncr53c8xx_add_msg_byte(dev, 0x01); /* EXTENDED MESSAGE */ - ncr53c8xx_add_msg_byte(dev, 0x02); /* EXTENDED MESSAGE LENGTH */ - ncr53c8xx_add_msg_byte(dev, 0x03); /* WIDE DATA TRANSFER REQUEST */ + ncr53c8xx_add_msg_byte(dev, 0x01); /* EXTENDED MESSAGE */ + ncr53c8xx_add_msg_byte(dev, 0x02); /* EXTENDED MESSAGE LENGTH */ + ncr53c8xx_add_msg_byte(dev, 0x03); /* WIDE DATA TRANSFER REQUEST */ ncr53c8xx_add_msg_byte(dev, exponent); /* TRANSFER WIDTH EXPONENT (16-bit) */ } #endif @@ -925,13 +940,14 @@ ncr53c8xx_do_msgout(ncr53c8xx_t *dev, uint8_t id) break; case 3: ncr53c8xx_log("WDTR (ignored)\n"); +#ifdef USE_WDTR + dev->tr_set[dev->sdid] = 1; +#endif if (arg > 0x01) { ncr53c8xx_bad_message(dev, msg); return; } -#ifdef USE_WDTR ncr53c8xx_set_phase(dev, PHASE_CMD); -#endif break; case 5: ncr53c8xx_log("PPR (ignored)\n"); @@ -960,9 +976,14 @@ ncr53c8xx_do_msgout(ncr53c8xx_t *dev, uint8_t id) scsi_device_command_stop(sd); ncr53c8xx_disconnect(dev); break; + case 0x0c: + /* BUS DEVICE RESET message, reset wide transfer request. */ +#ifdef USE_WDTR + dev->tr_set[dev->sdid] = 0; +#endif + /* FALLTHROUGH */ case 0x06: case 0x0e: - case 0x0c: /* clear the current I/O process */ scsi_device_command_stop(sd); ncr53c8xx_disconnect(dev); @@ -977,10 +998,11 @@ ncr53c8xx_do_msgout(ncr53c8xx_t *dev, uint8_t id) dev->current_lun = msg & 7; ncr53c8xx_log("Select LUN %d\n", dev->current_lun); #ifdef USE_WDTR - ncr53c8xx_do_wdtr(dev, 0x01); -#else - ncr53c8xx_set_phase(dev, PHASE_CMD); + if ((dev->chip == CHIP_875) && !dev->tr_set[dev->sdid]) + ncr53c8xx_do_wdtr(dev, 0x01); + else #endif + ncr53c8xx_set_phase(dev, PHASE_CMD); } break; } @@ -2625,6 +2647,7 @@ ncr53c8xx_init(const device_t *info) ncr53c8xx_pci_bar[0].addr_regs[0] = 1; ncr53c8xx_pci_bar[1].addr_regs[0] = 0; dev->chip = info->local; + ncr53c8xx_pci_regs[0x04] = 3; ncr53c8xx_mem_init(dev, 0x0fffff00); @@ -2632,12 +2655,14 @@ ncr53c8xx_init(const device_t *info) dev->has_bios = device_get_config_int("bios"); if (dev->has_bios) - rom_init(&dev->bios, NCR53C8XX_ROM, 0xc8000, 0x4000, 0x3fff, 0, MEM_MAPPING_EXTERNAL); + rom_init(&dev->bios, NCR53C8XX_ROM, 0xc8000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL); if (dev->chip >= CHIP_825) { - if (dev->chip == CHIP_875) { dev->chip_rev = 0x04; dev->nvr_path = L"ncr53c875.nvr"; + } else if (dev->chip == CHIP_860) { + dev->chip_rev = 0x04; + dev->nvr_path = L"ncr53c860.nvr"; } else { dev->chip_rev = 0x26; dev->nvr_path = L"ncr53c825a.nvr"; @@ -2654,8 +2679,8 @@ ncr53c8xx_init(const device_t *info) ncr53c8xx_bios_disable(dev); #endif } else { - if (dev->has_bios) - rom_init(&dev->bios, NCR53C8XX_ROM, 0xc8000, 0x4000, 0x3fff, 0, MEM_MAPPING_EXTERNAL); + /* if (dev->has_bios) + rom_init(&dev->bios, NCR53C8XX_ROM, 0xc8000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL); */ dev->nvr_path = L"ncr53c810.nvr"; } @@ -2715,6 +2740,16 @@ const device_t ncr53c825a_pci_device = ncr53c8xx_pci_config }; +const device_t ncr53c860_pci_device = +{ + "NCR 53c860 (SCSI)", + DEVICE_PCI, + CHIP_860, + ncr53c8xx_init, ncr53c8xx_close, NULL, + NULL, NULL, NULL, + ncr53c8xx_pci_config +}; + const device_t ncr53c875_pci_device = { "NCR 53c875 (SCSI)", diff --git a/src/scsi/scsi_ncr53c8xx.h b/src/scsi/scsi_ncr53c8xx.h index e50e6d954..b84c91c1c 100644 --- a/src/scsi/scsi_ncr53c8xx.h +++ b/src/scsi/scsi_ncr53c8xx.h @@ -27,6 +27,7 @@ extern const device_t ncr53c810_pci_device; extern const device_t ncr53c825a_pci_device; +extern const device_t ncr53c860_pci_device; extern const device_t ncr53c875_pci_device; diff --git a/src/sio_um8669f - Cópia.c b/src/sio_um8669f - Cópia.c deleted file mode 100644 index 4e86b6b3c..000000000 --- a/src/sio_um8669f - Cópia.c +++ /dev/null @@ -1,321 +0,0 @@ -/*um8669f : - - aa to 108 unlocks - next 108 write is register select (Cx?) - data read/write to 109 - 55 to 108 locks - -C1 -bit 7 - enable PnP registers - -PnP registers : - -07 - device : - 0 = FDC - 1 = COM1 - 2 = COM2 - 3 = LPT1 - 5 = Game port -30 - enable -60/61 - addr -70 - IRQ -74 - DMA*/ - -#include -#include -#include -#include -#include -#include "86box.h" -#include "device.h" -#include "86box_io.h" -#include "timer.h" -#include "pci.h" -#include "lpt.h" -#include "serial.h" -#include "fdd.h" -#include "fdc.h" -#include "sio.h" - - -#define DEV_FDC 0 -#define DEV_COM1 1 -#define DEV_COM2 2 -#define DEV_LPT1 3 -#define DEV_GAME 5 - -#define REG_DEVICE 0x07 -#define REG_ENABLE 0x30 -#define REG_ADDRHI 0x60 -#define REG_ADDRLO 0x61 -#define REG_IRQ 0x70 -#define REG_DMA 0x74 - - -typedef struct um8669f_t -{ - int locked, cur_reg_108, - cur_reg, cur_device, - pnp_active; - - uint8_t regs_108[256]; - - struct { - int enable; - uint16_t addr; - int irq; - int dma; - } dev[8]; - - fdc_t *fdc; - serial_t *uart[2]; -} um8669f_t; - - -static void -um8669f_pnp_write(uint16_t port, uint8_t val, void *priv) -{ - um8669f_t *dev = (um8669f_t *) priv; - - uint8_t valxor = 0; - uint8_t lpt_irq = 0xff; - - if (port == 0x279) - dev->cur_reg = val; - else { - if (dev->cur_reg == REG_DEVICE) - dev->cur_device = val & 7; - else { - switch (dev->cur_reg) { - case REG_ENABLE: - valxor = dev->dev[dev->cur_device].enable ^ val; - dev->dev[dev->cur_device].enable = val; - break; - case REG_ADDRLO: - valxor = (dev->dev[dev->cur_device].addr & 0xff) ^ val; - dev->dev[dev->cur_device].addr = (dev->dev[dev->cur_device].addr & 0xff00) | val; - break; - case REG_ADDRHI: - valxor = ((dev->dev[dev->cur_device].addr >> 8) & 0xff) ^ val; - dev->dev[dev->cur_device].addr = (dev->dev[dev->cur_device].addr & 0x00ff) | (val << 8); - break; - case REG_IRQ: - valxor = dev->dev[dev->cur_device].irq ^ val; - dev->dev[dev->cur_device].irq = val; - break; - case REG_DMA: - valxor = dev->dev[dev->cur_device].dma ^ val; - dev->dev[dev->cur_device].dma = val; - break; - default: - valxor = 0; - break; - } - - switch (dev->cur_device) { - case DEV_FDC: - if ((dev->cur_reg == REG_ENABLE) && valxor) { - fdc_remove(dev->fdc); - if (dev->dev[DEV_FDC].enable & 1) - fdc_set_base(dev->fdc, 0x03f0); - } - break; - case DEV_COM1: - if ((dev->cur_reg == REG_ENABLE) && valxor) { - serial_remove(dev->uart[0]); - if (dev->dev[DEV_COM1].enable & 1) - serial_setup(dev->uart[0], dev->dev[DEV_COM1].addr, dev->dev[DEV_COM1].irq); - } - break; - case DEV_COM2: - if ((dev->cur_reg == REG_ENABLE) && valxor) { - serial_remove(dev->uart[1]); - if (dev->dev[DEV_COM2].enable & 1) - serial_setup(dev->uart[1], dev->dev[DEV_COM2].addr, dev->dev[DEV_COM2].irq); - } - break; - case DEV_LPT1: - if ((dev->cur_reg == REG_ENABLE) && valxor) { - lpt1_remove(); - if (dev->dev[DEV_LPT1].enable & 1) - lpt1_init(dev->dev[DEV_LPT1].addr); - } - if (dev->dev[DEV_LPT1].irq <= 15) - lpt_irq = dev->dev[DEV_LPT1].irq; - lpt1_irq(lpt_irq); - break; - } - } - } -} - - -static uint8_t -um8669f_pnp_read(uint16_t port, void *priv) -{ - um8669f_t *dev = (um8669f_t *) priv; - uint8_t ret = 0xff; - - switch (dev->cur_reg) { - case REG_DEVICE: - ret = dev->cur_device; - break; - case REG_ENABLE: - ret = dev->dev[dev->cur_device].enable; - break; - case REG_ADDRLO: - ret = dev->dev[dev->cur_device].addr & 0xff; - break; - case REG_ADDRHI: - ret = dev->dev[dev->cur_device].addr >> 8; - break; - case REG_IRQ: - ret = dev->dev[dev->cur_device].irq; - break; - case REG_DMA: - ret = dev->dev[dev->cur_device].dma; - break; - } - - return ret; -} - - -void um8669f_write(uint16_t port, uint8_t val, void *priv) -{ - um8669f_t *dev = (um8669f_t *) priv; - int new_pnp_active; - - if (dev->locked) { - if ((port == 0x108) && (val == 0xaa)) - dev->locked = 0; - } else { - if (port == 0x108) { - if (val == 0x55) - dev->locked = 1; - else - dev->cur_reg_108 = val; - } else { - dev->regs_108[dev->cur_reg_108] = val; - - if (dev->cur_reg_108 == 0xc1) { - new_pnp_active = !!(dev->regs_108[0xc1] & 0x80); - if (new_pnp_active != dev->pnp_active) { - if (new_pnp_active) { - io_sethandler(0x0279, 0x0001, - NULL, NULL, NULL, um8669f_pnp_write, NULL, NULL, dev); - io_sethandler(0x0a79, 0x0001, - NULL, NULL, NULL, um8669f_pnp_write, NULL, NULL, dev); - io_sethandler(0x03e3, 0x0001, - um8669f_pnp_read, NULL, NULL, NULL, NULL, NULL, dev); - } else { - io_removehandler(0x0279, 0x0001, - NULL, NULL, NULL, um8669f_pnp_write, NULL, NULL, dev); - io_removehandler(0x0a79, 0x0001, - NULL, NULL, NULL, um8669f_pnp_write, NULL, NULL, dev); - io_removehandler(0x03e3, 0x0001, - um8669f_pnp_read, NULL, NULL, NULL, NULL, NULL, dev); - } - dev->pnp_active = new_pnp_active; - } - } - } - } -} - - -uint8_t um8669f_read(uint16_t port, void *priv) -{ - um8669f_t *dev = (um8669f_t *) priv; - uint8_t ret = 0xff; - - if (!dev->locked) { - if (port == 0x108) - ret = dev->cur_reg_108; /* ??? */ - else - ret = dev->regs_108[dev->cur_reg_108]; - } - - return ret; -} - - -void -um8669f_reset(um8669f_t *dev) -{ - fdc_reset(dev->fdc); - - serial_remove(dev->uart[0]); - serial_setup(dev->uart[0], SERIAL1_ADDR, SERIAL1_IRQ); - - serial_remove(dev->uart[1]); - serial_setup(dev->uart[1], SERIAL2_ADDR, SERIAL2_IRQ); - - lpt1_remove(); - lpt1_init(0x378); - - if (dev->pnp_active) { - io_removehandler(0x0279, 0x0001, NULL, NULL, NULL, um8669f_pnp_write, NULL, NULL, dev); - io_removehandler(0x0a79, 0x0001, NULL, NULL, NULL, um8669f_pnp_write, NULL, NULL, dev); - io_removehandler(0x03e3, 0x0001, um8669f_pnp_read, NULL, NULL, NULL, NULL, NULL, dev); - dev->pnp_active = 0; - } - - dev->locked = 1; - - dev->dev[DEV_FDC].enable = 1; - dev->dev[DEV_FDC].addr = 0x03f0; - dev->dev[DEV_FDC].irq = 6; - dev->dev[DEV_FDC].dma = 2; - - dev->dev[DEV_COM1].enable = 1; - dev->dev[DEV_COM1].addr = 0x03f8; - dev->dev[DEV_COM1].irq = 4; - - dev->dev[DEV_COM2].enable = 1; - dev->dev[DEV_COM2].addr = 0x02f8; - dev->dev[DEV_COM2].irq = 3; - - dev->dev[DEV_LPT1].enable = 1; - dev->dev[DEV_LPT1].addr = 0x0378; - dev->dev[DEV_LPT1].irq = 7; -} - - -static void -um8669f_close(void *priv) -{ - um8669f_t *dev = (um8669f_t *) priv; - - free(dev); -} - - -static void * -um8669f_init(const device_t *info) -{ - um8669f_t *dev = (um8669f_t *) malloc(sizeof(um8669f_t)); - memset(dev, 0, sizeof(um8669f_t)); - - dev->fdc = device_add(&fdc_at_device); - - dev->uart[0] = device_add_inst(&ns16550_device, 1); - dev->uart[1] = device_add_inst(&ns16550_device, 2); - - io_sethandler(0x0108, 0x0002, - um8669f_read, NULL, NULL, um8669f_write, NULL, NULL, dev); - - um8669f_reset(dev); - - return dev; -} - - -const device_t um8669f_device = { - "UMC UM8669F Super I/O", - 0, - 0, - um8669f_init, um8669f_close, NULL, - NULL, NULL, NULL, - NULL -}; diff --git a/src/sio_um8669f.c b/src/sio_um8669f.c index 462dfa09b..0d7b21511 100644 --- a/src/sio_um8669f.c +++ b/src/sio_um8669f.c @@ -80,8 +80,6 @@ um8669f_pnp_write(uint16_t port, uint8_t val, void *priv) uint8_t valxor = 0; uint8_t lpt_irq = 0xff; - pclog("Write %02X at %04X\n", val, port); - if (port == 0x279) dev->cur_reg = val; else { @@ -189,8 +187,6 @@ um8669f_write(uint16_t port, uint8_t val, void *priv) um8669f_t *dev = (um8669f_t *) priv; int new_pnp_active; - pclog("Write %02X at %04X\n", val, port); - if (dev->locked) { if ((port == 0x108) && (val == 0xaa)) dev->locked = 0; @@ -297,20 +293,6 @@ um8669f_close(void *priv) } -void -um8669f_detect_write(uint16_t port, uint8_t val, void *priv) -{ - pclog("Write %02X at %04X\n", val, port); -} - - -uint8_t -um8669f_detect_read(uint16_t port, void *priv) -{ - return 0xff; -} - - static void * um8669f_init(const device_t *info) { @@ -325,15 +307,6 @@ um8669f_init(const device_t *info) io_sethandler(0x0108, 0x0002, um8669f_read, NULL, NULL, um8669f_write, NULL, NULL, dev); - io_sethandler(0x0370, 0x0002, - um8669f_detect_read, NULL, NULL, um8669f_detect_write, NULL, NULL, dev); - io_sethandler(0x03bd, 0x0001, - um8669f_detect_read, NULL, NULL, um8669f_detect_write, NULL, NULL, dev); - io_sethandler(0x03bf, 0x0001, - um8669f_detect_read, NULL, NULL, um8669f_detect_write, NULL, NULL, dev); - io_sethandler(0x03f0, 0x0002, - um8669f_detect_read, NULL, NULL, um8669f_detect_write, NULL, NULL, dev); - um8669f_reset(dev); return dev; diff --git a/src/sound/snd_sb.c b/src/sound/snd_sb.c index 0c5a11d2d..25ed6b87d 100644 --- a/src/sound/snd_sb.c +++ b/src/sound/snd_sb.c @@ -679,13 +679,9 @@ void sb_ct1745_mixer_write(uint16_t addr, uint8_t val, void *p) sb_ct1745_mixer_t *mixer = &sb->mixer_sb16; if (!(addr & 1)) - { - pclog("CT1745: write IDX : %02X\n", val); mixer->index = val; - } else { - pclog("CT1745: write REG%02X: %02X\n", mixer->index, val); // TODO: and this? 001h: /*DESCRIPTION Contains previously selected register value. Mixer Data Register value @@ -868,10 +864,8 @@ uint8_t sb_ct1745_mixer_read(uint16_t addr, void *p) sb_ct1745_mixer_t *mixer = &sb->mixer_sb16; uint8_t temp, ret = 0xff; - if (!(addr & 1)) { + if (!(addr & 1)) ret = mixer->index; - pclog("CT1745: read IDX : %02X\n", ret); - } sb_log("sb_ct1745: received register READ: %02X\t%02X\n", mixer->index, mixer->regs[mixer->index]); @@ -1008,7 +1002,6 @@ uint8_t sb_ct1745_mixer_read(uint16_t addr, void *p) break; } - pclog("CT1745: read REG%02X: %02X\n", mixer->index, ret); return ret; } diff --git a/src/video/86Box.exe b/src/video/86Box.exe deleted file mode 100644 index 56b0faadc..000000000 Binary files a/src/video/86Box.exe and /dev/null differ diff --git a/src/video/vid_mga - Cópia.c b/src/video/vid_mga - Cópia.c deleted file mode 100644 index 4c26b8676..000000000 --- a/src/video/vid_mga - Cópia.c +++ /dev/null @@ -1,4876 +0,0 @@ -/* - * 86Box A hypervisor and IBM PC system emulator that specializes in - * running old operating systems and software designed for IBM - * PC systems and compatibles from 1981 through fairly recent - * system designs based on the PCI bus. - * - * This file is part of the 86Box distribution. - * - * Matrox MGA graphics card emulation. - * - * Version: @(#)vid_mga.c 1.0.3 2020/01/20 - * - * Author: Sarah Walker, - * Copyright 2008-2020 Sarah Walker. - */ -#include -#include -#include -#include -#include -#include "86box.h" -#include "86box_io.h" -#include "timer.h" -#include "mem.h" -#include "pci.h" -#include "rom.h" -#include "device.h" -#include "plat.h" -#include "video.h" -#include "vid_svga.h" -#include "vid_svga_render.h" - - -#define ROM_MYSTIQUE L"roms/video/matrox/MYSTIQUE.VBI" -#define ROM_MYSTIQUE_220 L"roms/video/matrox/Myst220_66-99mhz.vbi" - -#define FIFO_SIZE 65536 -#define FIFO_MASK (FIFO_SIZE - 1) -#define FIFO_ENTRY_SIZE (1 << 31) -#define FIFO_THRESHOLD 0xe000 - -#define WAKE_DELAY (100 * TIMER_USEC) /* 100us */ - -#define FIFO_ENTRIES (mystique->fifo_write_idx - mystique->fifo_read_idx) -#define FIFO_FULL ((mystique->fifo_write_idx - mystique->fifo_read_idx) >= (FIFO_SIZE-1)) -#define FIFO_EMPTY (mystique->fifo_read_idx == mystique->fifo_write_idx) - -#define FIFO_TYPE 0xff000000 -#define FIFO_ADDR 0x00ffffff - -#define DMA_POLL_TIME_US 100 /*100us*/ -#define DMA_MAX_WORDS 256 /*256 quad words per 100us poll*/ - -/*These registers are also mirrored into 0x1dxx, with the mirrored versions starting - the blitter*/ -#define REG_DWGCTL 0x1c00 -#define REG_MACCESS 0x1c04 -#define REG_MCTLWTST 0x1c08 -#define REG_ZORG 0x1c0c -#define REG_PAT0 0x1c10 -#define REG_PAT1 0x1c14 -#define REG_PLNWT 0x1c1c -#define REG_BCOL 0x1c20 -#define REG_FCOL 0x1c24 -#define REG_SRC0 0x1c30 -#define REG_SRC1 0x1c34 -#define REG_SRC2 0x1c38 -#define REG_SRC3 0x1c3c -#define REG_XYSTRT 0x1c40 -#define REG_XYEND 0x1c44 -#define REG_SHIFT 0x1c50 -#define REG_DMAPAD 0x1c54 -#define REG_SGN 0x1c58 -#define REG_LEN 0x1c5c -#define REG_AR0 0x1c60 -#define REG_AR1 0x1c64 -#define REG_AR2 0x1c68 -#define REG_AR3 0x1c6c -#define REG_AR4 0x1c70 -#define REG_AR5 0x1c74 -#define REG_AR6 0x1c78 -#define REG_CXBNDRY 0x1c80 -#define REG_FXBNDRY 0x1c84 -#define REG_YDSTLEN 0x1c88 -#define REG_PITCH 0x1c8c -#define REG_YDST 0x1c90 -#define REG_YDSTORG 0x1c94 -#define REG_YTOP 0x1c98 -#define REG_YBOT 0x1c9c -#define REG_CXLEFT 0x1ca0 -#define REG_CXRIGHT 0x1ca4 -#define REG_FXLEFT 0x1ca8 -#define REG_FXRIGHT 0x1cac -#define REG_XDST 0x1cb0 -#define REG_DR0 0x1cc0 -#define REG_DR2 0x1cc8 -#define REG_DR3 0x1ccc -#define REG_DR4 0x1cd0 -#define REG_DR6 0x1cd8 -#define REG_DR7 0x1cdc -#define REG_DR8 0x1ce0 -#define REG_DR10 0x1ce8 -#define REG_DR11 0x1cec -#define REG_DR12 0x1cf0 -#define REG_DR14 0x1cf8 -#define REG_DR15 0x1cfc - -#define REG_FIFOSTATUS 0x1e10 -#define REG_STATUS 0x1e14 -#define REG_ICLEAR 0x1e18 -#define REG_IEN 0x1e1c -#define REG_VCOUNT 0x1e20 -#define REG_DMAMAP 0x1e30 -#define REG_RST 0x1e40 -#define REG_OPMODE 0x1e54 -#define REG_PRIMADDRESS 0x1e58 -#define REG_PRIMEND 0x1e5c -#define REG_DWG_INDIR_WT 0x1e80 - -#define REG_ATTR_IDX 0x1fc0 -#define REG_ATTR_DATA 0x1fc1 -#define REG_INSTS0 0x1fc2 -#define REG_MISC 0x1fc2 -#define REG_SEQ_IDX 0x1fc4 -#define REG_SEQ_DATA 0x1fc5 -#define REG_MISCREAD 0x1fcc -#define REG_GCTL_IDX 0x1fce -#define REG_GCTL_DATA 0x1fcf -#define REG_CRTC_IDX 0x1fd4 -#define REG_CRTC_DATA 0x1fd5 -#define REG_INSTS1 0x1fda -#define REG_CRTCEXT_IDX 0x1fde -#define REG_CRTCEXT_DATA 0x1fdf -#define REG_CACHEFLUSH 0x1fff - -#define REG_TMR0 0x2c00 -#define REG_TMR1 0x2c04 -#define REG_TMR2 0x2c08 -#define REG_TMR3 0x2c0c -#define REG_TMR4 0x2c10 -#define REG_TMR5 0x2c14 -#define REG_TMR6 0x2c18 -#define REG_TMR7 0x2c1c -#define REG_TMR8 0x2c20 -#define REG_TEXORG 0x2c24 -#define REG_TEXWIDTH 0x2c28 -#define REG_TEXHEIGHT 0x2c2c -#define REG_TEXCTL 0x2c30 -#define REG_TEXTRANS 0x2c34 -#define REG_SECADDRESS 0x2c40 -#define REG_SECEND 0x2c44 -#define REG_SOFTRAP 0x2c48 - -#define REG_PALWTADD 0x3c00 -#define REG_PALDATA 0x3c01 -#define REG_PIXRDMSK 0x3c02 -#define REG_PALRDADD 0x3c03 -#define REG_X_DATAREG 0x3c0a -#define REG_CURPOSX 0x3c0c -#define REG_CURPOSY 0x3c0e - -#define REG_STATUS_VSYNCSTS (1 << 3) - -#define CRTCX_R0_STARTADD_MASK (0xf << 0) -#define CRTCX_R0_OFFSET_MASK (3 << 4) - -#define CRTCX_R1_HTOTAL8 (1 << 0) - -#define CRTCX_R2_VTOTAL10 (1 << 0) -#define CRTCX_R2_VTOTAL11 (1 << 1) -#define CRTCX_R2_VDISPEND10 (1 << 2) -#define CRTCX_R2_VBLKSTR10 (1 << 3) -#define CRTCX_R2_VBLKSTR11 (1 << 4) -#define CRTCX_R2_VSYNCSTR10 (1 << 5) -#define CRTCX_R2_VSYNCSTR11 (1 << 6) -#define CRTCX_R2_LINECOMP10 (1 << 7) - -#define CRTCX_R3_MGAMODE (1 << 7) - -#define XREG_XCURADDL 0x04 -#define XREG_XCURADDH 0x05 -#define XREG_XCURCTRL 0x06 - -#define XREG_XCURCOL0R 0x08 -#define XREG_XCURCOL0G 0x09 -#define XREG_XCURCOL0B 0x0a - -#define XREG_XCURCOL1R 0x0c -#define XREG_XCURCOL1G 0x0d -#define XREG_XCURCOL1B 0x0e - -#define XREG_XCURCOL2R 0x10 -#define XREG_XCURCOL2G 0x11 -#define XREG_XCURCOL2B 0x12 - -#define XREG_XVREFCTRL 0x18 -#define XREG_XMULCTRL 0x19 -#define XREG_XPIXCLKCTRL 0x1a -#define XREG_XGENCTRL 0x1d -#define XREG_XMISCCTRL 0x1e - -#define XREG_XGENIOCTRL 0x2a -#define XREG_XGENIODATA 0x2b - -#define XREG_XSYSPLLM 0x2c -#define XREG_XSYSPLLN 0x2d -#define XREG_XSYSPLLP 0x2e -#define XREG_XSYSPLLSTAT 0x2f - -#define XREG_XZOOMCTRL 0x38 - -#define XREG_XPIXPLLCM 0x4c -#define XREG_XPIXPLLCN 0x4d -#define XREG_XPIXPLLCP 0x4e -#define XREG_XPIXPLLSTAT 0x4f - -#define XMISCCTRL_VGA8DAC (1 << 3) - -#define XMULCTRL_DEPTH_MASK (7 << 0) -#define XMULCTRL_DEPTH_8 (0 << 0) -#define XMULCTRL_DEPTH_15 (1 << 0) -#define XMULCTRL_DEPTH_16 (2 << 0) -#define XMULCTRL_DEPTH_24 (3 << 0) -#define XMULCTRL_DEPTH_32_OVERLAYED (4 << 0) -#define XMULCTRL_DEPTH_2G8V16 (5 << 0) -#define XMULCTRL_DEPTH_G16V16 (6 << 0) -#define XMULCTRL_DEPTH_32 (7 << 0) - -#define XSYSPLLSTAT_SYSLOCK (1 << 6) - -#define XPIXPLLSTAT_SYSLOCK (1 << 6) - -#define DWGCTRL_OPCODE_MASK (0xf << 0) -#define DWGCTRL_OPCODE_LINE_OPEN (0x0 << 0) -#define DWGCTRL_OPCODE_AUTOLINE_OPEN (0x1 << 0) -#define DWGCTRL_OPCODE_AUTOLINE_CLOSE (0x3 << 0) -#define DWGCTRL_OPCODE_TRAP (0x4 << 0) -#define DWGCTRL_OPCODE_TEXTURE_TRAP (0x6 << 0) -#define DWGCTRL_OPCODE_ILOAD_HIGH (0x7 << 0) -#define DWGCTRL_OPCODE_BITBLT (0x8 << 0) -#define DWGCTRL_OPCODE_ILOAD (0x9 << 0) -#define DWGCTRL_OPCODE_IDUMP (0xa << 0) -#define DWGCTRL_OPCODE_ILOAD_SCALE (0xd << 0) -#define DWGCTRL_OPCODE_ILOAD_HIGHV (0xe << 0) -#define DWGCTRL_OPCODE_ILOAD_FILTER (0xf << 0) /* Not implemented. */ -#define DWGCTRL_ATYPE_MASK (7 << 4) -#define DWGCTRL_ATYPE_RPL (0 << 4) -#define DWGCTRL_ATYPE_RSTR (1 << 4) -#define DWGCTRL_ATYPE_ZI (3 << 4) -#define DWGCTRL_ATYPE_BLK (4 << 4) -#define DWGCTRL_ATYPE_I (7 << 4) -#define DWGCTRL_LINEAR (1 << 7) -#define DWGCTRL_ZMODE_MASK (7 << 8) -#define DWGCTRL_ZMODE_NOZCMP (0 << 8) -#define DWGCTRL_ZMODE_ZE (2 << 8) -#define DWGCTRL_ZMODE_ZNE (3 << 8) -#define DWGCTRL_ZMODE_ZLT (4 << 8) -#define DWGCTRL_ZMODE_ZLTE (5 << 8) -#define DWGCTRL_ZMODE_ZGT (6 << 8) -#define DWGCTRL_ZMODE_ZGTE (7 << 8) -#define DWGCTRL_SOLID (1 << 11) -#define DWGCTRL_ARZERO (1 << 12) -#define DWGCTRL_SGNZERO (1 << 13) -#define DWGCTRL_SHTZERO (1 << 14) -#define DWGCTRL_BOP_MASK (0xf << 16) -#define DWGCTRL_TRANS_SHIFT (20) -#define DWGCTRL_TRANS_MASK (0xf << DWGCTRL_TRANS_SHIFT) -#define DWGCTRL_BLTMOD_MASK (0xf << 25) -#define DWGCTRL_BLTMOD_BMONOLEF (0x0 << 25) -#define DWGCTRL_BLTMOD_BFCOL (0x2 << 25) -#define DWGCTRL_BLTMOD_BMONOWF (0x4 << 25) -#define DWGCTRL_BLTMOD_BU32RGB (0x7 << 25) -#define DWGCTRL_BLTMOD_BUYUV (0xe << 25) -#define DWGCTRL_BLTMOD_BU24RGB (0xf << 25) -#define DWGCTRL_PATTERN (1 << 29) -#define DWGCTRL_TRANSC (1 << 30) -#define BOP(x) ((x) << 16) - -#define MACCESS_PWIDTH_MASK (3 << 0) -#define MACCESS_PWIDTH_8 (0 << 0) -#define MACCESS_PWIDTH_16 (1 << 0) -#define MACCESS_PWIDTH_32 (2 << 0) -#define MACCESS_PWIDTH_24 (3 << 0) -#define MACCESS_TLUTLOAD (1 << 29) -#define MACCESS_NODITHER (1 << 30) -#define MACCESS_DIT555 (1 << 31) - -#define PITCH_MASK 0x7e0 -#define PITCH_YLIN (1 << 15) - -#define SGN_SDYDXL (1 << 0) -#define SGN_SCANLEFT (1 << 0) -#define SGN_SDXL (1 << 1) -#define SGN_SDY (1 << 2) -#define SGN_SDXR (1 << 5) - -#define DMA_ADDR_MASK 0xfffffffc -#define DMA_MODE_MASK 3 - -#define DMA_MODE_REG 0 -#define DMA_MODE_BLIT 1 -#define DMA_MODE_VECTOR 2 - -#define STATUS_SOFTRAPEN (1 << 0) -#define STATUS_VLINEPEN (1 << 5) -#define STATUS_DWGENGSTS (1 << 16) -#define STATUS_ENDPRDMASTS (1 << 17) - -#define ICLEAR_SOFTRAPICLR (1 << 0) -#define ICLEAR_VLINEICLR (1 << 5) - -#define IEN_SOFTRAPEN (1 << 0) - -#define TEXCTL_TEXFORMAT_MASK (7 << 0) -#define TEXCTL_TEXFORMAT_TW4 (0 << 0) -#define TEXCTL_TEXFORMAT_TW8 (1 << 0) -#define TEXCTL_TEXFORMAT_TW15 (2 << 0) -#define TEXCTL_TEXFORMAT_TW16 (3 << 0) -#define TEXCTL_TEXFORMAT_TW12 (4 << 0) -#define TEXCTL_PALSEL_MASK (0xf << 4) -#define TEXCTL_TPITCH_SHIFT (16) -#define TEXCTL_TPITCH_MASK (7 << TEXCTL_TPITCH_SHIFT) -#define TEXCTL_NPCEN (1 << 21) -#define TEXCTL_DECALCKEY (1 << 24) -#define TEXCTL_TAKEY (1 << 25) -#define TEXCTL_TAMASK (1 << 26) -#define TEXCTL_CLAMPV (1 << 27) -#define TEXCTL_CLAMPU (1 << 28) -#define TEXCTL_TMODULATE (1 << 29) -#define TEXCTL_STRANS (1 << 30) -#define TEXCTL_ITRANS (1 << 31) - -#define TEXHEIGHT_TH_MASK (0x3f << 0) -#define TEXHEIGHT_THMASK_SHIFT (18) -#define TEXHEIGHT_THMASK_MASK (0x7ff << TEXHEIGHT_THMASK_SHIFT) - -#define TEXWIDTH_TW_MASK (0x3f << 0) -#define TEXWIDTH_TWMASK_SHIFT (18) -#define TEXWIDTH_TWMASK_MASK (0x7ff << TEXWIDTH_TWMASK_SHIFT) - -#define TEXTRANS_TCKEY_MASK (0xffff) -#define TEXTRANS_TKMASK_SHIFT (16) -#define TEXTRANS_TKMASK_MASK (0xffff << TEXTRANS_TKMASK_SHIFT) - -#define DITHER_565 0 -#define DITHER_NONE_565 1 -#define DITHER_555 2 -#define DITHER_NONE_555 3 - - -enum -{ - FIFO_INVALID = (0x00 << 24), - FIFO_WRITE_CTRL_BYTE = (0x01 << 24), - FIFO_WRITE_CTRL_LONG = (0x02 << 24), - FIFO_WRITE_ILOAD_LONG = (0x03 << 24) -}; - -enum -{ - DMA_STATE_IDLE = 0, - DMA_STATE_PRI, - DMA_STATE_SEC -}; - - -typedef struct -{ - uint32_t addr_type; - uint32_t val; -} fifo_entry_t; - -typedef struct mystique_t -{ - svga_t svga; - - rom_t bios_rom; - - mem_mapping_t lfb_mapping, ctrl_mapping, - iload_mapping; - - uint8_t int_line, xcurctrl, - xsyspllm, xsysplln, xsyspllp, - xgenioctrl, xgeniodata, - xmulctrl, xgenctrl, - xmiscctrl, xpixclkctrl, - xvrefctrl, ien, dmamod, - dmadatasiz, dirdatasiz; - - uint8_t pci_regs[256], crtcext_regs[6], - xreg_regs[256], dmamap[16]; - - int card, vram_size, crtcext_idx, xreg_idx, - xzoomctrl, - pixel_count, trap_count; - - volatile int busy, blitter_submit_refcount, - blitter_submit_dma_refcount, blitter_complete_refcount, - endprdmasts_pending, softrap_pending, - fifo_read_idx, fifo_write_idx; - - uint32_t vram_mask, vram_mask_w, vram_mask_l, - lfb_base, ctrl_base, iload_base, - ma_latch_old, maccess, mctlwtst, maccess_running, - status, softrap_pending_val; - - uint64_t blitter_time, status_time; - - pc_timer_t softrap_pending_timer, wake_timer; - - fifo_entry_t fifo[FIFO_SIZE]; - - thread_t *fifo_thread; - - event_t *wake_fifo_thread, *fifo_not_full_event; - - struct - { - int m, n, p, s; - } xpixpll[3]; - - struct - { - uint8_t funcnt, stylelen, - dmamod; - - int16_t fxleft, fxright, - xdst; - - uint16_t cxleft, cxright, - length; - - int xoff, yoff, selline, ydst, - length_cur, iload_rem_count, idump_end_of_line, words, - ta_key, ta_mask, lastpix_r, lastpix_g, - lastpix_b, highv_line, beta, dither; - - int pattern[8][8]; - - uint32_t dwgctrl, dwgctrl_running, bcol, fcol, - pitch, plnwt, ybot, ydstorg, - ytop, texorg, texwidth, texheight, - texctl, textrans, zorg, ydst_lin, - src_addr, z_base, iload_rem_data, highv_data; - - uint32_t src[4], ar[7], - dr[16], tmr[9]; - - struct - { - int sdydxl, scanleft, sdxl, sdy, - sdxr; - } sgn; - } dwgreg; - - struct - { - uint8_t r, g, b; - } lut[256]; - - struct - { - uint16_t pos_x, pos_y, - addr; - uint32_t col[3]; - } cursor; - - struct - { - int pri_pos, sec_pos, iload_pos, - pri_state, sec_state, iload_state, state; - - uint32_t primaddress, primend, secaddress, secend, - pri_header, sec_header, - iload_header; - - mutex_t *lock; - } dma; -} mystique_t; - - -static const uint8_t trans_masks[16][16] = -{ - { - 1, 1, 1, 1, - 1, 1, 1, 1, - 1, 1, 1, 1, - 1, 1, 1, 1 - }, - { - 1, 0, 1, 0, - 0, 1, 0, 1, - 1, 0, 1, 0, - 0, 1, 0, 1 - }, - { - 0, 1, 0, 1, - 1, 0, 1, 0, - 0, 1, 0, 1, - 1, 0, 1, 0 - }, - { - 1, 0, 1, 0, - 0, 0, 0, 0, - 1, 0, 1, 0, - 0, 0, 0, 0 - }, - { - 0, 1, 0, 1, - 0, 0, 0, 0, - 0, 1, 0, 1, - 0, 0, 0, 0 - }, - { - 0, 0, 0, 0, - 1, 0, 1, 0, - 0, 0, 0, 0, - 1, 0, 1, 0 - }, - { - 0, 0, 0, 0, - 0, 1, 0, 1, - 0, 0, 0, 0, - 0, 1, 0, 1 - }, - { - 1, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 1, 0, - 0, 0, 0, 0 - }, - { - 0, 0, 0, 0, - 0, 1, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 1 - }, - { - 0, 0, 0, 1, - 0, 0, 0, 0, - 0, 1, 0, 0, - 0, 0, 0, 0 - }, - { - 0, 0, 0, 0, - 0, 0, 1, 0, - 0, 0, 0, 0, - 1, 0, 0, 0 - }, - { - 0, 0, 0, 0, - 1, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 1, 0 - }, - { - 0, 1, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 1, - 0, 0, 0, 0 - }, - { - 0, 0, 0, 0, - 0, 0, 0, 1, - 0, 0, 0, 0, - 0, 1, 0, 0 - }, - { - 0, 0, 1, 0, - 0, 0, 0, 0, - 1, 0, 0, 0, - 0, 0, 0, 0 - }, - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0 - } -}; - - -static int8_t dither5[256][2][2]; -static int8_t dither6[256][2][2]; - -static video_timings_t timing_matrox_mystique = {VIDEO_BUS, 4, 4, 4, 10, 10, 10}; - - -static void mystique_start_blit(mystique_t *mystique); -static void mystique_update_irqs(mystique_t *mystique); - -static void wake_fifo_thread(mystique_t *mystique); -static void wait_fifo_idle(mystique_t *mystique); -static void mystique_queue(mystique_t *mystique, uint32_t addr, uint32_t val, uint32_t type); - -static uint8_t mystique_readb_linear(uint32_t addr, void *p); -static uint16_t mystique_readw_linear(uint32_t addr, void *p); -static uint32_t mystique_readl_linear(uint32_t addr, void *p); -static void mystique_writeb_linear(uint32_t addr, uint8_t val, void *p); -static void mystique_writew_linear(uint32_t addr, uint16_t val, void *p); -static void mystique_writel_linear(uint32_t addr, uint32_t val, void *p); - -static void mystique_recalc_mapping(mystique_t *mystique); -static int mystique_line_compare(svga_t *svga); - -static uint8_t mystique_iload_read_b(uint32_t addr, void *p); -static uint32_t mystique_iload_read_l(uint32_t addr, void *p); -static void mystique_iload_write_b(uint32_t addr, uint8_t val, void *p); -static void mystique_iload_write_l(uint32_t addr, uint32_t val, void *p); - -static uint32_t blit_idump_read(mystique_t *mystique); -static void blit_iload_write(mystique_t *mystique, uint32_t data, int size); - - -void -mystique_out(uint16_t addr, uint8_t val, void *p) -{ - mystique_t *mystique = (mystique_t *)p; - svga_t *svga = &mystique->svga; - uint8_t old; - - if ((((addr&0xFFF0) == 0x3D0 || (addr&0xFFF0) == 0x3B0) && addr < 0x3de) && !(svga->miscout & 1)) - addr ^= 0x60; - - switch (addr) { - case 0x3c8: - mystique->xreg_idx = val; - break; - - case 0x3cf: - if ((svga->gdcaddr & 15) == 6 && svga->gdcreg[6] != val) { - svga->gdcreg[svga->gdcaddr & 15] = val; - mystique_recalc_mapping(mystique); - return; - } - break; - - case 0x3D4: - svga->crtcreg = val & 0x3f; - return; - case 0x3D5: - if (((svga->crtcreg & 31) < 7) && (svga->crtc[0x11] & 0x80)) - return; - if (((svga->crtcreg & 31) == 7) && (svga->crtc[0x11] & 0x80)) - val = (svga->crtc[7] & ~0x10) | (val & 0x10); - old = svga->crtc[svga->crtcreg & 0x3f]; - svga->crtc[svga->crtcreg & 31] = val; - if (old != val) { - if ((svga->crtcreg & 31) < 0xE || (svga->crtcreg & 31) > 0x10) { - svga->fullchange = changeframecount; - svga_recalctimings(svga); - } - } - break; - - case 0x3de: - mystique->crtcext_idx = val; - break; - case 0x3df: - if (mystique->crtcext_idx < 6) - mystique->crtcext_regs[mystique->crtcext_idx] = val; - if (mystique->crtcext_idx < 4) { - svga->fullchange = changeframecount; - svga_recalctimings(svga); - } - if (mystique->crtcext_idx == 3) { - if (val & CRTCX_R3_MGAMODE) - svga->fb_only = 1; - else - svga->fb_only = 0; - svga_recalctimings(svga); - } - if (mystique->crtcext_idx == 4) { - if (svga->gdcreg[6] & 0xc) { - /*64k banks*/ - svga->read_bank = (val & 0x7f) << 16; - svga->write_bank = (val & 0x7f) << 16; - } else { - /*128k banks*/ - svga->read_bank = (val & 0x7e) << 16; - svga->write_bank = (val & 0x7e) << 16; - } - } - break; - } - - svga_out(addr, val, svga); -} - - -uint8_t -mystique_in(uint16_t addr, void *p) -{ - mystique_t *mystique = (mystique_t *)p; - svga_t *svga = &mystique->svga; - uint8_t temp = 0xff; - - if ((((addr&0xFFF0) == 0x3D0 || (addr&0xFFF0) == 0x3B0) && addr < 0x3de) && !(svga->miscout & 1)) - addr ^= 0x60; - - switch (addr) { - case 0x3D4: - temp = svga->crtcreg; - break; - case 0x3D5: - temp = svga->crtc[svga->crtcreg & 0x3f]; - break; - - case 0x3df: - if (mystique->crtcext_idx < 6) - temp = mystique->crtcext_regs[mystique->crtcext_idx]; - break; - - default: - temp = svga_in(addr, svga); - break; - } - - return temp; -} - - -static int -mystique_line_compare(svga_t *svga) -{ - mystique_t *mystique = (mystique_t *)svga->p; - - mystique->status |= STATUS_VLINEPEN; - mystique_update_irqs(mystique); - - return 0; -} - - -void -mystique_recalctimings(svga_t *svga) -{ - mystique_t *mystique = (mystique_t *)svga->p; - int clk_sel = (svga->miscout >> 2) & 3; - - if (clk_sel & 2) { - int m = mystique->xpixpll[2].m; - int n = mystique->xpixpll[2].n; - int p = mystique->xpixpll[2].p; - - double fvco = 14318181.0 * (n + 1) / (m + 1); - double fo = fvco / (p + 1); - - svga->clock = (cpuclock * (float)(1ull << 32)) / fo; - } - - if (mystique->crtcext_regs[1] & CRTCX_R1_HTOTAL8) - svga->htotal += 0x100; - if (mystique->crtcext_regs[2] & CRTCX_R2_VTOTAL10) - svga->vtotal += 0x400; - if (mystique->crtcext_regs[2] & CRTCX_R2_VTOTAL11) - svga->vtotal += 0x800; - if (mystique->crtcext_regs[2] & CRTCX_R2_VDISPEND10) - svga->dispend += 0x400; - if (mystique->crtcext_regs[2] & CRTCX_R2_VBLKSTR10) - svga->vblankstart += 0x400; - if (mystique->crtcext_regs[2] & CRTCX_R2_VBLKSTR11) - svga->vblankstart += 0x800; - if (mystique->crtcext_regs[2] & CRTCX_R2_VSYNCSTR10) - svga->vsyncstart += 0x400; - if (mystique->crtcext_regs[2] & CRTCX_R2_VSYNCSTR11) - svga->vsyncstart += 0x800; - if (mystique->crtcext_regs[2] & CRTCX_R2_LINECOMP10) - svga->split += 0x400; - - svga->interlace = !!(mystique->crtcext_regs[0] & 0x80); - - if (mystique->crtcext_regs[3] & CRTCX_R3_MGAMODE) { - int row_offset = svga->crtc[0x13] | ((mystique->crtcext_regs[0] & CRTCX_R0_OFFSET_MASK) << 4); - - svga->lowres = 0; - svga->char_width = 8; - svga->hdisp = (svga->crtc[1] + 1) * 8; - svga->hdisp_time = svga->hdisp; - if (svga->interlace) - svga->rowoffset = row_offset; - else - svga->rowoffset = row_offset * 2; - svga->ma_latch = ((mystique->crtcext_regs[0] & CRTCX_R0_STARTADD_MASK) << 17) | - (svga->crtc[0xc] << 9) | (svga->crtc[0xd] << 1); - - /*Mystique, unlike most SVGA cards, allows display start to take - effect mid-screen*/ - if (svga->ma_latch != mystique->ma_latch_old) { - if (svga->interlace && svga->oddeven) - svga->ma = svga->maback = (svga->maback - (mystique->ma_latch_old << 2)) + (svga->ma_latch << 2) + (svga->rowoffset << 1); - else - svga->ma = svga->maback = (svga->maback - (mystique->ma_latch_old << 2)) + (svga->ma_latch << 2); - mystique->ma_latch_old = svga->ma_latch; - } - - switch (mystique->xmulctrl & XMULCTRL_DEPTH_MASK) { - case XMULCTRL_DEPTH_8: - case XMULCTRL_DEPTH_2G8V16: - svga->render = svga_render_8bpp_highres; - svga->bpp = 8; - break; - case XMULCTRL_DEPTH_15: - case XMULCTRL_DEPTH_G16V16: - svga->render = svga_render_15bpp_highres; - svga->bpp = 15; - break; - case XMULCTRL_DEPTH_16: - svga->render = svga_render_16bpp_highres; - svga->bpp = 16; - break; - case XMULCTRL_DEPTH_24: - svga->render = svga_render_24bpp_highres; - svga->bpp = 24; - break; - case XMULCTRL_DEPTH_32: - case XMULCTRL_DEPTH_32_OVERLAYED: - svga->render = svga_render_32bpp_highres; - svga->bpp = 32; - break; - } - - svga->line_compare = mystique_line_compare; - - mem_mapping_set_handler(&mystique->lfb_mapping, - mystique_readb_linear, mystique_readw_linear, mystique_readl_linear, - mystique_writeb_linear, mystique_writew_linear, mystique_writel_linear); - } else { - svga->line_compare = NULL; - svga->bpp = 8; - - mem_mapping_set_handler(&mystique->lfb_mapping, - svga_read_linear, svga_readw_linear, svga_readl_linear, - svga_write_linear, svga_writew_linear, svga_writel_linear); - } -} - - -static -void mystique_recalc_mapping(mystique_t *mystique) -{ - svga_t *svga = &mystique->svga; - - io_removehandler(0x03c0, 0x0020, mystique_in, NULL, NULL, mystique_out, NULL, NULL, mystique); - if ((mystique->pci_regs[PCI_REG_COMMAND] & PCI_COMMAND_IO) && (mystique->pci_regs[0x41] & 1)) - io_sethandler(0x03c0, 0x0020, mystique_in, NULL, NULL, mystique_out, NULL, NULL, mystique); - - if (!(mystique->pci_regs[PCI_REG_COMMAND] & PCI_COMMAND_MEM)) { - mem_mapping_disable(&svga->mapping); - mem_mapping_disable(&mystique->ctrl_mapping); - mem_mapping_disable(&mystique->lfb_mapping); - mem_mapping_disable(&mystique->iload_mapping); - return; - } - - if (mystique->ctrl_base) - mem_mapping_set_addr(&mystique->ctrl_mapping, mystique->ctrl_base, 0x4000); - else - mem_mapping_disable(&mystique->ctrl_mapping); - - if (mystique->lfb_base) - mem_mapping_set_addr(&mystique->lfb_mapping, mystique->lfb_base, 0x800000); - else - mem_mapping_disable(&mystique->lfb_mapping); - - if (mystique->iload_base) - mem_mapping_set_addr(&mystique->iload_mapping, mystique->iload_base, 0x800000); - else - mem_mapping_disable(&mystique->iload_mapping); - - if (mystique->pci_regs[0x41] & 1) { - switch (svga->gdcreg[6] & 0x0C) { - case 0x0: /*128k at A0000*/ - mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x10000); - svga->banked_mask = 0x1ffff; - break; - case 0x4: /*64k at A0000*/ - mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x10000); - svga->banked_mask = 0xffff; - break; - case 0x8: /*32k at B0000*/ - mem_mapping_set_addr(&svga->mapping, 0xb0000, 0x08000); - svga->banked_mask = 0x7fff; - break; - case 0xC: /*32k at B8000*/ - mem_mapping_set_addr(&svga->mapping, 0xb8000, 0x08000); - svga->banked_mask = 0x7fff; - break; - } - if (svga->gdcreg[6] & 0xc) { - /*64k banks*/ - svga->read_bank = (mystique->crtcext_regs[4] & 0x7f) << 16; - svga->write_bank = (mystique->crtcext_regs[4] & 0x7f) << 16; - } else { - /*128k banks*/ - svga->read_bank = (mystique->crtcext_regs[4] & 0x7e) << 16; - svga->write_bank = (mystique->crtcext_regs[4] & 0x7e) << 16; - } - } else - mem_mapping_disable(&svga->mapping); -} - - -static void -mystique_update_irqs(mystique_t *mystique) -{ - int irq = 0; - - if ((mystique->status & mystique->ien) & STATUS_SOFTRAPEN) - irq = 1; - - if (irq) - pci_set_irq(mystique->card, PCI_INTA); - else - pci_clear_irq(mystique->card, PCI_INTA); -} - - -#define READ8(addr, var) switch ((addr) & 3) { \ - case 0: ret = (var) & 0xff; break; \ - case 1: ret = ((var) >> 8) & 0xff; break; \ - case 2: ret = ((var) >> 16) & 0xff; break; \ - case 3: ret = ((var) >> 24) & 0xff; break; \ - } - -#define WRITE8(addr, var, val) switch ((addr) & 3) { \ - case 0: var = (var & 0xffffff00) | (val); break; \ - case 1: var = (var & 0xffff00ff) | ((val) << 8); break; \ - case 2: var = (var & 0xff00ffff) | ((val) << 16); break; \ - case 3: var = (var & 0x00ffffff) | ((val) << 24); break; \ - } - - -static uint8_t -mystique_read_xreg(mystique_t *mystique, int reg) -{ - uint8_t ret = 0xff; - - switch (reg) { - case XREG_XCURADDL: - ret = mystique->cursor.addr & 0xff; - break; - case XREG_XCURADDH: - ret = mystique->cursor.addr >> 8; - break; - case XREG_XCURCTRL: - ret = mystique->xcurctrl; - break; - - case XREG_XCURCOL0R: case XREG_XCURCOL0G: case XREG_XCURCOL0B: - READ8(reg, mystique->cursor.col[0]); - break; - case XREG_XCURCOL1R: case XREG_XCURCOL1G: case XREG_XCURCOL1B: - READ8(reg, mystique->cursor.col[1]); - break; - case XREG_XCURCOL2R: case XREG_XCURCOL2G: case XREG_XCURCOL2B: - READ8(reg, mystique->cursor.col[2]); - break; - - case XREG_XMULCTRL: - ret = mystique->xmulctrl; - break; - - case XREG_XMISCCTRL: - ret = mystique->xmiscctrl; - break; - - case XREG_XGENCTRL: - ret = mystique->xgenctrl; - break; - - case XREG_XGENIOCTRL: - ret = mystique->xgenioctrl; - break; - case XREG_XGENIODATA: - ret = mystique->xgeniodata; - break; - - case XREG_XSYSPLLM: - ret = mystique->xsyspllm; - break; - case XREG_XSYSPLLN: - ret = mystique->xsysplln; - break; - case XREG_XSYSPLLP: - ret = mystique->xsyspllp; - break; - - case XREG_XZOOMCTRL: - ret = mystique->xzoomctrl; - break; - - case XREG_XPIXCLKCTRL: - ret = mystique->xpixclkctrl; - break; - - case XREG_XSYSPLLSTAT: - ret = XSYSPLLSTAT_SYSLOCK; - break; - - case XREG_XPIXPLLSTAT: - ret = XPIXPLLSTAT_SYSLOCK; - break; - - case XREG_XPIXPLLCM: - ret = mystique->xpixpll[2].m; - break; - case XREG_XPIXPLLCN: - ret = mystique->xpixpll[2].n; - break; - case XREG_XPIXPLLCP: - ret = mystique->xpixpll[2].p | (mystique->xpixpll[2].s << 3); - break; - - case 0x00: case 0x20: case 0x3f: - ret = 0xff; - break; - - default: - if (reg >= 0x50) - ret = 0xff; - break; - } - - return ret; -} - - -static void -mystique_write_xreg(mystique_t *mystique, int reg, uint8_t val) -{ - svga_t *svga = &mystique->svga; - - switch (reg) { - case XREG_XCURADDL: - mystique->cursor.addr = (mystique->cursor.addr & 0x1f00) | val; - svga->hwcursor.addr = mystique->cursor.addr << 10; - break; - case XREG_XCURADDH: - mystique->cursor.addr = (mystique->cursor.addr & 0x00ff) | ((val & 0x1f) << 8); - svga->hwcursor.addr = mystique->cursor.addr << 10; - break; - - case XREG_XCURCTRL: - mystique->xcurctrl = val; - svga->hwcursor.ena = (val & 3) ? 1 : 0; - break; - - case XREG_XCURCOL0R: case XREG_XCURCOL0G: case XREG_XCURCOL0B: - WRITE8(reg, mystique->cursor.col[0], val); - break; - case XREG_XCURCOL1R: case XREG_XCURCOL1G: case XREG_XCURCOL1B: - WRITE8(reg, mystique->cursor.col[1], val); - break; - case XREG_XCURCOL2R: case XREG_XCURCOL2G: case XREG_XCURCOL2B: - WRITE8(reg, mystique->cursor.col[2], val); - break; - - case XREG_XMULCTRL: - mystique->xmulctrl = val; - break; - - case XREG_XMISCCTRL: - mystique->xmiscctrl = val; - svga_set_ramdac_type(svga, (val & XMISCCTRL_VGA8DAC) ? RAMDAC_8BIT : RAMDAC_6BIT); - break; - - case XREG_XGENCTRL: - mystique->xgenctrl = val; - break; - - case XREG_XVREFCTRL: - mystique->xvrefctrl = val; - break; - - case XREG_XGENIOCTRL: - mystique->xgenioctrl = val; - break; - case XREG_XGENIODATA: - mystique->xgeniodata = val; - break; - - case XREG_XSYSPLLM: - mystique->xsyspllm = val; - break; - case XREG_XSYSPLLN: - mystique->xsysplln = val; - break; - case XREG_XSYSPLLP: - mystique->xsyspllp = val; - break; - - case XREG_XZOOMCTRL: - mystique->xzoomctrl = val & 3; - break; - - case XREG_XPIXCLKCTRL: - mystique->xpixclkctrl = val; - break; - - case XREG_XPIXPLLCM: - mystique->xpixpll[2].m = val; - break; - case XREG_XPIXPLLCN: - mystique->xpixpll[2].n = val; - break; - case XREG_XPIXPLLCP: - mystique->xpixpll[2].p = val & 7; - mystique->xpixpll[2].s = (val >> 3) & 3; - break; - - case 0x00: case 0x01: case 0x02: case 0x03: - case 0x07: case 0x0b: case 0x0f: - case 0x13: case 0x14: case 0x15: case 0x16: case 0x17: - case 0x1b: case 0x1c: case 0x20: case 0x39: case 0x3b: case 0x3f: - case 0x47: case 0x4b: - break; - - default: - break; - } -} - - -static uint8_t -mystique_ctrl_read_b(uint32_t addr, void *p) -{ - mystique_t *mystique = (mystique_t *)p; - svga_t *svga = &mystique->svga; - uint8_t ret = 0xff; - int fifocount; - - switch (addr & 0x3fff) { - case REG_FIFOSTATUS: - fifocount = FIFO_SIZE - FIFO_ENTRIES; - if (fifocount > 64) - fifocount = 64; - ret = fifocount; - break; - case REG_FIFOSTATUS+1: - if (FIFO_EMPTY) - ret |= 2; - else if (FIFO_ENTRIES >= 64) - ret |= 1; - break; - case REG_FIFOSTATUS+2: case REG_FIFOSTATUS+3: - ret = 0; - break; - - case REG_STATUS: - ret = mystique->status & 0xff; - if (svga->cgastat & 8) - ret |= REG_STATUS_VSYNCSTS; - break; - case REG_STATUS+1: - ret = (mystique->status >> 8) & 0xff; - break; - case REG_STATUS+2: - ret = (mystique->status >> 16) & 0xff; - if (mystique->busy || - ((mystique->blitter_submit_refcount + mystique->blitter_submit_dma_refcount) != mystique->blitter_complete_refcount) || - !FIFO_EMPTY) - ret |= (STATUS_DWGENGSTS >> 16); - break; - case REG_STATUS+3: - ret = (mystique->status >> 24) & 0xff; - break; - - case REG_IEN: - ret = mystique->ien & 0x64; - break; - case REG_IEN+1: case REG_IEN+2: case REG_IEN+3: - ret = 0; - break; - - case REG_OPMODE: - ret = mystique->dmamod << 2; - break; - case REG_OPMODE+1: - ret = mystique->dmadatasiz; - break; - case REG_OPMODE+2: - ret = mystique->dirdatasiz; - break; - case REG_OPMODE+3: - break; - - case REG_PRIMADDRESS: case REG_PRIMADDRESS+1: case REG_PRIMADDRESS+2: case REG_PRIMADDRESS+3: - READ8(addr, mystique->dma.primaddress); - break; - case REG_PRIMEND: case REG_PRIMEND+1: case REG_PRIMEND+2: case REG_PRIMEND+3: - READ8(addr, mystique->dma.primend); - break; - - case REG_SECADDRESS: case REG_SECADDRESS+1: case REG_SECADDRESS+2: case REG_SECADDRESS+3: - READ8(addr, mystique->dma.secaddress); - break; - - case REG_VCOUNT: case REG_VCOUNT+1: case REG_VCOUNT+2: case REG_VCOUNT+3: - READ8(addr, svga->vc); - break; - - case REG_ATTR_IDX: - ret = svga_in(0x3c0, svga); - break; - case REG_ATTR_DATA: - ret = svga_in(0x3c1, svga); - break; - - case REG_INSTS0: - ret = svga_in(0x3c2, svga); - break; - - case REG_SEQ_IDX: - ret = svga_in(0x3c4, svga); - break; - case REG_SEQ_DATA: - ret = svga_in(0x3c5, svga); - break; - - case REG_MISCREAD: - ret = svga_in(0x3cc, svga); - break; - - case REG_GCTL_IDX: - ret = mystique_in(0x3ce, mystique); - break; - case REG_GCTL_DATA: - ret = mystique_in(0x3cf, mystique); - break; - - case REG_CRTC_IDX: - ret = mystique_in(0x3d4, mystique); - break; - case REG_CRTC_DATA: - ret = mystique_in(0x3d5, mystique); - break; - - case REG_INSTS1: - ret = mystique_in(0x3da, mystique); - break; - - case REG_CRTCEXT_IDX: - ret = mystique_in(0x3de, mystique); - break; - case REG_CRTCEXT_DATA: - ret = mystique_in(0x3df, mystique); - break; - - case REG_PALWTADD: - ret = svga_in(0x3c8, svga); - break; - case REG_PALDATA: - ret = svga_in(0x3c9, svga); - break; - case REG_PIXRDMSK: - ret = svga_in(0x3c6, svga); - break; - case REG_PALRDADD: - ret = svga_in(0x3c7, svga); - break; - - case REG_X_DATAREG: - ret = mystique_read_xreg(mystique, mystique->xreg_idx); - break; - - case 0x1e50: case 0x1e51: case 0x1e52: case 0x1e53: - case REG_ICLEAR: case REG_ICLEAR+1: case REG_ICLEAR+2: case REG_ICLEAR+3: - case 0x2c30: case 0x2c31: case 0x2c32: case 0x2c33: - case 0x3e08: - break; - - default: - if ((addr & 0x3fff) >= 0x2c00 && (addr & 0x3fff) < 0x2c40) - break; - if ((addr & 0x3fff) >= 0x3e00) - break; - break; - } - - return ret; -} - - -static void -mystique_accel_ctrl_write_b(uint32_t addr, uint8_t val, void *p) -{ - mystique_t *mystique = (mystique_t *)p; - int start_blit = 0; - int x; - - if ((addr & 0x300) == 0x100) { - addr &= ~0x100; - start_blit = 1; - } - - switch (addr & 0x3fff) { - case REG_MACCESS: case REG_MACCESS+1: case REG_MACCESS+2: case REG_MACCESS+3: - WRITE8(addr, mystique->maccess, val); - mystique->dwgreg.dither = mystique->maccess >> 30; - break; - - case REG_MCTLWTST: case REG_MCTLWTST+1: case REG_MCTLWTST+2: case REG_MCTLWTST+3: - WRITE8(addr, mystique->mctlwtst, val); - break; - - case REG_PAT0: case REG_PAT0+1: case REG_PAT0+2: case REG_PAT0+3: - case REG_PAT1: case REG_PAT1+1: case REG_PAT1+2: case REG_PAT1+3: - for (x = 0; x < 8; x++) - mystique->dwgreg.pattern[addr & 7][x] = val & (1 << (7-x)); - break; - - case REG_XYSTRT: case REG_XYSTRT+1: - WRITE8(addr&1, mystique->dwgreg.ar[5], val); - if (mystique->dwgreg.ar[5] & 0x8000) - mystique->dwgreg.ar[5] |= 0xffff8000; - else - mystique->dwgreg.ar[5] &= ~0xffff8000; - WRITE8(addr&1, mystique->dwgreg.xdst, val); - break; - case REG_XYSTRT+2: case REG_XYSTRT+3: - WRITE8(addr & 1, mystique->dwgreg.ar[6], val); - if (mystique->dwgreg.ar[6] & 0x8000) - mystique->dwgreg.ar[6] |= 0xffff8000; - else - mystique->dwgreg.ar[6] &= ~0xffff8000; - WRITE8(addr & 1, mystique->dwgreg.ydst, val); - mystique->dwgreg.ydst_lin = ((int32_t)(int16_t)mystique->dwgreg.ydst * (mystique->dwgreg.pitch & PITCH_MASK)) + mystique->dwgreg.ydstorg; - break; - - case REG_XYEND: case REG_XYEND+1: - WRITE8(addr&1, mystique->dwgreg.ar[0], val); - if (mystique->dwgreg.ar[0] & 0x8000) - mystique->dwgreg.ar[0] |= 0xffff8000; - else - mystique->dwgreg.ar[0] &= ~0xffff8000; - break; - case REG_XYEND+2: case REG_XYEND+3: - WRITE8(addr & 1, mystique->dwgreg.ar[2], val); - if (mystique->dwgreg.ar[2] & 0x8000) - mystique->dwgreg.ar[2] |= 0xffff8000; - else - mystique->dwgreg.ar[2] &= ~0xffff8000; - break; - - case REG_SGN: - mystique->dwgreg.sgn.sdydxl = val & SGN_SDYDXL; - mystique->dwgreg.sgn.scanleft = val & SGN_SCANLEFT; - mystique->dwgreg.sgn.sdxl = val & SGN_SDXL; - mystique->dwgreg.sgn.sdy = val & SGN_SDY; - mystique->dwgreg.sgn.sdxr = val & SGN_SDXR; - break; - case REG_SGN+1: case REG_SGN+2: case REG_SGN+3: - break; - - case REG_LEN: case REG_LEN+1: - WRITE8(addr, mystique->dwgreg.length, val); - break; - case REG_LEN+2: - break; - case REG_LEN+3: - mystique->dwgreg.beta = val >> 4; - if (!mystique->dwgreg.beta) - mystique->dwgreg.beta = 16; - break; - - case REG_CXBNDRY: case REG_CXBNDRY+1: - WRITE8(addr, mystique->dwgreg.cxleft, val); - break; - case REG_CXBNDRY+2: case REG_CXBNDRY+3: - WRITE8(addr & 1, mystique->dwgreg.cxright, val); - break; - case REG_FXBNDRY: case REG_FXBNDRY+1: - WRITE8(addr, mystique->dwgreg.fxleft, val); - break; - case REG_FXBNDRY+2: case REG_FXBNDRY+3: - WRITE8(addr & 1, mystique->dwgreg.fxright, val); - break; - - case REG_YDSTLEN: case REG_YDSTLEN+1: - WRITE8(addr, mystique->dwgreg.length, val); - /* pclog("Write YDSTLEN+%i %i\n", addr&1, mystique->dwgreg.length); */ - break; - case REG_YDSTLEN+2: - mystique->dwgreg.ydst = (mystique->dwgreg.ydst & ~0xff) | val; - if (mystique->dwgreg.pitch & PITCH_YLIN) - mystique->dwgreg.ydst_lin = (mystique->dwgreg.ydst << 5) + mystique->dwgreg.ydstorg; - else { - mystique->dwgreg.ydst_lin = ((int32_t)(int16_t)mystique->dwgreg.ydst * (mystique->dwgreg.pitch & PITCH_MASK)) + mystique->dwgreg.ydstorg; - mystique->dwgreg.selline = val & 7; - } - break; - case REG_YDSTLEN+3: - mystique->dwgreg.ydst = (mystique->dwgreg.ydst & 0xff) | (((int32_t)(int8_t)val) << 8); - if (mystique->dwgreg.pitch & PITCH_YLIN) - mystique->dwgreg.ydst_lin = (mystique->dwgreg.ydst << 5) + mystique->dwgreg.ydstorg; - else - mystique->dwgreg.ydst_lin = ((int32_t)(int16_t)mystique->dwgreg.ydst * (mystique->dwgreg.pitch & PITCH_MASK)) + mystique->dwgreg.ydstorg; - break; - - case REG_XDST: case REG_XDST+1: - WRITE8(addr & 1, mystique->dwgreg.xdst, val); - break; - case REG_XDST+2: case REG_XDST+3: - break; - - case REG_YDSTORG: case REG_YDSTORG+1: case REG_YDSTORG+2: case REG_YDSTORG+3: - WRITE8(addr, mystique->dwgreg.ydstorg, val); - mystique->dwgreg.z_base = mystique->dwgreg.ydstorg*2 + mystique->dwgreg.zorg; - break; - case REG_YTOP: case REG_YTOP+1: case REG_YTOP+2: case REG_YTOP+3: - WRITE8(addr, mystique->dwgreg.ytop, val); - break; - case REG_YBOT: case REG_YBOT+1: case REG_YBOT+2: case REG_YBOT+3: - WRITE8(addr, mystique->dwgreg.ybot, val); - break; - - case REG_CXLEFT: case REG_CXLEFT+1: - WRITE8(addr, mystique->dwgreg.cxleft, val); - break; - case REG_CXLEFT+2: case REG_CXLEFT+3: - break; - case REG_CXRIGHT: case REG_CXRIGHT+1: - WRITE8(addr, mystique->dwgreg.cxright, val); - break; - case REG_CXRIGHT+2: case REG_CXRIGHT+3: - break; - - case REG_FXLEFT: case REG_FXLEFT+1: - WRITE8(addr, mystique->dwgreg.fxleft, val); - break; - case REG_FXLEFT+2: case REG_FXLEFT+3: - break; - case REG_FXRIGHT: case REG_FXRIGHT+1: - WRITE8(addr, mystique->dwgreg.fxright, val); - break; - case REG_FXRIGHT+2: case REG_FXRIGHT+3: - break; - - case REG_SECADDRESS: case REG_SECADDRESS+1: case REG_SECADDRESS+2: case REG_SECADDRESS+3: - WRITE8(addr, mystique->dma.secaddress, val); - mystique->dma.sec_state = 0; - break; - - case REG_TMR0: case REG_TMR0+1: case REG_TMR0+2: case REG_TMR0+3: - WRITE8(addr, mystique->dwgreg.tmr[0], val); - break; - case REG_TMR1: case REG_TMR1+1: case REG_TMR1+2: case REG_TMR1+3: - WRITE8(addr, mystique->dwgreg.tmr[1], val); - break; - case REG_TMR2: case REG_TMR2+1: case REG_TMR2+2: case REG_TMR2+3: - WRITE8(addr, mystique->dwgreg.tmr[2], val); - break; - case REG_TMR3: case REG_TMR3+1: case REG_TMR3+2: case REG_TMR3+3: - WRITE8(addr, mystique->dwgreg.tmr[3], val); - break; - case REG_TMR4: case REG_TMR4+1: case REG_TMR4+2: case REG_TMR4+3: - WRITE8(addr, mystique->dwgreg.tmr[4], val); - break; - case REG_TMR5: case REG_TMR5+1: case REG_TMR5+2: case REG_TMR5+3: - WRITE8(addr, mystique->dwgreg.tmr[5], val); - break; - case REG_TMR6: case REG_TMR6+1: case REG_TMR6+2: case REG_TMR6+3: - WRITE8(addr, mystique->dwgreg.tmr[6], val); - break; - case REG_TMR7: case REG_TMR7+1: case REG_TMR7+2: case REG_TMR7+3: - WRITE8(addr, mystique->dwgreg.tmr[7], val); - break; - case REG_TMR8: case REG_TMR8+1: case REG_TMR8+2: case REG_TMR8+3: - WRITE8(addr, mystique->dwgreg.tmr[8], val); - break; - - case REG_TEXORG: case REG_TEXORG+1: case REG_TEXORG+2: case REG_TEXORG+3: - WRITE8(addr, mystique->dwgreg.texorg, val); - break; - case REG_TEXWIDTH: case REG_TEXWIDTH+1: case REG_TEXWIDTH+2: case REG_TEXWIDTH+3: - WRITE8(addr, mystique->dwgreg.texwidth, val); - break; - case REG_TEXHEIGHT: case REG_TEXHEIGHT+1: case REG_TEXHEIGHT+2: case REG_TEXHEIGHT+3: - WRITE8(addr, mystique->dwgreg.texheight, val); - break; - case REG_TEXCTL: case REG_TEXCTL+1: case REG_TEXCTL+2: case REG_TEXCTL+3: - WRITE8(addr, mystique->dwgreg.texctl, val); - mystique->dwgreg.ta_key = (mystique->dwgreg.texctl & TEXCTL_TAKEY) ? 1 : 0; - mystique->dwgreg.ta_mask = (mystique->dwgreg.texctl & TEXCTL_TAMASK) ? 1 : 0; - break; - case REG_TEXTRANS: case REG_TEXTRANS+1: case REG_TEXTRANS+2: case REG_TEXTRANS+3: - WRITE8(addr, mystique->dwgreg.textrans, val); - break; - - case 0x1c28: case 0x1c29: case 0x1c2a: case 0x1c2b: - case 0x1c2c: case 0x1c2d: case 0x1c2e: case 0x1c2f: - case 0x1cc4: case 0x1cc5: case 0x1cc6: case 0x1cc7: - case 0x1cd4: case 0x1cd5: case 0x1cd6: case 0x1cd7: - case 0x1ce4: case 0x1ce5: case 0x1ce6: case 0x1ce7: - case 0x1cf4: case 0x1cf5: case 0x1cf6: case 0x1cf7: - break; - - case REG_OPMODE: - mystique->dwgreg.dmamod = (val >> 2) & 3; - mystique->dma.iload_state = 0; - break; - - default: - if ((addr & 0x3fff) >= 0x2c4c && (addr & 0x3fff) <= 0x2cff) - break; - break; - } - - if (start_blit) - mystique_start_blit(mystique); -} - - -static void -mystique_ctrl_write_b(uint32_t addr, uint8_t val, void *p) -{ - mystique_t *mystique = (mystique_t *)p; - svga_t *svga = &mystique->svga; - - if ((addr & 0x3fff) < 0x1c00) { - mystique_iload_write_b(addr, val, p); - return; - } - if ((addr & 0x3e00) == 0x1c00 || (addr & 0x3e00) == 0x2c00) { - if ((addr & 0x300) == 0x100) - mystique->blitter_submit_refcount++; - mystique_queue(mystique, addr & 0x3fff, val, FIFO_WRITE_CTRL_BYTE); - return; - } - - switch (addr & 0x3fff) { - case REG_ICLEAR: - if (val & ICLEAR_SOFTRAPICLR) { - mystique->status &= ~STATUS_SOFTRAPEN; - mystique_update_irqs(mystique); - } - if (val & ICLEAR_VLINEICLR) { - mystique->status &= ~STATUS_VLINEPEN; - mystique_update_irqs(mystique); - } - break; - case REG_ICLEAR+1: case REG_ICLEAR+2: case REG_ICLEAR+3: - break; - - case REG_IEN: - mystique->ien = val & 0x65; - break; - case REG_IEN+1: case REG_IEN+2: case REG_IEN+3: - break; - - case REG_OPMODE: - mystique->dmamod = (val >> 2) & 3; - mystique_queue(mystique, addr & 0x3fff, val, FIFO_WRITE_CTRL_BYTE); - break; - case REG_OPMODE+1: - mystique->dmadatasiz = val & 3; - break; - case REG_OPMODE+2: - mystique->dirdatasiz = val & 3; - break; - case REG_OPMODE+3: - break; - - case REG_PRIMADDRESS: case REG_PRIMADDRESS+1: case REG_PRIMADDRESS+2: case REG_PRIMADDRESS+3: - thread_wait_mutex(mystique->dma.lock); - WRITE8(addr, mystique->dma.primaddress, val); - mystique->dma.pri_state = 0; - thread_release_mutex(mystique->dma.lock); - break; - - case REG_DMAMAP: case REG_DMAMAP+0x1: case REG_DMAMAP+0x2: case REG_DMAMAP+0x3: - case REG_DMAMAP+0x4: case REG_DMAMAP+0x5: case REG_DMAMAP+0x6: case REG_DMAMAP+0x7: - case REG_DMAMAP+0x8: case REG_DMAMAP+0x9: case REG_DMAMAP+0xa: case REG_DMAMAP+0xb: - case REG_DMAMAP+0xc: case REG_DMAMAP+0xd: case REG_DMAMAP+0xe: case REG_DMAMAP+0xf: - mystique->dmamap[addr & 0xf] = val; - break; - - case REG_RST: case REG_RST+1: case REG_RST+2: case REG_RST+3: - wait_fifo_idle(mystique); - mystique->busy = 0; - mystique->blitter_submit_refcount = 0; - mystique->blitter_submit_dma_refcount = 0; - mystique->blitter_complete_refcount = 0; - mystique->dwgreg.iload_rem_count = 0; - mystique->status = STATUS_ENDPRDMASTS; - break; - - case REG_ATTR_IDX: - svga_out(0x3c0, val, svga); - break; - case REG_ATTR_DATA: - svga_out(0x3c1, val, svga); - break; - - case REG_MISC: - svga_out(0x3c2, val, svga); - break; - - case REG_SEQ_IDX: - svga_out(0x3c4, val, svga); - break; - case REG_SEQ_DATA: - svga_out(0x3c5, val, svga); - break; - - case REG_GCTL_IDX: - mystique_out(0x3ce, val, mystique); - break; - case REG_GCTL_DATA: - mystique_out(0x3cf, val, mystique); - break; - - case REG_CRTC_IDX: - mystique_out(0x3d4, val, mystique); - break; - case REG_CRTC_DATA: - mystique_out(0x3d5, val, mystique); - break; - - case REG_CRTCEXT_IDX: - mystique_out(0x3de, val, mystique); - break; - case REG_CRTCEXT_DATA: - mystique_out(0x3df, val, mystique); - break; - - case REG_CACHEFLUSH: - break; - - case REG_PALWTADD: - svga_out(0x3c8, val, svga); - mystique->xreg_idx = val; - break; - case REG_PALDATA: - svga_out(0x3c9, val, svga); - break; - case REG_PIXRDMSK: - svga_out(0x3c6, val, svga); - break; - case REG_PALRDADD: - svga_out(0x3c7, val, svga); - break; - - case REG_X_DATAREG: - mystique_write_xreg(mystique, mystique->xreg_idx, val); - break; - - case REG_CURPOSX: case REG_CURPOSX+1: - WRITE8(addr, mystique->cursor.pos_x, val); - svga->hwcursor.x = mystique->cursor.pos_x - 64; - break; - case REG_CURPOSY: case REG_CURPOSY+1: - WRITE8(addr & 1, mystique->cursor.pos_y, val); - svga->hwcursor.y = mystique->cursor.pos_y - 64; - break; - - case 0x1e50: case 0x1e51: case 0x1e52: case 0x1e53: - case 0x3c0b: case 0x3e02: case 0x3e08: - break; - - default: - if ((addr & 0x3fff) >= 0x2c4c && (addr & 0x3fff) <= 0x2cff) - break; - if ((addr & 0x3fff) >= 0x3e00) - break; - break; - } -} - - -static uint32_t -mystique_ctrl_read_l(uint32_t addr, void *p) -{ - uint32_t ret; - - if ((addr & 0x3fff) < 0x1c00) - return mystique_iload_read_l(addr, p); - - ret = mystique_ctrl_read_b(addr, p); - ret |= mystique_ctrl_read_b(addr+1, p) << 8; - ret |= mystique_ctrl_read_b(addr+2, p) << 16; - ret |= mystique_ctrl_read_b(addr+3, p) << 24; - - return ret; -} - - -static void -mystique_accel_ctrl_write_l(uint32_t addr, uint32_t val, void *p) -{ - mystique_t *mystique = (mystique_t *)p; - int start_blit = 0; - - if ((addr & 0x300) == 0x100) { - addr &= ~0x100; - start_blit = 1; - } - - switch (addr & 0x3ffc) { - case REG_DWGCTL: - mystique->dwgreg.dwgctrl = val; - break; - - case REG_ZORG: - mystique->dwgreg.zorg = val; - mystique->dwgreg.z_base = mystique->dwgreg.ydstorg*2 + mystique->dwgreg.zorg; - break; - - case REG_PLNWT: - mystique->dwgreg.plnwt = val; - break; - - case REG_SHIFT: - mystique->dwgreg.funcnt = val & 0xff; - mystique->dwgreg.xoff = val & 7; - mystique->dwgreg.yoff = (val >> 4) & 7; - mystique->dwgreg.stylelen = (val >> 16) & 0xff; - break; - - case REG_PITCH: - mystique->dwgreg.pitch = val & 0xffff; - if (mystique->dwgreg.pitch & PITCH_YLIN) - mystique->dwgreg.ydst_lin = (mystique->dwgreg.ydst << 5) + mystique->dwgreg.ydstorg; - else - mystique->dwgreg.ydst_lin = ((int32_t)(int16_t)mystique->dwgreg.ydst * (mystique->dwgreg.pitch & PITCH_MASK)) + mystique->dwgreg.ydstorg; - break; - - case REG_YDST: - mystique->dwgreg.ydst = val & 0x3fffff; - if (mystique->dwgreg.pitch & PITCH_YLIN) { - mystique->dwgreg.ydst_lin = (mystique->dwgreg.ydst << 5) + mystique->dwgreg.ydstorg; - mystique->dwgreg.selline = val >> 29; - } else { - mystique->dwgreg.ydst_lin = ((int32_t)(int16_t)mystique->dwgreg.ydst * (mystique->dwgreg.pitch & PITCH_MASK)) + mystique->dwgreg.ydstorg; - mystique->dwgreg.selline = val & 7; - } - break; - case REG_BCOL: - mystique->dwgreg.bcol = val; - break; - case REG_FCOL: - mystique->dwgreg.fcol = val; - break; - - case REG_SRC0: - mystique->dwgreg.src[0] = val; - if ((mystique->dwgreg.dwgctrl_running & DWGCTRL_OPCODE_MASK) == DWGCTRL_OPCODE_ILOAD) - blit_iload_write(mystique, mystique->dwgreg.src[0], 32); - break; - case REG_SRC1: - mystique->dwgreg.src[1] = val; - if ((mystique->dwgreg.dwgctrl_running & DWGCTRL_OPCODE_MASK) == DWGCTRL_OPCODE_ILOAD) - blit_iload_write(mystique, mystique->dwgreg.src[1], 32); - break; - case REG_SRC2: - mystique->dwgreg.src[2] = val; - if ((mystique->dwgreg.dwgctrl_running & DWGCTRL_OPCODE_MASK) == DWGCTRL_OPCODE_ILOAD) - blit_iload_write(mystique, mystique->dwgreg.src[2], 32); - break; - case REG_SRC3: - mystique->dwgreg.src[3] = val; - if ((mystique->dwgreg.dwgctrl_running & DWGCTRL_OPCODE_MASK) == DWGCTRL_OPCODE_ILOAD) - blit_iload_write(mystique, mystique->dwgreg.src[3], 32); - break; - - case REG_DMAPAD: - if ((mystique->dwgreg.dwgctrl_running & DWGCTRL_OPCODE_MASK) == DWGCTRL_OPCODE_ILOAD) - blit_iload_write(mystique, mystique->dwgreg.src[0], 32); - break; - - case REG_AR0: - mystique->dwgreg.ar[0] = val; - break; - case REG_AR1: - mystique->dwgreg.ar[1] = val; - break; - case REG_AR2: - mystique->dwgreg.ar[2] = val; - break; - case REG_AR3: - mystique->dwgreg.ar[3] = val; - break; - case REG_AR4: - mystique->dwgreg.ar[4] = val; - break; - case REG_AR5: - mystique->dwgreg.ar[5] = val; - break; - case REG_AR6: - mystique->dwgreg.ar[6] = val; - break; - - case REG_DR0: - mystique->dwgreg.dr[0] = val; - break; - case REG_DR2: - mystique->dwgreg.dr[2] = val; - break; - case REG_DR3: - mystique->dwgreg.dr[3] = val; - break; - case REG_DR4: - mystique->dwgreg.dr[4] = val; - break; - case REG_DR6: - mystique->dwgreg.dr[6] = val; - break; - case REG_DR7: - mystique->dwgreg.dr[7] = val; - break; - case REG_DR8: - mystique->dwgreg.dr[8] = val; - break; - case REG_DR10: - mystique->dwgreg.dr[10] = val; - break; - case REG_DR11: - mystique->dwgreg.dr[11] = val; - break; - case REG_DR12: - mystique->dwgreg.dr[12] = val; - break; - case REG_DR14: - mystique->dwgreg.dr[14] = val; - break; - case REG_DR15: - mystique->dwgreg.dr[15] = val; - break; - - case REG_SECEND: - mystique->dma.secend = val; - if (mystique->dma.state != DMA_STATE_SEC && (mystique->dma.secaddress & DMA_ADDR_MASK) != (mystique->dma.secend & DMA_ADDR_MASK)) - mystique->dma.state = DMA_STATE_SEC; - break; - - case REG_SOFTRAP: - mystique->dma.state = DMA_STATE_IDLE; - mystique->endprdmasts_pending = 1; - mystique->softrap_pending_val = val; - mystique->softrap_pending = 1; - break; - - default: - mystique_accel_ctrl_write_b(addr, val & 0xff, p); - mystique_accel_ctrl_write_b(addr+1, (val >> 8) & 0xff, p); - mystique_accel_ctrl_write_b(addr+2, (val >> 16) & 0xff, p); - mystique_accel_ctrl_write_b(addr+3, (val >> 24) & 0xff, p); - break; - } - - if (start_blit) - mystique_start_blit(mystique); -} - - -static void -mystique_ctrl_write_l(uint32_t addr, uint32_t val, void *p) -{ - mystique_t *mystique = (mystique_t *)p; - uint32_t reg_addr; - - if ((addr & 0x3fff) < 0x1c00) { - mystique_iload_write_l(addr, val, p); - return; - } - - if ((addr & 0x3e00) == 0x1c00 || (addr & 0x3e00) == 0x2c00) { - if ((addr & 0x300) == 0x100) - mystique->blitter_submit_refcount++; - mystique_queue(mystique, addr & 0x3fff, val, FIFO_WRITE_CTRL_LONG); - return; - } - - switch (addr & 0x3ffc) { - case REG_PRIMEND: - thread_wait_mutex(mystique->dma.lock); - mystique->dma.primend = val; - if (mystique->dma.state == DMA_STATE_IDLE && (mystique->dma.primaddress & DMA_ADDR_MASK) != (mystique->dma.primend & DMA_ADDR_MASK)) { - mystique->endprdmasts_pending = 0; - mystique->status &= ~STATUS_ENDPRDMASTS; - - mystique->dma.state = DMA_STATE_PRI; - mystique->dma.pri_state = 0; - wake_fifo_thread(mystique); - } - thread_release_mutex(mystique->dma.lock); - break; - - case REG_DWG_INDIR_WT: case REG_DWG_INDIR_WT+0x04: case REG_DWG_INDIR_WT+0x08: case REG_DWG_INDIR_WT+0x0c: - case REG_DWG_INDIR_WT+0x10: case REG_DWG_INDIR_WT+0x14: case REG_DWG_INDIR_WT+0x18: case REG_DWG_INDIR_WT+0x1c: - case REG_DWG_INDIR_WT+0x20: case REG_DWG_INDIR_WT+0x24: case REG_DWG_INDIR_WT+0x28: case REG_DWG_INDIR_WT+0x2c: - case REG_DWG_INDIR_WT+0x30: case REG_DWG_INDIR_WT+0x34: case REG_DWG_INDIR_WT+0x38: case REG_DWG_INDIR_WT+0x3c: - reg_addr = (mystique->dmamap[(addr >> 2) & 0xf] & 0x7f) << 2; - if (mystique->dmamap[(addr >> 2) & 0xf] & 0x80) - reg_addr += 0x2c00; - else - reg_addr += 0x1c00; - - if ((reg_addr & 0x300) == 0x100) - mystique->blitter_submit_refcount++; - - mystique_queue(mystique, reg_addr, val, FIFO_WRITE_CTRL_LONG); - break; - - default: - mystique_ctrl_write_b(addr, val & 0xff, p); - mystique_ctrl_write_b(addr+1, (val >> 8) & 0xff, p); - mystique_ctrl_write_b(addr+2, (val >> 16) & 0xff, p); - mystique_ctrl_write_b(addr+3, (val >> 24) & 0xff, p); - break; - } -} - - -static uint8_t -mystique_iload_read_b(uint32_t addr, void *p) -{ - mystique_t *mystique = (mystique_t *)p; - - wait_fifo_idle(mystique); - - if (!mystique->busy) - return 0xff; - - return blit_idump_read(mystique); -} - - -static uint32_t -mystique_iload_read_l(uint32_t addr, void *p) -{ - mystique_t *mystique = (mystique_t *)p; - - wait_fifo_idle(mystique); - - if (!mystique->busy) - return 0xffffffff; - - mystique->dwgreg.words++; - return blit_idump_read(mystique); -} - - -static void -mystique_iload_write_b(uint32_t addr, uint8_t val, void *p) -{ - -} - - -static void -mystique_iload_write_l(uint32_t addr, uint32_t val, void *p) -{ - mystique_t *mystique = (mystique_t *)p; - - mystique_queue(mystique, 0, val, FIFO_WRITE_ILOAD_LONG); -} - -static void -mystique_accel_iload_write_l(uint32_t addr, uint32_t val, void *p) -{ - mystique_t *mystique = (mystique_t *)p; - - switch (mystique->dwgreg.dmamod) { - case DMA_MODE_REG: - if (mystique->dma.iload_state == 0) { - mystique->dma.iload_header = val; - mystique->dma.iload_state = 1; - } else { - uint32_t reg_addr = (mystique->dma.iload_header & 0x7f) << 2; - if (mystique->dma.iload_header & 0x80) - reg_addr += 0x2c00; - else - reg_addr += 0x1c00; - - if ((reg_addr & 0x300) == 0x100) - mystique->blitter_submit_dma_refcount++; - mystique_accel_ctrl_write_l(reg_addr, val, mystique); - - mystique->dma.iload_header >>= 8; - mystique->dma.iload_state = (mystique->dma.iload_state == 4) ? 0 : (mystique->dma.iload_state+1); - } - break; - - case DMA_MODE_BLIT: - if (!mystique->busy) - fatal("mystique_iload_write_l: !busy\n"); - blit_iload_write(mystique, val, 32); - break; - - /* default: - pclog("ILOAD write DMAMOD %i\n", mystique->dwgreg.dmamod); */ - } -} - -static uint8_t mystique_readb_linear(uint32_t addr, void *p) -{ - svga_t *svga = (svga_t *)p; - - egareads++; - - sub_cycles(video_timing_read_b); - - addr &= svga->decode_mask; - if (addr >= svga->vram_max) - return 0xff; - - return svga->vram[addr & svga->vram_mask]; -} -static uint16_t mystique_readw_linear(uint32_t addr, void *p) -{ - svga_t *svga = (svga_t *)p; - - egareads += 2; - - sub_cycles(video_timing_read_w); - - addr &= svga->decode_mask; - if (addr >= svga->vram_max) - return 0xffff; - - return *(uint16_t *)&svga->vram[addr & svga->vram_mask]; -} -static uint32_t mystique_readl_linear(uint32_t addr, void *p) -{ - svga_t *svga = (svga_t *)p; - - egareads += 4; - - sub_cycles(video_timing_read_l); - - addr &= svga->decode_mask; - if (addr >= svga->vram_max) - return 0xffffffff; - - return *(uint32_t *)&svga->vram[addr & svga->vram_mask]; -} - -static void mystique_writeb_linear(uint32_t addr, uint8_t val, void *p) -{ - svga_t *svga = (svga_t *)p; - - egawrites++; - - sub_cycles(video_timing_write_b); - - addr &= svga->decode_mask; - if (addr >= svga->vram_max) - return; - addr &= svga->vram_mask; - svga->changedvram[addr >> 12] = changeframecount; - svga->vram[addr] = val; -} -static void mystique_writew_linear(uint32_t addr, uint16_t val, void *p) -{ - svga_t *svga = (svga_t *)p; - - egawrites += 2; - - sub_cycles(video_timing_write_w); - - addr &= svga->decode_mask; - if (addr >= svga->vram_max) - return; - addr &= svga->vram_mask; - svga->changedvram[addr >> 12] = changeframecount; - *(uint16_t *)&svga->vram[addr] = val; -} -static void mystique_writel_linear(uint32_t addr, uint32_t val, void *p) -{ - svga_t *svga = (svga_t *)p; - - egawrites += 4; - - sub_cycles(video_timing_write_l); - - addr &= svga->decode_mask; - if (addr >= svga->vram_max) - return; - addr &= svga->vram_mask; - svga->changedvram[addr >> 12] = changeframecount; - *(uint32_t *)&svga->vram[addr] = val; -} - - -static void -run_dma(mystique_t *mystique) -{ - int words_transferred = 0; - - thread_wait_mutex(mystique->dma.lock); - - if (mystique->dma.state == DMA_STATE_IDLE) { - thread_release_mutex(mystique->dma.lock); - return; - } - - while (words_transferred < DMA_MAX_WORDS && mystique->dma.state != DMA_STATE_IDLE) { - switch (mystique->dma.state) { - case DMA_STATE_PRI: - switch (mystique->dma.primaddress & DMA_MODE_MASK) { - case DMA_MODE_REG: - if (mystique->dma.pri_state == 0) { - mystique->dma.pri_header = *(uint32_t *)&ram[mystique->dma.primaddress & DMA_ADDR_MASK]; - mystique->dma.primaddress += 4; - } - - if ((mystique->dma.pri_header & 0xff) != 0x15) { - uint32_t val = *(uint32_t *)&ram[mystique->dma.primaddress & DMA_ADDR_MASK]; - uint32_t reg_addr; - - mystique->dma.primaddress += 4; - - reg_addr = (mystique->dma.pri_header & 0x7f) << 2; - if (mystique->dma.pri_header & 0x80) - reg_addr += 0x2c00; - else - reg_addr += 0x1c00; - - if ((reg_addr & 0x300) == 0x100) - mystique->blitter_submit_dma_refcount++; - - mystique_accel_ctrl_write_l(reg_addr, val, mystique); - } - - mystique->dma.pri_header >>= 8; - mystique->dma.pri_state = (mystique->dma.pri_state + 1) & 3; - - words_transferred++; - if (mystique->dma.state == DMA_STATE_SEC) - mystique->dma.pri_state = 0; - else if ((mystique->dma.primaddress & DMA_ADDR_MASK) == (mystique->dma.primend & DMA_ADDR_MASK)) { - mystique->endprdmasts_pending = 1; - mystique->dma.state = DMA_STATE_IDLE; - } - break; - - default: - fatal("DMA_STATE_PRI: mode %i\n", mystique->dma.primaddress & DMA_MODE_MASK); - } - break; - - case DMA_STATE_SEC: - switch (mystique->dma.secaddress & DMA_MODE_MASK) { - case DMA_MODE_REG: - if (mystique->dma.sec_state == 0) { - mystique->dma.sec_header = *(uint32_t *)&ram[mystique->dma.secaddress & DMA_ADDR_MASK]; - mystique->dma.secaddress += 4; - } - - uint32_t val = *(uint32_t *)&ram[mystique->dma.secaddress & DMA_ADDR_MASK]; - uint32_t reg_addr; - - mystique->dma.secaddress += 4; - - reg_addr = (mystique->dma.sec_header & 0x7f) << 2; - if (mystique->dma.sec_header & 0x80) - reg_addr += 0x2c00; - else - reg_addr += 0x1c00; - - if ((reg_addr & 0x300) == 0x100) - mystique->blitter_submit_dma_refcount++; - - mystique_accel_ctrl_write_l(reg_addr, val, mystique); - - mystique->dma.sec_header >>= 8; - mystique->dma.sec_state = (mystique->dma.sec_state + 1) & 3; - - words_transferred++; - if ((mystique->dma.secaddress & DMA_ADDR_MASK) == (mystique->dma.secend & DMA_ADDR_MASK)) { - if ((mystique->dma.primaddress & DMA_ADDR_MASK) == (mystique->dma.primend & DMA_ADDR_MASK)) { - mystique->endprdmasts_pending = 1; - mystique->dma.state = DMA_STATE_IDLE; - } else - mystique->dma.state = DMA_STATE_PRI; - } - break; - - case DMA_MODE_BLIT: { - uint32_t val = *(uint32_t *)&ram[mystique->dma.secaddress & DMA_ADDR_MASK]; - mystique->dma.secaddress += 4; - - if (!mystique->busy) - fatal("mystique_iload_write_l: !busy\n"); - - blit_iload_write(mystique, val, 32); - - words_transferred++; - if ((mystique->dma.secaddress & DMA_ADDR_MASK) == (mystique->dma.secend & DMA_ADDR_MASK)) { - if ((mystique->dma.primaddress & DMA_ADDR_MASK) == (mystique->dma.primend & DMA_ADDR_MASK)) { - mystique->endprdmasts_pending = 1; - mystique->dma.state = DMA_STATE_IDLE; - } else - mystique->dma.state = DMA_STATE_PRI; - } - } break; - - default: - fatal("DMA_STATE_SEC: mode %i\n", mystique->dma.secaddress & DMA_MODE_MASK); - } - break; - } - } - - thread_release_mutex(mystique->dma.lock); -} - - -static void -fifo_thread(void *p) -{ - mystique_t *mystique = (mystique_t *)p; - - while (1) { - thread_set_event(mystique->fifo_not_full_event); - thread_wait_event(mystique->wake_fifo_thread, -1); - thread_reset_event(mystique->wake_fifo_thread); - - while (!FIFO_EMPTY || mystique->dma.state != DMA_STATE_IDLE) { - int words_transferred = 0; - - while (!FIFO_EMPTY && words_transferred < 100) { - fifo_entry_t *fifo = &mystique->fifo[mystique->fifo_read_idx & FIFO_MASK]; - - switch (fifo->addr_type & FIFO_TYPE) { - case FIFO_WRITE_CTRL_BYTE: - mystique_accel_ctrl_write_b(fifo->addr_type & FIFO_ADDR, fifo->val, mystique); - break; - case FIFO_WRITE_CTRL_LONG: - mystique_accel_ctrl_write_l(fifo->addr_type & FIFO_ADDR, fifo->val, mystique); - break; - case FIFO_WRITE_ILOAD_LONG: - mystique_accel_iload_write_l(fifo->addr_type & FIFO_ADDR, fifo->val, mystique); - break; - } - - fifo->addr_type = FIFO_INVALID; - mystique->fifo_read_idx++; - - if (FIFO_ENTRIES > FIFO_THRESHOLD) - thread_set_event(mystique->fifo_not_full_event); - - words_transferred++; - } - - /*Only run DMA once the FIFO is empty. Required by - Screamer 2 / Rally which will incorrectly clip an ILOAD - if DMA runs ahead*/ - if (!words_transferred) - run_dma(mystique); - } - } -} - - -static void -wake_fifo_thread(mystique_t *mystique) -{ - if (!timer_is_enabled(&mystique->wake_timer)) { - /* Don't wake FIFO thread immediately - if we do that it will probably - process one word and go back to sleep, requiring it to be woken on - almost every write. Instead, wait a short while so that the CPU - emulation writes more data so we have more batched-up work. */ - timer_set_delay_u64(&mystique->wake_timer, WAKE_DELAY); - } -} - - -static void -wake_fifo_thread_now(mystique_t *mystique) -{ - thread_set_event(mystique->wake_fifo_thread); -} - - -static void -mystique_wake_timer(void *p) -{ - mystique_t *mystique = (mystique_t *)p; - - thread_set_event(mystique->wake_fifo_thread); /*Wake up FIFO thread if moving from idle*/ -} - - -static void -wait_fifo_idle(mystique_t *mystique) -{ - while (!FIFO_EMPTY) { - wake_fifo_thread_now(mystique); - thread_wait_event(mystique->fifo_not_full_event, 1); - } -} - - -/*IRQ code (PCI & PIC) is not currently thread safe. SOFTRAP IRQ requests must - therefore be submitted from the main emulation thread, in this case via a timer - callback. End-of-DMA status is also deferred here to prevent races between - SOFTRAP IRQs and code reading the status register. Croc will get into an IRQ - loop and triple fault if the ENDPRDMASTS flag is seen before the IRQ is taken*/ -static void mystique_softrap_pending_timer(void *p) -{ - mystique_t *mystique = (mystique_t *)p; - - timer_advance_u64(&mystique->softrap_pending_timer, TIMER_USEC * 100); - - if (mystique->endprdmasts_pending) { - mystique->endprdmasts_pending = 0; - mystique->status |= STATUS_ENDPRDMASTS; - } - if (mystique->softrap_pending) { - mystique->softrap_pending = 0; - - mystique->dma.secaddress = mystique->softrap_pending_val; - mystique->status |= STATUS_SOFTRAPEN; - mystique_update_irqs(mystique); - } -} - - -static -void mystique_queue(mystique_t *mystique, uint32_t addr, uint32_t val, uint32_t type) -{ - fifo_entry_t *fifo = &mystique->fifo[mystique->fifo_write_idx & FIFO_MASK]; - - if (FIFO_FULL) { - thread_reset_event(mystique->fifo_not_full_event); - if (FIFO_FULL) - thread_wait_event(mystique->fifo_not_full_event, -1); /* Wait for room in ringbuffer */ - } - - fifo->val = val; - fifo->addr_type = (addr & FIFO_ADDR) | type; - - mystique->fifo_write_idx++; - - if (FIFO_ENTRIES > FIFO_THRESHOLD || FIFO_ENTRIES < 8) - wake_fifo_thread(mystique); -} - - -static uint32_t -bitop(uint32_t src, uint32_t dst, uint32_t dwgctrl) -{ - switch (dwgctrl & DWGCTRL_BOP_MASK) { - case BOP(0x0): return 0; - case BOP(0x1): return ~(dst | src); - case BOP(0x2): return dst & ~src; - case BOP(0x3): return ~src; - case BOP(0x4): return ~dst & src; - case BOP(0x5): return ~dst; - case BOP(0x6): return dst ^ src; - case BOP(0x7): return ~(dst & src); - case BOP(0x8): return dst & src; - case BOP(0x9): return ~(dst ^ src); - case BOP(0xa): return dst; - case BOP(0xb): return dst | ~src; - case BOP(0xc): return src; - case BOP(0xd): return ~dst | src; - case BOP(0xe): return dst | src; - case BOP(0xf): return ~0; - } - - return 0; -} - - -static uint16_t -dither(mystique_t *mystique, int r, int g, int b, int x, int y) -{ - switch (mystique->dwgreg.dither) { - case DITHER_NONE_555: - return (b >> 3) | ((g >> 3) << 5) | ((r >> 3) << 10); - - case DITHER_NONE_565: - return (b >> 3) | ((g >> 2) << 5) | ((r >> 3) << 11); - - case DITHER_555: - return dither5[b][y][x] | (dither5[g][y][x] << 5) | (dither5[r][y][x] << 10); - - case DITHER_565: - default: - return dither5[b][y][x] | (dither6[g][y][x] << 5) | (dither5[r][y][x] << 11); - } -} - - -static uint32_t -blit_idump_idump(mystique_t *mystique) -{ - svga_t *svga = &mystique->svga; - uint64_t val64 = 0; - uint32_t val = 0; - int count = 0; - - switch (mystique->dwgreg.dwgctrl_running & DWGCTRL_ATYPE_MASK) { - case DWGCTRL_ATYPE_RPL: - switch (mystique->dwgreg.dwgctrl_running & DWGCTRL_BLTMOD_MASK) { - case DWGCTRL_BLTMOD_BU32RGB: - switch (mystique->maccess_running & MACCESS_PWIDTH_MASK) { - case MACCESS_PWIDTH_8: - while (count < 32) { - val |= (svga->vram[mystique->dwgreg.src_addr & mystique->vram_mask] << count); - - if (mystique->dwgreg.src_addr == mystique->dwgreg.ar[0]) { - mystique->dwgreg.ar[0] += mystique->dwgreg.ar[5]; - mystique->dwgreg.ar[3] += mystique->dwgreg.ar[5]; - mystique->dwgreg.src_addr = mystique->dwgreg.ar[3]; - } else - mystique->dwgreg.src_addr++; - - if (mystique->dwgreg.xdst == mystique->dwgreg.fxright) { - mystique->dwgreg.xdst = mystique->dwgreg.fxleft; - mystique->dwgreg.length_cur--; - if (!mystique->dwgreg.length_cur) { - mystique->busy = 0; - mystique->blitter_complete_refcount++; - break; - } - break; - } else - mystique->dwgreg.xdst = (mystique->dwgreg.xdst + 1) & 0xffff; - - count += 8; - } - break; - - case MACCESS_PWIDTH_16: - while (count < 32) { - val |= (((uint16_t *)svga->vram)[mystique->dwgreg.src_addr & mystique->vram_mask_w] << count); - - if (mystique->dwgreg.src_addr == mystique->dwgreg.ar[0]) { - mystique->dwgreg.ar[0] += mystique->dwgreg.ar[5]; - mystique->dwgreg.ar[3] += mystique->dwgreg.ar[5]; - mystique->dwgreg.src_addr = mystique->dwgreg.ar[3]; - } else - mystique->dwgreg.src_addr++; - - if (mystique->dwgreg.xdst == mystique->dwgreg.fxright) { - mystique->dwgreg.xdst = mystique->dwgreg.fxleft; - mystique->dwgreg.length_cur--; - if (!mystique->dwgreg.length_cur) { - mystique->busy = 0; - mystique->blitter_complete_refcount++; - break; - } - break; - } else - mystique->dwgreg.xdst = (mystique->dwgreg.xdst + 1) & 0xffff; - - count += 16; - } - break; - - case MACCESS_PWIDTH_24: - if (mystique->dwgreg.idump_end_of_line) { - mystique->dwgreg.idump_end_of_line = 0; - val = mystique->dwgreg.iload_rem_data; - mystique->dwgreg.iload_rem_count = 0; - mystique->dwgreg.iload_rem_data = 0; - if (!mystique->dwgreg.length_cur) { - mystique->busy = 0; - mystique->blitter_complete_refcount++; - } - break; - } - - count += mystique->dwgreg.iload_rem_count; - val64 = mystique->dwgreg.iload_rem_data; - - while ((count < 32) && !mystique->dwgreg.idump_end_of_line) { - val64 |= (uint64_t)((*(uint32_t *)&svga->vram[(mystique->dwgreg.src_addr * 3) & mystique->vram_mask]) & 0xffffff) << count; - - if (mystique->dwgreg.src_addr == mystique->dwgreg.ar[0]) { - mystique->dwgreg.ar[0] += mystique->dwgreg.ar[5]; - mystique->dwgreg.ar[3] += mystique->dwgreg.ar[5]; - mystique->dwgreg.src_addr = mystique->dwgreg.ar[3]; - } else - mystique->dwgreg.src_addr++; - - if (mystique->dwgreg.xdst == mystique->dwgreg.fxright) { - mystique->dwgreg.xdst = mystique->dwgreg.fxleft; - mystique->dwgreg.length_cur--; - if (!mystique->dwgreg.length_cur) { - if (count > 8) - mystique->dwgreg.idump_end_of_line = 1; - else { - count = 32; - mystique->busy = 0; - mystique->blitter_complete_refcount++; - } - break; - } - if (!(mystique->dwgreg.dwgctrl_running & DWGCTRL_LINEAR)) { - if (count > 8) - mystique->dwgreg.idump_end_of_line = 1; - else { - count = 32; - break; - } - } - } else - mystique->dwgreg.xdst = (mystique->dwgreg.xdst + 1) & 0xffff; - - count += 24; - } - if (count > 32) - mystique->dwgreg.iload_rem_count = count - 32; - else - mystique->dwgreg.iload_rem_count = 0; - mystique->dwgreg.iload_rem_data = (uint32_t)(val64 >> 32); - val = val64 & 0xffffffff; - break; - - case MACCESS_PWIDTH_32: - val = (((uint32_t *)svga->vram)[mystique->dwgreg.src_addr & mystique->vram_mask_l] << count); - - if (mystique->dwgreg.src_addr == mystique->dwgreg.ar[0]) { - mystique->dwgreg.ar[0] += mystique->dwgreg.ar[5]; - mystique->dwgreg.ar[3] += mystique->dwgreg.ar[5]; - mystique->dwgreg.src_addr = mystique->dwgreg.ar[3]; - } else - mystique->dwgreg.src_addr++; - - if (mystique->dwgreg.xdst == mystique->dwgreg.fxright) { - mystique->dwgreg.xdst = mystique->dwgreg.fxleft; - mystique->dwgreg.length_cur--; - if (!mystique->dwgreg.length_cur) { - mystique->busy = 0; - mystique->blitter_complete_refcount++; - break; - } - break; - } else - mystique->dwgreg.xdst = (mystique->dwgreg.xdst + 1) & 0xffff; - break; - - default: - fatal("IDUMP DWGCTRL_BLTMOD_BU32RGB %x %08x\n", mystique->maccess_running & MACCESS_PWIDTH_MASK, mystique->maccess_running); - } - break; - - default: - fatal("IDUMP DWGCTRL_ATYPE_RPL %08x %08x\n", mystique->dwgreg.dwgctrl_running & DWGCTRL_BLTMOD_MASK, mystique->dwgreg.dwgctrl_running); - break; - } - break; - - default: - fatal("Unknown IDUMP atype %03x %08x\n", mystique->dwgreg.dwgctrl_running & DWGCTRL_ATYPE_MASK, mystique->dwgreg.dwgctrl_running); - } - - return val; -} - - -static uint32_t -blit_idump_read(mystique_t *mystique) -{ - uint32_t ret = 0xffffffff; - - switch (mystique->dwgreg.dwgctrl_running & DWGCTRL_OPCODE_MASK) { - case DWGCTRL_OPCODE_IDUMP: - ret = blit_idump_idump(mystique); - break; - - default: - /* pclog("blit_idump_read: bad opcode %08x\n", mystique->dwgreg.dwgctrl_running); */ - break; - } - - return ret; -} - - -static void -blit_iload_iload(mystique_t *mystique, uint32_t data, int size) -{ - svga_t *svga = &mystique->svga; - uint32_t src, dst; - uint64_t data64; - int min_size = 8; - uint32_t bltckey = mystique->dwgreg.fcol, bltcmsk = mystique->dwgreg.bcol; - const int transc = mystique->dwgreg.dwgctrl_running & DWGCTRL_TRANSC; - const int trans_sel = (mystique->dwgreg.dwgctrl_running & DWGCTRL_TRANS_MASK) >> DWGCTRL_TRANS_SHIFT; - uint8_t const * const trans = &trans_masks[trans_sel][(mystique->dwgreg.selline & 3) * 4]; - - switch (mystique->maccess_running & MACCESS_PWIDTH_MASK) { - case MACCESS_PWIDTH_8: - bltckey &= 0xff; - bltcmsk &= 0xff; - break; - case MACCESS_PWIDTH_16: - bltckey &= 0xffff; - bltcmsk &= 0xffff; - break; - } - - mystique->dwgreg.words++; - switch (mystique->dwgreg.dwgctrl_running & DWGCTRL_ATYPE_MASK) { - case DWGCTRL_ATYPE_RPL: - if (mystique->maccess_running & MACCESS_TLUTLOAD) { - while ((mystique->dwgreg.length_cur > 0) && (size >= 16)) { - uint16_t src = data & 0xffff; - - mystique->lut[mystique->dwgreg.ydst & 0xff].r = (src >> 11) << 3; - mystique->lut[mystique->dwgreg.ydst & 0xff].g = ((src >> 5) & 0x3f) << 2; - mystique->lut[mystique->dwgreg.ydst & 0xff].b = (src & 0x1f) << 3; - mystique->dwgreg.ydst++; - mystique->dwgreg.length_cur--; - data >>= 16; - size -= 16; - } - - if (!mystique->dwgreg.length_cur) { - mystique->busy = 0; - mystique->blitter_complete_refcount++; - } - break; - } - case DWGCTRL_ATYPE_RSTR: - case DWGCTRL_ATYPE_BLK: - switch (mystique->dwgreg.dwgctrl_running & DWGCTRL_BLTMOD_MASK) { - case DWGCTRL_BLTMOD_BFCOL: - size += mystique->dwgreg.iload_rem_count; - data64 = mystique->dwgreg.iload_rem_data | ((uint64_t)data << mystique->dwgreg.iload_rem_count); - - switch (mystique->maccess_running & MACCESS_PWIDTH_MASK) { - case MACCESS_PWIDTH_8: - min_size = 8; - break; - case MACCESS_PWIDTH_16: - min_size = 16; - break; - case MACCESS_PWIDTH_24: - min_size = 24; - break; - case MACCESS_PWIDTH_32: - min_size = 32; - break; - } - - while (size >= min_size) { - int draw = (!transc || (data & bltcmsk) != bltckey) && trans[mystique->dwgreg.xdst & 3]; - - switch (mystique->maccess_running & MACCESS_PWIDTH_MASK) { - case MACCESS_PWIDTH_8: - if (mystique->dwgreg.xdst >= mystique->dwgreg.cxleft && mystique->dwgreg.xdst <= mystique->dwgreg.cxright && - mystique->dwgreg.ydst_lin >= mystique->dwgreg.ytop && mystique->dwgreg.ydst_lin <= mystique->dwgreg.ybot && draw) { - dst = svga->vram[(mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask]; - - dst = bitop(data & 0xff, dst, mystique->dwgreg.dwgctrl_running); - svga->vram[(mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask] = dst; - svga->changedvram[((mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask) >> 12] = changeframecount; - } - - data >>= 8; - size -= 8; - break; - - case MACCESS_PWIDTH_16: - if (mystique->dwgreg.xdst >= mystique->dwgreg.cxleft && mystique->dwgreg.xdst <= mystique->dwgreg.cxright && - mystique->dwgreg.ydst_lin >= mystique->dwgreg.ytop && mystique->dwgreg.ydst_lin <= mystique->dwgreg.ybot && draw) { - dst = ((uint16_t *)svga->vram)[(mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask_w]; - - dst = bitop(data & 0xffff, dst, mystique->dwgreg.dwgctrl_running); - ((uint16_t *)svga->vram)[(mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask_w] = dst; - svga->changedvram[((mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask_w) >> 11] = changeframecount; - } - - data >>= 16; - size -= 16; - break; - - case MACCESS_PWIDTH_24: - if (mystique->dwgreg.xdst >= mystique->dwgreg.cxleft && mystique->dwgreg.xdst <= mystique->dwgreg.cxright && - mystique->dwgreg.ydst_lin >= mystique->dwgreg.ytop && mystique->dwgreg.ydst_lin <= mystique->dwgreg.ybot) { - uint32_t old_dst = *((uint32_t *)&svga->vram[((mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) * 3) & mystique->vram_mask]); - - dst = bitop(data64, old_dst, mystique->dwgreg.dwgctrl_running); - *((uint32_t *)&svga->vram[((mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) * 3) & mystique->vram_mask]) = (dst & 0xffffff) | (old_dst & 0xff000000); - svga->changedvram[(((mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) * 3) & mystique->vram_mask) >> 12] = changeframecount; - } - - data64 >>= 24; - size -= 24; - break; - - case MACCESS_PWIDTH_32: - if (mystique->dwgreg.xdst >= mystique->dwgreg.cxleft && mystique->dwgreg.xdst <= mystique->dwgreg.cxright && - mystique->dwgreg.ydst_lin >= mystique->dwgreg.ytop && mystique->dwgreg.ydst_lin <= mystique->dwgreg.ybot && draw) { - dst = ((uint32_t *)svga->vram)[(mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask_l]; - - dst = bitop(data, dst, mystique->dwgreg.dwgctrl_running); - ((uint32_t *)svga->vram)[(mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask_l] = dst; - svga->changedvram[((mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask_l) >> 10] = changeframecount; - } - - size = 0; - break; - - default: - fatal("ILOAD RSTR/RPL BFCOL pwidth %08x\n", mystique->maccess_running & MACCESS_PWIDTH_MASK); - } - - if (mystique->dwgreg.xdst == mystique->dwgreg.fxright) { - mystique->dwgreg.xdst = mystique->dwgreg.fxleft; - mystique->dwgreg.ydst_lin += (mystique->dwgreg.pitch & PITCH_MASK); - mystique->dwgreg.selline = (mystique->dwgreg.selline + 1) & 7; - mystique->dwgreg.length_cur--; - if (!mystique->dwgreg.length_cur) { - mystique->busy = 0; - mystique->blitter_complete_refcount++; - break; - } - data64 = 0; - size = 0; - break; - } else - mystique->dwgreg.xdst = (mystique->dwgreg.xdst + 1) & 0xffff; - } - mystique->dwgreg.iload_rem_count = size; - mystique->dwgreg.iload_rem_data = data64; - break; - - case DWGCTRL_BLTMOD_BMONOWF: - data = (data >> 24) | ((data & 0x00ff0000) >> 8) | ((data & 0x0000ff00) << 8) | (data << 24); - while (size) { - if (mystique->dwgreg.xdst >= mystique->dwgreg.cxleft && mystique->dwgreg.xdst <= mystique->dwgreg.cxright && - mystique->dwgreg.ydst_lin >= mystique->dwgreg.ytop && mystique->dwgreg.ydst_lin <= mystique->dwgreg.ybot && - ((data & 0x80000000) || !(mystique->dwgreg.dwgctrl_running & DWGCTRL_TRANSC)) && - trans[mystique->dwgreg.xdst & 3]) { - uint32_t old_dst; - - src = (data & 0x80000000) ? mystique->dwgreg.fcol : mystique->dwgreg.bcol; - switch (mystique->maccess_running & MACCESS_PWIDTH_MASK) { - case MACCESS_PWIDTH_8: - dst = svga->vram[(mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask]; - - dst = bitop(src, dst, mystique->dwgreg.dwgctrl_running); - - svga->vram[(mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask] = dst; - svga->changedvram[((mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask) >> 12] = changeframecount; - break; - - case MACCESS_PWIDTH_16: - dst = ((uint16_t *)svga->vram)[(mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask_w]; - - dst = bitop(src, dst, mystique->dwgreg.dwgctrl_running); - - ((uint16_t *)svga->vram)[(mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask_w] = dst; - svga->changedvram[((mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask_w) >> 11] = changeframecount; - break; - - case MACCESS_PWIDTH_24: - old_dst = *(uint32_t *)&svga->vram[((mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) * 3) & mystique->vram_mask]; - - dst = bitop(src, old_dst, mystique->dwgreg.dwgctrl_running); - - *(uint32_t *)&svga->vram[((mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) * 3) & mystique->vram_mask] = (dst & 0xffffff) | (old_dst & 0xff000000); - svga->changedvram[(((mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) * 3) & mystique->vram_mask) >> 12] = changeframecount; - break; - - case MACCESS_PWIDTH_32: - dst = ((uint32_t *)svga->vram)[(mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask_l]; - - dst = bitop(src, dst, mystique->dwgreg.dwgctrl_running); - - ((uint32_t *)svga->vram)[(mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask_l] = dst; - svga->changedvram[((mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask_l) >> 10] = changeframecount; - break; - - default: - fatal("ILOAD RSTR/RPL BMONOWF pwidth %08x\n", mystique->maccess_running & MACCESS_PWIDTH_MASK); - } - } - - if (mystique->dwgreg.xdst == mystique->dwgreg.fxright) { - mystique->dwgreg.xdst = mystique->dwgreg.fxleft; - mystique->dwgreg.ydst_lin += (mystique->dwgreg.pitch & PITCH_MASK); - mystique->dwgreg.length_cur--; - if (!mystique->dwgreg.length_cur) { - mystique->busy = 0; - mystique->blitter_complete_refcount++; - break; - } - if (!(mystique->dwgreg.dwgctrl_running & DWGCTRL_LINEAR)) - break; - } else - mystique->dwgreg.xdst = (mystique->dwgreg.xdst + 1) & 0xffff; - data <<= 1; - size--; - } - break; - - case DWGCTRL_BLTMOD_BU24RGB: - size += mystique->dwgreg.iload_rem_count; - data64 = mystique->dwgreg.iload_rem_data | ((uint64_t)data << mystique->dwgreg.iload_rem_count); - - while (size >= 24) { - if (mystique->dwgreg.xdst >= mystique->dwgreg.cxleft && mystique->dwgreg.xdst <= mystique->dwgreg.cxright && - mystique->dwgreg.ydst_lin >= mystique->dwgreg.ytop && mystique->dwgreg.ydst_lin <= mystique->dwgreg.ybot) { - switch (mystique->maccess_running & MACCESS_PWIDTH_MASK) { - case MACCESS_PWIDTH_32: - dst = ((uint32_t *)svga->vram)[(mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask_l]; - - dst = bitop(data64 & 0xffffff, dst, mystique->dwgreg.dwgctrl_running); - - ((uint32_t *)svga->vram)[(mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask_l] = dst; - svga->changedvram[((mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask_l) >> 10] = changeframecount; - break; - - default: - fatal("ILOAD RSTR/RPL BU24RGB pwidth %08x\n", mystique->maccess_running & MACCESS_PWIDTH_MASK); - } - } - - data64 >>= 24; - size -= 24; - if (mystique->dwgreg.xdst == mystique->dwgreg.fxright) { - mystique->dwgreg.xdst = mystique->dwgreg.fxleft; - mystique->dwgreg.ydst_lin += (mystique->dwgreg.pitch & PITCH_MASK); - mystique->dwgreg.length_cur--; - if (!mystique->dwgreg.length_cur) { - mystique->busy = 0; - mystique->blitter_complete_refcount++; - break; - } - data64 = 0; - size = 0; - break; - } else - mystique->dwgreg.xdst = (mystique->dwgreg.xdst + 1) & 0xffff; - } - - mystique->dwgreg.iload_rem_count = size; - mystique->dwgreg.iload_rem_data = data64; - break; - - case DWGCTRL_BLTMOD_BU32RGB: - size += mystique->dwgreg.iload_rem_count; - while (size >= 32) { - if (mystique->dwgreg.xdst >= mystique->dwgreg.cxleft && mystique->dwgreg.xdst <= mystique->dwgreg.cxright && - mystique->dwgreg.ydst_lin >= mystique->dwgreg.ytop && mystique->dwgreg.ydst_lin <= mystique->dwgreg.ybot) { - switch (mystique->maccess_running & MACCESS_PWIDTH_MASK) { - case MACCESS_PWIDTH_32: - dst = ((uint32_t *)svga->vram)[(mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask_l]; - - dst = bitop(data, dst, mystique->dwgreg.dwgctrl_running); - - ((uint32_t *)svga->vram)[(mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask_l] = dst; - svga->changedvram[((mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask_l) >> 10] = changeframecount; - break; - - default: - fatal("ILOAD RSTR/RPL BU32RGB pwidth %08x\n", mystique->maccess_running & MACCESS_PWIDTH_MASK); - } - } - - size = 0; - if (mystique->dwgreg.xdst == mystique->dwgreg.fxright) { - mystique->dwgreg.xdst = mystique->dwgreg.fxleft; - mystique->dwgreg.ydst_lin += (mystique->dwgreg.pitch & PITCH_MASK); - mystique->dwgreg.length_cur--; - if (!mystique->dwgreg.length_cur) { - mystique->busy = 0; - mystique->blitter_complete_refcount++; - break; - } - break; - } else - mystique->dwgreg.xdst = (mystique->dwgreg.xdst + 1) & 0xffff; - } - - mystique->dwgreg.iload_rem_count = size; - break; - - default: - fatal("ILOAD DWGCTRL_ATYPE_RPL\n"); - break; - } - break; - - default: - fatal("Unknown ILOAD iload atype %03x %08x\n", mystique->dwgreg.dwgctrl_running & DWGCTRL_ATYPE_MASK, mystique->dwgreg.dwgctrl_running); - } -} - - -#define CLAMP(x) do { \ - if ((x) & ~0xff) \ - x = ((x) < 0) ? 0 : 0xff; \ - } while (0) - - -static void -blit_iload_iload_scale(mystique_t *mystique, uint32_t data, int size) -{ - svga_t *svga = &mystique->svga; - uint64_t data64 = 0; - int y0, y1; - int u, v; - int dR, dG, dB; - int r0, g0, b0; - int r1, g1, b1; - - switch (mystique->dwgreg.dwgctrl_running & DWGCTRL_BLTMOD_MASK) { - case DWGCTRL_BLTMOD_BUYUV: - y0 = (298 * ((int)(data & 0xff) - 16)) >> 8; - u = ((data >> 8) & 0xff) - 0x80; - y1 = (298 * ((int)((data >> 16) & 0xff) - 16)) >> 8; - v = ((data >> 24) & 0xff) - 0x80; - - dR = (309*v) >> 8; - dG = (100*u + 208*v) >> 8; - dB = (516*u) >> 8; - - r0 = y0 + dR; - CLAMP(r0); - g0 = y0 - dG; - CLAMP(g0); - b0 = y0 + dB; - CLAMP(b0); - r1 = y1 + dR; - CLAMP(r1); - g1 = y1 - dG; - CLAMP(g1); - b1 = y1 + dB; - CLAMP(b1); - - switch (mystique->maccess_running & MACCESS_PWIDTH_MASK) { - case MACCESS_PWIDTH_16: - data = (b0 >> 3) | ((g0 >> 2) << 5) | ((r0 >> 3) << 11); - data |= (((b1 >> 3) | ((g1 >> 2) << 5) | ((r1 >> 3) << 11)) << 16); - size = 32; - break; - case MACCESS_PWIDTH_32: - data64 = b0 | (g0 << 8) | (r0 << 16); - data64 |= ((uint64_t)b0 << 32) | ((uint64_t)g0 << 40) | ((uint64_t)r0 << 48); - size = 64; - break; - - default: - fatal("blit_iload_iload_scale BUYUV pwidth %i\n", mystique->maccess_running & MACCESS_PWIDTH_MASK); - } - break; - - default: - fatal("blit_iload_iload_scale bltmod %08x\n", mystique->dwgreg.dwgctrl_running & DWGCTRL_BLTMOD_MASK); - break; - } - - switch (mystique->maccess_running & MACCESS_PWIDTH_MASK) { - case MACCESS_PWIDTH_16: - while (size >= 16) { - if (mystique->dwgreg.xdst >= mystique->dwgreg.cxleft && mystique->dwgreg.xdst <= mystique->dwgreg.cxright && - mystique->dwgreg.ydst_lin >= mystique->dwgreg.ytop && mystique->dwgreg.ydst_lin <= mystique->dwgreg.ybot) { - uint16_t dst = ((uint16_t *)svga->vram)[(mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask_w]; - dst = bitop(data & 0xffff, dst, mystique->dwgreg.dwgctrl_running); - ((uint16_t *)svga->vram)[(mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask_w] = dst; - svga->changedvram[((mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask_w) >> 11] = changeframecount; - } - - mystique->dwgreg.ar[6] += mystique->dwgreg.ar[2]; - if ((int32_t)mystique->dwgreg.ar[6] >= 0) { - mystique->dwgreg.ar[6] -= (mystique->dwgreg.fxright - mystique->dwgreg.fxleft); - data >>= 16; - size -= 16; - } - - if (mystique->dwgreg.xdst == mystique->dwgreg.fxright) { - mystique->dwgreg.xdst = mystique->dwgreg.fxleft; - mystique->dwgreg.ydst_lin += (mystique->dwgreg.pitch & PITCH_MASK); - mystique->dwgreg.ar[6] = mystique->dwgreg.ar[2] - (mystique->dwgreg.fxright - mystique->dwgreg.fxleft); - mystique->dwgreg.length_cur--; - if (!mystique->dwgreg.length_cur) { - mystique->busy = 0; - mystique->blitter_complete_refcount++; - break; - } - break; - } else - mystique->dwgreg.xdst = (mystique->dwgreg.xdst + 1) & 0xffff; - } - break; - - case MACCESS_PWIDTH_32: - while (size >= 32) { - if (mystique->dwgreg.xdst >= mystique->dwgreg.cxleft && mystique->dwgreg.xdst <= mystique->dwgreg.cxright && - mystique->dwgreg.ydst_lin >= mystique->dwgreg.ytop && mystique->dwgreg.ydst_lin <= mystique->dwgreg.ybot) { - uint32_t dst = ((uint32_t *)svga->vram)[(mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask_l]; - dst = bitop(data64, dst, mystique->dwgreg.dwgctrl_running); - ((uint32_t *)svga->vram)[(mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask_l] = dst; - svga->changedvram[((mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask_l) >> 10] = changeframecount; - } - - mystique->dwgreg.ar[6] += mystique->dwgreg.ar[2]; - if ((int32_t)mystique->dwgreg.ar[6] >= 0) { - mystique->dwgreg.ar[6] -= (mystique->dwgreg.fxright - mystique->dwgreg.fxleft); - data64 >>= 32; - size -= 32; - } - - if (mystique->dwgreg.xdst == mystique->dwgreg.fxright) { - mystique->dwgreg.xdst = mystique->dwgreg.fxleft; - mystique->dwgreg.ydst_lin += (mystique->dwgreg.pitch & PITCH_MASK); - mystique->dwgreg.ar[6] = mystique->dwgreg.ar[2] - (mystique->dwgreg.fxright - mystique->dwgreg.fxleft); - mystique->dwgreg.length_cur--; - if (!mystique->dwgreg.length_cur) { - mystique->busy = 0; - mystique->blitter_complete_refcount++; - break; - } - break; - } else - mystique->dwgreg.xdst = (mystique->dwgreg.xdst + 1) & 0xffff; - } - break; - - default: - fatal("ILOAD_SCALE pwidth %08x\n", mystique->maccess_running & MACCESS_PWIDTH_MASK); - } -} - - -static void -blit_iload_iload_high(mystique_t *mystique, uint32_t data, int size) -{ - svga_t *svga = &mystique->svga; - uint32_t out_data; - int y0, y1, u, v; - int dR, dG, dB; - int r = 0, g = 0, b = 0; - int next_r = 0, next_g = 0, next_b = 0; - - switch (mystique->dwgreg.dwgctrl_running & DWGCTRL_BLTMOD_MASK) { - case DWGCTRL_BLTMOD_BUYUV: - y0 = (298 * ((int)(data & 0xff) - 16)) >> 8; - u = ((data >> 8) & 0xff) - 0x80; - y1 = (298 * ((int)((data >> 16) & 0xff) - 16)) >> 8; - v = ((data >> 24) & 0xff) - 0x80; - - dR = (309*v) >> 8; - dG = (100*u + 208*v) >> 8; - dB = (516*u) >> 8; - - r = y0 + dR; - CLAMP(r); - g = y0 - dG; - CLAMP(g); - b = y0 + dB; - CLAMP(b); - - next_r = y1 + dR; - CLAMP(next_r); - next_g = y1 - dG; - CLAMP(next_g); - next_b = y1 + dB; - CLAMP(next_b); - - size = 32; - break; - - default: - fatal("blit_iload_iload_high bltmod %08x\n", mystique->dwgreg.dwgctrl_running & DWGCTRL_BLTMOD_MASK); - break; - } - - while (size >= 16) { - if (mystique->dwgreg.xdst >= mystique->dwgreg.cxleft && mystique->dwgreg.xdst <= mystique->dwgreg.cxright && - mystique->dwgreg.ydst_lin >= mystique->dwgreg.ytop && mystique->dwgreg.ydst_lin <= mystique->dwgreg.ybot) { - uint32_t dst; - int f1 = (mystique->dwgreg.ar[6] >> 12) & 0xf; - int f0 = 0x10 - f1; - int out_r = ((mystique->dwgreg.lastpix_r * f0) + (r * f1)) >> 4; - int out_g = ((mystique->dwgreg.lastpix_g * f0) + (g * f1)) >> 4; - int out_b = ((mystique->dwgreg.lastpix_b * f0) + (b * f1)) >> 4; - - switch (mystique->maccess_running & MACCESS_PWIDTH_MASK) { - case MACCESS_PWIDTH_16: - out_data = (out_b >> 3) | ((out_g >> 2) << 5) | ((out_r >> 3) << 11); - dst = ((uint16_t *)svga->vram)[(mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask_w]; - dst = bitop(out_data, dst, mystique->dwgreg.dwgctrl_running); - ((uint16_t *)svga->vram)[(mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask_w] = dst; - svga->changedvram[((mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask_w) >> 11] = changeframecount; - break; - case MACCESS_PWIDTH_32: - out_data = out_b | (out_g << 8) | (out_r << 16); - dst = ((uint32_t *)svga->vram)[(mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask_l]; - dst = bitop(out_data, dst, mystique->dwgreg.dwgctrl_running); - ((uint32_t *)svga->vram)[(mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask_l] = dst; - svga->changedvram[((mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask_l) >> 10] = changeframecount; - break; - - default: - fatal("ILOAD_SCALE_HIGH RSTR/RPL BUYUV pwidth %08x\n", mystique->maccess_running & MACCESS_PWIDTH_MASK); - } - } - - mystique->dwgreg.ar[6] += mystique->dwgreg.ar[2]; - if ((int32_t)mystique->dwgreg.ar[6] >= 0) { - mystique->dwgreg.ar[6] -= 65536; - size -= 16; - - mystique->dwgreg.lastpix_r = r; - mystique->dwgreg.lastpix_g = g; - mystique->dwgreg.lastpix_b = b; - r = next_r; - g = next_g; - b = next_b; - } - - if (mystique->dwgreg.xdst == mystique->dwgreg.fxright) { - mystique->dwgreg.xdst = mystique->dwgreg.fxleft; - mystique->dwgreg.ydst_lin += (mystique->dwgreg.pitch & PITCH_MASK); - mystique->dwgreg.ar[6] = mystique->dwgreg.ar[2] - (mystique->dwgreg.fxright - mystique->dwgreg.fxleft); - mystique->dwgreg.lastpix_r = 0; - mystique->dwgreg.lastpix_g = 0; - mystique->dwgreg.lastpix_b = 0; - - mystique->dwgreg.length_cur--; - if (!mystique->dwgreg.length_cur) { - mystique->busy = 0; - mystique->blitter_complete_refcount++; - break; - } - break; - } else - mystique->dwgreg.xdst = (mystique->dwgreg.xdst + 1) & 0xffff; - } -} - - -static void -blit_iload_iload_highv(mystique_t *mystique, uint32_t data, int size) -{ - uint8_t *src0, *src1; - - switch (mystique->dwgreg.dwgctrl_running & DWGCTRL_BLTMOD_MASK) { - case DWGCTRL_BLTMOD_BUYUV: - if (!mystique->dwgreg.highv_line) { - mystique->dwgreg.highv_data = data; - mystique->dwgreg.highv_line = 1; - return; - } - mystique->dwgreg.highv_line = 0; - - src0 = (uint8_t *)&mystique->dwgreg.highv_data; - src1 = (uint8_t *)&data; - - src1[0] = ((src0[0] * mystique->dwgreg.beta) + (src1[0] * (16 - mystique->dwgreg.beta))) >> 4; - src1[1] = ((src0[1] * mystique->dwgreg.beta) + (src1[1] * (16 - mystique->dwgreg.beta))) >> 4; - src1[2] = ((src0[2] * mystique->dwgreg.beta) + (src1[2] * (16 - mystique->dwgreg.beta))) >> 4; - src1[3] = ((src0[3] * mystique->dwgreg.beta) + (src1[3] * (16 - mystique->dwgreg.beta))) >> 4; - blit_iload_iload_high(mystique, data, 32); - break; - - default: - fatal("blit_iload_iload_highv bltmod %08x\n", mystique->dwgreg.dwgctrl_running & DWGCTRL_BLTMOD_MASK); - break; - } -} - - -static void -blit_iload_write(mystique_t *mystique, uint32_t data, int size) -{ - switch (mystique->dwgreg.dwgctrl_running & DWGCTRL_OPCODE_MASK) { - case DWGCTRL_OPCODE_ILOAD: - blit_iload_iload(mystique, data, size); - break; - - case DWGCTRL_OPCODE_ILOAD_SCALE: - blit_iload_iload_scale(mystique, data, size); - break; - - case DWGCTRL_OPCODE_ILOAD_HIGH: - blit_iload_iload_high(mystique, data, size); - break; - - case DWGCTRL_OPCODE_ILOAD_HIGHV: - blit_iload_iload_highv(mystique, data, size); - break; - - default: - fatal("blit_iload_write: bad opcode %08x\n", mystique->dwgreg.dwgctrl_running); - } -} - - -static int -z_check(uint16_t z, uint16_t old_z, uint32_t z_mode)//mystique->dwgreg.dwgctrl & DWGCTRL_ZMODE_MASK) -{ - switch (z_mode) { - case DWGCTRL_ZMODE_ZE: - return (z == old_z); - case DWGCTRL_ZMODE_ZNE: - return (z != old_z); - case DWGCTRL_ZMODE_ZLT: - return (z < old_z); - case DWGCTRL_ZMODE_ZLTE: - return (z <= old_z); - case DWGCTRL_ZMODE_ZGT: - return (z > old_z); - case DWGCTRL_ZMODE_ZGTE: - return (z >= old_z); - - case DWGCTRL_ZMODE_NOZCMP: - default: - return 1; - } -} - - -static void -blit_line(mystique_t *mystique, int closed) -{ - svga_t *svga = &mystique->svga; - uint32_t src, dst, old_dst; - int x; - int z_write; - - switch (mystique->dwgreg.dwgctrl_running & DWGCTRL_ATYPE_MASK) { - case DWGCTRL_ATYPE_RSTR: - case DWGCTRL_ATYPE_RPL: - x = mystique->dwgreg.xdst; - while (mystique->dwgreg.length > 0) { - if (x >= mystique->dwgreg.cxleft && x <= mystique->dwgreg.cxright && - mystique->dwgreg.ydst_lin >= mystique->dwgreg.ytop && mystique->dwgreg.ydst_lin <= mystique->dwgreg.ybot) { - switch (mystique->maccess_running & MACCESS_PWIDTH_MASK) { - case MACCESS_PWIDTH_8: - src = mystique->dwgreg.fcol; - dst = svga->vram[(mystique->dwgreg.ydst_lin + x) & mystique->vram_mask]; - - dst = bitop(src, dst, mystique->dwgreg.dwgctrl_running); - svga->vram[(mystique->dwgreg.ydst_lin + x) & mystique->vram_mask] = dst; - svga->changedvram[((mystique->dwgreg.ydst_lin + x) & mystique->vram_mask) >> 12] = changeframecount; - break; - - case MACCESS_PWIDTH_16: - src = mystique->dwgreg.fcol; - dst = ((uint16_t *)svga->vram)[(mystique->dwgreg.ydst_lin + x) & mystique->vram_mask_w]; - - dst = bitop(src, dst, mystique->dwgreg.dwgctrl_running); - ((uint16_t *)svga->vram)[(mystique->dwgreg.ydst_lin + x) & mystique->vram_mask_w] = dst; - svga->changedvram[((mystique->dwgreg.ydst_lin + x) & mystique->vram_mask_w) >> 11] = changeframecount; - break; - - case MACCESS_PWIDTH_24: - src = mystique->dwgreg.fcol; - old_dst = *(uint32_t *)&svga->vram[((mystique->dwgreg.ydst_lin + x) * 3) & mystique->vram_mask]; - - dst = bitop(src, old_dst, mystique->dwgreg.dwgctrl_running); - *(uint32_t *)&svga->vram[((mystique->dwgreg.ydst_lin + x) * 3) & mystique->vram_mask] = (dst & 0xffffff) | (old_dst & 0xff000000); - svga->changedvram[(((mystique->dwgreg.ydst_lin + x) * 3) & mystique->vram_mask) >> 12] = changeframecount; - break; - - case MACCESS_PWIDTH_32: - src = mystique->dwgreg.fcol; - dst = ((uint32_t *)svga->vram)[(mystique->dwgreg.ydst_lin + x) & mystique->vram_mask_l]; - - dst = bitop(src, dst, mystique->dwgreg.dwgctrl_running); - ((uint32_t *)svga->vram)[(mystique->dwgreg.ydst_lin + x) & mystique->vram_mask_l] = dst; - svga->changedvram[((mystique->dwgreg.ydst_lin + x) & mystique->vram_mask_l) >> 10] = changeframecount; - break; - - default: - fatal("LINE RSTR/RPL PWIDTH %x %08x\n", mystique->maccess_running & MACCESS_PWIDTH_MASK, mystique->dwgreg.dwgctrl_running); - } - } - - if (mystique->dwgreg.sgn.sdydxl) - x += (mystique->dwgreg.sgn.sdxl ? -1 : 1); - else - mystique->dwgreg.ydst_lin += (mystique->dwgreg.sgn.sdy ? -(mystique->dwgreg.pitch & PITCH_MASK) : (mystique->dwgreg.pitch & PITCH_MASK)); - - if ((int32_t)mystique->dwgreg.ar[1] >= 0) { - mystique->dwgreg.ar[1] += mystique->dwgreg.ar[2]; - if (mystique->dwgreg.sgn.sdydxl) - mystique->dwgreg.ydst_lin += (mystique->dwgreg.sgn.sdy ? -(mystique->dwgreg.pitch & PITCH_MASK) : (mystique->dwgreg.pitch & PITCH_MASK)); - else - x += (mystique->dwgreg.sgn.sdxl ? -1 : 1); - } else - mystique->dwgreg.ar[1] += mystique->dwgreg.ar[0]; - - mystique->dwgreg.length--; - } - break; - - case DWGCTRL_ATYPE_I: - case DWGCTRL_ATYPE_ZI: - z_write = ((mystique->dwgreg.dwgctrl_running & DWGCTRL_ATYPE_MASK) == DWGCTRL_ATYPE_ZI); - x = mystique->dwgreg.xdst; - while (mystique->dwgreg.length > 0) { - if (x >= mystique->dwgreg.cxleft && x <= mystique->dwgreg.cxright && - mystique->dwgreg.ydst_lin >= mystique->dwgreg.ytop && mystique->dwgreg.ydst_lin <= mystique->dwgreg.ybot) { - uint16_t z = ((int32_t)mystique->dwgreg.dr[0] < 0) ? 0 : (mystique->dwgreg.dr[0] >> 15); - uint16_t *z_p = (uint16_t *)&svga->vram[(mystique->dwgreg.ydst_lin*2 + mystique->dwgreg.zorg) & mystique->vram_mask]; - uint16_t old_z = z_p[x]; - - if (z_check(z, old_z, mystique->dwgreg.dwgctrl_running & DWGCTRL_ZMODE_MASK)) { - int r = 0, g = 0, b = 0; - - if (z_write) - z_p[x] = z; - - switch (mystique->maccess_running & MACCESS_PWIDTH_MASK) { - case MACCESS_PWIDTH_16: - if (!(mystique->dwgreg.dr[4] & (1 << 23))) - r = (mystique->dwgreg.dr[4] >> 18) & 0x1f; - if (!(mystique->dwgreg.dr[8] & (1 << 23))) - g = (mystique->dwgreg.dr[8] >> 17) & 0x3f; - if (!(mystique->dwgreg.dr[12] & (1 << 23))) - b = (mystique->dwgreg.dr[12] >> 18) & 0x1f; - dst = (r << 11) | (g << 5) | b; - - ((uint16_t *)svga->vram)[(mystique->dwgreg.ydst_lin + x) & mystique->vram_mask_w] = dst; - svga->changedvram[((mystique->dwgreg.ydst_lin + x) & mystique->vram_mask_w) >> 11] = changeframecount; - break; - - default: - fatal("LINE I/ZI PWIDTH %x %08x\n", mystique->maccess_running & MACCESS_PWIDTH_MASK, mystique->dwgreg.dwgctrl_running); - } - } - } - - if (mystique->dwgreg.sgn.sdydxl) - x += (mystique->dwgreg.sgn.sdxl ? -1 : 1); - else - mystique->dwgreg.ydst_lin += (mystique->dwgreg.sgn.sdy ? -(mystique->dwgreg.pitch & PITCH_MASK) : (mystique->dwgreg.pitch & PITCH_MASK)); - - mystique->dwgreg.dr[0] += mystique->dwgreg.dr[2]; - mystique->dwgreg.dr[4] += mystique->dwgreg.dr[6]; - mystique->dwgreg.dr[8] += mystique->dwgreg.dr[10]; - mystique->dwgreg.dr[12] += mystique->dwgreg.dr[14]; - - if ((int32_t)mystique->dwgreg.ar[1] >= 0) { - mystique->dwgreg.ar[1] += mystique->dwgreg.ar[2]; - - if (mystique->dwgreg.sgn.sdydxl) - mystique->dwgreg.ydst_lin += (mystique->dwgreg.sgn.sdy ? -(mystique->dwgreg.pitch & PITCH_MASK) : (mystique->dwgreg.pitch & PITCH_MASK)); - else - x += (mystique->dwgreg.sgn.sdxl ? -1 : 1); - - mystique->dwgreg.dr[0] += mystique->dwgreg.dr[3]; - mystique->dwgreg.dr[4] += mystique->dwgreg.dr[7]; - mystique->dwgreg.dr[8] += mystique->dwgreg.dr[11]; - mystique->dwgreg.dr[12] += mystique->dwgreg.dr[15]; - } else - mystique->dwgreg.ar[1] += mystique->dwgreg.ar[0]; - - mystique->dwgreg.length--; - } - break; - - default: - /* pclog("Unknown atype %03x %08x LINE\n", mystique->dwgreg.dwgctrl_running & DWGCTRL_ATYPE_MASK, mystique->dwgreg.dwgctrl_running); */ - break; - } - - mystique->blitter_complete_refcount++; -} - - -static void -blit_autoline(mystique_t *mystique, int closed) -{ - int start_x = (int32_t)mystique->dwgreg.ar[5]; - int start_y = (int32_t)mystique->dwgreg.ar[6]; - int end_x = (int32_t)mystique->dwgreg.ar[0]; - int end_y = (int32_t)mystique->dwgreg.ar[2]; - int dx = end_x - start_x; - int dy = end_y - start_y; - - if (ABS(dx) > ABS(dy)) { - mystique->dwgreg.sgn.sdydxl = 1; - mystique->dwgreg.ar[0] = 2*ABS(dy); - mystique->dwgreg.ar[1] = 2*ABS(dy) - ABS(dx) - ((start_y > end_y) ? 1 : 0); - mystique->dwgreg.ar[2] = 2*ABS(dy) - 2*ABS(dx); - mystique->dwgreg.length = ABS(end_x - start_x); - } else { - mystique->dwgreg.sgn.sdydxl = 0; - mystique->dwgreg.ar[0] = 2*ABS(dx); - mystique->dwgreg.ar[1] = 2*ABS(dx) - ABS(dy) - ((start_y > end_y) ? 1 : 0); - mystique->dwgreg.ar[2] = 2*ABS(dx) - 2*ABS(dy); - mystique->dwgreg.length = ABS(end_y - start_y); - } - mystique->dwgreg.sgn.sdxl = (start_x > end_x) ? 1 : 0; - mystique->dwgreg.sgn.sdy = (start_y > end_y) ? 1 : 0; - - blit_line(mystique, closed); - - mystique->dwgreg.ar[5] = end_x; - mystique->dwgreg.xdst = end_x; - mystique->dwgreg.ar[6] = end_y; - mystique->dwgreg.ydst = end_y; - mystique->dwgreg.ydst_lin = ((int32_t)(int16_t)mystique->dwgreg.ydst * (mystique->dwgreg.pitch & PITCH_MASK)) + mystique->dwgreg.ydstorg; -} - - -static void -blit_trap(mystique_t *mystique) -{ - svga_t *svga = &mystique->svga; - uint32_t z_back, r_back, g_back, b_back; - int z_write; - int y; - const int trans_sel = (mystique->dwgreg.dwgctrl_running & DWGCTRL_TRANS_MASK) >> DWGCTRL_TRANS_SHIFT; - - mystique->trap_count++; - - switch (mystique->dwgreg.dwgctrl_running & DWGCTRL_ATYPE_MASK) { - case DWGCTRL_ATYPE_BLK: - case DWGCTRL_ATYPE_RPL: - for (y = 0; y < mystique->dwgreg.length; y++) { - uint8_t const * const trans = &trans_masks[trans_sel][(mystique->dwgreg.selline & 3) * 4]; - int16_t x_l = mystique->dwgreg.fxleft & 0xffff; - int16_t x_r = mystique->dwgreg.fxright & 0xffff; - int yoff = (mystique->dwgreg.yoff + mystique->dwgreg.ydst) & 7; - - while (x_l != x_r) { - if (x_l >= mystique->dwgreg.cxleft && x_l <= mystique->dwgreg.cxright && - mystique->dwgreg.ydst_lin >= mystique->dwgreg.ytop && mystique->dwgreg.ydst_lin <= mystique->dwgreg.ybot && - trans[x_l & 3]) { - int xoff = (mystique->dwgreg.xoff + x_l) & 7; - int pattern = mystique->dwgreg.pattern[yoff][xoff]; - uint32_t dst; - - switch (mystique->maccess_running & MACCESS_PWIDTH_MASK) { - case MACCESS_PWIDTH_8: - svga->vram[(mystique->dwgreg.ydst_lin + x_l) & mystique->vram_mask] = - (pattern ? mystique->dwgreg.fcol : mystique->dwgreg.bcol) & 0xff; - svga->changedvram[((mystique->dwgreg.ydst_lin + x_l) & mystique->vram_mask) >> 12] = changeframecount; - break; - - case MACCESS_PWIDTH_16: - ((uint16_t *)svga->vram)[(mystique->dwgreg.ydst_lin + x_l) & mystique->vram_mask_w] = - (pattern ? mystique->dwgreg.fcol : mystique->dwgreg.bcol) & 0xffff; - svga->changedvram[((mystique->dwgreg.ydst_lin + x_l) & mystique->vram_mask_w) >> 11] = changeframecount; - break; - - case MACCESS_PWIDTH_24: - dst = *(uint32_t *)(&svga->vram[((mystique->dwgreg.ydst_lin + x_l) * 3) & mystique->vram_mask]) & 0xff000000; - *(uint32_t *)(&svga->vram[((mystique->dwgreg.ydst_lin + x_l) * 3) & mystique->vram_mask]) = - ((pattern ? mystique->dwgreg.fcol : mystique->dwgreg.bcol) & 0xffffff) | dst; - svga->changedvram[(((mystique->dwgreg.ydst_lin + x_l) * 3) & mystique->vram_mask) >> 12] = changeframecount; - break; - - case MACCESS_PWIDTH_32: - ((uint32_t *)svga->vram)[(mystique->dwgreg.ydst_lin + x_l) & mystique->vram_mask_l] = - pattern ? mystique->dwgreg.fcol : mystique->dwgreg.bcol; - svga->changedvram[((mystique->dwgreg.ydst_lin + x_l) & mystique->vram_mask_l) >> 10] = changeframecount; - break; - - default: - fatal("TRAP BLK/RPL PWIDTH %x %08x\n", mystique->maccess_running & MACCESS_PWIDTH_MASK, mystique->dwgreg.dwgctrl_running); - } - } - x_l++; - mystique->pixel_count++; - } - - if ((int32_t)mystique->dwgreg.ar[1] < 0) { - while ((int32_t)mystique->dwgreg.ar[1] < 0 && mystique->dwgreg.ar[0]) { - mystique->dwgreg.ar[1] += mystique->dwgreg.ar[0]; - mystique->dwgreg.fxleft += (mystique->dwgreg.sgn.sdxl ? -1 : 1); - } - } else - mystique->dwgreg.ar[1] += mystique->dwgreg.ar[2]; - - if ((int32_t)mystique->dwgreg.ar[4] < 0) { - while ((int32_t)mystique->dwgreg.ar[4] < 0 && mystique->dwgreg.ar[6]) { - mystique->dwgreg.ar[4] += mystique->dwgreg.ar[6]; - mystique->dwgreg.fxright += (mystique->dwgreg.sgn.sdxr ? -1 : 1); - } - } else - mystique->dwgreg.ar[4] += mystique->dwgreg.ar[5]; - - mystique->dwgreg.ydst++; - mystique->dwgreg.ydst &= 0x7fffff; - mystique->dwgreg.ydst_lin += (mystique->dwgreg.pitch & PITCH_MASK); - - mystique->dwgreg.selline = (mystique->dwgreg.selline + 1) & 7; - } - break; - - case DWGCTRL_ATYPE_RSTR: - for (y = 0; y < mystique->dwgreg.length; y++) { - uint8_t const * const trans = &trans_masks[trans_sel][(mystique->dwgreg.selline & 3) * 4]; - int16_t x_l = mystique->dwgreg.fxleft & 0xffff; - int16_t x_r = mystique->dwgreg.fxright & 0xffff; - int yoff = (mystique->dwgreg.yoff + mystique->dwgreg.ydst) & 7; - - while (x_l != x_r) { - if (x_l >= mystique->dwgreg.cxleft && x_l <= mystique->dwgreg.cxright && - mystique->dwgreg.ydst_lin >= mystique->dwgreg.ytop && mystique->dwgreg.ydst_lin <= mystique->dwgreg.ybot && - trans[x_l & 3]) { - int xoff = (mystique->dwgreg.xoff + x_l) & 7; - int pattern = mystique->dwgreg.pattern[yoff][xoff]; - uint32_t src = pattern ? mystique->dwgreg.fcol : mystique->dwgreg.bcol; - uint32_t dst, old_dst; - - switch (mystique->maccess_running & MACCESS_PWIDTH_MASK) { - case MACCESS_PWIDTH_8: - dst = svga->vram[(mystique->dwgreg.ydst_lin + x_l) & mystique->vram_mask]; - - dst = bitop(src, dst, mystique->dwgreg.dwgctrl_running); - svga->vram[(mystique->dwgreg.ydst_lin + x_l) & mystique->vram_mask] = dst; - svga->changedvram[((mystique->dwgreg.ydst_lin + x_l) & mystique->vram_mask) >> 12] = changeframecount; - break; - - case MACCESS_PWIDTH_16: - dst = ((uint16_t *)svga->vram)[(mystique->dwgreg.ydst_lin + x_l) & mystique->vram_mask_w]; - - dst = bitop(src, dst, mystique->dwgreg.dwgctrl_running); - ((uint16_t *)svga->vram)[(mystique->dwgreg.ydst_lin + x_l) & mystique->vram_mask_w] = dst; - svga->changedvram[((mystique->dwgreg.ydst_lin + x_l) & mystique->vram_mask_w) >> 11] = changeframecount; - break; - - case MACCESS_PWIDTH_24: - old_dst = *(uint32_t *)&svga->vram[((mystique->dwgreg.ydst_lin + x_l) * 3) & mystique->vram_mask]; - - dst = bitop(src, old_dst, mystique->dwgreg.dwgctrl_running); - *(uint32_t *)&svga->vram[((mystique->dwgreg.ydst_lin + x_l) * 3) & mystique->vram_mask] = (dst & 0xffffff) | (old_dst & 0xff000000); - svga->changedvram[(((mystique->dwgreg.ydst_lin + x_l) * 3) & mystique->vram_mask) >> 12] = changeframecount; - break; - - case MACCESS_PWIDTH_32: - dst = ((uint32_t *)svga->vram)[(mystique->dwgreg.ydst_lin + x_l) & mystique->vram_mask_l]; - - dst = bitop(src, dst, mystique->dwgreg.dwgctrl_running); - ((uint32_t *)svga->vram)[(mystique->dwgreg.ydst_lin + x_l) & mystique->vram_mask_l] = dst; - svga->changedvram[((mystique->dwgreg.ydst_lin + x_l) & mystique->vram_mask_l) >> 10] = changeframecount; - break; - - default: - fatal("TRAP RSTR PWIDTH %x %08x\n", mystique->maccess_running & MACCESS_PWIDTH_MASK, mystique->dwgreg.dwgctrl_running); - } - } - x_l++; - mystique->pixel_count++; - } - - if ((int32_t)mystique->dwgreg.ar[1] < 0) { - while ((int32_t)mystique->dwgreg.ar[1] < 0 && mystique->dwgreg.ar[0]) { - mystique->dwgreg.ar[1] += mystique->dwgreg.ar[0]; - mystique->dwgreg.fxleft += (mystique->dwgreg.sgn.sdxl ? -1 : 1); - } - } else - mystique->dwgreg.ar[1] += mystique->dwgreg.ar[2]; - - if ((int32_t)mystique->dwgreg.ar[4] < 0) { - while ((int32_t)mystique->dwgreg.ar[4] < 0 && mystique->dwgreg.ar[6]) { - mystique->dwgreg.ar[4] += mystique->dwgreg.ar[6]; - mystique->dwgreg.fxright += (mystique->dwgreg.sgn.sdxr ? -1 : 1); - } - } else - mystique->dwgreg.ar[4] += mystique->dwgreg.ar[5]; - - mystique->dwgreg.ydst++; - mystique->dwgreg.ydst &= 0x7fffff; - mystique->dwgreg.ydst_lin += (mystique->dwgreg.pitch & PITCH_MASK); - - mystique->dwgreg.selline = (mystique->dwgreg.selline + 1) & 7; - } - break; - - case DWGCTRL_ATYPE_I: - case DWGCTRL_ATYPE_ZI: - z_write = ((mystique->dwgreg.dwgctrl_running & DWGCTRL_ATYPE_MASK) == DWGCTRL_ATYPE_ZI); - - for (y = 0; y < mystique->dwgreg.length; y++) { - uint8_t const * const trans = &trans_masks[trans_sel][(mystique->dwgreg.selline & 3) * 4]; - uint16_t *z_p = (uint16_t *)&svga->vram[(mystique->dwgreg.ydst_lin*2 + mystique->dwgreg.zorg) & mystique->vram_mask]; - int16_t x_l = mystique->dwgreg.fxleft & 0xffff; - int16_t x_r = mystique->dwgreg.fxright & 0xffff; - int16_t old_x_l = x_l; - int dx; - - z_back = mystique->dwgreg.dr[0]; - r_back = mystique->dwgreg.dr[4]; - g_back = mystique->dwgreg.dr[8]; - b_back = mystique->dwgreg.dr[12]; - - while (x_l != x_r) { - if (x_l >= mystique->dwgreg.cxleft && x_l <= mystique->dwgreg.cxright && - mystique->dwgreg.ydst_lin >= mystique->dwgreg.ytop && mystique->dwgreg.ydst_lin <= mystique->dwgreg.ybot && - trans[x_l & 3]) { - uint16_t z = ((int32_t)mystique->dwgreg.dr[0] < 0) ? 0 : (mystique->dwgreg.dr[0] >> 15); - uint16_t old_z = z_p[x_l]; - - if (z_check(z, old_z, mystique->dwgreg.dwgctrl_running & DWGCTRL_ZMODE_MASK)) { - uint32_t dst = 0, old_dst; - int r = 0, g = 0, b = 0; - - if (!(mystique->dwgreg.dr[4] & (1 << 23))) - r = (mystique->dwgreg.dr[4] >> 15) & 0xff; - if (!(mystique->dwgreg.dr[8] & (1 << 23))) - g = (mystique->dwgreg.dr[8] >> 15) & 0xff; - if (!(mystique->dwgreg.dr[12] & (1 << 23))) - b = (mystique->dwgreg.dr[12] >> 15) & 0xff; - - if (z_write) - z_p[x_l] = z; - - switch (mystique->maccess_running & MACCESS_PWIDTH_MASK) { - case MACCESS_PWIDTH_8: - svga->vram[(mystique->dwgreg.ydst_lin + x_l) & mystique->vram_mask] = dst; - svga->changedvram[((mystique->dwgreg.ydst_lin + x_l) & mystique->vram_mask) >> 12] = changeframecount; - break; - - case MACCESS_PWIDTH_16: - dst = dither(mystique, r, g, b, x_l & 1, mystique->dwgreg.selline & 1); - ((uint16_t *)svga->vram)[(mystique->dwgreg.ydst_lin + x_l) & mystique->vram_mask_w] = dst; - svga->changedvram[((mystique->dwgreg.ydst_lin + x_l) & mystique->vram_mask_w) >> 11] = changeframecount; - break; - - case MACCESS_PWIDTH_24: - old_dst = *(uint32_t *)(&svga->vram[((mystique->dwgreg.ydst_lin + x_l) * 3) & mystique->vram_mask]) & 0xff000000; - *(uint32_t *)(&svga->vram[((mystique->dwgreg.ydst_lin + x_l) * 3) & mystique->vram_mask]) = old_dst | dst; - svga->changedvram[(((mystique->dwgreg.ydst_lin + x_l) * 3) & mystique->vram_mask) >> 12] = changeframecount; - break; - - case MACCESS_PWIDTH_32: - ((uint32_t *)svga->vram)[(mystique->dwgreg.ydst_lin + x_l) & mystique->vram_mask_l] = b | (g << 8) | (r << 16); - svga->changedvram[((mystique->dwgreg.ydst_lin + x_l) & mystique->vram_mask_l) >> 10] = changeframecount; - break; - - default: - fatal("TRAP BLK/RPL PWIDTH %x %08x\n", mystique->maccess_running & MACCESS_PWIDTH_MASK, mystique->dwgreg.dwgctrl_running); - } - } - } - - mystique->dwgreg.dr[0] += mystique->dwgreg.dr[2]; - mystique->dwgreg.dr[4] += mystique->dwgreg.dr[6]; - mystique->dwgreg.dr[8] += mystique->dwgreg.dr[10]; - mystique->dwgreg.dr[12] += mystique->dwgreg.dr[14]; - - x_l++; - mystique->pixel_count++; - } - - mystique->dwgreg.dr[0] = z_back + mystique->dwgreg.dr[3]; - mystique->dwgreg.dr[4] = r_back + mystique->dwgreg.dr[7]; - mystique->dwgreg.dr[8] = g_back + mystique->dwgreg.dr[11]; - mystique->dwgreg.dr[12] = b_back + mystique->dwgreg.dr[15]; - - while ((int32_t)mystique->dwgreg.ar[1] < 0 && mystique->dwgreg.ar[0]) { - mystique->dwgreg.ar[1] += mystique->dwgreg.ar[0]; - mystique->dwgreg.fxleft += (mystique->dwgreg.sgn.sdxl ? -1 : 1); - } - mystique->dwgreg.ar[1] += mystique->dwgreg.ar[2]; - - while ((int32_t)mystique->dwgreg.ar[4] < 0 && mystique->dwgreg.ar[6]) { - mystique->dwgreg.ar[4] += mystique->dwgreg.ar[6]; - mystique->dwgreg.fxright += (mystique->dwgreg.sgn.sdxr ? -1 : 1); - } - mystique->dwgreg.ar[4] += mystique->dwgreg.ar[5]; - - dx = (int16_t)((mystique->dwgreg.fxleft - old_x_l) & 0xffff); - mystique->dwgreg.dr[0] += dx*mystique->dwgreg.dr[2]; - mystique->dwgreg.dr[4] += dx*mystique->dwgreg.dr[6]; - mystique->dwgreg.dr[8] += dx*mystique->dwgreg.dr[10]; - mystique->dwgreg.dr[12] += dx*mystique->dwgreg.dr[14]; - - mystique->dwgreg.ydst++; - mystique->dwgreg.ydst &= 0x7fffff; - mystique->dwgreg.ydst_lin += (mystique->dwgreg.pitch & PITCH_MASK); - - mystique->dwgreg.selline = (mystique->dwgreg.selline + 1) & 7; - } - break; - - default: - fatal("Unknown atype %03x %08x TRAP\n", mystique->dwgreg.dwgctrl_running & DWGCTRL_ATYPE_MASK, mystique->dwgreg.dwgctrl_running); - } - - mystique->blitter_complete_refcount++; -} - - -static int texture_read(mystique_t *mystique, int *tex_r, int *tex_g, int *tex_b, int *atransp) -{ - svga_t *svga = &mystique->svga; - - const int tex_shift = 3 + ((mystique->dwgreg.texctl & TEXCTL_TPITCH_MASK) >> TEXCTL_TPITCH_SHIFT); - const unsigned int palsel = mystique->dwgreg.texctl & TEXCTL_PALSEL_MASK; - const uint16_t tckey = mystique->dwgreg.textrans & TEXTRANS_TCKEY_MASK; - const uint16_t tkmask = (mystique->dwgreg.textrans & TEXTRANS_TKMASK_MASK) >> TEXTRANS_TKMASK_SHIFT; - const unsigned int w_mask = (mystique->dwgreg.texwidth & TEXWIDTH_TWMASK_MASK) >> TEXWIDTH_TWMASK_SHIFT; - const unsigned int h_mask = (mystique->dwgreg.texheight & TEXHEIGHT_THMASK_MASK) >> TEXHEIGHT_THMASK_SHIFT; - uint16_t src = 0; - int s, t; - - if (mystique->dwgreg.texctl & TEXCTL_NPCEN) { - const int s_shift = 20 - (mystique->dwgreg.texwidth & TEXWIDTH_TW_MASK); - const int t_shift = 20 - (mystique->dwgreg.texheight & TEXHEIGHT_TH_MASK); - - s = (int32_t)mystique->dwgreg.tmr[6] >> s_shift; - t = (int32_t)mystique->dwgreg.tmr[7] >> t_shift; - } else { - const int s_shift = (20 + 16) - (mystique->dwgreg.texwidth & TEXWIDTH_TW_MASK); - const int t_shift = (20 + 16) - (mystique->dwgreg.texheight & TEXHEIGHT_TH_MASK); - int64_t q = mystique->dwgreg.tmr[8] ? ((0x100000000ll / (int64_t)(int32_t)mystique->dwgreg.tmr[8]) /*>> 16*/) : 0; - - s = (((int64_t)(int32_t)mystique->dwgreg.tmr[6] * q) /*<< 8*/) >> s_shift;/*((16+20)-12);*/ - t = (((int64_t)(int32_t)mystique->dwgreg.tmr[7] * q) /*<< 8*/) >> t_shift;/*((16+20)-9);*/ - } - - if (mystique->dwgreg.texctl & TEXCTL_CLAMPU) { - if (s < 0) - s = 0; - else if (s > w_mask) - s = w_mask; - } else - s &= w_mask; - - if (mystique->dwgreg.texctl & TEXCTL_CLAMPV) { - if (t < 0) - t = 0; - else if (t > h_mask) - t = h_mask; - } else - t &= h_mask; - - switch (mystique->dwgreg.texctl & TEXCTL_TEXFORMAT_MASK) { - case TEXCTL_TEXFORMAT_TW4: - src = svga->vram[(mystique->dwgreg.texorg + (((t << tex_shift) + s) >> 1)) & mystique->vram_mask]; - if (s & 1) - src >>= 4; - else - src &= 0xf; - *tex_r = mystique->lut[src | palsel].r; - *tex_g = mystique->lut[src | palsel].g; - *tex_b = mystique->lut[src | palsel].b; - *atransp = 0; - break; - case TEXCTL_TEXFORMAT_TW8: - src = svga->vram[(mystique->dwgreg.texorg + (t << tex_shift) + s) & mystique->vram_mask]; - *tex_r = mystique->lut[src].r; - *tex_g = mystique->lut[src].g; - *tex_b = mystique->lut[src].b; - *atransp = 0; - break; - case TEXCTL_TEXFORMAT_TW15: - src = ((uint16_t *)svga->vram)[((mystique->dwgreg.texorg >> 1) + (t << tex_shift) + s) & mystique->vram_mask_w]; - *tex_r = ((src >> 10) & 0x1f) << 3; - *tex_g = ((src >> 5) & 0x1f) << 3; - *tex_b = (src & 0x1f) << 3; - if (((src >> 15) & mystique->dwgreg.ta_mask) == mystique->dwgreg.ta_key) - *atransp = 1; - else - *atransp = 0; - break; - case TEXCTL_TEXFORMAT_TW16: - src = ((uint16_t *)svga->vram)[((mystique->dwgreg.texorg >> 1) + (t << tex_shift) + s) & mystique->vram_mask_w]; - *tex_r = (src >> 11) << 3; - *tex_g = ((src >> 5) & 0x3f) << 2; - *tex_b = (src & 0x1f) << 3; - *atransp = 0; - break; - default: - fatal("Unknown texture format %i\n", mystique->dwgreg.texctl & TEXCTL_TEXFORMAT_MASK); - break; - } - - return ((src & tkmask) == tckey); -} - - -static void -blit_texture_trap(mystique_t *mystique) -{ - svga_t *svga = &mystique->svga; - int y; - int z_write; - const int trans_sel = (mystique->dwgreg.dwgctrl_running & DWGCTRL_TRANS_MASK) >> DWGCTRL_TRANS_SHIFT; - const int dest32 = ((mystique->maccess_running & MACCESS_PWIDTH_MASK) == MACCESS_PWIDTH_32); - - mystique->trap_count++; - - switch (mystique->dwgreg.dwgctrl_running & DWGCTRL_ATYPE_MASK) { - case DWGCTRL_ATYPE_I: - case DWGCTRL_ATYPE_ZI: - z_write = ((mystique->dwgreg.dwgctrl_running & DWGCTRL_ATYPE_MASK) == DWGCTRL_ATYPE_ZI); - - for (y = 0; y < mystique->dwgreg.length; y++) { - uint8_t const * const trans = &trans_masks[trans_sel][(mystique->dwgreg.selline & 3) * 4]; - uint16_t *z_p = (uint16_t *)&svga->vram[(mystique->dwgreg.ydst_lin*2 + mystique->dwgreg.zorg) & mystique->vram_mask]; - int16_t x_l = mystique->dwgreg.fxleft & 0xffff; - int16_t x_r = mystique->dwgreg.fxright & 0xffff; - int16_t old_x_l = x_l; - int dx; - - uint32_t z_back = mystique->dwgreg.dr[0]; - uint32_t r_back = mystique->dwgreg.dr[4]; - uint32_t g_back = mystique->dwgreg.dr[8]; - uint32_t b_back = mystique->dwgreg.dr[12]; - uint32_t s_back = mystique->dwgreg.tmr[6]; - uint32_t t_back = mystique->dwgreg.tmr[7]; - uint32_t q_back = mystique->dwgreg.tmr[8]; - - while (x_l != x_r) { - if (x_l >= mystique->dwgreg.cxleft && x_l <= mystique->dwgreg.cxright && - mystique->dwgreg.ydst_lin >= mystique->dwgreg.ytop && mystique->dwgreg.ydst_lin <= mystique->dwgreg.ybot && - trans[x_l & 3]) { - uint16_t z = ((int32_t)mystique->dwgreg.dr[0] < 0) ? 0 : (mystique->dwgreg.dr[0] >> 15); - uint16_t old_z = z_p[x_l]; - - if (z_check(z, old_z, mystique->dwgreg.dwgctrl_running & DWGCTRL_ZMODE_MASK)) { - int tex_r = 0, tex_g = 0, tex_b = 0; - int ctransp, atransp = 0; - int i_r = 0, i_g = 0, i_b = 0; - - if (!(mystique->dwgreg.dr[4] & (1 << 23))) - i_r = (mystique->dwgreg.dr[4] >> 15) & 0xff; - if (!(mystique->dwgreg.dr[8] & (1 << 23))) - i_g = (mystique->dwgreg.dr[8] >> 15) & 0xff; - if (!(mystique->dwgreg.dr[12] & (1 << 23))) - i_b = (mystique->dwgreg.dr[12] >> 15) & 0xff; - - ctransp = texture_read(mystique, &tex_r, &tex_g, &tex_b, &atransp); - - switch (mystique->dwgreg.texctl & (TEXCTL_TMODULATE | TEXCTL_STRANS | TEXCTL_ITRANS | TEXCTL_DECALCKEY)) { - case 0: - if (ctransp) - goto skip_pixel; - if (atransp) { - tex_r = i_r; - tex_g = i_g; - tex_b = i_b; - } - break; - - case TEXCTL_DECALCKEY: - if (ctransp) { - tex_r = i_r; - tex_g = i_g; - tex_b = i_b; - } - break; - - case (TEXCTL_STRANS | TEXCTL_DECALCKEY): - if (ctransp) - goto skip_pixel; - break; - - case TEXCTL_TMODULATE: - if (ctransp) - goto skip_pixel; - if (mystique->dwgreg.texctl & TEXCTL_TMODULATE) { - tex_r = (tex_r * i_r) >> 8; - tex_g = (tex_g * i_g) >> 8; - tex_b = (tex_b * i_b) >> 8; - } - break; - - case (TEXCTL_TMODULATE | TEXCTL_STRANS): - if (ctransp || atransp) - goto skip_pixel; - if (mystique->dwgreg.texctl & TEXCTL_TMODULATE) { - tex_r = (tex_r * i_r) >> 8; - tex_g = (tex_g * i_g) >> 8; - tex_b = (tex_b * i_b) >> 8; - } - break; - - default: - fatal("Bad TEXCTL %08x %08x\n", mystique->dwgreg.texctl, mystique->dwgreg.texctl & (TEXCTL_TMODULATE | TEXCTL_STRANS | TEXCTL_ITRANS | TEXCTL_DECALCKEY)); - } - - if (dest32) { - ((uint32_t *)svga->vram)[(mystique->dwgreg.ydst_lin + x_l) & mystique->vram_mask_l] = tex_b | (tex_g << 8) | (tex_r << 16); - svga->changedvram[((mystique->dwgreg.ydst_lin + x_l) & mystique->vram_mask_l) >> 10] = changeframecount; - } else { - ((uint16_t *)svga->vram)[(mystique->dwgreg.ydst_lin + x_l) & mystique->vram_mask_w] = dither(mystique, tex_r, tex_g, tex_b, x_l & 1, mystique->dwgreg.selline & 1); - svga->changedvram[((mystique->dwgreg.ydst_lin + x_l) & mystique->vram_mask_w) >> 11] = changeframecount; - } - if (z_write) - z_p[x_l] = z; - } - } -skip_pixel: - x_l++; - mystique->pixel_count++; - - mystique->dwgreg.dr[0] += mystique->dwgreg.dr[2]; - mystique->dwgreg.dr[4] += mystique->dwgreg.dr[6]; - mystique->dwgreg.dr[8] += mystique->dwgreg.dr[10]; - mystique->dwgreg.dr[12] += mystique->dwgreg.dr[14]; - mystique->dwgreg.tmr[6] += mystique->dwgreg.tmr[0]; - mystique->dwgreg.tmr[7] += mystique->dwgreg.tmr[2]; - mystique->dwgreg.tmr[8] += mystique->dwgreg.tmr[4]; - } - - mystique->dwgreg.dr[0] = z_back + mystique->dwgreg.dr[3]; - mystique->dwgreg.dr[4] = r_back + mystique->dwgreg.dr[7]; - mystique->dwgreg.dr[8] = g_back + mystique->dwgreg.dr[11]; - mystique->dwgreg.dr[12] = b_back + mystique->dwgreg.dr[15]; - mystique->dwgreg.tmr[6] = s_back + mystique->dwgreg.tmr[1]; - mystique->dwgreg.tmr[7] = t_back + mystique->dwgreg.tmr[3]; - mystique->dwgreg.tmr[8] = q_back + mystique->dwgreg.tmr[5]; - - while ((int32_t)mystique->dwgreg.ar[1] < 0 && mystique->dwgreg.ar[0]) { - mystique->dwgreg.ar[1] += mystique->dwgreg.ar[0]; - mystique->dwgreg.fxleft += (mystique->dwgreg.sgn.sdxl ? -1 : 1); - } - mystique->dwgreg.ar[1] += mystique->dwgreg.ar[2]; - - while ((int32_t)mystique->dwgreg.ar[4] < 0 && mystique->dwgreg.ar[6]) { - mystique->dwgreg.ar[4] += mystique->dwgreg.ar[6]; - mystique->dwgreg.fxright += (mystique->dwgreg.sgn.sdxr ? -1 : 1); - } - mystique->dwgreg.ar[4] += mystique->dwgreg.ar[5]; - - dx = (int16_t)((mystique->dwgreg.fxleft - old_x_l) & 0xffff); - mystique->dwgreg.dr[0] += dx*mystique->dwgreg.dr[2]; - mystique->dwgreg.dr[4] += dx*mystique->dwgreg.dr[6]; - mystique->dwgreg.dr[8] += dx*mystique->dwgreg.dr[10]; - mystique->dwgreg.dr[12] += dx*mystique->dwgreg.dr[14]; - mystique->dwgreg.tmr[6] += dx*mystique->dwgreg.tmr[0]; - mystique->dwgreg.tmr[7] += dx*mystique->dwgreg.tmr[2]; - mystique->dwgreg.tmr[8] += dx*mystique->dwgreg.tmr[4]; - - mystique->dwgreg.ydst++; - mystique->dwgreg.ydst &= 0x7fffff; - mystique->dwgreg.ydst_lin += (mystique->dwgreg.pitch & PITCH_MASK); - - mystique->dwgreg.selline = (mystique->dwgreg.selline + 1) & 7; - } - break; - - default: - fatal("Unknown atype %03x %08x TEXTURE_TRAP\n", mystique->dwgreg.dwgctrl_running & DWGCTRL_ATYPE_MASK, mystique->dwgreg.dwgctrl_running); - } - - mystique->blitter_complete_refcount++; -} - - -static void -blit_bitblt(mystique_t *mystique) -{ - svga_t *svga = &mystique->svga; - uint32_t src_addr; - int y; - int x_dir = mystique->dwgreg.sgn.scanleft ? -1 : 1; - int16_t x_start = mystique->dwgreg.sgn.scanleft ? mystique->dwgreg.fxright : mystique->dwgreg.fxleft; - int16_t x_end = mystique->dwgreg.sgn.scanleft ? mystique->dwgreg.fxleft : mystique->dwgreg.fxright; - const int trans_sel = (mystique->dwgreg.dwgctrl_running & DWGCTRL_TRANS_MASK) >> DWGCTRL_TRANS_SHIFT; - - switch (mystique->dwgreg.dwgctrl_running & DWGCTRL_ATYPE_MASK) { - case DWGCTRL_ATYPE_BLK: - switch (mystique->dwgreg.dwgctrl_running & DWGCTRL_BLTMOD_MASK) { - case DWGCTRL_BLTMOD_BMONOLEF: - src_addr = mystique->dwgreg.ar[3]; - - for (y = 0; y < mystique->dwgreg.length; y++) { - int16_t x = x_start; - - while (1) { - if (x >= mystique->dwgreg.cxleft && x <= mystique->dwgreg.cxright && - mystique->dwgreg.ydst_lin >= mystique->dwgreg.ytop && mystique->dwgreg.ydst_lin <= mystique->dwgreg.ybot) { - uint32_t byte_addr = (src_addr >> 3) & mystique->vram_mask; - int bit_offset = src_addr & 7; - uint32_t old_dst; - - switch (mystique->maccess_running & MACCESS_PWIDTH_MASK) { - case MACCESS_PWIDTH_8: - if (mystique->dwgreg.dwgctrl_running & DWGCTRL_TRANSC) { - if (svga->vram[byte_addr] & (1 << bit_offset)) - svga->vram[(mystique->dwgreg.ydst_lin + x) & mystique->vram_mask] = mystique->dwgreg.fcol; - } else - svga->vram[(mystique->dwgreg.ydst_lin + x) & mystique->vram_mask] = - (svga->vram[byte_addr] & (1 << bit_offset)) ? mystique->dwgreg.fcol : mystique->dwgreg.bcol; - svga->changedvram[((mystique->dwgreg.ydst_lin + x) & mystique->vram_mask) >> 12] = changeframecount; - break; - - case MACCESS_PWIDTH_16: - if (mystique->dwgreg.dwgctrl_running & DWGCTRL_TRANSC) { - if (svga->vram[byte_addr] & (1 << bit_offset)) - ((uint16_t *)svga->vram)[(mystique->dwgreg.ydst_lin + x) & mystique->vram_mask_w] = mystique->dwgreg.fcol; - } else - ((uint16_t *)svga->vram)[(mystique->dwgreg.ydst_lin + x) & mystique->vram_mask_w] = - (svga->vram[byte_addr] & (1 << bit_offset)) ? mystique->dwgreg.fcol : mystique->dwgreg.bcol; - svga->changedvram[((mystique->dwgreg.ydst_lin + x) & mystique->vram_mask_w) >> 11] = changeframecount; - break; - - case MACCESS_PWIDTH_24: - old_dst = *(uint32_t *)&svga->vram[((mystique->dwgreg.ydst_lin + x) * 3) & mystique->vram_mask]; - if (mystique->dwgreg.dwgctrl_running & DWGCTRL_TRANSC) { - if (svga->vram[byte_addr] & (1 << bit_offset)) - *(uint32_t *)&svga->vram[((mystique->dwgreg.ydst_lin + x) * 3) & mystique->vram_mask] = - (old_dst & 0xff000000) | (mystique->dwgreg.fcol & 0xffffff); - } else - *(uint32_t *)&svga->vram[((mystique->dwgreg.ydst_lin + x) * 3) & mystique->vram_mask] = - (old_dst & 0xff000000) | (((svga->vram[byte_addr] & (1 << bit_offset)) ? mystique->dwgreg.fcol : mystique->dwgreg.bcol) & 0xffffff); - svga->changedvram[(((mystique->dwgreg.ydst_lin + x) * 3) & mystique->vram_mask) >> 12] = changeframecount; - break; - - case MACCESS_PWIDTH_32: - if (mystique->dwgreg.dwgctrl_running & DWGCTRL_TRANSC) { - if (svga->vram[byte_addr] & (1 << bit_offset)) - ((uint32_t *)svga->vram)[(mystique->dwgreg.ydst_lin + x) & mystique->vram_mask_l] = mystique->dwgreg.fcol; - } else - ((uint32_t *)svga->vram)[(mystique->dwgreg.ydst_lin + x) & mystique->vram_mask_l] = - (svga->vram[byte_addr] & (1 << bit_offset)) ? mystique->dwgreg.fcol : mystique->dwgreg.bcol; - svga->changedvram[((mystique->dwgreg.ydst_lin + x) & mystique->vram_mask_l) >> 11] = changeframecount; - break; - - default: - fatal("BITBLT DWGCTRL_ATYPE_BLK unknown MACCESS %i\n", mystique->maccess_running & MACCESS_PWIDTH_MASK); - } - } - - if (src_addr == mystique->dwgreg.ar[0]) { - mystique->dwgreg.ar[0] += mystique->dwgreg.ar[5]; - mystique->dwgreg.ar[3] += mystique->dwgreg.ar[5]; - src_addr = mystique->dwgreg.ar[3]; - } else - src_addr += x_dir; - - if (x != x_end) - x += x_dir; - else - break; - } - - if (mystique->dwgreg.sgn.sdy) - mystique->dwgreg.ydst_lin -= (mystique->dwgreg.pitch & PITCH_MASK); - else - mystique->dwgreg.ydst_lin += (mystique->dwgreg.pitch & PITCH_MASK); - } - break; - - default: - fatal("BITBLT BLK %08x\n", mystique->dwgreg.dwgctrl_running & DWGCTRL_BLTMOD_MASK); - break; - } - break; - - case DWGCTRL_ATYPE_RPL: - if (mystique->maccess_running & MACCESS_TLUTLOAD) { - src_addr = mystique->dwgreg.ar[3]; - - y = mystique->dwgreg.ydst; - - while (mystique->dwgreg.length) { - uint16_t src = ((uint16_t *)svga->vram)[src_addr & mystique->vram_mask_w]; - - mystique->lut[y & 0xff].r = (src >> 11) << 3; - mystique->lut[y & 0xff].g = ((src >> 5) & 0x3f) << 2; - mystique->lut[y & 0xff].b = (src & 0x1f) << 3; - src_addr++; - y++; - mystique->dwgreg.length--; - } - break; - } - case DWGCTRL_ATYPE_RSTR: - switch (mystique->dwgreg.dwgctrl_running & DWGCTRL_BLTMOD_MASK) { - case DWGCTRL_BLTMOD_BMONOLEF: - if (mystique->dwgreg.dwgctrl_running & DWGCTRL_PATTERN) - fatal("BITBLT RPL/RSTR BMONOLEF with pattern\n"); - - src_addr = mystique->dwgreg.ar[3]; - - for (y = 0; y < mystique->dwgreg.length; y++) { - uint8_t const * const trans = &trans_masks[trans_sel][(mystique->dwgreg.selline & 3) * 4]; - int16_t x = x_start; - - while (1) { - uint32_t byte_addr = (src_addr >> 3) & mystique->vram_mask; - int bit_offset = src_addr & 7; - - if (x >= mystique->dwgreg.cxleft && x <= mystique->dwgreg.cxright && - mystique->dwgreg.ydst_lin >= mystique->dwgreg.ytop && mystique->dwgreg.ydst_lin <= mystique->dwgreg.ybot && - ((svga->vram[byte_addr] & (1 << bit_offset)) || !(mystique->dwgreg.dwgctrl_running & DWGCTRL_TRANSC)) && - trans[x & 3]) { - uint32_t src = (svga->vram[byte_addr] & (1 << bit_offset)) ? mystique->dwgreg.fcol : mystique->dwgreg.bcol; - uint32_t dst, old_dst; - - switch (mystique->maccess_running & MACCESS_PWIDTH_MASK) { - case MACCESS_PWIDTH_8: - dst = svga->vram[(mystique->dwgreg.ydst_lin + x) & mystique->vram_mask]; - - dst = bitop(src, dst, mystique->dwgreg.dwgctrl_running); - - svga->vram[(mystique->dwgreg.ydst_lin + x) & mystique->vram_mask] = dst; - svga->changedvram[((mystique->dwgreg.ydst_lin + x) & mystique->vram_mask) >> 12] = changeframecount; - break; - - case MACCESS_PWIDTH_16: - dst = ((uint16_t *)svga->vram)[(mystique->dwgreg.ydst_lin + x) & mystique->vram_mask_w]; - - dst = bitop(src, dst, mystique->dwgreg.dwgctrl_running); - - ((uint16_t *)svga->vram)[(mystique->dwgreg.ydst_lin + x) & mystique->vram_mask_w] = dst; - svga->changedvram[((mystique->dwgreg.ydst_lin + x) & mystique->vram_mask_w) >> 11] = changeframecount; - break; - - case MACCESS_PWIDTH_24: - old_dst = *(uint32_t *)&svga->vram[((mystique->dwgreg.ydst_lin + x) * 3) & mystique->vram_mask]; - - dst = bitop(src, old_dst, mystique->dwgreg.dwgctrl_running);// & DWGCTRL_BOP_MASK - - *(uint32_t *)&svga->vram[((mystique->dwgreg.ydst_lin + x) * 3) & mystique->vram_mask] = (dst & 0xffffff) | (old_dst & 0xff000000); - svga->changedvram[(((mystique->dwgreg.ydst_lin + x) * 3) & mystique->vram_mask) >> 12] = changeframecount; - break; - - default: - fatal("BITBLT RPL BMONOLEF PWIDTH %x %08x\n", mystique->maccess_running & MACCESS_PWIDTH_MASK, mystique->dwgreg.dwgctrl_running); - } - } - - if (src_addr == mystique->dwgreg.ar[0]) { - mystique->dwgreg.ar[0] += mystique->dwgreg.ar[5]; - mystique->dwgreg.ar[3] += mystique->dwgreg.ar[5]; - src_addr = mystique->dwgreg.ar[3]; - } else - src_addr += x_dir; - - if (x != x_end) - x += x_dir; - else - break; - } - - if (mystique->dwgreg.sgn.sdy) - mystique->dwgreg.ydst_lin -= (mystique->dwgreg.pitch & PITCH_MASK); - else - mystique->dwgreg.ydst_lin += (mystique->dwgreg.pitch & PITCH_MASK); - } - break; - - case DWGCTRL_BLTMOD_BFCOL: - case DWGCTRL_BLTMOD_BU32RGB: - src_addr = mystique->dwgreg.ar[3]; - - for (y = 0; y < mystique->dwgreg.length; y++) { - uint8_t const * const trans = &trans_masks[trans_sel][(mystique->dwgreg.selline & 3) * 4]; - uint32_t old_src_addr = src_addr; - int16_t x = x_start; - - while (1) { - if (x >= mystique->dwgreg.cxleft && x <= mystique->dwgreg.cxright && - mystique->dwgreg.ydst_lin >= mystique->dwgreg.ytop && mystique->dwgreg.ydst_lin <= mystique->dwgreg.ybot && - trans[x & 3]) { - uint32_t src, dst, old_dst; - - switch (mystique->maccess_running & MACCESS_PWIDTH_MASK) { - case MACCESS_PWIDTH_8: - src = svga->vram[src_addr & mystique->vram_mask]; - dst = svga->vram[(mystique->dwgreg.ydst_lin + x) & mystique->vram_mask]; - - dst = bitop(src, dst, mystique->dwgreg.dwgctrl_running); - - svga->vram[(mystique->dwgreg.ydst_lin + x) & mystique->vram_mask] = dst; - svga->changedvram[((mystique->dwgreg.ydst_lin + x) & mystique->vram_mask) >> 12] = changeframecount; - break; - - case MACCESS_PWIDTH_16: - src = ((uint16_t *)svga->vram)[src_addr & mystique->vram_mask_w]; - dst = ((uint16_t *)svga->vram)[(mystique->dwgreg.ydst_lin + x) & mystique->vram_mask_w]; - - dst = bitop(src, dst, mystique->dwgreg.dwgctrl_running); - - ((uint16_t *)svga->vram)[(mystique->dwgreg.ydst_lin + x) & mystique->vram_mask_w] = dst; - svga->changedvram[((mystique->dwgreg.ydst_lin + x) & mystique->vram_mask_w) >> 11] = changeframecount; - break; - - case MACCESS_PWIDTH_24: - src = *(uint32_t *)&svga->vram[(src_addr * 3) & mystique->vram_mask]; - old_dst = *(uint32_t *)&svga->vram[((mystique->dwgreg.ydst_lin + x) * 3) & mystique->vram_mask]; - - dst = bitop(src, old_dst, mystique->dwgreg.dwgctrl_running); - - *(uint32_t *)&svga->vram[((mystique->dwgreg.ydst_lin + x) * 3) & mystique->vram_mask] = (dst & 0xffffff) | (old_dst & 0xff000000); - svga->changedvram[(((mystique->dwgreg.ydst_lin + x) * 3) & mystique->vram_mask) >> 12] = changeframecount; - break; - - case MACCESS_PWIDTH_32: - src = ((uint32_t *)svga->vram)[src_addr & mystique->vram_mask_l]; - dst = ((uint32_t *)svga->vram)[(mystique->dwgreg.ydst_lin + x) & mystique->vram_mask_l]; - - dst = bitop(src, dst, mystique->dwgreg.dwgctrl_running); - - ((uint32_t *)svga->vram)[(mystique->dwgreg.ydst_lin + x) & mystique->vram_mask_l] = dst; - svga->changedvram[((mystique->dwgreg.ydst_lin + x) & mystique->vram_mask_l) >> 10] = changeframecount; - break; - - default: - fatal("BITBLT RPL BFCOL PWIDTH %x %08x\n", mystique->maccess_running & MACCESS_PWIDTH_MASK, mystique->dwgreg.dwgctrl_running); - } - } - - if (mystique->dwgreg.dwgctrl_running & DWGCTRL_PATTERN) - src_addr = ((src_addr + x_dir) & 7) | (src_addr & ~7); - else if (src_addr == mystique->dwgreg.ar[0]) { - mystique->dwgreg.ar[0] += mystique->dwgreg.ar[5]; - mystique->dwgreg.ar[3] += mystique->dwgreg.ar[5]; - src_addr = mystique->dwgreg.ar[3]; - } else - src_addr += x_dir; - - if (x != x_end) - x += x_dir; - else - break; - } - - if (mystique->dwgreg.dwgctrl_running & DWGCTRL_PATTERN) { - src_addr = old_src_addr; - if (mystique->dwgreg.sgn.sdy) - src_addr = ((src_addr - 32) & 0xe0) | (src_addr & ~0xe0); - else - src_addr = ((src_addr + 32) & 0xe0) | (src_addr & ~0xe0); - } - - if (mystique->dwgreg.sgn.sdy) - mystique->dwgreg.ydst_lin -= (mystique->dwgreg.pitch & PITCH_MASK); - else - mystique->dwgreg.ydst_lin += (mystique->dwgreg.pitch & PITCH_MASK); - } - break; - - default: - fatal("BITBLT DWGCTRL_ATYPE_RPL unknown BLTMOD %08x %08x\n", mystique->dwgreg.dwgctrl_running & DWGCTRL_BLTMOD_MASK, mystique->dwgreg.dwgctrl_running); - } - break; - - default: - /* pclog("Unknown BITBLT atype %03x %08x\n", mystique->dwgreg.dwgctrl_running & DWGCTRL_ATYPE_MASK, mystique->dwgreg.dwgctrl_running); */ - break; - } - - mystique->blitter_complete_refcount++; -} - - -static void -blit_iload(mystique_t *mystique) -{ - switch (mystique->dwgreg.dwgctrl_running & DWGCTRL_ATYPE_MASK) { - case DWGCTRL_ATYPE_RPL: - case DWGCTRL_ATYPE_RSTR: - case DWGCTRL_ATYPE_BLK: - /* pclog("ILOAD BLTMOD DWGCTRL = %08x\n", mystique->dwgreg.dwgctrl_running & DWGCTRL_BLTMOD_MASK); */ - switch (mystique->dwgreg.dwgctrl_running & DWGCTRL_BLTMOD_MASK) { - case DWGCTRL_BLTMOD_BFCOL: - case DWGCTRL_BLTMOD_BMONOWF: - case DWGCTRL_BLTMOD_BU24RGB: - case DWGCTRL_BLTMOD_BU32RGB: - mystique->dwgreg.length_cur = mystique->dwgreg.length; - mystique->dwgreg.xdst = mystique->dwgreg.fxleft; - mystique->dwgreg.iload_rem_data = 0; - mystique->dwgreg.iload_rem_count = 0; - mystique->busy = 1; - /* pclog("ILOAD busy\n"); */ - mystique->dwgreg.words = 0; - break; - - default: - fatal("ILOAD DWGCTRL_ATYPE_RPL %08x %08x\n", mystique->dwgreg.dwgctrl_running & DWGCTRL_BLTMOD_MASK, mystique->dwgreg.dwgctrl_running); - break; - } - break; - - default: - fatal("Unknown ILOAD atype %03x %08x\n", mystique->dwgreg.dwgctrl_running & DWGCTRL_ATYPE_MASK, mystique->dwgreg.dwgctrl_running); - } -} - - -static void -blit_idump(mystique_t *mystique) -{ - switch (mystique->dwgreg.dwgctrl_running & DWGCTRL_ATYPE_MASK) { - case DWGCTRL_ATYPE_RPL: - mystique->dwgreg.length_cur = mystique->dwgreg.length; - mystique->dwgreg.xdst = mystique->dwgreg.fxleft; - mystique->dwgreg.src_addr = mystique->dwgreg.ar[3]; - mystique->dwgreg.words = 0; - mystique->dwgreg.iload_rem_count = 0; - mystique->dwgreg.iload_rem_data = 0; - mystique->dwgreg.idump_end_of_line = 0; - mystique->busy = 1; - /* pclog("IDUMP ATYPE RPL busy\n"); */ - break; - - default: - fatal("Unknown IDUMP atype %03x %08x\n", mystique->dwgreg.dwgctrl_running & DWGCTRL_ATYPE_MASK, mystique->dwgreg.dwgctrl_running); - } -} - - -static void -blit_iload_scale(mystique_t *mystique) -{ - switch (mystique->dwgreg.dwgctrl_running & DWGCTRL_ATYPE_MASK) { - case DWGCTRL_ATYPE_RPL: - switch (mystique->dwgreg.dwgctrl_running & DWGCTRL_BLTMOD_MASK) { - case DWGCTRL_BLTMOD_BUYUV: - mystique->dwgreg.length_cur = mystique->dwgreg.length; - mystique->dwgreg.xdst = mystique->dwgreg.fxleft; - mystique->dwgreg.iload_rem_data = 0; - mystique->dwgreg.iload_rem_count = 0; - mystique->busy = 1; - mystique->dwgreg.words = 0; - /* pclog("ILOAD SCALE ATYPE RPL BLTMOD BUYUV busy\n"); */ - break; - - default: - fatal("ILOAD_SCALE DWGCTRL_ATYPE_RPL %08x %08x\n", mystique->dwgreg.dwgctrl_running & DWGCTRL_BLTMOD_MASK, mystique->dwgreg.dwgctrl_running); - break; - } - break; - - default: - fatal("Unknown ILOAD_SCALE atype %03x %08x\n", mystique->dwgreg.dwgctrl_running & DWGCTRL_ATYPE_MASK, mystique->dwgreg.dwgctrl_running); - } -} - - -static void -blit_iload_high(mystique_t *mystique) -{ - switch (mystique->dwgreg.dwgctrl_running & DWGCTRL_ATYPE_MASK) { - case DWGCTRL_ATYPE_RPL: - switch (mystique->dwgreg.dwgctrl_running & DWGCTRL_BLTMOD_MASK) { - case DWGCTRL_BLTMOD_BUYUV: - mystique->dwgreg.length_cur = mystique->dwgreg.length; - mystique->dwgreg.xdst = mystique->dwgreg.fxleft; - mystique->dwgreg.iload_rem_data = 0; - mystique->dwgreg.iload_rem_count = 0; - mystique->busy = 1; - mystique->dwgreg.words = 0; - /* pclog("ILOAD HIGH ATYPE RPL BLTMOD BUYUV busy\n"); */ - break; - - default: - fatal("ILOAD_HIGH DWGCTRL_ATYPE_RPL %08x %08x\n", mystique->dwgreg.dwgctrl_running & DWGCTRL_BLTMOD_MASK, mystique->dwgreg.dwgctrl_running); - break; - } - break; - - default: - fatal("Unknown ILOAD_HIGH atype %03x %08x\n", mystique->dwgreg.dwgctrl_running & DWGCTRL_ATYPE_MASK, mystique->dwgreg.dwgctrl_running); - } -} - - -static -void blit_iload_highv(mystique_t *mystique) -{ - switch (mystique->dwgreg.dwgctrl_running & DWGCTRL_ATYPE_MASK) { - case DWGCTRL_ATYPE_RPL: - switch (mystique->dwgreg.dwgctrl_running & DWGCTRL_BLTMOD_MASK) { - case DWGCTRL_BLTMOD_BUYUV: - mystique->dwgreg.length_cur = mystique->dwgreg.length; - mystique->dwgreg.xdst = mystique->dwgreg.fxleft; - mystique->dwgreg.iload_rem_data = 0; - mystique->dwgreg.iload_rem_count = 0; - mystique->busy = 1; - mystique->dwgreg.words = 0; - mystique->dwgreg.highv_line = 0; - mystique->dwgreg.lastpix_r = 0; - mystique->dwgreg.lastpix_g = 0; - mystique->dwgreg.lastpix_b = 0; - /* pclog("ILOAD HIGHV ATYPE RPL BLTMOD BUYUV busy\n"); */ - break; - - default: - fatal("ILOAD_HIGHV DWGCTRL_ATYPE_RPL %08x %08x\n", mystique->dwgreg.dwgctrl_running & DWGCTRL_BLTMOD_MASK, mystique->dwgreg.dwgctrl_running); - break; - } - break; - - default: - fatal("Unknown ILOAD_HIGHV atype %03x %08x\n", mystique->dwgreg.dwgctrl_running & DWGCTRL_ATYPE_MASK, mystique->dwgreg.dwgctrl_running); - } -} - - -static void -mystique_start_blit(mystique_t *mystique) -{ - uint64_t start_time = plat_timer_read(); - uint64_t end_time; - - mystique->dwgreg.dwgctrl_running = mystique->dwgreg.dwgctrl; - mystique->maccess_running = mystique->maccess; - - if (mystique->dwgreg.dwgctrl_running & DWGCTRL_SOLID) { - int x, y; - - for (y = 0; y < 8; y++) { - for (x = 0; x < 8; x++) - mystique->dwgreg.pattern[y][x] = 1; - } - mystique->dwgreg.src[0] = 0xffffffff; - mystique->dwgreg.src[1] = 0xffffffff; - mystique->dwgreg.src[2] = 0xffffffff; - mystique->dwgreg.src[3] = 0xffffffff; - } - if (mystique->dwgreg.dwgctrl_running & DWGCTRL_ARZERO) { - mystique->dwgreg.ar[0] = 0; - mystique->dwgreg.ar[1] = 0; - mystique->dwgreg.ar[2] = 0; - mystique->dwgreg.ar[4] = 0; - mystique->dwgreg.ar[5] = 0; - mystique->dwgreg.ar[6] = 0; - } - if (mystique->dwgreg.dwgctrl_running & DWGCTRL_SGNZERO) { - mystique->dwgreg.sgn.sdydxl = 0; - mystique->dwgreg.sgn.scanleft = 0; - mystique->dwgreg.sgn.sdxl = 0; - mystique->dwgreg.sgn.sdy = 0; - mystique->dwgreg.sgn.sdxr = 0; - } - if (mystique->dwgreg.dwgctrl_running & DWGCTRL_SHTZERO) { - mystique->dwgreg.funcnt = 0; - mystique->dwgreg.stylelen = 0; - mystique->dwgreg.xoff = 0; - mystique->dwgreg.yoff = 0; - } - - switch (mystique->dwgreg.dwgctrl_running & DWGCTRL_OPCODE_MASK) { - case DWGCTRL_OPCODE_LINE_OPEN: - blit_line(mystique, 0); - break; - - case DWGCTRL_OPCODE_AUTOLINE_OPEN: - blit_autoline(mystique, 0); - break; - - case DWGCTRL_OPCODE_AUTOLINE_CLOSE: - blit_autoline(mystique, 1); - break; - - case DWGCTRL_OPCODE_TRAP: - blit_trap(mystique); - break; - - case DWGCTRL_OPCODE_TEXTURE_TRAP: - blit_texture_trap(mystique); - break; - - case DWGCTRL_OPCODE_ILOAD_HIGH: - blit_iload_high(mystique); - break; - - case DWGCTRL_OPCODE_BITBLT: - blit_bitblt(mystique); - break; - - case DWGCTRL_OPCODE_ILOAD: - blit_iload(mystique); - break; - - case DWGCTRL_OPCODE_IDUMP: - blit_idump(mystique); - break; - - case DWGCTRL_OPCODE_ILOAD_SCALE: - blit_iload_scale(mystique); - break; - - case DWGCTRL_OPCODE_ILOAD_HIGHV: - blit_iload_highv(mystique); - break; - - case DWGCTRL_OPCODE_ILOAD_FILTER: - /* TODO: Actually implement this. */ - break; - - default: - fatal("mystique_start_blit: unknown blit %08x\n", mystique->dwgreg.dwgctrl_running); - } - - end_time = plat_timer_read(); - mystique->blitter_time += end_time - start_time; -} - - -static void -mystique_hwcursor_draw(svga_t *svga, int displine) -{ - int x; - uint64_t dat[2]; - int offset = svga->hwcursor_latch.x - svga->hwcursor_latch.xoff; - - if (svga->interlace && svga->hwcursor_oddeven) - svga->hwcursor_latch.addr += 16; - - dat[0] = *(uint64_t *)(&svga->vram[svga->hwcursor_latch.addr]); - dat[1] = *(uint64_t *)(&svga->vram[svga->hwcursor_latch.addr + 8]); - svga->hwcursor_latch.addr += 16; - for (x = 0; x < 64; x ++) { - if (!(dat[1] & (1ull << 63))) - buffer32->line[displine][offset + svga->x_add] = (dat[0] & (1ull << 63)) ? 0xffffff : 0; - else if (dat[0] & (1ull << 63)) - buffer32->line[displine][offset + svga->x_add] ^= 0xffffff; - - offset++; - dat[0] <<= 1; - dat[1] <<= 1; - } - - if (svga->interlace && !svga->hwcursor_oddeven) - svga->hwcursor_latch.addr += 16; -} - - -static -uint8_t mystique_pci_read(int func, int addr, void *p) -{ - mystique_t *mystique = (mystique_t *)p; - uint8_t ret = 0x00; - - if ((addr >= 0x30) && (addr <= 0x33) && !(mystique->pci_regs[0x43] & 0x40)) - ret = 0x00; - else switch (addr) { - case 0x00: ret = 0x2b; break; /*Matrox*/ - case 0x01: ret = 0x10; break; - - case 0x02: ret = 0x1a; break; /*MGA-1064SG*/ - case 0x03: ret = 0x05; break; - - case PCI_REG_COMMAND: - ret = mystique->pci_regs[PCI_REG_COMMAND]; break; /*Respond to IO and memory accesses*/ - - case 0x07: ret = 0 << 1; break; /*Fast DEVSEL timing*/ - - case 0x08: ret = 0; break; /*Revision ID*/ - case 0x09: ret = 0; break; /*Programming interface*/ - - case 0x0a: ret = 0x00; break; /*Supports VGA interface*/ - case 0x0b: ret = 0x03; break; - - case 0x10: ret = 0x00; break; /*Control aperture*/ - case 0x11: ret = (mystique->ctrl_base >> 8) & 0xc0; break; - case 0x12: ret = mystique->ctrl_base >> 16; break; - case 0x13: ret = mystique->ctrl_base >> 24; break; - - case 0x14: ret = 0x00; break; /*Linear frame buffer*/ - case 0x16: ret = (mystique->lfb_base >> 16) & 0x80; break; - case 0x17: ret = mystique->lfb_base >> 24; break; - - case 0x18: ret = 0x00; break; /*Pseudo-DMA (ILOAD)*/ - case 0x1a: ret = (mystique->iload_base >> 16) & 0x80; break; - case 0x1b: ret = mystique->iload_base >> 24; break; - - case 0x30: ret = mystique->pci_regs[0x30] & 0x01; break; /*BIOS ROM address*/ - case 0x31: ret = 0x00; break; - case 0x32: ret = mystique->pci_regs[0x32]; break; - case 0x33: ret = mystique->pci_regs[0x33]; break; - - case 0x3c: ret = mystique->int_line; break; - case 0x3d: ret = PCI_INTA; break; - - case 0x40: ret = mystique->pci_regs[0x40]; break; - case 0x41: ret = mystique->pci_regs[0x41]; break; - case 0x42: ret = mystique->pci_regs[0x42]; break; - case 0x43: ret = mystique->pci_regs[0x43]; break; - - case 0x44: ret = mystique->pci_regs[0x44]; break; - case 0x45: ret = mystique->pci_regs[0x45]; break; - - case 0x48: case 0x49: case 0x4a: case 0x4b: - addr = (mystique->pci_regs[0x44] & 0xfc) | ((mystique->pci_regs[0x45] & 0x3f) << 8) | - (addr & 3); - ret = mystique_ctrl_read_b(addr, mystique); break; - } - - return ret; -} - -static void -mystique_pci_write(int func, int addr, uint8_t val, void *p) -{ - mystique_t *mystique = (mystique_t *)p; - - switch (addr) { - case PCI_REG_COMMAND: - mystique->pci_regs[PCI_REG_COMMAND] = val & 0x23; - mystique_recalc_mapping(mystique); - break; - - case 0x11: - mystique->ctrl_base = (mystique->ctrl_base & 0xffff0000) | ((val & 0xc0) << 8); - mystique_recalc_mapping(mystique); - break; - case 0x12: - mystique->ctrl_base = (mystique->ctrl_base & 0xff00c000) | (val << 16); - mystique_recalc_mapping(mystique); - break; - case 0x13: - mystique->ctrl_base = (mystique->ctrl_base & 0x00ffc000) | (val << 24); - mystique_recalc_mapping(mystique); - break; - - case 0x16: - mystique->lfb_base = (mystique->lfb_base & 0xff000000) | ((val & 0x80) << 16); - mystique_recalc_mapping(mystique); - break; - case 0x17: - mystique->lfb_base = (mystique->lfb_base & 0x00800000) | (val << 24); - mystique_recalc_mapping(mystique); - break; - - case 0x1a: - mystique->iload_base = (mystique->iload_base & 0xff000000) | ((val & 0x80) << 16); - mystique_recalc_mapping(mystique); - break; - case 0x1b: - mystique->iload_base = (mystique->iload_base & 0x00800000) | (val << 24); - mystique_recalc_mapping(mystique); - break; - - case 0x30: case 0x32: case 0x33: - if (!(mystique->pci_regs[0x43] & 0x40)) - return; - mystique->pci_regs[addr] = val; - if (mystique->pci_regs[0x30] & 0x01) { - uint32_t addr = (mystique->pci_regs[0x32] << 16) | (mystique->pci_regs[0x33] << 24); - mem_mapping_set_addr(&mystique->bios_rom.mapping, addr, 0x8000); - } else - mem_mapping_disable(&mystique->bios_rom.mapping); - return; - - case 0x3c: - mystique->int_line = val; - return; - - case 0x40: case 0x41: case 0x42: case 0x43: - mystique->pci_regs[addr] = val; - if (addr == 0x43) { - if (val & 0x40) { - if (mystique->pci_regs[0x30] & 0x01) { - uint32_t addr = (mystique->pci_regs[0x32] << 16) | (mystique->pci_regs[0x33] << 24); - mem_mapping_set_addr(&mystique->bios_rom.mapping, addr, 0x8000); - } else - mem_mapping_disable(&mystique->bios_rom.mapping); - } else - mem_mapping_set_addr(&mystique->bios_rom.mapping, 0x000c0000, 0x8000); - } - break; - - case 0x4c: case 0x4d: case 0x4e: case 0x4f: - mystique->pci_regs[addr-0x20] = val; - break; - - case 0x44: case 0x45: - mystique->pci_regs[addr] = val; - break; - - case 0x48: case 0x49: case 0x4a: case 0x4b: - addr = (mystique->pci_regs[0x44] & 0xfc) | ((mystique->pci_regs[0x45] & 0x3f) << 8) | - (addr & 3); - mystique_ctrl_write_b(addr, val, mystique); - break; - } -} - - - -static void * -mystique_init(const device_t *info) -{ - int c; - mystique_t *mystique = malloc(sizeof(mystique_t)); - wchar_t *romfn; - - memset(mystique, 0, sizeof(mystique_t)); - - if (info->local == 1) - romfn = ROM_MYSTIQUE_220; - else - romfn = ROM_MYSTIQUE; - - rom_init(&mystique->bios_rom, romfn, 0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL); - mem_mapping_disable(&mystique->bios_rom.mapping); - - mystique->vram_size = device_get_config_int("memory"); - mystique->vram_mask = (mystique->vram_size << 20) - 1; - mystique->vram_mask_w = mystique->vram_mask >> 1; - mystique->vram_mask_l = mystique->vram_mask >> 2; - - video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_matrox_mystique); - - svga_init(&mystique->svga, mystique, mystique->vram_size << 20, - mystique_recalctimings, - mystique_in, mystique_out, - mystique_hwcursor_draw, - NULL); - - io_sethandler(0x03c0, 0x0020, mystique_in, NULL, NULL, mystique_out, NULL, NULL, mystique); - mem_mapping_add(&mystique->ctrl_mapping, 0, 0, - mystique_ctrl_read_b, NULL, mystique_ctrl_read_l, - mystique_ctrl_write_b, NULL, mystique_ctrl_write_l, - NULL, 0, mystique); - mem_mapping_disable(&mystique->ctrl_mapping); - - mem_mapping_add(&mystique->lfb_mapping, 0, 0, - svga_read_linear, svga_readw_linear, svga_readl_linear, - svga_write_linear, svga_writew_linear, svga_writel_linear, - NULL, 0, mystique); - mem_mapping_disable(&mystique->lfb_mapping); - - mem_mapping_add(&mystique->iload_mapping, 0, 0, - mystique_iload_read_b, NULL, mystique_iload_read_l, - mystique_iload_write_b, NULL, mystique_iload_write_l, - NULL, 0, mystique); - mem_mapping_disable(&mystique->iload_mapping); - - mystique->card = pci_add_card(PCI_ADD_VIDEO, mystique_pci_read, mystique_pci_write, mystique); - mystique->pci_regs[0x2c] = mystique->bios_rom.rom[0x7ff8]; - mystique->pci_regs[0x2d] = mystique->bios_rom.rom[0x7ff8]; - mystique->pci_regs[0x2e] = mystique->bios_rom.rom[0x7ff8]; - mystique->pci_regs[0x2f] = mystique->bios_rom.rom[0x7ff8]; - - mystique->svga.miscout = 1; - mystique->pci_regs[0x41] = 0x01; /* vgaboot = 1 */ - mystique->pci_regs[0x43] = 0x40; /* biosen = 1 */ - - for (c = 0; c < 256; c++) { - dither5[c][0][0] = c >> 3; - dither5[c][1][1] = (c + 2) >> 3; - dither5[c][1][0] = (c + 4) >> 3; - dither5[c][0][1] = (c + 6) >> 3; - - if (dither5[c][1][1] > 31) - dither5[c][1][1] = 31; - if (dither5[c][1][0] > 31) - dither5[c][1][0] = 31; - if (dither5[c][0][1] > 31) - dither5[c][0][1] = 31; - - dither6[c][0][0] = c >> 2; - dither6[c][1][1] = (c + 1) >> 2; - dither6[c][1][0] = (c + 2) >> 2; - dither6[c][0][1] = (c + 3) >> 2; - - if (dither6[c][1][1] > 63) - dither6[c][1][1] = 63; - if (dither6[c][1][0] > 63) - dither6[c][1][0] = 63; - if (dither6[c][0][1] > 63) - dither6[c][0][1] = 63; - } - - mystique->wake_fifo_thread = thread_create_event(); - mystique->fifo_not_full_event = thread_create_event(); - mystique->fifo_thread = thread_create(fifo_thread, mystique); - mystique->dma.lock = thread_create_mutex(L"86Box.MGAMutex"); - - timer_add(&mystique->wake_timer, mystique_wake_timer, (void *)mystique, 0); - timer_add(&mystique->softrap_pending_timer, mystique_softrap_pending_timer, (void *)mystique, 1); - - mystique->status = STATUS_ENDPRDMASTS; - - return mystique; -} - - -static void -mystique_close(void *p) -{ - mystique_t *mystique = (mystique_t *)p; - - thread_kill(mystique->fifo_thread); - thread_destroy_event(mystique->wake_fifo_thread); - thread_destroy_event(mystique->fifo_not_full_event); - thread_close_mutex(mystique->dma.lock); - - svga_close(&mystique->svga); - - free(mystique); -} - - -static int -mystique_available(void) -{ - return rom_present(ROM_MYSTIQUE); -} - - -static int -mystique_220_available(void) -{ - return rom_present(ROM_MYSTIQUE_220); -} - - -static void -mystique_speed_changed(void *p) -{ - mystique_t *mystique = (mystique_t *)p; - - svga_recalctimings(&mystique->svga); -} - - -static void -mystique_force_redraw(void *p) -{ - mystique_t *mystique = (mystique_t *)p; - - mystique->svga.fullchange = changeframecount; -} - - -static const device_config_t mystique_config[] = -{ - { - .name = "memory", - .description = "Memory size", - .type = CONFIG_SELECTION, - .selection = - { - { - .description = "2 MB", - .value = 2 - }, - { - .description = "4 MB", - .value = 4 - }, - { - .description = "8 MB", - .value = 8 - }, - { - .description = "" - } - }, - .default_int = 8 - }, - { - .type = -1 - } -}; - - -const device_t mystique_device = -{ - "Matrox Mystique", - DEVICE_PCI, - 0, - mystique_init, - mystique_close, - NULL, - mystique_available, - mystique_speed_changed, - mystique_force_redraw, - mystique_config -}; - - -const device_t mystique_220_device = -{ - "Matrox Mystique 220", - DEVICE_PCI, - 1, - mystique_init, - mystique_close, - NULL, - mystique_220_available, - mystique_speed_changed, - mystique_force_redraw, - mystique_config -}; diff --git a/src/video/vid_mga.c b/src/video/vid_mga.c index 332dfb09a..fd27f7a54 100644 --- a/src/video/vid_mga.c +++ b/src/video/vid_mga.c @@ -4765,7 +4765,7 @@ mystique_pci_write(int func, int addr, uint8_t val, void *p) case 0x48: case 0x49: case 0x4a: case 0x4b: addr = (mystique->pci_regs[0x44] & 0xfc) | ((mystique->pci_regs[0x45] & 0x3f) << 8) | (addr & 3); - pclog("mystique_ctrl_write_b(%04X, %02X)\n", addr, val); + /* pclog("mystique_ctrl_write_b(%04X, %02X)\n", addr, val); */ mystique_ctrl_write_b(addr, val, mystique); break; }