From 1a7bcec0f41a475ed73eae915ecab7cd0d3b0ae6 Mon Sep 17 00:00:00 2001 From: OBattler Date: Tue, 13 Apr 2021 00:31:09 +0200 Subject: [PATCH 1/5] The Soyo 4SA2 now correctly has the Winbond W83787F Super I/O chip. --- src/machine/m_at_386dx_486.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/machine/m_at_386dx_486.c b/src/machine/m_at_386dx_486.c index 3fc72e971..1852f9846 100644 --- a/src/machine/m_at_386dx_486.c +++ b/src/machine/m_at_386dx_486.c @@ -887,7 +887,7 @@ machine_at_4sa2_init(const machine_t *model) pci_register_slot(0x0F, PCI_CARD_NORMAL, 3, 4, 1, 2); pci_register_slot(0x11, PCI_CARD_NORMAL, 4, 1, 2, 3); - device_add(&pc87332_device); + device_add(&w83787f_device); device_add(&keyboard_ps2_pci_device); device_add(&intel_flash_bxt_device); From 77c18c0708a9b458e38e037d24ca0cebc5531315 Mon Sep 17 00:00:00 2001 From: OBattler Date: Tue, 13 Apr 2021 01:18:56 +0200 Subject: [PATCH 2/5] Improved the status bar's handling of hard disks and other storage devices on internal controllers. --- src/win/win_stbar.c | 58 ++++++++++++++++++++++++++------------------- 1 file changed, 33 insertions(+), 25 deletions(-) diff --git a/src/win/win_stbar.c b/src/win/win_stbar.c index 58566ab71..3ae3f0f5c 100644 --- a/src/win/win_stbar.c +++ b/src/win/win_stbar.c @@ -432,7 +432,8 @@ ui_sb_set_ready(int ready) void ui_sb_update_panes(void) { - int i, id, hdint; + int i, id; + int mfm_int, xta_int, esdi_int, ide_int, scsi_int; int edge = 0; int c_mfm, c_esdi, c_xta; int c_ide, c_scsi; @@ -446,7 +447,12 @@ ui_sb_update_panes(void) sb_ready = 0; } - hdint = (machines[machine].flags & MACHINE_HDC) ? 1 : 0; + mfm_int = (machines[machine].flags & MACHINE_MFM) ? 1 : 0; + xta_int = (machines[machine].flags & MACHINE_XTA) ? 1 : 0; + esdi_int = (machines[machine].flags & MACHINE_ESDI) ? 1 : 0; + ide_int = (machines[machine].flags & MACHINE_IDE_QUAD) ? 1 : 0; + scsi_int = (machines[machine].flags & MACHINE_SCSI_DUAL) ? 1 : 0; + c_mfm = hdd_count(HDD_BUS_MFM); c_esdi = hdd_count(HDD_BUS_ESDI); c_xta = hdd_count(HDD_BUS_XTA); @@ -487,11 +493,11 @@ ui_sb_update_panes(void) for (i=0; i Date: Tue, 13 Apr 2021 02:33:40 +0200 Subject: [PATCH 3/5] The Intel 420TX and 420ZX chipsets now correctly have 57h as the SMRAM control register (identified by register write logging on the ASUS P/I-486SP3G) rather than 72h, fixes hangs and errors on the ASUS P/I-486SP3G. --- src/chipset/intel_4x0.c | 64 ++++++++++++++++++++++++++++++++--------- src/mem/mem.c | 2 +- 2 files changed, 51 insertions(+), 15 deletions(-) diff --git a/src/chipset/intel_4x0.c b/src/chipset/intel_4x0.c index 5a7b79e3c..2f0c7cc39 100644 --- a/src/chipset/intel_4x0.c +++ b/src/chipset/intel_4x0.c @@ -120,20 +120,22 @@ i4x0_smram_handler_phase0(i4x0_t *dev) static void i4x0_smram_handler_phase1(i4x0_t *dev) { + uint8_t *regs = (uint8_t *) dev->regs; uint32_t tom = (mem_size << 10); + uint8_t *reg = (dev->type >= INTEL_430LX) ? &(regs[0x72]) : &(regs[0x57]); uint8_t *ext_reg = (dev->type >= INTEL_440BX) ? &(regs[0x73]) : &(regs[0x71]); uint32_t s, base[2] = { 0x000a0000, 0x00000000 }; uint32_t size[2] = { 0x00010000, 0x00000000 }; - if (dev->type >= INTEL_430FX) { + if ((dev->type <= INTEL_420ZX) || (dev->type >= INTEL_430FX)) { /* Set temporary bases and sizes. */ if (((dev->type == INTEL_430TX) || (dev->type >= INTEL_440BX)) && (*ext_reg & 0x80)) { base[0] = 0x100a0000; size[0] = 0x00060000; - } else if (((dev->type == INTEL_440LX) || (dev->type == INTEL_440EX)) && ((regs[0x72] & 0x07) == 0x04)) { + } else if (((dev->type == INTEL_440LX) || (dev->type == INTEL_440EX)) && ((*reg & 0x07) == 0x04)) { base[0] = 0x000c0000; size[0] = 0x00010000; } else { @@ -141,11 +143,11 @@ i4x0_smram_handler_phase1(i4x0_t *dev) size[0] = 0x00020000; } - if (regs[0x72] & 0x08) + if (*reg & 0x08) smram_enable(dev->smram_low, base[0], base[0] & 0x000f0000, size[0], - ((regs[0x72] & 0x78) == 0x48), (regs[0x72] & 0x08)); + ((*reg & 0x78) == 0x48), (*reg & 0x08)); - if ((regs[0x72] & 0x28) == 0x28) { + if ((*reg & 0x28) == 0x28) { /* If SMRAM is enabled and DCLS is set, then data goes to PCI, but code still goes to DRAM. */ mem_set_mem_state_smram_ex(1, base[0], size[0], 0x02); @@ -153,7 +155,7 @@ i4x0_smram_handler_phase1(i4x0_t *dev) /* TSEG mapping. */ if ((dev->type == INTEL_430TX) || (dev->type >= INTEL_440BX)) { - if ((regs[0x72] & 0x08) && (*ext_reg & 0x01)) { + if ((*reg & 0x08) && (*ext_reg & 0x01)) { size[1] = (1 << (17 + ((*ext_reg >> 1) & 0x03))); tom -= size[1]; base[1] = tom; @@ -169,7 +171,7 @@ i4x0_smram_handler_phase1(i4x0_t *dev) } } else { size[0] = 0x00010000; - switch (regs[0x72] & 0x03) { + switch (*reg & 0x03) { case 0: default: base[0] = (mem_size << 10) - size[0]; @@ -191,9 +193,9 @@ i4x0_smram_handler_phase1(i4x0_t *dev) if (size[0] != 0x00000000) { smram_enable(dev->smram_low, base[0], base[0], size[0], - (((regs[0x72] & 0x38) == 0x20) || s), 1); + (((*reg & 0x38) == 0x20) || s), 1); - if (regs[0x72] & 0x10) { + if (*reg & 0x10) { /* If SMRAM is enabled and DCLS is set, then data goes to PCI, but code still goes to DRAM. */ mem_set_mem_state_smram_ex(1, base[0], size[0], 0x02); @@ -517,7 +519,19 @@ i4x0_write(int func, int addr, uint8_t val, void *priv) break; case 0x57: switch (dev->type) { + /* On the 420TX and 420ZX, this is the SMRAM space register. */ case INTEL_420TX: case INTEL_420ZX: + i4x0_smram_handler_phase0(dev); + if (dev->smram_locked) + regs[0x57] = (regs[0x57] & 0xdf) | (val & 0x20); + else { + regs[0x57] = (regs[0x57] & 0x87) | (val & 0x78); + dev->smram_locked = (val & 0x10); + if (dev->smram_locked) + regs[0x57] &= 0xbf; + } + i4x0_smram_handler_phase1(dev); + break; case INTEL_430LX: default: regs[0x57] = val & 0x3f; break; @@ -824,6 +838,9 @@ i4x0_write(int func, int addr, uint8_t val, void *priv) } break; case 0x72: /* SMRAM */ + if (dev->type <= INTEL_420ZX) + break; + i4x0_smram_handler_phase0(dev); if (dev->type >= INTEL_430FX) { if (dev->smram_locked) @@ -1215,6 +1232,10 @@ i4x0_reset(void *priv) i4x0_t *dev = (i4x0_t *)priv; int i; + if ((dev->type == INTEL_440LX) || (dev->type == INTEL_440BX) || + (dev->type == INTEL_440ZX)) + memset(dev->regs_locked, 0x00, 256 * sizeof(uint8_t)); + if (dev->type >= INTEL_430FX) i4x0_write(0, 0x59, 0x00, priv); else @@ -1229,14 +1250,18 @@ i4x0_reset(void *priv) if (dev->type >= INTEL_430FX) { dev->regs[0x72] &= 0xef; /* Forcibly unlock the SMRAM register. */ i4x0_write(0, 0x72, 0x02, priv); - } else { + } else if (dev->type >= INTEL_430LX) { dev->regs[0x72] &= 0xf7; /* Forcibly unlock the SMRAM register. */ i4x0_write(0, 0x72, 0x00, priv); + } else { + dev->regs[0x57] &= 0xef; /* Forcibly unlock the SMRAM register. */ + i4x0_write(0, 0x57, 0x02, priv); } - if ((dev->type == INTEL_440LX) || (dev->type == INTEL_440BX) || - (dev->type == INTEL_440ZX)) - memset(dev->regs_locked, 0x00, 256 * sizeof(uint8_t)); + if ((dev->type == INTEL_430TX) || (dev->type >= INTEL_440BX)) { + i4x0_write(0, (dev->type >= INTEL_440BX) ? 0x73 : 0x71, + (dev->type >= INTEL_440BX) ? 0x38 : 0x00, priv); + } } @@ -1554,7 +1579,18 @@ static void i4x0_write(regs[0x5d], 0x5d, 0x00, dev); i4x0_write(regs[0x5e], 0x5e, 0x00, dev); i4x0_write(regs[0x5f], 0x5f, 0x00, dev); - i4x0_write(regs[0x72], 0x72, 0x00, dev); + + if (dev->type >= INTEL_430FX) + i4x0_write(0, 0x72, 0x02, dev); + else if (dev->type >= INTEL_430LX) + i4x0_write(0, 0x72, 0x00, dev); + else + i4x0_write(0, 0x57, 0x02, dev); + + if ((dev->type == INTEL_430TX) || (dev->type >= INTEL_440BX)) { + i4x0_write(0, (dev->type >= INTEL_440BX) ? 0x73 : 0x71, + (dev->type >= INTEL_440BX) ? 0x38 : 0x00, dev); + } pci_add_card(PCI_ADD_NORTHBRIDGE, i4x0_read, i4x0_write, dev); diff --git a/src/mem/mem.c b/src/mem/mem.c index 000937341..1d54d7880 100644 --- a/src/mem/mem.c +++ b/src/mem/mem.c @@ -691,7 +691,7 @@ getpccache(uint32_t a) return &_mem_exec[a64 >> MEM_GRANULARITY_BITS][(uintptr_t)(a64 & MEM_GRANULARITY_PAGE) - (uintptr_t)(a2 & ~0xfff)]; } - mem_log("Bad getpccache %08X%08X\n", (uint32_t) (a >> 32), (uint32_t) (a & 0xffffffff)); + mem_log("Bad getpccache %08X%08X\n", (uint32_t) (a64 >> 32), (uint32_t) (a64 & 0xffffffffULL)); return (uint8_t *)&ff_pccache; } From 5a228ba8dbe954068eee69907cd57698cb959f76 Mon Sep 17 00:00:00 2001 From: OBattler Date: Tue, 13 Apr 2021 02:35:13 +0200 Subject: [PATCH 4/5] Removed excess logging from intel_sio.c. --- src/chipset/intel_sio.c | 1 - 1 file changed, 1 deletion(-) diff --git a/src/chipset/intel_sio.c b/src/chipset/intel_sio.c index d456c96df..ed1c141b1 100644 --- a/src/chipset/intel_sio.c +++ b/src/chipset/intel_sio.c @@ -218,7 +218,6 @@ sio_write(int func, int addr, uint8_t val, void *priv) break; case 0x60: case 0x61: case 0x62: case 0x63: if (dev->id == 0x03) { - pclog("Set IRQ routing: INT %c -> %02X\n", 0x41 + (addr & 0x03), val); sio_log("Set IRQ routing: INT %c -> %02X\n", 0x41 + (addr & 0x03), val); dev->regs[addr] = val & 0x8f; if (val & 0x80) From 76f3f08d785597ea00c7f29bc70fb81a22577a87 Mon Sep 17 00:00:00 2001 From: OBattler Date: Tue, 13 Apr 2021 03:47:46 +0200 Subject: [PATCH 5/5] The Intel SIO and PIIX* southbridges now have the undocumented (by the datasheets, but fully documented by the Intel motherboard technical specifications) second PIT on ports 48h-4Bh. --- src/chipset/intel_piix.c | 2 ++ src/chipset/intel_sio.c | 2 ++ src/include/86box/pit.h | 1 + src/pit.c | 18 ++++++++++++++++-- 4 files changed, 21 insertions(+), 2 deletions(-) diff --git a/src/chipset/intel_piix.c b/src/chipset/intel_piix.c index 2c6ed1500..50d345448 100644 --- a/src/chipset/intel_piix.c +++ b/src/chipset/intel_piix.c @@ -1374,6 +1374,8 @@ static void else dev->board_config[1] |= 0x00; + device_add(&i8254_sec_device); + return dev; } diff --git a/src/chipset/intel_sio.c b/src/chipset/intel_sio.c index ed1c141b1..91f9128a0 100644 --- a/src/chipset/intel_sio.c +++ b/src/chipset/intel_sio.c @@ -539,6 +539,8 @@ sio_init(const device_t *info) timer_add(&dev->timer, NULL, NULL, 0); + device_add(&i8254_sec_device); + return dev; } diff --git a/src/include/86box/pit.h b/src/include/86box/pit.h index 027955c69..bf8d71048 100644 --- a/src/include/86box/pit.h +++ b/src/include/86box/pit.h @@ -109,6 +109,7 @@ extern void pit_handler(int set, uint16_t base, int size, void *priv); #ifdef EMU_DEVICE_H extern const device_t i8253_device; extern const device_t i8254_device; +extern const device_t i8254_sec_device; extern const device_t i8254_ext_io_device; extern const device_t i8254_ps2_device; #endif diff --git a/src/pit.c b/src/pit.c index a4b865f1c..9db4c45dd 100644 --- a/src/pit.c +++ b/src/pit.c @@ -63,6 +63,7 @@ int64_t firsttime = 1; #define PIT_PS2 16 /* The PIT is the PS/2's second PIT. */ #define PIT_EXT_IO 32 /* The PIT has externally specified port I/O. */ #define PIT_CUSTOM_CLOCK 64 /* The PIT uses custom clock inputs provided by another provider. */ +#define PIT_SECONDARY 128 /* The PIT is secondary (ports 0048-004B). */ enum { @@ -826,8 +827,10 @@ pit_init(const device_t *info) dev->flags = info->local; - if (!(dev->flags & PIT_EXT_IO)) - io_sethandler(0x0040, 0x0004, pit_read, NULL, NULL, pit_write, NULL, NULL, dev); + if (!(dev->flags & PIT_EXT_IO)) { + io_sethandler((dev->flags & PIT_SECONDARY) ? 0x0048 : 0x0040, 0x0004, + pit_read, NULL, NULL, pit_write, NULL, NULL, dev); + } return dev; } @@ -855,6 +858,17 @@ const device_t i8254_device = }; +const device_t i8254_sec_device = +{ + "Intel 8254 Programmable Interval Timer (Secondary)", + DEVICE_ISA, + PIT_8254 | PIT_SECONDARY, + pit_init, pit_close, NULL, + { NULL }, NULL, NULL, + NULL +}; + + const device_t i8254_ext_io_device = { "Intel 8254 Programmable Interval Timer (External I/O)",