Applied all mainline PCem commits;

Added experimental NVidia Riva TNT2 emulation (patch from MoochMcGee);
ASUS P/I-P54TP4XE, ASUS P/I-P55T2P4, and ASUS P/I-P55TVP4 are back;
National Semiconductor PC87306 Super I/O chip now correctly reenables devices after a chip power cycle;
Several FDC improvements and the behavior is now a bit closer to real hardware (based on actual tests);
Added MR Intel Advanced/ATX with Microid Research BIOS with support for 4 floppy drives and up to 4 IDE controllers;
Added floppy drives 3 and 4, bringing the maximum to 4;
You can now connect hard disks to the tertiary IDE controller;
Correct undocumented behavior of the LEA instruction with register is back on 286 and later CPU's;
Pentium-rea models with Intel chipsets now have port 92 (with alternate reset and alternate A20 toggle);
Overhauled DMA channel read and write routines and fixed cascading;
Improved IMG detection of a bad BPB (or complete lack of a BPB);
Added preliminary emulation of PS/2 1.44 MB and PC-98 1.25 MB 3-mode drives (both have an inverted DENSEL pin);
Removed the incorrect Amstrad mouse patch from TheCollector1995;
Fixed ATAPI CD-ROM disk change detection;
Windows IOCTL CD-ROM handler now tries to use direct SCSI passthrough for more things, including obtaining CD-ROM capacity;
The Diamond Stealth32 (ET4000/W32p) now also works correctly on the two Award SiS 496/497 boxes;
The (S)VGA handler now converts 6-bit RAMDAC RGB channels to standard 8-bit RGB using a lookup table generated at emulator start, calculated using the correct intensity conversion method and treating intensity 64 as equivalent to 63;
Moved a few options from the Configuration dialog box to the menu;
SIO, PIIX, and PIIX3 now have the reset control register on port CF9 as they should;
Several bugfixes.

src/808x.c

@@ -101,7 +101,6 @@ int oldcpl;
 
 int tempc;
 uint8_t opcode;
-int times=0;
 uint16_t pc2,pc3;
 int noint=0;
 
@@ -640,6 +639,8 @@ void resetx86()
                 cr0 = 1 << 30;
         else
                 cr0 = 0;
+        cpu_cache_int_enabled = 0;
+        cpu_update_waitstates();
         cr4 = 0;
         eflags=0;
         cgate32=0;
@@ -667,6 +668,7 @@ void resetx86()
         x86seg_reset();
         codegen_reset();
         x86_was_reset = 1;
+	port_92_clear_reset();
 }
 
 void softresetx86()
@@ -689,6 +691,7 @@ void softresetx86()
         idt.base = 0;
         x86seg_reset();
         x86_was_reset = 1;
+	port_92_clear_reset();
 }
 
 static void setznp8(uint8_t val)