Applied all mainline PCem commits;
Added experimental NVidia Riva TNT2 emulation (patch from MoochMcGee); ASUS P/I-P54TP4XE, ASUS P/I-P55T2P4, and ASUS P/I-P55TVP4 are back; National Semiconductor PC87306 Super I/O chip now correctly reenables devices after a chip power cycle; Several FDC improvements and the behavior is now a bit closer to real hardware (based on actual tests); Added MR Intel Advanced/ATX with Microid Research BIOS with support for 4 floppy drives and up to 4 IDE controllers; Added floppy drives 3 and 4, bringing the maximum to 4; You can now connect hard disks to the tertiary IDE controller; Correct undocumented behavior of the LEA instruction with register is back on 286 and later CPU's; Pentium-rea models with Intel chipsets now have port 92 (with alternate reset and alternate A20 toggle); Overhauled DMA channel read and write routines and fixed cascading; Improved IMG detection of a bad BPB (or complete lack of a BPB); Added preliminary emulation of PS/2 1.44 MB and PC-98 1.25 MB 3-mode drives (both have an inverted DENSEL pin); Removed the incorrect Amstrad mouse patch from TheCollector1995; Fixed ATAPI CD-ROM disk change detection; Windows IOCTL CD-ROM handler now tries to use direct SCSI passthrough for more things, including obtaining CD-ROM capacity; The Diamond Stealth32 (ET4000/W32p) now also works correctly on the two Award SiS 496/497 boxes; The (S)VGA handler now converts 6-bit RAMDAC RGB channels to standard 8-bit RGB using a lookup table generated at emulator start, calculated using the correct intensity conversion method and treating intensity 64 as equivalent to 63; Moved a few options from the Configuration dialog box to the menu; SIO, PIIX, and PIIX3 now have the reset control register on port CF9 as they should; Several bugfixes.
This commit is contained in:
OBattler
@@ -504,3 +504,153 @@ static uint32_t ropMOVSX_l_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
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return op_pc + 1;
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}
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static uint32_t ropMOV_w_seg(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
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{
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int host_reg;
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switch (fetchdat & 0x38)
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{
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case 0x00: /*ES*/
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host_reg = LOAD_VAR_WL(&ES);
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break;
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case 0x08: /*CS*/
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host_reg = LOAD_VAR_WL(&CS);
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break;
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case 0x18: /*DS*/
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host_reg = LOAD_VAR_WL(&DS);
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break;
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case 0x10: /*SS*/
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host_reg = LOAD_VAR_WL(&SS);
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break;
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case 0x20: /*FS*/
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host_reg = LOAD_VAR_WL(&FS);
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break;
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case 0x28: /*GS*/
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host_reg = LOAD_VAR_WL(&GS);
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break;
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default:
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return 0;
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}
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if ((fetchdat & 0xc0) == 0xc0)
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{
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if (op_32 & 0x100)
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STORE_REG_TARGET_L_RELEASE(host_reg, fetchdat & 7);
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else
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STORE_REG_TARGET_W_RELEASE(host_reg, fetchdat & 7);
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}
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else
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{
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x86seg *target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
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STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
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CHECK_SEG_WRITE(target_seg);
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CHECK_SEG_LIMITS(target_seg, 1);
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MEM_STORE_ADDR_EA_W(target_seg, host_reg);
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RELEASE_REG(host_reg);
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}
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return op_pc + 1;
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}
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static uint32_t ropMOV_seg_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
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{
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int host_reg;
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switch (fetchdat & 0x38)
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{
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case 0x00: /*ES*/
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case 0x18: /*DS*/
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case 0x20: /*FS*/
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case 0x28: /*GS*/
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break;
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case 0x10: /*SS*/
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default:
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return 0;
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}
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STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
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if ((fetchdat & 0xc0) == 0xc0)
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host_reg = LOAD_REG_W(fetchdat & 7);
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else
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{
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x86seg *target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32);
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CHECK_SEG_READ(target_seg);
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MEM_LOAD_ADDR_EA_W(target_seg);
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host_reg = 0;
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}
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switch (fetchdat & 0x38)
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{
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case 0x00: /*ES*/
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LOAD_SEG(host_reg, &_es);
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break;
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case 0x18: /*DS*/
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LOAD_SEG(host_reg, &_ds);
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break;
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case 0x20: /*FS*/
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LOAD_SEG(host_reg, &_fs);
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break;
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case 0x28: /*GS*/
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LOAD_SEG(host_reg, &_gs);
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break;
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}
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return op_pc + 1;
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}
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#define ropLseg(seg, rseg) \
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static uint32_t ropL ## seg(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block) \
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{ \
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int dest_reg = (fetchdat >> 3) & 7; \
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x86seg *target_seg; \
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\
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if ((fetchdat & 0xc0) == 0xc0) \
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return 0; \
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\
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STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc); \
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target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32); \
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SAVE_EA(); \
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\
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if (op_32 & 0x100) \
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{ \
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MEM_LOAD_ADDR_EA_L(target_seg); \
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STORE_HOST_REG_ADDR((uintptr_t)&codegen_temp, 0); \
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LOAD_EA(); \
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MEM_LOAD_ADDR_EA_W_OFFSET(target_seg, 4); \
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} \
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else \
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{ \
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MEM_LOAD_ADDR_EA_W(target_seg); \
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STORE_HOST_REG_ADDR_W((uintptr_t)&codegen_temp, 0); \
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LOAD_EA(); \
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MEM_LOAD_ADDR_EA_W_OFFSET(target_seg, 2); \
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} \
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LOAD_SEG(0, &rseg); \
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if (op_32 & 0x100) \
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{ \
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\
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int host_reg = LOAD_VAR_L((uintptr_t)&codegen_temp); \
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STORE_REG_TARGET_L_RELEASE(host_reg, dest_reg); \
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} \
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else \
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{ \
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int host_reg = LOAD_VAR_W((uintptr_t)&codegen_temp); \
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STORE_REG_TARGET_W_RELEASE(host_reg, dest_reg); \
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} \
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\
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if (&rseg == &_ss) \
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CPU_BLOCK_END(); /*Instruction might change stack size, so end block here*/ \
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return op_pc + 1; \
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}
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ropLseg(DS, _ds)
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ropLseg(ES, _es)
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ropLseg(FS, _fs)
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ropLseg(GS, _gs)
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ropLseg(SS, _ss)
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