Applied all mainline PCem commits;
Added experimental NVidia Riva TNT2 emulation (patch from MoochMcGee); ASUS P/I-P54TP4XE, ASUS P/I-P55T2P4, and ASUS P/I-P55TVP4 are back; National Semiconductor PC87306 Super I/O chip now correctly reenables devices after a chip power cycle; Several FDC improvements and the behavior is now a bit closer to real hardware (based on actual tests); Added MR Intel Advanced/ATX with Microid Research BIOS with support for 4 floppy drives and up to 4 IDE controllers; Added floppy drives 3 and 4, bringing the maximum to 4; You can now connect hard disks to the tertiary IDE controller; Correct undocumented behavior of the LEA instruction with register is back on 286 and later CPU's; Pentium-rea models with Intel chipsets now have port 92 (with alternate reset and alternate A20 toggle); Overhauled DMA channel read and write routines and fixed cascading; Improved IMG detection of a bad BPB (or complete lack of a BPB); Added preliminary emulation of PS/2 1.44 MB and PC-98 1.25 MB 3-mode drives (both have an inverted DENSEL pin); Removed the incorrect Amstrad mouse patch from TheCollector1995; Fixed ATAPI CD-ROM disk change detection; Windows IOCTL CD-ROM handler now tries to use direct SCSI passthrough for more things, including obtaining CD-ROM capacity; The Diamond Stealth32 (ET4000/W32p) now also works correctly on the two Award SiS 496/497 boxes; The (S)VGA handler now converts 6-bit RAMDAC RGB channels to standard 8-bit RGB using a lookup table generated at emulator start, calculated using the correct intensity conversion method and treating intensity 64 as equivalent to 63; Moved a few options from the Configuration dialog box to the menu; SIO, PIIX, and PIIX3 now have the reset control register on port CF9 as they should; Several bugfixes.
This commit is contained in:
12
src/cpu.h
12
src/cpu.h
@@ -78,14 +78,19 @@ typedef struct
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uint32_t cpuid_model;
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uint16_t cyrix_id;
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int cpu_flags;
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int mem_read_cycles, mem_write_cycles;
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int cache_read_cycles, cache_write_cycles;
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} CPU;
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extern CPU cpus_8088[];
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extern CPU cpus_8086[];
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extern CPU cpus_286[];
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extern CPU cpus_i386[];
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extern CPU cpus_i386DX[];
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extern CPU cpus_Am386[];
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extern CPU cpus_Am386DX[];
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extern CPU cpus_486SDLC[];
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extern CPU cpus_486DLC[];
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extern CPU cpus_i486[];
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extern CPU cpus_Am486[];
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extern CPU cpus_Cx486[];
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@@ -129,6 +134,11 @@ extern uint64_t cpu_CR4_mask;
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#define CPU_REQUIRES_DYNAREC 2
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// #define CPU_REQUIRES_DYNAREC 0
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extern int cpu_cycles_read, cpu_cycles_read_l, cpu_cycles_write, cpu_cycles_write_l;
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extern int cpu_prefetch_cycles, cpu_prefetch_width;
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extern int cpu_waitstates;
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extern int cpu_cache_int_enabled, cpu_cache_ext_enabled;
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extern uint64_t tsc;
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void cyrix_write(uint16_t addr, uint8_t val, void *priv);
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@@ -149,4 +159,6 @@ extern int xt_cpu_multi;
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extern int isa_cycles;
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#define ISA_CYCLES(x) ((x * isa_cycles) >> ISA_CYCLES_SHIFT)
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void cpu_update_waitstates();
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#endif
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