Applied all mainline PCem commits;
Added experimental NVidia Riva TNT2 emulation (patch from MoochMcGee); ASUS P/I-P54TP4XE, ASUS P/I-P55T2P4, and ASUS P/I-P55TVP4 are back; National Semiconductor PC87306 Super I/O chip now correctly reenables devices after a chip power cycle; Several FDC improvements and the behavior is now a bit closer to real hardware (based on actual tests); Added MR Intel Advanced/ATX with Microid Research BIOS with support for 4 floppy drives and up to 4 IDE controllers; Added floppy drives 3 and 4, bringing the maximum to 4; You can now connect hard disks to the tertiary IDE controller; Correct undocumented behavior of the LEA instruction with register is back on 286 and later CPU's; Pentium-rea models with Intel chipsets now have port 92 (with alternate reset and alternate A20 toggle); Overhauled DMA channel read and write routines and fixed cascading; Improved IMG detection of a bad BPB (or complete lack of a BPB); Added preliminary emulation of PS/2 1.44 MB and PC-98 1.25 MB 3-mode drives (both have an inverted DENSEL pin); Removed the incorrect Amstrad mouse patch from TheCollector1995; Fixed ATAPI CD-ROM disk change detection; Windows IOCTL CD-ROM handler now tries to use direct SCSI passthrough for more things, including obtaining CD-ROM capacity; The Diamond Stealth32 (ET4000/W32p) now also works correctly on the two Award SiS 496/497 boxes; The (S)VGA handler now converts 6-bit RAMDAC RGB channels to standard 8-bit RGB using a lookup table generated at emulator start, calculated using the correct intensity conversion method and treating intensity 64 as equivalent to 63; Moved a few options from the Configuration dialog box to the menu; SIO, PIIX, and PIIX3 now have the reset control register on port CF9 as they should; Several bugfixes.
This commit is contained in:
@@ -14,7 +14,6 @@
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#include "ide.h"
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#include "io.h"
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#include "lpt.h"
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#include "mouse_serial.h"
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#include "serial.h"
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#include "fdc37c932fr.h"
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@@ -245,6 +244,8 @@ process_value:
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if (valxor & 0xC) fdc_update_densel_force((val & 0xC) >> 2);
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break;
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case 0xF2:
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if (valxor & 0xC0) fdc_update_rwc(3, (valxor & 0xC0) >> 6);
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if (valxor & 0x30) fdc_update_rwc(2, (valxor & 0x30) >> 4);
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if (valxor & 0x0C) fdc_update_rwc(1, (valxor & 0x0C) >> 2);
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if (valxor & 0x03) fdc_update_rwc(0, (valxor & 0x03));
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break;
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@@ -254,6 +255,12 @@ process_value:
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case 0xF5:
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if (valxor & 0x18) fdc_update_drvrate(1, (val & 0x18) >> 3);
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break;
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case 0xF6:
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if (valxor & 0x18) fdc_update_drvrate(2, (val & 0x18) >> 3);
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break;
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case 0xF7:
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if (valxor & 0x18) fdc_update_drvrate(3, (val & 0x18) >> 3);
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break;
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}
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break;
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case 3:
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@@ -471,8 +478,12 @@ void fdc37c932fr_init()
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fdd_swap = 0;
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fdc_update_rwc(0, 0);
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fdc_update_rwc(1, 0);
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fdc_update_rwc(2, 0);
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fdc_update_rwc(3, 0);
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fdc_update_drvrate(0, 0);
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fdc_update_drvrate(1, 0);
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fdc_update_drvrate(2, 0);
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fdc_update_drvrate(3, 0);
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fdc_update_max_track(79);
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io_sethandler(0xe0, 0x0006, fdc37c932fr_gpio_read, NULL, NULL, fdc37c932fr_gpio_write, NULL, NULL, NULL);
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io_sethandler(0xea, 0x0002, fdc37c932fr_gpio_read, NULL, NULL, fdc37c932fr_gpio_write, NULL, NULL, NULL);
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