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Applied all mainline PCem commits;

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Added experimental NVidia Riva TNT2 emulation (patch from MoochMcGee);
ASUS P/I-P54TP4XE, ASUS P/I-P55T2P4, and ASUS P/I-P55TVP4 are back;
National Semiconductor PC87306 Super I/O chip now correctly reenables devices after a chip power cycle;
Several FDC improvements and the behavior is now a bit closer to real hardware (based on actual tests);
Added MR Intel Advanced/ATX with Microid Research BIOS with support for 4 floppy drives and up to 4 IDE controllers;
Added floppy drives 3 and 4, bringing the maximum to 4;
You can now connect hard disks to the tertiary IDE controller;
Correct undocumented behavior of the LEA instruction with register is back on 286 and later CPU's;
Pentium-rea models with Intel chipsets now have port 92 (with alternate reset and alternate A20 toggle);
Overhauled DMA channel read and write routines and fixed cascading;
Improved IMG detection of a bad BPB (or complete lack of a BPB);
Added preliminary emulation of PS/2 1.44 MB and PC-98 1.25 MB 3-mode drives (both have an inverted DENSEL pin);
Removed the incorrect Amstrad mouse patch from TheCollector1995;
Fixed ATAPI CD-ROM disk change detection;
Windows IOCTL CD-ROM handler now tries to use direct SCSI passthrough for more things, including obtaining CD-ROM capacity;
The Diamond Stealth32 (ET4000/W32p) now also works correctly on the two Award SiS 496/497 boxes;
The (S)VGA handler now converts 6-bit RAMDAC RGB channels to standard 8-bit RGB using a lookup table generated at emulator start, calculated using the correct intensity conversion method and treating intensity 64 as equivalent to 63;
Moved a few options from the Configuration dialog box to the menu;
SIO, PIIX, and PIIX3 now have the reset control register on port CF9 as they should;
Several bugfixes.
This commit is contained in:
OBattler
2016-12-23 03:16:24 +01:00
parent 724c5699ca
commit dc46480aa4
142 changed files with 8778 additions and 3331 deletions
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80
src/sio.c
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@@ -37,6 +37,38 @@ void sio_write(int func, int addr, uint8_t val, void *priv)
return;
}
card_sio[addr] = val;
if (addr == 0x40)
{
if (!((val ^ card_sio[addr]) & 0x40))
{
return;
}
if (val & 0x40)
{
dma_alias_remove();
}
else
{
dma_alias_set();
}
}
else if (addr == 0x4f)
{
if (!((val ^ card_sio[addr]) & 0x40))
{
return;
}
if (val & 0x40)
{
port_92_add();
}
else
{
port_92_remove();
}
}
}
}
@@ -50,10 +82,10 @@ uint8_t sio_read(int func, int addr, void *priv)
return card_sio[addr];
}
void sio_init(int card)
static int reset_reg = 0;
void sio_reset()
{
pci_add_specific(card, sio_read, sio_write, NULL);
memset(card_sio, 0, 256);
card_sio[0x00] = 0x86; card_sio[0x01] = 0x80; /*Intel*/
card_sio[0x02] = 0x84; card_sio[0x03] = 0x04; /*82378ZB (SIO)*/
@@ -76,3 +108,45 @@ void sio_init(int card)
card_sio[0xA0] = 0x08;
card_sio[0xA8] = 0x0F;
}
static uint8_t rc_read(uint16_t port, void *priv)
{
return reset_reg & 0xfb;
}
static void rc_write(uint16_t port, uint8_t val, void *priv)
{
if (!(reset_reg & 4) && (val & 4))
{
if (reset_reg & 2)
{
// pclog("SIO: Hard reset\n");
resetpchard();
}
else
{
// pclog("SIO: Soft reset\n");
sio_reset();
resetide();
softresetx86();
}
}
reset_reg = val;
}
void sio_init(int card)
{
pci_add_specific(card, sio_read, sio_write, NULL);
sio_reset();
reset_reg = 0;
io_sethandler(0x0cf9, 0x0001, rc_read, NULL, NULL, rc_write, NULL, NULL, NULL);
port_92_reset();
port_92_add();
dma_alias_set();
}