claunia/86Box
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Applied all mainline PCem commits;

Browse Source 
Added experimental NVidia Riva TNT2 emulation (patch from MoochMcGee);
ASUS P/I-P54TP4XE, ASUS P/I-P55T2P4, and ASUS P/I-P55TVP4 are back;
National Semiconductor PC87306 Super I/O chip now correctly reenables devices after a chip power cycle;
Several FDC improvements and the behavior is now a bit closer to real hardware (based on actual tests);
Added MR Intel Advanced/ATX with Microid Research BIOS with support for 4 floppy drives and up to 4 IDE controllers;
Added floppy drives 3 and 4, bringing the maximum to 4;
You can now connect hard disks to the tertiary IDE controller;
Correct undocumented behavior of the LEA instruction with register is back on 286 and later CPU's;
Pentium-rea models with Intel chipsets now have port 92 (with alternate reset and alternate A20 toggle);
Overhauled DMA channel read and write routines and fixed cascading;
Improved IMG detection of a bad BPB (or complete lack of a BPB);
Added preliminary emulation of PS/2 1.44 MB and PC-98 1.25 MB 3-mode drives (both have an inverted DENSEL pin);
Removed the incorrect Amstrad mouse patch from TheCollector1995;
Fixed ATAPI CD-ROM disk change detection;
Windows IOCTL CD-ROM handler now tries to use direct SCSI passthrough for more things, including obtaining CD-ROM capacity;
The Diamond Stealth32 (ET4000/W32p) now also works correctly on the two Award SiS 496/497 boxes;
The (S)VGA handler now converts 6-bit RAMDAC RGB channels to standard 8-bit RGB using a lookup table generated at emulator start, calculated using the correct intensity conversion method and treating intensity 64 as equivalent to 63;
Moved a few options from the Configuration dialog box to the menu;
SIO, PIIX, and PIIX3 now have the reset control register on port CF9 as they should;
Several bugfixes.
This commit is contained in:
OBattler
2016-12-23 03:16:24 +01:00
parent 724c5699ca
commit dc46480aa4
142 changed files with 8778 additions and 3331 deletions
Download Patch File Download Diff File Expand all files Collapse all files

89
src/x86_ops_arith.h
View File

@@ -10,6 +10,7 @@
setflags ## 8 flagops; \
setr8(cpu_rm, operation); \
CLOCK_CYCLES(timing_rr); \
PREFETCH_RUN(timing_rr, 2, rmdat, 0,0,0,0, 0); \
} \
else \
{ \
@@ -18,6 +19,7 @@
seteab(operation); if (cpu_state.abrt) return 1; \
setflags ## 8 flagops; \
CLOCK_CYCLES(timing_mr); \
PREFETCH_RUN(timing_mr, 2, rmdat, 1,0,1,0, 0); \
} \
return 0; \
} \
@@ -32,6 +34,7 @@
setflags ## 8 flagops; \
setr8(cpu_rm, operation); \
CLOCK_CYCLES(timing_rr); \
PREFETCH_RUN(timing_rr, 2, rmdat, 0,0,0,0, 1); \
} \
else \
{ \
@@ -40,6 +43,7 @@
seteab(operation); if (cpu_state.abrt) return 1; \
setflags ## 8 flagops; \
CLOCK_CYCLES(timing_mr); \
PREFETCH_RUN(timing_mr, 2, rmdat, 1,0,1,0, 1); \
} \
return 0; \
} \
@@ -55,6 +59,7 @@
setflags ## 16 flagops; \
cpu_state.regs[cpu_rm].w = operation; \
CLOCK_CYCLES(timing_rr); \
PREFETCH_RUN(timing_rr, 2, rmdat, 0,0,0,0, 0); \
} \
else \
{ \
@@ -63,6 +68,7 @@
seteaw(operation); if (cpu_state.abrt) return 1; \
setflags ## 16 flagops; \
CLOCK_CYCLES(timing_mr); \
PREFETCH_RUN(timing_rr, 2, rmdat, 1,0,1,0, 0); \
} \
return 0; \
} \
@@ -77,6 +83,7 @@
setflags ## 16 flagops; \
cpu_state.regs[cpu_rm].w = operation; \
CLOCK_CYCLES(timing_rr); \
PREFETCH_RUN(timing_rr, 2, rmdat, 0,0,0,0, 1); \
} \
else \
{ \
@@ -85,6 +92,7 @@
seteaw(operation); if (cpu_state.abrt) return 1; \
setflags ## 16 flagops; \
CLOCK_CYCLES(timing_mr); \
PREFETCH_RUN(timing_rr, 2, rmdat, 1,0,1,0, 1); \
} \
return 0; \
} \
@@ -100,6 +108,7 @@
setflags ## 32 flagops; \
cpu_state.regs[cpu_rm].l = operation; \
CLOCK_CYCLES(timing_rr); \
PREFETCH_RUN(timing_rr, 2, rmdat, 0,0,0,0, 0); \
} \
else \
{ \
@@ -107,7 +116,8 @@
uint32_t src = cpu_state.regs[cpu_reg].l; \
seteal(operation); if (cpu_state.abrt) return 1; \
setflags ## 32 flagops; \
CLOCK_CYCLES(timing_mrl); \
CLOCK_CYCLES(timing_mr); \
PREFETCH_RUN(timing_rr, 2, rmdat, 0,1,0,1, 0); \
} \
return 0; \
} \
@@ -122,6 +132,7 @@
setflags ## 32 flagops; \
cpu_state.regs[cpu_rm].l = operation; \
CLOCK_CYCLES(timing_rr); \
PREFETCH_RUN(timing_rr, 2, rmdat, 0,0,0,0, 1); \
} \
else \
{ \
@@ -129,7 +140,8 @@
uint32_t src = cpu_state.regs[cpu_reg].l; \
seteal(operation); if (cpu_state.abrt) return 1; \
setflags ## 32 flagops; \
CLOCK_CYCLES(timing_mrl); \
CLOCK_CYCLES(timing_mr); \
PREFETCH_RUN(timing_rr, 2, rmdat, 0,1,0,1, 1); \
} \
return 0; \
} \
@@ -144,6 +156,7 @@
setflags ## 8 flagops; \
setr8(cpu_reg, operation); \
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rm); \
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, (cpu_mod == 3) ? 0 : 1,0,0,0, 0); \
return 0; \
} \
static int op ## name ## _b_rm_a32(uint32_t fetchdat) \
@@ -156,6 +169,7 @@
setflags ## 8 flagops; \
setr8(cpu_reg, operation); \
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rm); \
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, (cpu_mod == 3) ? 0 : 1,0,0,0, 1); \
return 0; \
} \
\
@@ -169,6 +183,7 @@
setflags ## 16 flagops; \
cpu_state.regs[cpu_reg].w = operation; \
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rm); \
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, (cpu_mod == 3) ? 0 : 1,0,0,0, 0); \
return 0; \
} \
static int op ## name ## _w_rm_a32(uint32_t fetchdat) \
@@ -181,6 +196,7 @@
setflags ## 16 flagops; \
cpu_state.regs[cpu_reg].w = operation; \
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rm); \
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, (cpu_mod == 3) ? 0 : 1,0,0,0, 1); \
return 0; \
} \
\
@@ -194,6 +210,7 @@
setflags ## 32 flagops; \
cpu_state.regs[cpu_reg].l = operation; \
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rml); \
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, 0, (cpu_mod == 3) ? 0 : 1,0,0, 0); \
return 0; \
} \
static int op ## name ## _l_rm_a32(uint32_t fetchdat) \
@@ -206,6 +223,7 @@
setflags ## 32 flagops; \
cpu_state.regs[cpu_reg].l = operation; \
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rml); \
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, 0, (cpu_mod == 3) ? 0 : 1,0,0, 1); \
return 0; \
} \
\
@@ -217,6 +235,7 @@
setflags ## 8 flagops; \
AL = operation; \
CLOCK_CYCLES(timing_rr); \
PREFETCH_RUN(timing_rr, 2, -1, 0,0,0,0, 0); \
return 0; \
} \
\
@@ -228,6 +247,7 @@
setflags ## 16 flagops; \
AX = operation; \
CLOCK_CYCLES(timing_rr); \
PREFETCH_RUN(timing_rr, 3, -1, 0,0,0,0, 0); \
return 0; \
} \
\
@@ -239,6 +259,7 @@
setflags ## 32 flagops; \
EAX = operation; \
CLOCK_CYCLES(timing_rr); \
PREFETCH_RUN(timing_rr, 5, -1, 0,0,0,0, 0); \
return 0; \
}
@@ -258,6 +279,7 @@ static int opCMP_b_rmw_a16(uint32_t fetchdat)
setsub8(dst, getr8(cpu_reg));
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, (cpu_mod == 3) ? 0 : 1,0,0,0, 0);
return 0;
}
static int opCMP_b_rmw_a32(uint32_t fetchdat)
@@ -268,6 +290,7 @@ static int opCMP_b_rmw_a32(uint32_t fetchdat)
setsub8(dst, getr8(cpu_reg));
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, (cpu_mod == 3) ? 0 : 1,0,0,0, 1);
return 0;
}
@@ -279,6 +302,7 @@ static int opCMP_w_rmw_a16(uint32_t fetchdat)
setsub16(dst, cpu_state.regs[cpu_reg].w);
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, (cpu_mod == 3) ? 0 : 1,0,0,0, 0);
return 0;
}
static int opCMP_w_rmw_a32(uint32_t fetchdat)
@@ -289,6 +313,7 @@ static int opCMP_w_rmw_a32(uint32_t fetchdat)
setsub16(dst, cpu_state.regs[cpu_reg].w);
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, (cpu_mod == 3) ? 0 : 1,0,0,0, 1);
return 0;
}
@@ -300,6 +325,7 @@ static int opCMP_l_rmw_a16(uint32_t fetchdat)
setsub32(dst, cpu_state.regs[cpu_reg].l);
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, 0, (cpu_mod == 3) ? 0 : 1,0,0, 0);
return 0;
}
static int opCMP_l_rmw_a32(uint32_t fetchdat)
@@ -310,6 +336,7 @@ static int opCMP_l_rmw_a32(uint32_t fetchdat)
setsub32(dst, cpu_state.regs[cpu_reg].l);
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, 0, (cpu_mod == 3) ? 0 : 1,0,0, 1);
return 0;
}
@@ -320,6 +347,7 @@ static int opCMP_b_rm_a16(uint32_t fetchdat)
src = geteab(); if (cpu_state.abrt) return 1;
setsub8(getr8(cpu_reg), src);
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rm);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, (cpu_mod == 3) ? 0 : 1,0,0,0, 0);
return 0;
}
static int opCMP_b_rm_a32(uint32_t fetchdat)
@@ -329,6 +357,7 @@ static int opCMP_b_rm_a32(uint32_t fetchdat)
src = geteab(); if (cpu_state.abrt) return 1;
setsub8(getr8(cpu_reg), src);
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rm);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, (cpu_mod == 3) ? 0 : 1,0,0,0, 1);
return 0;
}
@@ -339,6 +368,7 @@ static int opCMP_w_rm_a16(uint32_t fetchdat)
src = geteaw(); if (cpu_state.abrt) return 1;
setsub16(cpu_state.regs[cpu_reg].w, src);
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rm);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, (cpu_mod == 3) ? 0 : 1,0,0,0, 0);
return 0;
}
static int opCMP_w_rm_a32(uint32_t fetchdat)
@@ -348,6 +378,7 @@ static int opCMP_w_rm_a32(uint32_t fetchdat)
src = geteaw(); if (cpu_state.abrt) return 1;
setsub16(cpu_state.regs[cpu_reg].w, src);
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rm);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, (cpu_mod == 3) ? 0 : 1,0,0,0, 1);
return 0;
}
@@ -358,6 +389,7 @@ static int opCMP_l_rm_a16(uint32_t fetchdat)
src = geteal(); if (cpu_state.abrt) return 1;
setsub32(cpu_state.regs[cpu_reg].l, src);
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rml);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, 0, (cpu_mod == 3) ? 0 : 1,0,0, 0);
return 0;
}
static int opCMP_l_rm_a32(uint32_t fetchdat)
@@ -367,6 +399,7 @@ static int opCMP_l_rm_a32(uint32_t fetchdat)
src = geteal(); if (cpu_state.abrt) return 1;
setsub32(cpu_state.regs[cpu_reg].l, src);
CLOCK_CYCLES((cpu_mod == 3) ? timing_rr : timing_rml);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, 0, (cpu_mod == 3) ? 0 : 1,0,0, 1);
return 0;
}
@@ -375,6 +408,7 @@ static int opCMP_AL_imm(uint32_t fetchdat)
uint8_t src = getbytef();
setsub8(AL, src);
CLOCK_CYCLES(timing_rr);
PREFETCH_RUN(timing_rr, 2, -1, 0,0,0,0, 0);
return 0;
}
@@ -383,6 +417,7 @@ static int opCMP_AX_imm(uint32_t fetchdat)
uint16_t src = getwordf();
setsub16(AX, src);
CLOCK_CYCLES(timing_rr);
PREFETCH_RUN(timing_rr, 3, -1, 0,0,0,0, 0);
return 0;
}
@@ -391,6 +426,7 @@ static int opCMP_EAX_imm(uint32_t fetchdat)
uint32_t src = getlong(); if (cpu_state.abrt) return 1;
setsub32(EAX, src);
CLOCK_CYCLES(timing_rr);
PREFETCH_RUN(timing_rr, 5, -1, 0,0,0,0, 0);
return 0;
}
@@ -403,6 +439,7 @@ static int opTEST_b_a16(uint32_t fetchdat)
setznp8(temp & temp2);
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, (cpu_mod == 3) ? 0 : 1,0,0,0, 0);
return 0;
}
static int opTEST_b_a32(uint32_t fetchdat)
@@ -414,6 +451,7 @@ static int opTEST_b_a32(uint32_t fetchdat)
setznp8(temp & temp2);
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, (cpu_mod == 3) ? 0 : 1,0,0,0, 1);
return 0;
}
@@ -426,6 +464,7 @@ static int opTEST_w_a16(uint32_t fetchdat)
setznp16(temp & temp2);
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, (cpu_mod == 3) ? 0 : 1,0,0,0, 0);
return 0;
}
static int opTEST_w_a32(uint32_t fetchdat)
@@ -437,6 +476,7 @@ static int opTEST_w_a32(uint32_t fetchdat)
setznp16(temp & temp2);
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, (cpu_mod == 3) ? 0 : 1,0,0,0, 1);
return 0;
}
@@ -449,6 +489,7 @@ static int opTEST_l_a16(uint32_t fetchdat)
setznp32(temp & temp2);
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, 0,(cpu_mod == 3) ? 0 : 1,0,0, 0);
return 0;
}
static int opTEST_l_a32(uint32_t fetchdat)
@@ -460,6 +501,7 @@ static int opTEST_l_a32(uint32_t fetchdat)
setznp32(temp & temp2);
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, 0,(cpu_mod == 3) ? 0 : 1,0,0, 1);
return 0;
}
@@ -468,6 +510,7 @@ static int opTEST_AL(uint32_t fetchdat)
uint8_t temp = getbytef();
setznp8(AL & temp);
CLOCK_CYCLES(timing_rr);
PREFETCH_RUN(timing_rr, 2, -1, 0,0,0,0, 0);
return 0;
}
static int opTEST_AX(uint32_t fetchdat)
@@ -475,6 +518,7 @@ static int opTEST_AX(uint32_t fetchdat)
uint16_t temp = getwordf();
setznp16(AX & temp);
CLOCK_CYCLES(timing_rr);
PREFETCH_RUN(timing_rr, 3, -1, 0,0,0,0, 0);
return 0;
}
static int opTEST_EAX(uint32_t fetchdat)
@@ -482,6 +526,7 @@ static int opTEST_EAX(uint32_t fetchdat)
uint32_t temp = getlong(); if (cpu_state.abrt) return 1;
setznp32(EAX & temp);
CLOCK_CYCLES(timing_rr);
PREFETCH_RUN(timing_rr, 5, -1, 0,0,0,0, 0);
return 0;
}
@@ -545,6 +590,10 @@ static int op80_a16(uint32_t fetchdat)
fetch_ea_16(fetchdat);
src = getbyte(); if (cpu_state.abrt) return 1;
ARITH_MULTI(b, 8);
if ((rmdat & 0x38) == 0x38)
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mr, 3, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 0);
else
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 3, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, 0);
return 0;
}
@@ -555,6 +604,10 @@ static int op80_a32(uint32_t fetchdat)
fetch_ea_32(fetchdat);
src = getbyte(); if (cpu_state.abrt) return 1;
ARITH_MULTI(b, 8);
if ((rmdat & 0x38) == 0x38)
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mr, 3, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 1);
else
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 3, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, 1);
return 0;
}
@@ -565,6 +618,10 @@ static int op81_w_a16(uint32_t fetchdat)
fetch_ea_16(fetchdat);
src = getword(); if (cpu_state.abrt) return 1;
ARITH_MULTI(w, 16);
if ((rmdat & 0x38) == 0x38)
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mr, 4, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 0);
else
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 4, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, 0);
return 0;
}
@@ -575,6 +632,10 @@ static int op81_w_a32(uint32_t fetchdat)
fetch_ea_32(fetchdat);
src = getword(); if (cpu_state.abrt) return 1;
ARITH_MULTI(w, 16);
if ((rmdat & 0x38) == 0x38)
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mr, 4, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 1);
else
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 4, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, 1);
return 0;
}
@@ -585,6 +646,10 @@ static int op81_l_a16(uint32_t fetchdat)
fetch_ea_16(fetchdat);
src = getlong(); if (cpu_state.abrt) return 1;
ARITH_MULTI(l, 32);
if ((rmdat & 0x38) == 0x38)
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mr, 6, rmdat, 0,(cpu_mod == 3) ? 0:1,0,0, 0);
else
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 6, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, 0);
return 0;
}
@@ -595,6 +660,10 @@ static int op81_l_a32(uint32_t fetchdat)
fetch_ea_32(fetchdat);
src = getlong(); if (cpu_state.abrt) return 1;
ARITH_MULTI(l, 32);
if ((rmdat & 0x38) == 0x38)
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mr, 6, rmdat, 0,(cpu_mod == 3) ? 0:1,0,0, 1);
else
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 6, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, 1);
return 0;
}
@@ -607,6 +676,10 @@ static int op83_w_a16(uint32_t fetchdat)
src = getbyte(); if (cpu_state.abrt) return 1;
if (src & 0x80) src |= 0xff00;
ARITH_MULTI(w, 16);
if ((rmdat & 0x38) == 0x38)
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mr, 3, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 0);
else
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 3, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, 0);
return 0;
}
@@ -618,6 +691,10 @@ static int op83_w_a32(uint32_t fetchdat)
src = getbyte(); if (cpu_state.abrt) return 1;
if (src & 0x80) src |= 0xff00;
ARITH_MULTI(w, 16);
if ((rmdat & 0x38) == 0x38)
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mr, 3, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 1);
else
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 3, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, 1);
return 0;
}
@@ -630,6 +707,10 @@ static int op83_l_a16(uint32_t fetchdat)
src = getbyte(); if (cpu_state.abrt) return 1;
if (src & 0x80) src |= 0xffffff00;
ARITH_MULTI(l, 32);
if ((rmdat & 0x38) == 0x38)
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mr, 3, rmdat, 0,(cpu_mod == 3) ? 0:1,0,0, 0);
else
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 3, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, 0);
return 0;
}
@@ -641,6 +722,10 @@ static int op83_l_a32(uint32_t fetchdat)
src = getbyte(); if (cpu_state.abrt) return 1;
if (src & 0x80) src |= 0xffffff00;
ARITH_MULTI(l, 32);
if ((rmdat & 0x38) == 0x38)
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mr, 3, rmdat, 0,(cpu_mod == 3) ? 0:1,0,0, 1);
else
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 3, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, 1);
return 0;
}