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Applied all mainline PCem commits;

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Added experimental NVidia Riva TNT2 emulation (patch from MoochMcGee);
ASUS P/I-P54TP4XE, ASUS P/I-P55T2P4, and ASUS P/I-P55TVP4 are back;
National Semiconductor PC87306 Super I/O chip now correctly reenables devices after a chip power cycle;
Several FDC improvements and the behavior is now a bit closer to real hardware (based on actual tests);
Added MR Intel Advanced/ATX with Microid Research BIOS with support for 4 floppy drives and up to 4 IDE controllers;
Added floppy drives 3 and 4, bringing the maximum to 4;
You can now connect hard disks to the tertiary IDE controller;
Correct undocumented behavior of the LEA instruction with register is back on 286 and later CPU's;
Pentium-rea models with Intel chipsets now have port 92 (with alternate reset and alternate A20 toggle);
Overhauled DMA channel read and write routines and fixed cascading;
Improved IMG detection of a bad BPB (or complete lack of a BPB);
Added preliminary emulation of PS/2 1.44 MB and PC-98 1.25 MB 3-mode drives (both have an inverted DENSEL pin);
Removed the incorrect Amstrad mouse patch from TheCollector1995;
Fixed ATAPI CD-ROM disk change detection;
Windows IOCTL CD-ROM handler now tries to use direct SCSI passthrough for more things, including obtaining CD-ROM capacity;
The Diamond Stealth32 (ET4000/W32p) now also works correctly on the two Award SiS 496/497 boxes;
The (S)VGA handler now converts 6-bit RAMDAC RGB channels to standard 8-bit RGB using a lookup table generated at emulator start, calculated using the correct intensity conversion method and treating intensity 64 as equivalent to 63;
Moved a few options from the Configuration dialog box to the menu;
SIO, PIIX, and PIIX3 now have the reset control register on port CF9 as they should;
Several bugfixes.
This commit is contained in:
OBattler
2016-12-23 03:16:24 +01:00
parent 724c5699ca
commit dc46480aa4
142 changed files with 8778 additions and 3331 deletions
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27
src/x86_ops_bitscan.h
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@@ -7,6 +7,7 @@
for (c = start; c != end; c += dir) \
{ \
CLOCK_CYCLES(time); \
instr_cycles += time; \
if (temp & (1 << c)) \
{ \
dest = c; \
@@ -20,6 +21,7 @@
static int opBSF_w_a16(uint32_t fetchdat)
{
uint16_t temp;
int instr_cycles;
fetch_ea_16(fetchdat);
temp = geteaw(); if (cpu_state.abrt) return 1;
@@ -27,11 +29,14 @@ static int opBSF_w_a16(uint32_t fetchdat)
BS_common(0, 16, 1, cpu_state.regs[cpu_reg].w, (is486) ? 1 : 3);
CLOCK_CYCLES((is486) ? 6 : 10);
instr_cycles += ((is486) ? 6 : 10);
PREFETCH_RUN(instr_cycles, 2, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 0);
return 0;
}
static int opBSF_w_a32(uint32_t fetchdat)
{
uint16_t temp;
int instr_cycles;
fetch_ea_32(fetchdat);
temp = geteaw(); if (cpu_state.abrt) return 1;
@@ -39,11 +44,14 @@ static int opBSF_w_a32(uint32_t fetchdat)
BS_common(0, 16, 1, cpu_state.regs[cpu_reg].w, (is486) ? 1 : 3);
CLOCK_CYCLES((is486) ? 6 : 10);
instr_cycles += ((is486) ? 6 : 10);
PREFETCH_RUN(instr_cycles, 2, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 1);
return 0;
}
static int opBSF_l_a16(uint32_t fetchdat)
{
uint32_t temp;
int instr_cycles;
fetch_ea_16(fetchdat);
temp = geteal(); if (cpu_state.abrt) return 1;
@@ -51,24 +59,30 @@ static int opBSF_l_a16(uint32_t fetchdat)
BS_common(0, 32, 1, cpu_state.regs[cpu_reg].l, (is486) ? 1 : 3);
CLOCK_CYCLES((is486) ? 6 : 10);
instr_cycles += ((is486) ? 6 : 10);
PREFETCH_RUN(instr_cycles, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,0, 0);
return 0;
}
static int opBSF_l_a32(uint32_t fetchdat)
{
uint32_t temp;
int instr_cycles;
fetch_ea_32(fetchdat);
temp = geteal(); if (cpu_state.abrt) return 1;
BS_common(0, 32, 1, cpu_state.regs[cpu_reg].l, (is486) ? 1 : 3);
CLOCK_CYCLES((is486) ? 6 : 10);
instr_cycles += ((is486) ? 6 : 10);
PREFETCH_RUN(instr_cycles, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,0, 1);
return 0;
}
static int opBSR_w_a16(uint32_t fetchdat)
{
uint16_t temp;
int instr_cycles;
fetch_ea_16(fetchdat);
temp = geteaw(); if (cpu_state.abrt) return 1;
@@ -76,11 +90,14 @@ static int opBSR_w_a16(uint32_t fetchdat)
BS_common(15, -1, -1, cpu_state.regs[cpu_reg].w, 3);
CLOCK_CYCLES((is486) ? 6 : 10);
instr_cycles += ((is486) ? 6 : 10);
PREFETCH_RUN(instr_cycles, 2, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 0);
return 0;
}
static int opBSR_w_a32(uint32_t fetchdat)
{
uint16_t temp;
int instr_cycles;
fetch_ea_32(fetchdat);
temp = geteaw(); if (cpu_state.abrt) return 1;
@@ -88,11 +105,14 @@ static int opBSR_w_a32(uint32_t fetchdat)
BS_common(15, -1, -1, cpu_state.regs[cpu_reg].w, 3);
CLOCK_CYCLES((is486) ? 6 : 10);
instr_cycles += ((is486) ? 6 : 10);
PREFETCH_RUN(instr_cycles, 2, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 1);
return 0;
}
static int opBSR_l_a16(uint32_t fetchdat)
{
uint32_t temp;
int instr_cycles;
fetch_ea_16(fetchdat);
temp = geteal(); if (cpu_state.abrt) return 1;
@@ -100,11 +120,14 @@ static int opBSR_l_a16(uint32_t fetchdat)
BS_common(31, -1, -1, cpu_state.regs[cpu_reg].l, 3);
CLOCK_CYCLES((is486) ? 6 : 10);
instr_cycles += ((is486) ? 6 : 10);
PREFETCH_RUN(instr_cycles, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,0, 0);
return 0;
}
static int opBSR_l_a32(uint32_t fetchdat)
{
uint32_t temp;
int instr_cycles;
fetch_ea_32(fetchdat);
temp = geteal(); if (cpu_state.abrt) return 1;
@@ -112,6 +135,8 @@ static int opBSR_l_a32(uint32_t fetchdat)
BS_common(31, -1, -1, cpu_state.regs[cpu_reg].l, 3);
CLOCK_CYCLES((is486) ? 6 : 10);
instr_cycles += ((is486) ? 6 : 10);
PREFETCH_RUN(instr_cycles, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,0, 1);
return 0;
}