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Applied all mainline PCem commits;

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Added experimental NVidia Riva TNT2 emulation (patch from MoochMcGee);
ASUS P/I-P54TP4XE, ASUS P/I-P55T2P4, and ASUS P/I-P55TVP4 are back;
National Semiconductor PC87306 Super I/O chip now correctly reenables devices after a chip power cycle;
Several FDC improvements and the behavior is now a bit closer to real hardware (based on actual tests);
Added MR Intel Advanced/ATX with Microid Research BIOS with support for 4 floppy drives and up to 4 IDE controllers;
Added floppy drives 3 and 4, bringing the maximum to 4;
You can now connect hard disks to the tertiary IDE controller;
Correct undocumented behavior of the LEA instruction with register is back on 286 and later CPU's;
Pentium-rea models with Intel chipsets now have port 92 (with alternate reset and alternate A20 toggle);
Overhauled DMA channel read and write routines and fixed cascading;
Improved IMG detection of a bad BPB (or complete lack of a BPB);
Added preliminary emulation of PS/2 1.44 MB and PC-98 1.25 MB 3-mode drives (both have an inverted DENSEL pin);
Removed the incorrect Amstrad mouse patch from TheCollector1995;
Fixed ATAPI CD-ROM disk change detection;
Windows IOCTL CD-ROM handler now tries to use direct SCSI passthrough for more things, including obtaining CD-ROM capacity;
The Diamond Stealth32 (ET4000/W32p) now also works correctly on the two Award SiS 496/497 boxes;
The (S)VGA handler now converts 6-bit RAMDAC RGB channels to standard 8-bit RGB using a lookup table generated at emulator start, calculated using the correct intensity conversion method and treating intensity 64 as equivalent to 63;
Moved a few options from the Configuration dialog box to the menu;
SIO, PIIX, and PIIX3 now have the reset control register on port CF9 as they should;
Several bugfixes.
This commit is contained in:
OBattler
2016-12-23 03:16:24 +01:00
parent 724c5699ca
commit dc46480aa4
142 changed files with 8778 additions and 3331 deletions
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49
src/x86_ops_jump.h
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@@ -25,8 +25,11 @@
cpu_state.pc += offset; \
CLOCK_CYCLES_ALWAYS(timing_bt); \
CPU_BLOCK_END(); \
PREFETCH_RUN(timing_bt+timing_bnt, 2, -1, 0,0,0,0, 0); \
PREFETCH_FLUSH(); \
return 1; \
} \
PREFETCH_RUN(timing_bnt, 2, -1, 0,0,0,0, 0); \
return 0; \
} \
\
@@ -39,8 +42,11 @@
cpu_state.pc += offset; \
CLOCK_CYCLES_ALWAYS(timing_bt); \
CPU_BLOCK_END(); \
PREFETCH_RUN(timing_bt+timing_bnt, 3, -1, 0,0,0,0, 0); \
PREFETCH_FLUSH(); \
return 1; \
} \
PREFETCH_RUN(timing_bnt, 3, -1, 0,0,0,0, 0); \
return 0; \
} \
\
@@ -53,8 +59,11 @@
cpu_state.pc += offset; \
CLOCK_CYCLES_ALWAYS(timing_bt); \
CPU_BLOCK_END(); \
PREFETCH_RUN(timing_bt+timing_bnt, 5, -1, 0,0,0,0, 0); \
PREFETCH_FLUSH(); \
return 1; \
} \
PREFETCH_RUN(timing_bnt, 5, -1, 0,0,0,0, 0); \
return 0; \
} \
@@ -82,10 +91,12 @@ static int opLOOPNE_w(uint32_t fetchdat)
int8_t offset = (int8_t)getbytef();
CX--;
CLOCK_CYCLES((is486) ? 7 : 11);
PREFETCH_RUN(11, 2, -1, 0,0,0,0, 0);
if (CX && !ZF_SET())
{
cpu_state.pc += offset;
CPU_BLOCK_END();
PREFETCH_FLUSH();
return 1;
}
return 0;
@@ -95,10 +106,12 @@ static int opLOOPNE_l(uint32_t fetchdat)
int8_t offset = (int8_t)getbytef();
ECX--;
CLOCK_CYCLES((is486) ? 7 : 11);
PREFETCH_RUN(11, 2, -1, 0,0,0,0, 0);
if (ECX && !ZF_SET())
{
cpu_state.pc += offset;
CPU_BLOCK_END();
PREFETCH_FLUSH();
return 1;
}
return 0;
@@ -109,10 +122,12 @@ static int opLOOPE_w(uint32_t fetchdat)
int8_t offset = (int8_t)getbytef();
CX--;
CLOCK_CYCLES((is486) ? 7 : 11);
PREFETCH_RUN(11, 2, -1, 0,0,0,0, 0);
if (CX && ZF_SET())
{
cpu_state.pc += offset;
CPU_BLOCK_END();
PREFETCH_FLUSH();
return 1;
}
return 0;
@@ -122,10 +137,12 @@ static int opLOOPE_l(uint32_t fetchdat)
int8_t offset = (int8_t)getbytef();
ECX--;
CLOCK_CYCLES((is486) ? 7 : 11);
PREFETCH_RUN(11, 2, -1, 0,0,0,0, 0);
if (ECX && ZF_SET())
{
cpu_state.pc += offset;
CPU_BLOCK_END();
PREFETCH_FLUSH();
return 1;
}
return 0;
@@ -136,10 +153,12 @@ static int opLOOP_w(uint32_t fetchdat)
int8_t offset = (int8_t)getbytef();
CX--;
CLOCK_CYCLES((is486) ? 7 : 11);
PREFETCH_RUN(11, 2, -1, 0,0,0,0, 0);
if (CX)
{
cpu_state.pc += offset;
CPU_BLOCK_END();
PREFETCH_FLUSH();
return 1;
}
return 0;
@@ -149,10 +168,12 @@ static int opLOOP_l(uint32_t fetchdat)
int8_t offset = (int8_t)getbytef();
ECX--;
CLOCK_CYCLES((is486) ? 7 : 11);
PREFETCH_RUN(11, 2, -1, 0,0,0,0, 0);
if (ECX)
{
cpu_state.pc += offset;
CPU_BLOCK_END();
PREFETCH_FLUSH();
return 1;
}
return 0;
@@ -167,8 +188,11 @@ static int opJCXZ(uint32_t fetchdat)
cpu_state.pc += offset;
CLOCK_CYCLES(4);
CPU_BLOCK_END();
PREFETCH_RUN(9, 2, -1, 0,0,0,0, 0);
PREFETCH_FLUSH();
return 1;
}
PREFETCH_RUN(5, 2, -1, 0,0,0,0, 0);
return 0;
}
static int opJECXZ(uint32_t fetchdat)
@@ -180,8 +204,11 @@ static int opJECXZ(uint32_t fetchdat)
cpu_state.pc += offset;
CLOCK_CYCLES(4);
CPU_BLOCK_END();
PREFETCH_RUN(9, 2, -1, 0,0,0,0, 0);
PREFETCH_FLUSH();
return 1;
}
PREFETCH_RUN(5, 2, -1, 0,0,0,0, 0);
return 0;
}
@@ -192,6 +219,8 @@ static int opJMP_r8(uint32_t fetchdat)
cpu_state.pc += offset;
CPU_BLOCK_END();
CLOCK_CYCLES((is486) ? 3 : 7);
PREFETCH_RUN(7, 2, -1, 0,0,0,0, 0);
PREFETCH_FLUSH();
return 0;
}
static int opJMP_r16(uint32_t fetchdat)
@@ -200,6 +229,8 @@ static int opJMP_r16(uint32_t fetchdat)
cpu_state.pc += offset;
CPU_BLOCK_END();
CLOCK_CYCLES((is486) ? 3 : 7);
PREFETCH_RUN(7, 3, -1, 0,0,0,0, 0);
PREFETCH_FLUSH();
return 0;
}
static int opJMP_r32(uint32_t fetchdat)
@@ -208,6 +239,8 @@ static int opJMP_r32(uint32_t fetchdat)
cpu_state.pc += offset;
CPU_BLOCK_END();
CLOCK_CYCLES((is486) ? 3 : 7);
PREFETCH_RUN(7, 5, -1, 0,0,0,0, 0);
PREFETCH_FLUSH();
return 0;
}
@@ -219,6 +252,8 @@ static int opJMP_far_a16(uint32_t fetchdat)
cpu_state.pc = addr;
loadcsjmp(seg, oxpc);
CPU_BLOCK_END();
PREFETCH_RUN(11, 5, -1, 0,0,0,0, 0);
PREFETCH_FLUSH();
return 0;
}
static int opJMP_far_a32(uint32_t fetchdat)
@@ -229,6 +264,8 @@ static int opJMP_far_a32(uint32_t fetchdat)
cpu_state.pc = addr;
loadcsjmp(seg, oxpc);
CPU_BLOCK_END();
PREFETCH_RUN(11, 7, -1, 0,0,0,0, 0);
PREFETCH_FLUSH();
return 0;
}
@@ -239,6 +276,8 @@ static int opCALL_r16(uint32_t fetchdat)
cpu_state.pc += addr;
CPU_BLOCK_END();
CLOCK_CYCLES((is486) ? 3 : 7);
PREFETCH_RUN(7, 3, -1, 0,0,1,0, 0);
PREFETCH_FLUSH();
return 0;
}
static int opCALL_r32(uint32_t fetchdat)
@@ -248,6 +287,8 @@ static int opCALL_r32(uint32_t fetchdat)
cpu_state.pc += addr;
CPU_BLOCK_END();
CLOCK_CYCLES((is486) ? 3 : 7);
PREFETCH_RUN(7, 5, -1, 0,0,0,1, 0);
PREFETCH_FLUSH();
return 0;
}
@@ -260,6 +301,8 @@ static int opRET_w(uint32_t fetchdat)
CPU_BLOCK_END();
CLOCK_CYCLES((is486) ? 5 : 10);
PREFETCH_RUN(10, 1, -1, 1,0,0,0, 0);
PREFETCH_FLUSH();
return 0;
}
static int opRET_l(uint32_t fetchdat)
@@ -271,6 +314,8 @@ static int opRET_l(uint32_t fetchdat)
CPU_BLOCK_END();
CLOCK_CYCLES((is486) ? 5 : 10);
PREFETCH_RUN(10, 1, -1, 0,1,0,0, 0);
PREFETCH_FLUSH();
return 0;
}
@@ -286,6 +331,8 @@ static int opRET_w_imm(uint32_t fetchdat)
CPU_BLOCK_END();
CLOCK_CYCLES((is486) ? 5 : 10);
PREFETCH_RUN(10, 5, -1, 1,0,0,0, 0);
PREFETCH_FLUSH();
return 0;
}
static int opRET_l_imm(uint32_t fetchdat)
@@ -300,6 +347,8 @@ static int opRET_l_imm(uint32_t fetchdat)
CPU_BLOCK_END();
CLOCK_CYCLES((is486) ? 5 : 10);
PREFETCH_RUN(10, 5, -1, 0,1,0,0, 0);
PREFETCH_FLUSH();
return 0;
}