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Applied all mainline PCem commits;

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Added experimental NVidia Riva TNT2 emulation (patch from MoochMcGee);
ASUS P/I-P54TP4XE, ASUS P/I-P55T2P4, and ASUS P/I-P55TVP4 are back;
National Semiconductor PC87306 Super I/O chip now correctly reenables devices after a chip power cycle;
Several FDC improvements and the behavior is now a bit closer to real hardware (based on actual tests);
Added MR Intel Advanced/ATX with Microid Research BIOS with support for 4 floppy drives and up to 4 IDE controllers;
Added floppy drives 3 and 4, bringing the maximum to 4;
You can now connect hard disks to the tertiary IDE controller;
Correct undocumented behavior of the LEA instruction with register is back on 286 and later CPU's;
Pentium-rea models with Intel chipsets now have port 92 (with alternate reset and alternate A20 toggle);
Overhauled DMA channel read and write routines and fixed cascading;
Improved IMG detection of a bad BPB (or complete lack of a BPB);
Added preliminary emulation of PS/2 1.44 MB and PC-98 1.25 MB 3-mode drives (both have an inverted DENSEL pin);
Removed the incorrect Amstrad mouse patch from TheCollector1995;
Fixed ATAPI CD-ROM disk change detection;
Windows IOCTL CD-ROM handler now tries to use direct SCSI passthrough for more things, including obtaining CD-ROM capacity;
The Diamond Stealth32 (ET4000/W32p) now also works correctly on the two Award SiS 496/497 boxes;
The (S)VGA handler now converts 6-bit RAMDAC RGB channels to standard 8-bit RGB using a lookup table generated at emulator start, calculated using the correct intensity conversion method and treating intensity 64 as equivalent to 63;
Moved a few options from the Configuration dialog box to the menu;
SIO, PIIX, and PIIX3 now have the reset control register on port CF9 as they should;
Several bugfixes.
This commit is contained in:
OBattler
2016-12-23 03:16:24 +01:00
parent 724c5699ca
commit dc46480aa4
142 changed files with 8778 additions and 3331 deletions
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12
src/x86_ops_mul.h
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@@ -15,6 +15,7 @@ static int opIMUL_w_iw_a16(uint32_t fetchdat)
cpu_state.regs[cpu_reg].w = templ & 0xffff;
CLOCK_CYCLES((cpu_mod == 3) ? 14 : 17);
PREFETCH_RUN((cpu_mod == 3) ? 14 : 17, 4, rmdat, 1,0,0,0, 0);
return 0;
}
static int opIMUL_w_iw_a32(uint32_t fetchdat)
@@ -34,6 +35,7 @@ static int opIMUL_w_iw_a32(uint32_t fetchdat)
cpu_state.regs[cpu_reg].w = templ & 0xffff;
CLOCK_CYCLES((cpu_mod == 3) ? 14 : 17);
PREFETCH_RUN((cpu_mod == 3) ? 14 : 17, 4, rmdat, 1,0,0,0, 1);
return 0;
}
@@ -54,6 +56,7 @@ static int opIMUL_l_il_a16(uint32_t fetchdat)
cpu_state.regs[cpu_reg].l = temp64 & 0xffffffff;
CLOCK_CYCLES(25);
PREFETCH_RUN(25, 6, rmdat, 0,1,0,0, 0);
return 0;
}
static int opIMUL_l_il_a32(uint32_t fetchdat)
@@ -73,6 +76,7 @@ static int opIMUL_l_il_a32(uint32_t fetchdat)
cpu_state.regs[cpu_reg].l = temp64 & 0xffffffff;
CLOCK_CYCLES(25);
PREFETCH_RUN(25, 6, rmdat, 0,1,0,0, 1);
return 0;
}
@@ -94,6 +98,7 @@ static int opIMUL_w_ib_a16(uint32_t fetchdat)
cpu_state.regs[cpu_reg].w = templ & 0xffff;
CLOCK_CYCLES((cpu_mod == 3) ? 14 : 17);
PREFETCH_RUN((cpu_mod == 3) ? 14 : 17, 3, rmdat, 1,0,0,0, 0);
return 0;
}
static int opIMUL_w_ib_a32(uint32_t fetchdat)
@@ -114,6 +119,7 @@ static int opIMUL_w_ib_a32(uint32_t fetchdat)
cpu_state.regs[cpu_reg].w = templ & 0xffff;
CLOCK_CYCLES((cpu_mod == 3) ? 14 : 17);
PREFETCH_RUN((cpu_mod == 3) ? 14 : 17, 3, rmdat, 1,0,0,0, 1);
return 0;
}
@@ -134,6 +140,7 @@ static int opIMUL_l_ib_a16(uint32_t fetchdat)
cpu_state.regs[cpu_reg].l = temp64 & 0xffffffff;
CLOCK_CYCLES(20);
PREFETCH_RUN(20, 3, rmdat, 0,1,0,0, 0);
return 0;
}
static int opIMUL_l_ib_a32(uint32_t fetchdat)
@@ -153,6 +160,7 @@ static int opIMUL_l_ib_a32(uint32_t fetchdat)
cpu_state.regs[cpu_reg].l = temp64 & 0xffffffff;
CLOCK_CYCLES(20);
PREFETCH_RUN(20, 3, rmdat, 0,1,0,0, 1);
return 0;
}
@@ -171,6 +179,7 @@ static int opIMUL_w_w_a16(uint32_t fetchdat)
else flags &= ~(C_FLAG | V_FLAG);
CLOCK_CYCLES(18);
PREFETCH_RUN(18, 2, rmdat, 1,0,0,0, 0);
return 0;
}
static int opIMUL_w_w_a32(uint32_t fetchdat)
@@ -186,6 +195,7 @@ static int opIMUL_w_w_a32(uint32_t fetchdat)
else flags &= ~(C_FLAG | V_FLAG);
CLOCK_CYCLES(18);
PREFETCH_RUN(18, 2, rmdat, 1,0,0,0, 1);
return 0;
}
@@ -202,6 +212,7 @@ static int opIMUL_l_l_a16(uint32_t fetchdat)
else flags &= ~(C_FLAG | V_FLAG);
CLOCK_CYCLES(30);
PREFETCH_RUN(30, 2, rmdat, 0,1,0,0, 0);
return 0;
}
static int opIMUL_l_l_a32(uint32_t fetchdat)
@@ -217,6 +228,7 @@ static int opIMUL_l_l_a32(uint32_t fetchdat)
else flags &= ~(C_FLAG | V_FLAG);
CLOCK_CYCLES(30);
PREFETCH_RUN(30, 2, rmdat, 0,1,0,0, 1);
return 0;
}