Moved the IBM PS/1 Model 2133 out of dev branch.
Added the VLSI VL82c480 chipset and the unknown sio that the PS/1 2133 EMEA 451 uses. Added on-board Cirrus GD5426 video card
This commit is contained in:
TC1995
185
src/chipset/vl82c480.c
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185
src/chipset/vl82c480.c
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/*
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* 86Box A hypervisor and IBM PC system emulator that specializes in
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* running old operating systems and software designed for IBM
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* PC systems and compatibles from 1981 through fairly recent
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* system designs based on the PCI bus.
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*
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* This file is part of the 86Box distribution.
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*
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* Implementation of the VLSI VL82c480 chipset.
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*
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* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
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*
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* Copyright 2020 Sarah Walker.
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*/
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#include <stdio.h>
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#include <stdint.h>
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#include <stdlib.h>
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#include <string.h>
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#include <wchar.h>
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#include <86box/86box.h>
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#include "cpu.h"
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#include <86box/timer.h>
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#include <86box/device.h>
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#include <86box/io.h>
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#include <86box/mem.h>
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#include <86box/nmi.h>
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#include <86box/port_92.h>
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#include <86box/chipset.h>
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typedef struct {
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int cfg_index;
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uint8_t cfg_regs[256];
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} vl82c480_t;
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#define CFG_ID 0x00
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#define CFG_AAXS 0x0d
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#define CFG_BAXS 0x0e
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#define CFG_CAXS 0x0f
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#define CFG_DAXS 0x10
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#define CFG_EAXS 0x11
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#define CFG_FAXS 0x12
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#define ID_VL82C480 0x90
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static void
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shadow_control(uint32_t addr, uint32_t size, int state)
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{
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/* pclog("shadow_control: addr=%08x size=%04x state=%i\n", addr, size, state); */
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switch (state) {
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case 0:
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mem_set_mem_state(addr, size, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
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break;
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case 1:
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mem_set_mem_state(addr, size, MEM_READ_EXTANY | MEM_WRITE_INTERNAL);
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break;
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case 2:
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mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_EXTANY);
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break;
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case 3:
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mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
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break;
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}
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flushmmucache_nopc();
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}
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static void
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vl82c480_write(uint16_t addr, uint8_t val, void *p)
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{
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vl82c480_t *dev = (vl82c480_t *)p;
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switch (addr) {
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case 0xec:
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dev->cfg_index = val;
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break;
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case 0xed:
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if (dev->cfg_index >= 0x01 && dev->cfg_index <= 0x24) {
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dev->cfg_regs[dev->cfg_index] = val;
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switch (dev->cfg_index) {
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case CFG_AAXS:
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shadow_control(0xa0000, 0x4000, val & 3);
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shadow_control(0xa4000, 0x4000, (val >> 2) & 3);
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shadow_control(0xa8000, 0x4000, (val >> 4) & 3);
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shadow_control(0xac000, 0x4000, (val >> 6) & 3);
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break;
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case CFG_BAXS:
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shadow_control(0xb0000, 0x4000, val & 3);
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shadow_control(0xb4000, 0x4000, (val >> 2) & 3);
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shadow_control(0xb8000, 0x4000, (val >> 4) & 3);
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shadow_control(0xbc000, 0x4000, (val >> 6) & 3);
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break;
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case CFG_CAXS:
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shadow_control(0xc0000, 0x4000, val & 3);
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shadow_control(0xc4000, 0x4000, (val >> 2) & 3);
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shadow_control(0xc8000, 0x4000, (val >> 4) & 3);
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shadow_control(0xcc000, 0x4000, (val >> 6) & 3);
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break;
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case CFG_DAXS:
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shadow_control(0xd0000, 0x4000, val & 3);
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shadow_control(0xd4000, 0x4000, (val >> 2) & 3);
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shadow_control(0xd8000, 0x4000, (val >> 4) & 3);
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shadow_control(0xdc000, 0x4000, (val >> 6) & 3);
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break;
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case CFG_EAXS:
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shadow_control(0xe0000, 0x4000, val & 3);
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shadow_control(0xe4000, 0x4000, (val >> 2) & 3);
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shadow_control(0xe8000, 0x4000, (val >> 4) & 3);
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shadow_control(0xec000, 0x4000, (val >> 6) & 3);
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break;
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case CFG_FAXS:
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shadow_control(0xf0000, 0x4000, val & 3);
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shadow_control(0xf4000, 0x4000, (val >> 2) & 3);
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shadow_control(0xf8000, 0x4000, (val >> 4) & 3);
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shadow_control(0xfc000, 0x4000, (val >> 6) & 3);
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break;
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}
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}
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break;
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case 0xee:
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if (mem_a20_alt)
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outb(0x92, inb(0x92) & ~2);
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break;
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}
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}
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static uint8_t
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vl82c480_read(uint16_t addr, void *p)
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{
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vl82c480_t *dev = (vl82c480_t *)p;
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uint8_t ret = 0xff;
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switch (addr) {
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case 0xec:
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ret = dev->cfg_index;
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break;
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case 0xed:
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ret = dev->cfg_regs[dev->cfg_index];
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break;
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case 0xee:
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if (!mem_a20_alt)
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outb(0x92, inb(0x92) | 2);
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break;
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case 0xef:
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softresetx86();
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cpu_set_edx();
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break;
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}
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return ret;
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}
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static void
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vl82c480_close(void *p)
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{
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vl82c480_t *dev = (vl82c480_t *)p;
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free(dev);
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}
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static void *
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vl82c480_init(const device_t *info)
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{
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vl82c480_t *dev = (vl82c480_t *)malloc(sizeof(vl82c480_t));
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memset(dev, 0, sizeof(vl82c480_t));
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dev->cfg_regs[CFG_ID] = ID_VL82C480;
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io_sethandler(0x00ec, 0x0004, vl82c480_read, NULL, NULL, vl82c480_write, NULL, NULL, dev);
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return dev;
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}
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const device_t vl82c480_device = {
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"VLSI VL82c480",
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0,
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0,
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vl82c480_init, vl82c480_close, NULL,
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NULL, NULL, NULL,
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NULL
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};
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