Applied the mainline PCem commit that reorganizes the REP instructions.
This commit is contained in:
OBattler
@@ -401,828 +401,6 @@ int checkio(int port)
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return d&(1<<(port&7));
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}
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int rep386(int fv)
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{
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uint8_t temp;
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uint32_t c;
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uint8_t temp2;
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uint16_t tempw,tempw2,of;
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uint32_t ipc = cpu_state.oldpc;
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uint32_t rep32 = cpu_state.op32;
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uint32_t templ,templ2;
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int tempz;
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int tempi;
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/*Limit the amount of time the instruction is uninterruptable for, so
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that high frequency timers still work okay. This amount is different
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for interpreter and recompiler*/
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int cycles_end = cycles - ((is386 && cpu_use_dynarec) ? 1000 : 100);
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int reads = 0, reads_l = 0, writes = 0, writes_l = 0, total_cycles = 0;
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if (trap)
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cycles_end = cycles+1; /*Force the instruction to end after only one iteration when trap flag set*/
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cpu_reps++;
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flags_rebuild();
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of = flags;
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startrep:
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temp=opcode2=readmemb(cs,cpu_state.pc); cpu_state.pc++;
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c=(rep32&0x200)?ECX:CX;
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switch (temp|rep32)
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{
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case 0xC3: case 0x1C3: case 0x2C3: case 0x3C3:
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cpu_state.pc--;
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break;
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case 0x08:
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cpu_state.pc=ipc+1;
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break;
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case 0x26: case 0x126: case 0x226: case 0x326: /*ES:*/
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cpu_state.ea_seg = &_es;
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PREFETCH_PREFIX();
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goto startrep;
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break;
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case 0x2E: case 0x12E: case 0x22E: case 0x32E: /*CS:*/
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cpu_state.ea_seg = &_cs;
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PREFETCH_PREFIX();
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goto startrep;
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case 0x36: case 0x136: case 0x236: case 0x336: /*SS:*/
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cpu_state.ea_seg = &_ss;
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PREFETCH_PREFIX();
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goto startrep;
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case 0x3E: case 0x13E: case 0x23E: case 0x33E: /*DS:*/
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cpu_state.ea_seg = &_ds;
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PREFETCH_PREFIX();
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goto startrep;
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case 0x64: case 0x164: case 0x264: case 0x364: /*FS:*/
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cpu_state.ea_seg = &_fs;
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PREFETCH_PREFIX();
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goto startrep;
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case 0x65: case 0x165: case 0x265: case 0x365: /*GS:*/
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cpu_state.ea_seg = &_gs;
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PREFETCH_PREFIX();
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goto startrep;
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case 0x66: case 0x166: case 0x266: case 0x366: /*Data size prefix*/
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rep32 = (rep32 & 0x200) | ((use32 ^ 0x100) & 0x100);
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PREFETCH_PREFIX();
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goto startrep;
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case 0x67: case 0x167: case 0x267: case 0x367: /*Address size prefix*/
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rep32 = (rep32 & 0x100) | ((use32 ^ 0x200) & 0x200);
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PREFETCH_PREFIX();
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goto startrep;
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case 0x6C: case 0x16C: /*REP INSB*/
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if (c>0)
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{
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checkio_perm(DX);
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temp2=inb(DX);
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writememb(es,DI,temp2);
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if (cpu_state.abrt) break;
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if (flags&D_FLAG) DI--;
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else DI++;
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c--;
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cycles-=15;
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reads++; writes++; total_cycles += 15;
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}
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if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
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else firstrepcycle=1;
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break;
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case 0x26C: case 0x36C: /*REP INSB*/
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if (c>0)
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{
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checkio_perm(DX);
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temp2=inb(DX);
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writememb(es,EDI,temp2);
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if (cpu_state.abrt) break;
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if (flags&D_FLAG) EDI--;
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else EDI++;
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c--;
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cycles-=15;
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reads++; writes++; total_cycles += 15;
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}
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if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
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else firstrepcycle=1;
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break;
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case 0x6D: /*REP INSW*/
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if (c>0)
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{
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tempw=inw(DX);
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writememw(es,DI,tempw);
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if (cpu_state.abrt) break;
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if (flags&D_FLAG) DI-=2;
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else DI+=2;
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c--;
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cycles-=15;
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reads++; writes++; total_cycles += 15;
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}
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if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
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else firstrepcycle=1;
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break;
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case 0x16D: /*REP INSL*/
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if (c>0)
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{
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templ=inl(DX);
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writememl(es,DI,templ);
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if (cpu_state.abrt) break;
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if (flags&D_FLAG) DI-=4;
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else DI+=4;
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c--;
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cycles-=15;
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reads_l++; writes_l++; total_cycles += 15;
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}
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if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
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else firstrepcycle=1;
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break;
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case 0x26D: /*REP INSW*/
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if (c>0)
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{
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tempw=inw(DX);
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writememw(es,EDI,tempw);
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if (cpu_state.abrt) break;
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if (flags&D_FLAG) EDI-=2;
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else EDI+=2;
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c--;
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cycles-=15;
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reads++; writes++; total_cycles += 15;
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}
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if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
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else firstrepcycle=1;
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break;
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case 0x36D: /*REP INSL*/
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if (c>0)
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{
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templ=inl(DX);
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writememl(es,EDI,templ);
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if (cpu_state.abrt) break;
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if (flags&D_FLAG) EDI-=4;
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else EDI+=4;
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c--;
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cycles-=15;
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reads_l++; writes_l++; total_cycles += 15;
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}
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if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
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else firstrepcycle=1;
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break;
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case 0x6E: case 0x16E: /*REP OUTSB*/
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if (c>0)
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{
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temp2 = readmemb(cpu_state.ea_seg->base, SI);
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if (cpu_state.abrt) break;
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checkio_perm(DX);
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outb(DX,temp2);
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if (flags&D_FLAG) SI--;
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else SI++;
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c--;
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cycles-=14;
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reads++; writes++; total_cycles += 14;
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}
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if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
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else firstrepcycle=1;
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break;
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case 0x26E: case 0x36E: /*REP OUTSB*/
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if (c>0)
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{
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temp2 = readmemb(cpu_state.ea_seg->base, ESI);
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if (cpu_state.abrt) break;
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checkio_perm(DX);
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outb(DX,temp2);
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if (flags&D_FLAG) ESI--;
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else ESI++;
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c--;
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cycles-=14;
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reads++; writes++; total_cycles += 14;
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}
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if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
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else firstrepcycle=1;
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break;
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case 0x6F: /*REP OUTSW*/
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if (c>0)
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{
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tempw = readmemw(cpu_state.ea_seg->base, SI);
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if (cpu_state.abrt) break;
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outw(DX,tempw);
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if (flags&D_FLAG) SI-=2;
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else SI+=2;
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c--;
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cycles-=14;
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reads++; writes++; total_cycles += 14;
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}
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if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
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else firstrepcycle=1;
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break;
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case 0x16F: /*REP OUTSL*/
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if (c > 0)
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{
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templ = readmeml(cpu_state.ea_seg->base, SI);
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if (cpu_state.abrt) break;
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outl(DX, templ);
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if (flags & D_FLAG) SI -= 4;
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else SI += 4;
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c--;
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cycles -= 14;
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reads_l++; writes_l++; total_cycles += 14;
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}
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if (c > 0) { firstrepcycle = 0; cpu_state.pc = ipc; }
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else firstrepcycle = 1;
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break;
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case 0x26F: /*REP OUTSW*/
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if (c>0)
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{
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tempw = readmemw(cpu_state.ea_seg->base, ESI);
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if (cpu_state.abrt) break;
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outw(DX,tempw);
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if (flags&D_FLAG) ESI-=2;
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else ESI+=2;
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c--;
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cycles-=14;
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reads++; writes++; total_cycles += 14;
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}
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if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
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else firstrepcycle=1;
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break;
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case 0x36F: /*REP OUTSL*/
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if (c > 0)
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{
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templ = readmeml(cpu_state.ea_seg->base, ESI);
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if (cpu_state.abrt) break;
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outl(DX, templ);
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if (flags & D_FLAG) ESI -= 4;
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else ESI += 4;
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c--;
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cycles -= 14;
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reads_l++; writes_l++; total_cycles += 14;
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}
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if (c > 0) { firstrepcycle = 0; cpu_state.pc = ipc; }
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else firstrepcycle = 1;
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break;
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case 0x90: case 0x190: /*REP NOP*/
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case 0x290: case 0x390:
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break;
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case 0xA4: case 0x1A4: /*REP MOVSB*/
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while (c > 0)
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{
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CHECK_WRITE_REP(&_es, DI, DI);
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temp2 = readmemb(cpu_state.ea_seg->base, SI); if (cpu_state.abrt) break;
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writememb(es,DI,temp2); if (cpu_state.abrt) break;
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if (flags&D_FLAG) { DI--; SI--; }
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else { DI++; SI++; }
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c--;
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cycles-=(is486)?3:4;
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ins++;
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reads++; writes++; total_cycles += is486 ? 3 : 4;
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if (cycles < cycles_end)
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break;
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}
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ins--;
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if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
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else firstrepcycle=1;
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break;
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case 0x2A4: case 0x3A4: /*REP MOVSB*/
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while (c > 0)
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{
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CHECK_WRITE_REP(&_es, EDI, EDI);
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temp2 = readmemb(cpu_state.ea_seg->base, ESI); if (cpu_state.abrt) break;
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writememb(es,EDI,temp2); if (cpu_state.abrt) break;
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if (flags&D_FLAG) { EDI--; ESI--; }
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else { EDI++; ESI++; }
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c--;
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cycles-=(is486)?3:4;
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ins++;
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reads++; writes++; total_cycles += is486 ? 3 : 4;
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if (cycles < cycles_end)
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break;
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}
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ins--;
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if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
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else firstrepcycle=1;
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break;
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case 0xA5: /*REP MOVSW*/
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while (c > 0)
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{
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CHECK_WRITE_REP(&_es, DI, DI+1);
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tempw = readmemw(cpu_state.ea_seg->base, SI); if (cpu_state.abrt) break;
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writememw(es,DI,tempw); if (cpu_state.abrt) break;
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if (flags&D_FLAG) { DI-=2; SI-=2; }
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else { DI+=2; SI+=2; }
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c--;
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cycles-=(is486)?3:4;
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ins++;
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reads++; writes++; total_cycles += is486 ? 3 : 4;
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if (cycles < cycles_end)
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break;
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}
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ins--;
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if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
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else firstrepcycle=1;
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break;
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case 0x1A5: /*REP MOVSL*/
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while (c > 0)
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{
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CHECK_WRITE_REP(&_es, DI, DI+3);
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templ = readmeml(cpu_state.ea_seg->base, SI); if (cpu_state.abrt) break;
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writememl(es,DI,templ); if (cpu_state.abrt) break;
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if (flags&D_FLAG) { DI-=4; SI-=4; }
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else { DI+=4; SI+=4; }
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c--;
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cycles-=(is486)?3:4;
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ins++;
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reads_l++; writes_l++; total_cycles += is486 ? 3 : 4;
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if (cycles < cycles_end)
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break;
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}
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ins--;
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if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
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else firstrepcycle=1;
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break;
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case 0x2A5: /*REP MOVSW*/
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while (c > 0)
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{
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CHECK_WRITE_REP(&_es, EDI, EDI+1);
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tempw = readmemw(cpu_state.ea_seg->base, ESI); if (cpu_state.abrt) break;
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writememw(es,EDI,tempw); if (cpu_state.abrt) break;
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if (flags&D_FLAG) { EDI-=2; ESI-=2; }
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else { EDI+=2; ESI+=2; }
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c--;
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cycles-=(is486)?3:4;
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ins++;
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reads++; writes++; total_cycles += is486 ? 3 : 4;
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if (cycles < cycles_end)
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break;
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}
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ins--;
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if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
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else firstrepcycle=1;
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break;
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case 0x3A5: /*REP MOVSL*/
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while (c > 0)
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{
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CHECK_WRITE_REP(&_es, EDI, EDI+3);
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templ = readmeml(cpu_state.ea_seg->base, ESI); if (cpu_state.abrt) break;
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writememl(es,EDI,templ); if (cpu_state.abrt) break;
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if (flags&D_FLAG) { EDI-=4; ESI-=4; }
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else { EDI+=4; ESI+=4; }
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c--;
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cycles-=(is486)?3:4;
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ins++;
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reads_l++; writes_l++; total_cycles += is486 ? 3 : 4;
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if (cycles < cycles_end)
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break;
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}
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ins--;
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if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
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else firstrepcycle=1;
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break;
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case 0xA6: case 0x1A6: /*REP CMPSB*/
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tempz = (fv) ? 1 : 0;
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if ((c>0) && (fv==tempz))
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{
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temp = readmemb(cpu_state.ea_seg->base, SI);
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temp2=readmemb(es,DI);
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if (cpu_state.abrt) { flags=of; break; }
|
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if (flags&D_FLAG) { DI--; SI--; }
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else { DI++; SI++; }
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c--;
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cycles-=(is486)?7:9;
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reads += 2; total_cycles += is486 ? 7 : 9;
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setsub8(temp,temp2);
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tempz = (ZF_SET()) ? 1 : 0;
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}
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if ((c>0) && (fv==tempz)) { cpu_state.pc=ipc; firstrepcycle=0; }
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else firstrepcycle=1;
|
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break;
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case 0x2A6: case 0x3A6: /*REP CMPSB*/
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tempz = (fv) ? 1 : 0;
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if ((c>0) && (fv==tempz))
|
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{
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temp = readmemb(cpu_state.ea_seg->base, ESI);
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temp2=readmemb(es,EDI);
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if (cpu_state.abrt) { flags=of; break; }
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if (flags&D_FLAG) { EDI--; ESI--; }
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else { EDI++; ESI++; }
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c--;
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cycles-=(is486)?7:9;
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reads += 2; total_cycles += is486 ? 7 : 9;
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setsub8(temp,temp2);
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tempz = (ZF_SET()) ? 1 : 0;
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}
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if ((c>0) && (fv==tempz)) { cpu_state.pc=ipc; firstrepcycle=0; }
|
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else firstrepcycle=1;
|
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break;
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case 0xA7: /*REP CMPSW*/
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tempz = (fv) ? 1 : 0;
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if ((c>0) && (fv==tempz))
|
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{
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tempw = readmemw(cpu_state.ea_seg->base, SI);
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tempw2=readmemw(es,DI);
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if (cpu_state.abrt) { flags=of; break; }
|
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if (flags&D_FLAG) { DI-=2; SI-=2; }
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else { DI+=2; SI+=2; }
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c--;
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cycles-=(is486)?7:9;
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reads += 2; total_cycles += is486 ? 7 : 9;
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setsub16(tempw,tempw2);
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tempz = (ZF_SET()) ? 1 : 0;
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}
|
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if ((c>0) && (fv==tempz)) { cpu_state.pc=ipc; firstrepcycle=0; }
|
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else firstrepcycle=1;
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break;
|
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case 0x1A7: /*REP CMPSL*/
|
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tempz = (fv) ? 1 : 0;
|
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if ((c>0) && (fv==tempz))
|
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{
|
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templ = readmeml(cpu_state.ea_seg->base, SI);
|
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templ2=readmeml(es,DI);
|
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if (cpu_state.abrt) { flags=of; break; }
|
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if (flags&D_FLAG) { DI-=4; SI-=4; }
|
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else { DI+=4; SI+=4; }
|
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c--;
|
||||
cycles-=(is486)?7:9;
|
||||
reads_l += 2; total_cycles += is486 ? 7 : 9;
|
||||
setsub32(templ,templ2);
|
||||
tempz = (ZF_SET()) ? 1 : 0;
|
||||
}
|
||||
if ((c>0) && (fv==tempz)) { cpu_state.pc=ipc; firstrepcycle=0; }
|
||||
else firstrepcycle=1;
|
||||
break;
|
||||
case 0x2A7: /*REP CMPSW*/
|
||||
tempz = (fv) ? 1 : 0;
|
||||
if ((c>0) && (fv==tempz))
|
||||
{
|
||||
tempw = readmemw(cpu_state.ea_seg->base, ESI);
|
||||
tempw2=readmemw(es,EDI);
|
||||
if (cpu_state.abrt) { flags=of; break; }
|
||||
if (flags&D_FLAG) { EDI-=2; ESI-=2; }
|
||||
else { EDI+=2; ESI+=2; }
|
||||
c--;
|
||||
cycles-=(is486)?7:9;
|
||||
reads += 2; total_cycles += is486 ? 7 : 9;
|
||||
setsub16(tempw,tempw2);
|
||||
tempz = (ZF_SET()) ? 1 : 0;
|
||||
}
|
||||
if ((c>0) && (fv==tempz)) { cpu_state.pc=ipc; firstrepcycle=0; }
|
||||
else firstrepcycle=1;
|
||||
break;
|
||||
case 0x3A7: /*REP CMPSL*/
|
||||
tempz = (fv) ? 1 : 0;
|
||||
if ((c>0) && (fv==tempz))
|
||||
{
|
||||
templ = readmeml(cpu_state.ea_seg->base, ESI);
|
||||
templ2=readmeml(es,EDI);
|
||||
if (cpu_state.abrt) { flags=of; break; }
|
||||
if (flags&D_FLAG) { EDI-=4; ESI-=4; }
|
||||
else { EDI+=4; ESI+=4; }
|
||||
c--;
|
||||
cycles-=(is486)?7:9;
|
||||
reads_l += 2; total_cycles += is486 ? 7 : 9;
|
||||
setsub32(templ,templ2);
|
||||
tempz = (ZF_SET()) ? 1 : 0;
|
||||
}
|
||||
if ((c>0) && (fv==tempz)) { cpu_state.pc=ipc; firstrepcycle=0; }
|
||||
else firstrepcycle=1;
|
||||
break;
|
||||
|
||||
case 0xAA: case 0x1AA: /*REP STOSB*/
|
||||
while (c > 0)
|
||||
{
|
||||
CHECK_WRITE_REP(&_es, DI, DI);
|
||||
writememb(es,DI,AL);
|
||||
if (cpu_state.abrt) break;
|
||||
if (flags&D_FLAG) DI--;
|
||||
else DI++;
|
||||
c--;
|
||||
cycles-=(is486)?4:5;
|
||||
writes++; total_cycles += is486 ? 4 : 5;
|
||||
ins++;
|
||||
if (cycles < cycles_end)
|
||||
break;
|
||||
}
|
||||
ins--;
|
||||
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
|
||||
else firstrepcycle=1;
|
||||
break;
|
||||
case 0x2AA: case 0x3AA: /*REP STOSB*/
|
||||
while (c > 0)
|
||||
{
|
||||
CHECK_WRITE_REP(&_es, EDI, EDI);
|
||||
writememb(es,EDI,AL);
|
||||
if (cpu_state.abrt) break;
|
||||
if (flags&D_FLAG) EDI--;
|
||||
else EDI++;
|
||||
c--;
|
||||
cycles-=(is486)?4:5;
|
||||
writes++; total_cycles += is486 ? 4 : 5;
|
||||
ins++;
|
||||
if (cycles < cycles_end)
|
||||
break;
|
||||
}
|
||||
ins--;
|
||||
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
|
||||
else firstrepcycle=1;
|
||||
break;
|
||||
case 0xAB: /*REP STOSW*/
|
||||
while (c > 0)
|
||||
{
|
||||
CHECK_WRITE_REP(&_es, DI, DI+1);
|
||||
writememw(es,DI,AX);
|
||||
if (cpu_state.abrt) break;
|
||||
if (flags&D_FLAG) DI-=2;
|
||||
else DI+=2;
|
||||
c--;
|
||||
cycles-=(is486)?4:5;
|
||||
writes++; total_cycles += is486 ? 4 : 5;
|
||||
ins++;
|
||||
if (cycles < cycles_end)
|
||||
break;
|
||||
}
|
||||
ins--;
|
||||
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
|
||||
else firstrepcycle=1;
|
||||
break;
|
||||
case 0x2AB: /*REP STOSW*/
|
||||
while (c > 0)
|
||||
{
|
||||
CHECK_WRITE_REP(&_es, EDI, EDI+1);
|
||||
writememw(es,EDI,AX);
|
||||
if (cpu_state.abrt) break;
|
||||
if (flags&D_FLAG) EDI-=2;
|
||||
else EDI+=2;
|
||||
c--;
|
||||
cycles-=(is486)?4:5;
|
||||
writes++; total_cycles += is486 ? 4 : 5;
|
||||
ins++;
|
||||
if (cycles < cycles_end)
|
||||
break;
|
||||
}
|
||||
ins--;
|
||||
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
|
||||
else firstrepcycle=1;
|
||||
break;
|
||||
case 0x1AB: /*REP STOSL*/
|
||||
while (c > 0)
|
||||
{
|
||||
CHECK_WRITE_REP(&_es, DI, DI+3);
|
||||
writememl(es,DI,EAX);
|
||||
if (cpu_state.abrt) break;
|
||||
if (flags&D_FLAG) DI-=4;
|
||||
else DI+=4;
|
||||
c--;
|
||||
cycles-=(is486)?4:5;
|
||||
writes_l++; total_cycles += is486 ? 4 : 5;
|
||||
ins++;
|
||||
if (cycles < cycles_end)
|
||||
break;
|
||||
}
|
||||
ins--;
|
||||
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
|
||||
else firstrepcycle=1;
|
||||
break;
|
||||
case 0x3AB: /*REP STOSL*/
|
||||
while (c > 0)
|
||||
{
|
||||
CHECK_WRITE_REP(&_es, EDI, EDI+3);
|
||||
writememl(es,EDI,EAX);
|
||||
if (cpu_state.abrt) break;
|
||||
if (flags&D_FLAG) EDI-=4;
|
||||
else EDI+=4;
|
||||
c--;
|
||||
cycles-=(is486)?4:5;
|
||||
writes_l++; total_cycles += is486 ? 4 : 5;
|
||||
ins++;
|
||||
if (cycles < cycles_end)
|
||||
break;
|
||||
}
|
||||
ins--;
|
||||
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
|
||||
else firstrepcycle=1;
|
||||
break;
|
||||
case 0xAC: case 0x1AC: /*REP LODSB*/
|
||||
if (c>0)
|
||||
{
|
||||
AL = readmemb(cpu_state.ea_seg->base, SI);
|
||||
if (cpu_state.abrt) break;
|
||||
if (flags&D_FLAG) SI--;
|
||||
else SI++;
|
||||
c--;
|
||||
cycles-=5;
|
||||
reads++; total_cycles += 5;
|
||||
}
|
||||
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
|
||||
else firstrepcycle=1;
|
||||
break;
|
||||
case 0x2AC: case 0x3AC: /*REP LODSB*/
|
||||
if (c>0)
|
||||
{
|
||||
AL = readmemb(cpu_state.ea_seg->base, ESI);
|
||||
if (cpu_state.abrt) break;
|
||||
if (flags&D_FLAG) ESI--;
|
||||
else ESI++;
|
||||
c--;
|
||||
cycles-=5;
|
||||
reads++; total_cycles += 5;
|
||||
}
|
||||
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
|
||||
else firstrepcycle=1;
|
||||
break;
|
||||
case 0xAD: /*REP LODSW*/
|
||||
if (c>0)
|
||||
{
|
||||
AX = readmemw(cpu_state.ea_seg->base, SI);
|
||||
if (cpu_state.abrt) break;
|
||||
if (flags&D_FLAG) SI-=2;
|
||||
else SI+=2;
|
||||
c--;
|
||||
cycles-=5;
|
||||
reads++; total_cycles += 5;
|
||||
}
|
||||
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
|
||||
else firstrepcycle=1;
|
||||
break;
|
||||
case 0x1AD: /*REP LODSL*/
|
||||
if (c>0)
|
||||
{
|
||||
EAX = readmeml(cpu_state.ea_seg->base, SI);
|
||||
if (cpu_state.abrt) break;
|
||||
if (flags&D_FLAG) SI-=4;
|
||||
else SI+=4;
|
||||
c--;
|
||||
cycles-=5;
|
||||
reads_l++; total_cycles += 5;
|
||||
}
|
||||
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
|
||||
else firstrepcycle=1;
|
||||
break;
|
||||
case 0x2AD: /*REP LODSW*/
|
||||
if (c>0)
|
||||
{
|
||||
AX = readmemw(cpu_state.ea_seg->base, ESI);
|
||||
if (cpu_state.abrt) break;
|
||||
if (flags&D_FLAG) ESI-=2;
|
||||
else ESI+=2;
|
||||
c--;
|
||||
cycles-=5;
|
||||
reads++; total_cycles += 5;
|
||||
}
|
||||
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
|
||||
else firstrepcycle=1;
|
||||
break;
|
||||
case 0x3AD: /*REP LODSL*/
|
||||
if (c>0)
|
||||
{
|
||||
EAX = readmeml(cpu_state.ea_seg->base, ESI);
|
||||
if (cpu_state.abrt) break;
|
||||
if (flags&D_FLAG) ESI-=4;
|
||||
else ESI+=4;
|
||||
c--;
|
||||
cycles-=5;
|
||||
reads_l++; total_cycles += 5;
|
||||
}
|
||||
if (c>0) { firstrepcycle=0; cpu_state.pc=ipc; }
|
||||
else firstrepcycle=1;
|
||||
break;
|
||||
case 0xAE: case 0x1AE: /*REP SCASB*/
|
||||
cpu_notreps++;
|
||||
tempz = (fv) ? 1 : 0;
|
||||
while ((c > 0) && (fv == tempz))
|
||||
{
|
||||
temp2=readmemb(es,DI);
|
||||
if (cpu_state.abrt) { flags=of; break; }
|
||||
setsub8(AL,temp2);
|
||||
tempz = (ZF_SET()) ? 1 : 0;
|
||||
if (flags&D_FLAG) DI--;
|
||||
else DI++;
|
||||
c--;
|
||||
cycles-=(is486)?5:8;
|
||||
reads++; total_cycles += is486 ? 5 : 8;
|
||||
ins++;
|
||||
if (cycles < cycles_end)
|
||||
break;
|
||||
}
|
||||
ins--;
|
||||
if ((c>0) && (fv==tempz)) { cpu_state.pc=ipc; firstrepcycle=0; }
|
||||
else firstrepcycle=1;
|
||||
break;
|
||||
case 0x2AE: case 0x3AE: /*REP SCASB*/
|
||||
cpu_notreps++;
|
||||
tempz = (fv) ? 1 : 0;
|
||||
while ((c > 0) && (fv == tempz))
|
||||
{
|
||||
temp2=readmemb(es,EDI);
|
||||
if (cpu_state.abrt) { flags=of; break; }
|
||||
setsub8(AL,temp2);
|
||||
tempz = (ZF_SET()) ? 1 : 0;
|
||||
if (flags&D_FLAG) EDI--;
|
||||
else EDI++;
|
||||
c--;
|
||||
cycles-=(is486)?5:8;
|
||||
reads++; total_cycles += is486 ? 5 : 8;
|
||||
ins++;
|
||||
if (cycles < cycles_end)
|
||||
break;
|
||||
}
|
||||
ins--;
|
||||
if ((c>0) && (fv==tempz)) { cpu_state.pc=ipc; firstrepcycle=0; }
|
||||
else firstrepcycle=1;
|
||||
break;
|
||||
case 0xAF: /*REP SCASW*/
|
||||
cpu_notreps++;
|
||||
tempz = (fv) ? 1 : 0;
|
||||
while ((c > 0) && (fv == tempz))
|
||||
{
|
||||
tempw=readmemw(es,DI);
|
||||
if (cpu_state.abrt) { flags=of; break; }
|
||||
setsub16(AX,tempw);
|
||||
tempz = (ZF_SET()) ? 1 : 0;
|
||||
if (flags&D_FLAG) DI-=2;
|
||||
else DI+=2;
|
||||
c--;
|
||||
cycles-=(is486)?5:8;
|
||||
reads++; total_cycles += is486 ? 5 : 8;
|
||||
ins++;
|
||||
if (cycles < cycles_end)
|
||||
break;
|
||||
}
|
||||
ins--;
|
||||
if ((c>0) && (fv==tempz)) { cpu_state.pc=ipc; firstrepcycle=0; }
|
||||
else firstrepcycle=1;
|
||||
break;
|
||||
case 0x1AF: /*REP SCASL*/
|
||||
cpu_notreps++;
|
||||
tempz = (fv) ? 1 : 0;
|
||||
while ((c > 0) && (fv == tempz))
|
||||
{
|
||||
templ=readmeml(es,DI);
|
||||
if (cpu_state.abrt) { flags=of; break; }
|
||||
setsub32(EAX,templ);
|
||||
tempz = (ZF_SET()) ? 1 : 0;
|
||||
if (flags&D_FLAG) DI-=4;
|
||||
else DI+=4;
|
||||
c--;
|
||||
cycles-=(is486)?5:8;
|
||||
reads_l++; total_cycles += is486 ? 5 : 8;
|
||||
ins++;
|
||||
if (cycles < cycles_end)
|
||||
break;
|
||||
}
|
||||
ins--;
|
||||
if ((c>0) && (fv==tempz)) { cpu_state.pc=ipc; firstrepcycle=0; }
|
||||
else firstrepcycle=1;
|
||||
break;
|
||||
case 0x2AF: /*REP SCASW*/
|
||||
cpu_notreps++;
|
||||
tempz = (fv) ? 1 : 0;
|
||||
while ((c > 0) && (fv == tempz))
|
||||
{
|
||||
tempw=readmemw(es,EDI);
|
||||
if (cpu_state.abrt) { flags=of; break; }
|
||||
setsub16(AX,tempw);
|
||||
tempz = (ZF_SET()) ? 1 : 0;
|
||||
if (flags&D_FLAG) EDI-=2;
|
||||
else EDI+=2;
|
||||
c--;
|
||||
cycles-=(is486)?5:8;
|
||||
reads++; total_cycles += is486 ? 5 : 8;
|
||||
ins++;
|
||||
if (cycles < cycles_end)
|
||||
break;
|
||||
}
|
||||
ins--;
|
||||
if ((c>0) && (fv==tempz)) { cpu_state.pc=ipc; firstrepcycle=0; }
|
||||
else firstrepcycle=1;
|
||||
break;
|
||||
case 0x3AF: /*REP SCASL*/
|
||||
cpu_notreps++;
|
||||
tempz = (fv) ? 1 : 0;
|
||||
while ((c > 0) && (fv == tempz))
|
||||
{
|
||||
templ=readmeml(es,EDI);
|
||||
if (cpu_state.abrt) { flags=of; break; }
|
||||
setsub32(EAX,templ);
|
||||
tempz = (ZF_SET()) ? 1 : 0;
|
||||
if (flags&D_FLAG) EDI-=4;
|
||||
else EDI+=4;
|
||||
c--;
|
||||
cycles-=(is486)?5:8;
|
||||
reads_l++; total_cycles += is486 ? 5 : 8;
|
||||
ins++;
|
||||
if (cycles < cycles_end)
|
||||
break;
|
||||
}
|
||||
ins--;
|
||||
if ((c>0) && (fv==tempz)) { cpu_state.pc=ipc; firstrepcycle=0; }
|
||||
else firstrepcycle=1;
|
||||
break;
|
||||
|
||||
|
||||
default:
|
||||
cpu_state.pc = ipc+1;
|
||||
break;
|
||||
}
|
||||
if (rep32&0x200) ECX=c;
|
||||
else CX=c;
|
||||
CPU_BLOCK_END();
|
||||
PREFETCH_RUN(total_cycles, 1, -1, reads, reads_l, writes, writes_l, 0);
|
||||
return cpu_state.abrt;
|
||||
}
|
||||
|
||||
int xout=0;
|
||||
|
||||
|
||||
|
||||
Reference in New Issue
Block a user