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PCI PIRQ's are now always level when PCI IRQ steering is present, and MIRQ's are now edge/level according to the device that issues them, per the Intel datasheets, fixes annoyingly long wait at POST on PCI Pentium AMI BIOS'es because of secondary IDE.

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This commit is contained in:
OBattler
2019-10-30 04:26:36 +01:00
parent 13402ff207
commit ddbecb039a
3 changed files with 27 additions and 31 deletions
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10
src/disk/hdc_ide_sff8038i.c
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@@ -10,13 +10,13 @@
* word 0 - base address
* word 1 - bits 1-15 = byte count, bit 31 = end of transfer
*
* Version: @(#)hdc_ide_sff8038i.c 1.0.0 2019/05/12
* Version: @(#)hdc_ide_sff8038i.c 1.0.1 2019/10/30
*
* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
*
* Copyright 2008-2018 Sarah Walker.
* Copyright 2016-2018 Miran Grca.
* Copyright 2008-2019 Sarah Walker.
* Copyright 2016-2019 Miran Grca.
*/
#include <stdarg.h>
#include <stdint.h>
@@ -371,12 +371,12 @@ sff_bus_master_set_irq(int channel, void *priv)
channel &= 0x01;
if (dev->status & 0x04) {
if (channel && pci_use_mirq(0))
pci_set_mirq(0);
pci_set_mirq(0, 0);
else
picint(1 << (14 + channel));
} else {
if ((channel & 1) && pci_use_mirq(0))
pci_clear_mirq(0);
pci_clear_mirq(0, 0);
else
picintc(1 << (14 + channel));
}