diff --git a/src/chipset/opti822.c b/src/chipset/opti822.c index 210a7726e..b7f8697d6 100644 --- a/src/chipset/opti822.c +++ b/src/chipset/opti822.c @@ -46,7 +46,7 @@ typedef struct pci_regs[256]; } opti822_t; -#define ENABLE_OPTI822_LOG 1 +// #define ENABLE_OPTI822_LOG 1 #ifdef ENABLE_OPTI822_LOG int opti822_do_log = ENABLE_OPTI822_LOG; @@ -104,7 +104,8 @@ opti822_update_irqs(opti822_t *dev, int set) int irq_map[8] = { -1, 5, 9, 10, 11, 12, 14, 15 }; pic_t *temp_pic; - dev->irq_convert = (dev->pci_regs[0x53] & 0x08); + // dev->irq_convert = (dev->pci_regs[0x53] & 0x08); + dev->irq_convert = 1; for (i = 0; i < 4; i++) { reg = 0x80 + (i >> 1); @@ -127,6 +128,7 @@ opti822_pci_write(int func, int addr, uint8_t val, void *priv) { opti822_t *dev = (opti822_t *) priv; int irq, irq_map[8] = { -1, 5, 9, 10, 11, 12, 14, 15 }; + int pin, slot; opti822_log("opti822_write(%02X, %02X, %02X)\n", func, addr, val); @@ -295,20 +297,24 @@ opti822_pci_write(int func, int addr, uint8_t val, void *priv) dev->pci_regs[addr] = val; opti822_update_irqs(dev, 0); irq = irq_map[val & 0x07]; + pin = 4 - ((addr & 0x01) << 1); + slot = ((addr & 0x06) >> 1); if (irq >= 0) { - opti822_log("Set IRQ routing: INT %c%c -> %02X\n", 0x41 + ((addr & 0x01) << 1), ((addr & 0x06) >> 1) + 1, irq); - pci_set_irq_routing(PCI_INTA + ((addr & 0x07) << 1), irq); + opti822_log("Set IRQ routing: INT %c%c -> %02X\n", pin + 0x40, slot + 0x31, irq); + pci_set_irq_routing(pin + (slot << 2), irq); } else { - opti822_log("Set IRQ routing: INT %c%c -> FF\n", 0x41 + ((addr & 0x01) << 1), ((addr & 0x06) >> 1) + 1); - pci_set_irq_routing(PCI_INTA + ((addr & 0x07) << 1), PCI_IRQ_DISABLED); + opti822_log("Set IRQ routing: INT %c%c -> FF\n", pin + 0x40, slot + 0x31); + pci_set_irq_routing(pin + (slot << 2), PCI_IRQ_DISABLED); } irq = irq_map[(val >> 4) & 0x07]; + pin = 3 - ((addr & 0x01) << 1); + slot = ((addr & 0x06) >> 1); if (irq >= 0) { - opti822_log("Set IRQ routing: INT %c%c -> %02X\n", 0x42 + ((addr & 0x01) << 1), ((addr & 0x06) >> 1) + 1, irq); - pci_set_irq_routing(PCI_INTB + ((addr & 0x07) << 1), irq); + opti822_log("Set IRQ routing: INT %c%c -> %02X\n", pin + 0x40, slot + 0x31, irq); + pci_set_irq_routing(pin + (slot << 2), irq); } else { - opti822_log("Set IRQ routing: INT %c%c -> FF\n", 0x42 + ((addr & 0x01) << 1), ((addr & 0x06) >> 1) + 1); - pci_set_irq_routing(PCI_INTB + ((addr & 0x07) << 1), PCI_IRQ_DISABLED); + opti822_log("Set IRQ routing: INT %c%c -> FF\n", pin + 0x40, slot + 0x31); + pci_set_irq_routing(pin + (slot << 2), PCI_IRQ_DISABLED); } opti822_update_irqs(dev, 1); break; @@ -336,8 +342,6 @@ opti822_reset(void *priv) { opti822_t *dev = (opti822_t *) priv; - pci_set_pmc(0); - memset(dev->pci_regs, 0, 256); dev->pci_regs[0x00] = 0x45; dev->pci_regs[0x01] = 0x10; /*OPTi*/ diff --git a/src/machine/m_at_386dx_486.c b/src/machine/m_at_386dx_486.c index 0a4e7c21f..4d0b27b98 100644 --- a/src/machine/m_at_386dx_486.c +++ b/src/machine/m_at_386dx_486.c @@ -633,7 +633,7 @@ machine_at_pc330_6573_init(const machine_t *model) /* doesn't like every CPU oth machine_at_common_init(model); - pci_init(PCI_CAN_SWITCH_TYPE | PCI_ALWAYS_EXPOSE_DEV0); + pci_init(PCI_CONFIG_TYPE_1); pci_register_slot(0x10, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0); pci_register_slot(0x11, PCI_CARD_NORMAL, 1, 2, 3, 4); diff --git a/src/machine/m_at_socket4.c b/src/machine/m_at_socket4.c index 7c9ccaf42..a5bff87d7 100644 --- a/src/machine/m_at_socket4.c +++ b/src/machine/m_at_socket4.c @@ -386,12 +386,13 @@ machine_at_p5vl_init(const machine_t *model) machine_at_common_init(model); - pci_init(PCI_CAN_SWITCH_TYPE | PCI_ALWAYS_EXPOSE_DEV0); + pci_init(PCI_CONFIG_TYPE_1); pci_register_slot(0x10, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0); pci_register_slot(0x11, PCI_CARD_NORMAL, 1, 2, 3, 4); - pci_register_slot(0x12, PCI_CARD_NORMAL, 2, 3, 4, 1); - pci_register_slot(0x13, PCI_CARD_NORMAL, 3, 4, 1, 2); + pci_register_slot(0x12, PCI_CARD_NORMAL, 5, 6, 7, 8); + pci_register_slot(0x13, PCI_CARD_NORMAL, 9, 10, 11, 12); + pci_register_slot(0x14, PCI_CARD_NORMAL, 13, 14, 15, 16); device_add(&opti5x7_pci_device); device_add(&opti822_device); diff --git a/src/machine/m_at_socket5.c b/src/machine/m_at_socket5.c index 3a0adbe50..c0c18f3c7 100644 --- a/src/machine/m_at_socket5.c +++ b/src/machine/m_at_socket5.c @@ -336,7 +336,7 @@ machine_at_hot543_init(const machine_t *model) machine_at_common_init(model); - pci_init(PCI_CAN_SWITCH_TYPE | PCI_ALWAYS_EXPOSE_DEV0); + pci_init(PCI_CONFIG_TYPE_1); pci_register_slot(0x10, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0); pci_register_slot(0x11, PCI_CARD_NORMAL, 1, 2, 3, 4); diff --git a/src/pci.c b/src/pci.c index a872d4e00..6b51b0769 100644 --- a/src/pci.c +++ b/src/pci.c @@ -389,6 +389,7 @@ static uint8_t pci_type2_read(uint16_t port, void *priv); void pci_set_pmc(uint8_t pmc) { + pci_log("pci_set_pmc(%02X)\n", pmc); // pci_reset_regs(); if (!pci_pmc && (pmc & 0x01)) { @@ -649,7 +650,7 @@ pci_set_irq(uint8_t card, uint8_t pci_int) if (pci_type & PCI_NO_IRQ_STEERING) irq_line = pci_cards[slot].read(0, 0x3c, pci_cards[slot].priv); else { - irq_routing = (pci_cards[slot].irq_routing[pci_int_index] - PCI_INTA) & 3; + irq_routing = (pci_cards[slot].irq_routing[pci_int_index] - PCI_INTA) & 15; pci_log("pci_set_irq(%02X, %02X): IRQ routing for this slot and INT pin combination: %02X\n", card, pci_int, irq_routing); irq_line = pci_irqs[irq_routing]; @@ -774,7 +775,7 @@ pci_clear_irq(uint8_t card, uint8_t pci_int) if (pci_type & PCI_NO_IRQ_STEERING) irq_line = pci_cards[slot].read(0, 0x3c, pci_cards[slot].priv); else { - irq_routing = (pci_cards[slot].irq_routing[pci_int_index] - PCI_INTA) & 3; + irq_routing = (pci_cards[slot].irq_routing[pci_int_index] - PCI_INTA) & 15; // pci_log("pci_clear_irq(%02X, %02X): IRQ routing for this slot and INT pin combination: %02X\n", card, pci_int, irq_routing); irq_line = pci_irqs[irq_routing]; @@ -855,6 +856,7 @@ void pci_reset(void) { if (pci_switch) { + pci_log("pci_reset(): Switchable configuration mechanism\n"); pci_pmc = 0x00; io_removehandler(0x0cf8, 1, @@ -987,6 +989,7 @@ pci_init(int type) pci_switch = !!(type & PCI_CAN_SWITCH_TYPE); if (pci_switch) { + pci_log("PCI: Switchable configuration mechanism\n"); pci_pmc = 0x00; io_sethandler(0x0cfb, 1, @@ -1002,12 +1005,14 @@ pci_init(int type) } if ((type & PCI_CONFIG_TYPE_MASK) == PCI_CONFIG_TYPE_1) { + pci_log("PCI: Configuration mechanism #1\n"); io_sethandler(0x0cf8, 1, NULL, NULL, pci_cf8_read, NULL, NULL, pci_cf8_write, NULL); io_sethandler(0x0cfc, 4, pci_read, pci_readw, pci_readl, pci_write, pci_writew, pci_writel, NULL); pci_pmc = 1; } else { + pci_log("PCI: Configuration mechanism #2\n"); io_sethandler(0x0cf8, 1, pci_type2_read, NULL, NULL, pci_type2_write, NULL, NULL, NULL); io_sethandler(0x0cfa, 1, @@ -1015,6 +1020,7 @@ pci_init(int type) pci_pmc = 0; if (type & PCI_ALWAYS_EXPOSE_DEV0) { + pci_log("PCI: Always expose device 0\n"); pci_base = 0xc100; pci_size = 0x0f00;