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Changed several char arrays all around the code to const char pointers, debloats the executable file from 8.7 MB to 5.6 MB;

Browse Source 
Replaced the Cirrus Logic code with the latest code from TheCollector1995 - the CL-GD 5428 is now fully working, as is the CL-GD 5429;
Minor clean-up in the AHA/BusLogic BIOS commands code;
Slightly rewritten mem_readb_phys_dma() and mem_writeb_phys_dma().
This commit is contained in:
OBattler
2018-02-18 10:32:51 +01:00
parent 86af6c6ac1
commit e0a9de85c9
32 changed files with 1570 additions and 4070 deletions
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1028
src/video/vid_cl5428.c
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4
src/video/vid_cl5429.h
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/* Copyright holders: Sarah Walker
see COPYING for more details
*/
extern device_t gd5429_device;

1413
src/video/vid_cl54xx.c Normal file
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1
src/video/vid_cl5428.h → src/video/vid_cl54xx.h
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@@ -2,3 +2,4 @@
see COPYING for more details
*/
extern device_t gd5428_device;
extern device_t gd5429_device;

1174
src/video/vid_cl_gd.c
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220
src/video/vid_cl_gd.h
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// ID
#define CIRRUS_ID_CLGD6225 (0x02<<2)
#define CIRRUS_ID_CLGD5402 (0x06<<2) /* Also Acumos AVGA2 */
#define CIRRUS_ID_CLGD7542 (0x0B<<2) /* Nordic */
#define CIRRUS_ID_CLGD7543 (0x0C<<2) /* Viking - guess */
#define CIRRUS_ID_CLGD7541 (0x0D<<2) /* Nordic Lite */
#define CIRRUS_ID_CLGD6215 (0x12<<2)
#define CIRRUS_ID_CLGD6235 (0x22<<2) /* Also 5402 */
#define CIRRUS_ID_CLGD5422 (0x23<<2)
#define CIRRUS_ID_CLGD5426 (0x24<<2)
#define CIRRUS_ID_CLGD5424 (0x25<<2) /* Also 5422-80 */
#define CIRRUS_ID_CLGD5428 (0x26<<2)
#define CIRRUS_ID_CLGD5429 (0x27<<2)
#define CIRRUS_ID_CLGD5430 (0x28<<2)
#define CIRRUS_ID_CLGD5430VL (0x28<<2)+10000 /* gets fixed in code */
#define CIRRUS_ID_CLGD5432 0xA2
#define CIRRUS_ID_CLGD5434O (0x29<<2) /* O = obsolete, never used? */
#define CIRRUS_ID_CLGD5434 (0x2A<<2)
#define CIRRUS_ID_CLGD5436 (0x2B<<2)
#define CIRRUS_ID_CLGD5436U (0x3A<<2)
#define CIRRUS_ID_CLGD5440 (0x2C<<2)
#define CIRRUS_ID_CLGD5442 (0x2D<<2)
#define CIRRUS_ID_CLGD5446 (0x2E<<2)
#define CIRRUS_ID_CLGD5455 (0x2F<<2) /* Laguna 3D */
#define CIRRUS_ID_CLGD6205 (0x32<<2) /* Laguna 3D */
#define CIRRUS_ID_CLGD5462 (0x34<<2) /* Laguna */
#define CIRRUS_ID_CLGD5464 (0xD5) /* Laguna BD */
#define CIRRUS_ID_CLGD5465 (0xD6) /* Laguna 3D */
// sequencer 0x07
#define CIRRUS_SR7_BPP_VGA 0x00
#define CIRRUS_SR7_BPP_SVGA 0x01
#define CIRRUS_SR7_BPP_MASK 0x0e
#define CIRRUS_SR7_BPP_8 0x00
#define CIRRUS_SR7_BPP_16_DOUBLEVCLK 0x02
#define CIRRUS_SR7_BPP_24 0x04
#define CIRRUS_SR7_BPP_16 0x06
#define CIRRUS_SR7_BPP_32 0x08
#define CIRRUS_SR7_ISAADDR_MASK 0xe0
// sequencer 0x0f
#define CIRRUS_MEMSIZE_512k 0x08
#define CIRRUS_MEMSIZE_1M 0x10
#define CIRRUS_MEMSIZE_2M 0x18
#define CIRRUS_MEMFLAGS_BANKSWITCH 0x80 // bank switching is enabled.
// sequencer 0x12
#define CIRRUS_CURSOR_SHOW 0x01
#define CIRRUS_CURSOR_HIDDENPEL 0x02
#define CIRRUS_CURSOR_LARGE 0x04 // 64x64 if set, 32x32 if clear
// sequencer 0x17
#define CIRRUS_BUSTYPE_VLBFAST 0x10
#define CIRRUS_BUSTYPE_PCI 0x20
#define CIRRUS_BUSTYPE_VLBSLOW 0x30
#define CIRRUS_BUSTYPE_ISA 0x38
#define CIRRUS_MMIO_ENABLE 0x04
#define CIRRUS_MMIO_USE_PCIADDR 0x40 // 0xb8000 if cleared.
#define CIRRUS_MEMSIZEEXT_DOUBLE 0x80
// control 0x0b
#define CIRRUS_BANKING_DUAL 0x01
#define CIRRUS_BANKING_GRANULARITY_16K 0x20 // set:16k, clear:4k
// control 0x30
#define CIRRUS_BLTMODE_BACKWARDS 0x01
#define CIRRUS_BLTMODE_MEMSYSDEST 0x02
#define CIRRUS_BLTMODE_MEMSYSSRC 0x04
#define CIRRUS_BLTMODE_TRANSPARENTCOMP 0x08
#define CIRRUS_BLTMODE_PATTERNCOPY 0x40
#define CIRRUS_BLTMODE_COLOREXPAND 0x80
#define CIRRUS_BLTMODE_PIXELWIDTHMASK 0x30
#define CIRRUS_BLTMODE_PIXELWIDTH8 0x00
#define CIRRUS_BLTMODE_PIXELWIDTH16 0x10
#define CIRRUS_BLTMODE_PIXELWIDTH24 0x20
#define CIRRUS_BLTMODE_PIXELWIDTH32 0x30
// control 0x31
#define CIRRUS_BLT_BUSY 0x01
#define CIRRUS_BLT_START 0x02
#define CIRRUS_BLT_RESET 0x04
#define CIRRUS_BLT_FIFOUSED 0x10
#define CIRRUS_BLT_AUTOSTART 0x80
// control 0x32
#define CIRRUS_ROP_0 0x00
#define CIRRUS_ROP_SRC_AND_DST 0x05
#define CIRRUS_ROP_NOP 0x06
#define CIRRUS_ROP_SRC_AND_NOTDST 0x09
#define CIRRUS_ROP_NOTDST 0x0b
#define CIRRUS_ROP_SRC 0x0d
#define CIRRUS_ROP_1 0x0e
#define CIRRUS_ROP_NOTSRC_AND_DST 0x50
#define CIRRUS_ROP_SRC_XOR_DST 0x59
#define CIRRUS_ROP_SRC_OR_DST 0x6d
#define CIRRUS_ROP_NOTSRC_OR_NOTDST 0x90
#define CIRRUS_ROP_SRC_NOTXOR_DST 0x95
#define CIRRUS_ROP_SRC_OR_NOTDST 0xad
#define CIRRUS_ROP_NOTSRC 0xd0
#define CIRRUS_ROP_NOTSRC_OR_DST 0xd6
#define CIRRUS_ROP_NOTSRC_AND_NOTDST 0xda
#define CIRRUS_ROP_NOP_INDEX 2
#define CIRRUS_ROP_SRC_INDEX 5
// control 0x33
#define CIRRUS_BLTMODEEXT_SOLIDFILL 0x04
#define CIRRUS_BLTMODEEXT_COLOREXPINV 0x02
#define CIRRUS_BLTMODEEXT_DWORDGRANULARITY 0x01
// memory-mapped IO
#define CIRRUS_MMIO_BLTBGCOLOR 0x00 // dword
#define CIRRUS_MMIO_BLTFGCOLOR 0x04 // dword
#define CIRRUS_MMIO_BLTWIDTH 0x08 // word
#define CIRRUS_MMIO_BLTHEIGHT 0x0a // word
#define CIRRUS_MMIO_BLTDESTPITCH 0x0c // word
#define CIRRUS_MMIO_BLTSRCPITCH 0x0e // word
#define CIRRUS_MMIO_BLTDESTADDR 0x10 // dword
#define CIRRUS_MMIO_BLTSRCADDR 0x14 // dword
#define CIRRUS_MMIO_BLTWRITEMASK 0x17 // byte
#define CIRRUS_MMIO_BLTMODE 0x18 // byte
#define CIRRUS_MMIO_BLTROP 0x1a // byte
#define CIRRUS_MMIO_BLTMODEEXT 0x1b // byte
#define CIRRUS_MMIO_BLTTRANSPARENTCOLOR 0x1c // word?
#define CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK 0x20 // word?
#define CIRRUS_MMIO_LINEARDRAW_START_X 0x24 // word
#define CIRRUS_MMIO_LINEARDRAW_START_Y 0x26 // word
#define CIRRUS_MMIO_LINEARDRAW_END_X 0x28 // word
#define CIRRUS_MMIO_LINEARDRAW_END_Y 0x2a // word
#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_INC 0x2c // byte
#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ROLLOVER 0x2d // byte
#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_MASK 0x2e // byte
#define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ACCUM 0x2f // byte
#define CIRRUS_MMIO_BRESENHAM_K1 0x30 // word
#define CIRRUS_MMIO_BRESENHAM_K3 0x32 // word
#define CIRRUS_MMIO_BRESENHAM_ERROR 0x34 // word
#define CIRRUS_MMIO_BRESENHAM_DELTA_MAJOR 0x36 // word
#define CIRRUS_MMIO_BRESENHAM_DIRECTION 0x38 // byte
#define CIRRUS_MMIO_LINEDRAW_MODE 0x39 // byte
#define CIRRUS_MMIO_BLTSTATUS 0x40 // byte
#define CIRRUS_PNPMMIO_SIZE 0x1000
#define CIRRUS_BLTBUFSIZE (2048 * 4) /* one line width */
typedef struct clgd_t
{
mem_mapping_t mmio_mapping;
svga_t svga;
cl_ramdac_t ramdac;
rom_t bios_rom;
PALETTE hiddenpal;
uint32_t vram_size;
uint8_t vram_code;
uint32_t linear_mmio_mask;
uint32_t bank[2];
uint32_t limit[2];
uint32_t ramptr;
int src_counter;
uint8_t *src_ptr;
uint8_t *src_ptr_end;
struct
{
uint8_t bpp;
uint32_t bg_col, fg_col;
uint16_t width, height;
uint16_t dst_pitch, src_pitch;
int32_t dst_addr, src_addr;
uint8_t mask, mode, rop, modeext;
uint32_t blttc, blttcmask;
uint16_t ld_start_x, ld_start_y, ld_end_x, ld_end_y;
uint8_t ld_ls_inc, ld_ls_ro, ld_ls_mask, ld_ls_ac;
uint16_t bres_k1, bres_k3, bres_err, bres_dm;
uint8_t bres_dir, ld_mode, blt_status;
uint32_t dst_addr_backup, src_addr_backup;
uint16_t width_backup, height_internal;
int x_count;
uint8_t buf[CIRRUS_BLTBUFSIZE];
uint16_t pixel_width, pixel_height;
} blt;
} clgd_t;
typedef void (*cirrus_bitblt_rop_t) (clgd_t *clgd, svga_t *svga,
uint8_t * dst, const uint8_t * src,
int dstpitch, int srcpitch,
int bltwidth, int bltheight);
typedef void (*cirrus_fill_t)(clgd_t *clgd, svga_t *svga,
uint8_t *dst, int dst_pitch, int width, int height);
cirrus_bitblt_rop_t cirrus_rop;
extern device_t gd5422_device;
extern device_t gd5429_device;
extern device_t gd5430_device;
extern device_t dia5430_device;
extern device_t gd5434_device;
extern device_t gd5436_device;
extern device_t gd5440_device;
extern device_t gd5446_device;
extern device_t gd6235_device;
clgd_t *clgd;
void clgd_recalctimings(svga_t *svga);
void cirrus_update_memory_access(clgd_t *clgd);
void cirrus_write(uint32_t addr, uint8_t val, void *p);
uint8_t cirrus_read(uint32_t addr, void *p);

847
src/video/vid_cl_gd_blit.c
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/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* This is the CL-GD 5446 blitter, directly from QEMU.
*
* Version: @(#)vid_cl_gd_blit.c 1.0.2 2017/11/04
*
* Author: Miran Grca, <mgrca8@gmail.com>
*
* Copyright 2016,2017 Miran Grca.
*/
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <stdlib.h>
#include <wchar.h>
#include "../86box.h"
#include "../io.h"
#include "../mem.h"
#include "../rom.h"
#include "../device.h"
#include "video.h"
#include "vid_svga.h"
#include "vid_svga_render.h"
#include "vid_cl_ramdac.h"
#include "vid_cl_gd.h"
#include "vid_cl_gd_blit.h"
// Same for all the svga->vrammask which are -s>cirrus_addr_mask in the original.
// Eventually this needs to be configurable
#define clgd_vram_size clgd->vram_size
#define true 1
#define false 0
#define bool int
#define glue(a,b) glue_hidden(a,b)
#define glue_hidden(a,b) a ## b
static uint8_t rop_to_index[256];
int cl_gd_ABS(int sval)
{
if (sval < 0)
{
return -sval;
}
else
{
return sval;
}
}
bool blit_region_is_unsafe(clgd_t *clgd, svga_t *svga, int32_t pitch, int32_t addr)
{
if (pitch < 0)
{
int64_t min = addr + ((int64_t)clgd->blt.height-1) * pitch;
int32_t max = addr + clgd->blt.width;
if (min < 0 || max >= clgd_vram_size) return true;
}
else
{
int64_t max = addr + ((int64_t)clgd->blt.height-1) * pitch + clgd->blt.width;
if (max >= clgd_vram_size) return true;
}
return false;
}
bool blit_is_unsafe(clgd_t *clgd, svga_t *svga)
{
if (clgd->blt.width > 0) fatal("CL-clgd: Blit width is 0!\n");
if (clgd->blt.height > 0) fatal("CL-clgd: Blit height is 0!\n");
if (clgd->blt.width > CIRRUS_BLTBUFSIZE) return true;
if (blit_region_is_unsafe(clgd, svga, clgd->blt.dst_pitch, clgd->blt.dst_addr & svga->vram_display_mask)) return true;
if (blit_region_is_unsafe(clgd, svga, clgd->blt.src_pitch, clgd->blt.src_addr & svga->vram_display_mask)) return true;
return false;
}
void cirrus_bitblt_rop_nop(clgd_t *clgd, svga_t *svga, uint8_t *dst, const uint8_t *src, int dstpitch, int srcpitch, int bltwidth, int bltheight)
{
}
void cirrus_bitblt_fill_nop(clgd_t *clgd, svga_t *svga, uint8_t *dst, int dstpitch, int bltwidth, int bltheight)
{
}
#define ROP_NAME 0
#define ROP_FN(d, s) 0
#include "vid_cl_gd_vga_rop.h"
#define ROP_NAME src_and_dst
#define ROP_FN(d, s) (s) & (d)
#include "vid_cl_gd_vga_rop.h"
#define ROP_NAME src_and_notdst
#define ROP_FN(d, s) (s) & (~(d))
#include "vid_cl_gd_vga_rop.h"
#define ROP_NAME notdst
#define ROP_FN(d, s) ~(d)
#include "vid_cl_gd_vga_rop.h"
#define ROP_NAME src
#define ROP_FN(d, s) s
#include "vid_cl_gd_vga_rop.h"
#define ROP_NAME 1
#define ROP_FN(d, s) ~0
#include "vid_cl_gd_vga_rop.h"
#define ROP_NAME notsrc_and_dst
#define ROP_FN(d, s) (~(s)) & (d)
#include "vid_cl_gd_vga_rop.h"
#define ROP_NAME src_xor_dst
#define ROP_FN(d, s) (s) ^ (d)
#include "vid_cl_gd_vga_rop.h"
#define ROP_NAME src_or_dst
#define ROP_FN(d, s) (s) | (d)
#include "vid_cl_gd_vga_rop.h"
#define ROP_NAME notsrc_or_notdst
#define ROP_FN(d, s) (~(s)) | (~(d))
#include "vid_cl_gd_vga_rop.h"
#define ROP_NAME src_notxor_dst
#define ROP_FN(d, s) ~((s) ^ (d))
#include "vid_cl_gd_vga_rop.h"
#define ROP_NAME src_or_notdst
#define ROP_FN(d, s) (s) | (~(d))
#include "vid_cl_gd_vga_rop.h"
#define ROP_NAME notsrc
#define ROP_FN(d, s) (~(s))
#include "vid_cl_gd_vga_rop.h"
#define ROP_NAME notsrc_or_dst
#define ROP_FN(d, s) (~(s)) | (d)
#include "vid_cl_gd_vga_rop.h"
#define ROP_NAME notsrc_and_notdst
#define ROP_FN(d, s) (~(s)) & (~(d))
#include "vid_cl_gd_vga_rop.h"
const cirrus_bitblt_rop_t cirrus_fwd_rop[16] = {
cirrus_bitblt_rop_fwd_0,
cirrus_bitblt_rop_fwd_src_and_dst,
cirrus_bitblt_rop_nop,
cirrus_bitblt_rop_fwd_src_and_notdst,
cirrus_bitblt_rop_fwd_notdst,
cirrus_bitblt_rop_fwd_src,
cirrus_bitblt_rop_fwd_1,
cirrus_bitblt_rop_fwd_notsrc_and_dst,
cirrus_bitblt_rop_fwd_src_xor_dst,
cirrus_bitblt_rop_fwd_src_or_dst,
cirrus_bitblt_rop_fwd_notsrc_or_notdst,
cirrus_bitblt_rop_fwd_src_notxor_dst,
cirrus_bitblt_rop_fwd_src_or_notdst,
cirrus_bitblt_rop_fwd_notsrc,
cirrus_bitblt_rop_fwd_notsrc_or_dst,
cirrus_bitblt_rop_fwd_notsrc_and_notdst,
};
const cirrus_bitblt_rop_t cirrus_bkwd_rop[16] = {
cirrus_bitblt_rop_bkwd_0,
cirrus_bitblt_rop_bkwd_src_and_dst,
cirrus_bitblt_rop_nop,
cirrus_bitblt_rop_bkwd_src_and_notdst,
cirrus_bitblt_rop_bkwd_notdst,
cirrus_bitblt_rop_bkwd_src,
cirrus_bitblt_rop_bkwd_1,
cirrus_bitblt_rop_bkwd_notsrc_and_dst,
cirrus_bitblt_rop_bkwd_src_xor_dst,
cirrus_bitblt_rop_bkwd_src_or_dst,
cirrus_bitblt_rop_bkwd_notsrc_or_notdst,
cirrus_bitblt_rop_bkwd_src_notxor_dst,
cirrus_bitblt_rop_bkwd_src_or_notdst,
cirrus_bitblt_rop_bkwd_notsrc,
cirrus_bitblt_rop_bkwd_notsrc_or_dst,
cirrus_bitblt_rop_bkwd_notsrc_and_notdst,
};
#define TRANSP_ROP(name) {\
name ## _8,\
name ## _16,\
}
#define TRANSP_NOP(func) {\
func,\
func,\
}
const cirrus_bitblt_rop_t cirrus_fwd_transp_rop[16][2] = {
TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_0),
TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_dst),
TRANSP_NOP(cirrus_bitblt_rop_nop),
TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_notdst),
TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notdst),
TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src),
TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_1),
TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_dst),
TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_xor_dst),
TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_dst),
TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_notdst),
TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_notxor_dst),
TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_notdst),
TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc),
TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_dst),
TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_notdst),
};
const cirrus_bitblt_rop_t cirrus_bkwd_transp_rop[16][2] = {
TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_0),
TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_dst),
TRANSP_NOP(cirrus_bitblt_rop_nop),
TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_notdst),
TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notdst),
TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src),
TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_1),
TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_dst),
TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_xor_dst),
TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_dst),
TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_notdst),
TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_notxor_dst),
TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_notdst),
TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc),
TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_dst),
TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_notdst),
};
#define ROP2(name) {\
name ## _8,\
name ## _16,\
name ## _24,\
name ## _32,\
}
#define ROP_NOP2(func) {\
func,\
func,\
func,\
func,\
}
const cirrus_bitblt_rop_t cirrus_patternfill[16][4] = {
ROP2(cirrus_patternfill_0),
ROP2(cirrus_patternfill_src_and_dst),
ROP_NOP2(cirrus_bitblt_rop_nop),
ROP2(cirrus_patternfill_src_and_notdst),
ROP2(cirrus_patternfill_notdst),
ROP2(cirrus_patternfill_src),
ROP2(cirrus_patternfill_1),
ROP2(cirrus_patternfill_notsrc_and_dst),
ROP2(cirrus_patternfill_src_xor_dst),
ROP2(cirrus_patternfill_src_or_dst),
ROP2(cirrus_patternfill_notsrc_or_notdst),
ROP2(cirrus_patternfill_src_notxor_dst),
ROP2(cirrus_patternfill_src_or_notdst),
ROP2(cirrus_patternfill_notsrc),
ROP2(cirrus_patternfill_notsrc_or_dst),
ROP2(cirrus_patternfill_notsrc_and_notdst),
};
const cirrus_bitblt_rop_t cirrus_colorexpand_transp[16][4] = {
ROP2(cirrus_colorexpand_transp_0),
ROP2(cirrus_colorexpand_transp_src_and_dst),
ROP_NOP2(cirrus_bitblt_rop_nop),
ROP2(cirrus_colorexpand_transp_src_and_notdst),
ROP2(cirrus_colorexpand_transp_notdst),
ROP2(cirrus_colorexpand_transp_src),
ROP2(cirrus_colorexpand_transp_1),
ROP2(cirrus_colorexpand_transp_notsrc_and_dst),
ROP2(cirrus_colorexpand_transp_src_xor_dst),
ROP2(cirrus_colorexpand_transp_src_or_dst),
ROP2(cirrus_colorexpand_transp_notsrc_or_notdst),
ROP2(cirrus_colorexpand_transp_src_notxor_dst),
ROP2(cirrus_colorexpand_transp_src_or_notdst),
ROP2(cirrus_colorexpand_transp_notsrc),
ROP2(cirrus_colorexpand_transp_notsrc_or_dst),
ROP2(cirrus_colorexpand_transp_notsrc_and_notdst),
};
const cirrus_bitblt_rop_t cirrus_colorexpand[16][4] = {
ROP2(cirrus_colorexpand_0),
ROP2(cirrus_colorexpand_src_and_dst),
ROP_NOP2(cirrus_bitblt_rop_nop),
ROP2(cirrus_colorexpand_src_and_notdst),
ROP2(cirrus_colorexpand_notdst),
ROP2(cirrus_colorexpand_src),
ROP2(cirrus_colorexpand_1),
ROP2(cirrus_colorexpand_notsrc_and_dst),
ROP2(cirrus_colorexpand_src_xor_dst),
ROP2(cirrus_colorexpand_src_or_dst),
ROP2(cirrus_colorexpand_notsrc_or_notdst),
ROP2(cirrus_colorexpand_src_notxor_dst),
ROP2(cirrus_colorexpand_src_or_notdst),
ROP2(cirrus_colorexpand_notsrc),
ROP2(cirrus_colorexpand_notsrc_or_dst),
ROP2(cirrus_colorexpand_notsrc_and_notdst),
};
const cirrus_bitblt_rop_t cirrus_colorexpand_pattern_transp[16][4] = {
ROP2(cirrus_colorexpand_pattern_transp_0),
ROP2(cirrus_colorexpand_pattern_transp_src_and_dst),
ROP_NOP2(cirrus_bitblt_rop_nop),
ROP2(cirrus_colorexpand_pattern_transp_src_and_notdst),
ROP2(cirrus_colorexpand_pattern_transp_notdst),
ROP2(cirrus_colorexpand_pattern_transp_src),
ROP2(cirrus_colorexpand_pattern_transp_1),
ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_dst),
ROP2(cirrus_colorexpand_pattern_transp_src_xor_dst),
ROP2(cirrus_colorexpand_pattern_transp_src_or_dst),
ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_notdst),
ROP2(cirrus_colorexpand_pattern_transp_src_notxor_dst),
ROP2(cirrus_colorexpand_pattern_transp_src_or_notdst),
ROP2(cirrus_colorexpand_pattern_transp_notsrc),
ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_dst),
ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_notdst),
};
const cirrus_bitblt_rop_t cirrus_colorexpand_pattern[16][4] = {
ROP2(cirrus_colorexpand_pattern_0),
ROP2(cirrus_colorexpand_pattern_src_and_dst),
ROP_NOP2(cirrus_bitblt_rop_nop),
ROP2(cirrus_colorexpand_pattern_src_and_notdst),
ROP2(cirrus_colorexpand_pattern_notdst),
ROP2(cirrus_colorexpand_pattern_src),
ROP2(cirrus_colorexpand_pattern_1),
ROP2(cirrus_colorexpand_pattern_notsrc_and_dst),
ROP2(cirrus_colorexpand_pattern_src_xor_dst),
ROP2(cirrus_colorexpand_pattern_src_or_dst),
ROP2(cirrus_colorexpand_pattern_notsrc_or_notdst),
ROP2(cirrus_colorexpand_pattern_src_notxor_dst),
ROP2(cirrus_colorexpand_pattern_src_or_notdst),
ROP2(cirrus_colorexpand_pattern_notsrc),
ROP2(cirrus_colorexpand_pattern_notsrc_or_dst),
ROP2(cirrus_colorexpand_pattern_notsrc_and_notdst),
};
const cirrus_fill_t cirrus_fill[16][4] = {
ROP2(cirrus_fill_0),
ROP2(cirrus_fill_src_and_dst),
ROP_NOP2(cirrus_bitblt_fill_nop),
ROP2(cirrus_fill_src_and_notdst),
ROP2(cirrus_fill_notdst),
ROP2(cirrus_fill_src),
ROP2(cirrus_fill_1),
ROP2(cirrus_fill_notsrc_and_dst),
ROP2(cirrus_fill_src_xor_dst),
ROP2(cirrus_fill_src_or_dst),
ROP2(cirrus_fill_notsrc_or_notdst),
ROP2(cirrus_fill_src_notxor_dst),
ROP2(cirrus_fill_src_or_notdst),
ROP2(cirrus_fill_notsrc),
ROP2(cirrus_fill_notsrc_or_dst),
ROP2(cirrus_fill_notsrc_and_notdst),
};
inline void cirrus_bitblt_fgcol(clgd_t *clgd, svga_t *svga)
{
unsigned int color;
switch (clgd->blt.pixel_width)
{
case 1:
clgd->blt.fg_col = (clgd->blt.fg_col & 0xffffff00);
break;
case 2:
color = (clgd->blt.fg_col & 0xffff00ff) | (svga->gdcreg[0x11] << 8);
clgd->blt.fg_col = le16_to_cpu(color);
break;
case 3:
clgd->blt.fg_col = (clgd->blt.fg_col & 0xff00ffff) | (svga->gdcreg[0x11] << 8) | (svga->gdcreg[0x13] << 16);
break;
default:
case 4:
color = (clgd->blt.fg_col & 0x00ffffff) | (svga->gdcreg[0x11] << 8) | (svga->gdcreg[0x13] << 16) | (svga->gdcreg[0x15] << 24);
clgd->blt.fg_col = le32_to_cpu(color);
break;
}
}
inline void cirrus_bitblt_bgcol(clgd_t *clgd, svga_t *svga)
{
unsigned int color;
switch (clgd->blt.pixel_width)
{
case 1:
clgd->blt.bg_col = (clgd->blt.bg_col & 0xffffff00);
break;
case 2:
color = (clgd->blt.bg_col & 0xffff00ff) | (svga->gdcreg[0x10] << 8);
clgd->blt.bg_col = le16_to_cpu(color);
break;
case 3:
clgd->blt.bg_col = (clgd->blt.bg_col & 0xff00ffff) | (svga->gdcreg[0x10] << 8) | (svga->gdcreg[0x12] << 16);
break;
default:
case 4:
color = (clgd->blt.bg_col & 0x00ffffff) | (svga->gdcreg[0x10] << 8) | (svga->gdcreg[0x12] << 16) | (svga->gdcreg[0x14] << 24);
clgd->blt.bg_col = le32_to_cpu(color);
break;
}
}
void cirrus_invalidate_region(clgd_t *clgd, svga_t *svga, int off_begin, int off_pitch, int bytesperline, int lines)
{
int x, y;
int off_cur;
int off_cur_end;
for (y = 0; y < lines; y++)
{
off_cur = off_begin;
off_cur_end = ((off_cur + bytesperline) & svga->vram_display_mask);
// Memory region set dirty
off_begin += off_pitch;
for (x = (off_cur >> 12); x <= (off_cur_end >> 12); x++)
{
svga->changedvram[x]++;
}
}
}
int cirrus_bitblt_common_patterncopy(clgd_t *clgd, svga_t *svga, const uint8_t * src)
{
uint8_t *dst;
dst = svga->vram + (clgd->blt.dst_addr & svga->vram_display_mask);
if (blit_is_unsafe(clgd, svga)) return 0;
(*cirrus_rop) (clgd, svga, dst, src, clgd->blt.dst_pitch, 0, clgd->blt.width, clgd->blt.height);
cirrus_invalidate_region(clgd, svga, clgd->blt.dst_addr, clgd->blt.dst_pitch, clgd->blt.width, clgd->blt.height);
return 1;
}
/* fill */
int cirrus_bitblt_solidfill(clgd_t *clgd, svga_t *svga, int blt_rop)
{
cirrus_fill_t rop_func;
if (blit_is_unsafe(clgd, svga)) return 0;
rop_func = cirrus_fill[rop_to_index[blt_rop]][clgd->blt.pixel_width - 1];
rop_func(clgd, svga, svga->vram + (clgd->blt.dst_addr & svga->vram_display_mask), clgd->blt.dst_pitch, clgd->blt.width, clgd->blt.height);
cirrus_invalidate_region(clgd, svga, clgd->blt.dst_addr, clgd->blt.dst_pitch, clgd->blt.width, clgd->blt.height);
cirrus_bitblt_reset(clgd, svga);
return 1;
}
int cirrus_bitblt_videotovideo_patterncopy(clgd_t *clgd, svga_t *svga)
{
return cirrus_bitblt_common_patterncopy(clgd, svga, svga->vram + ((clgd->blt.src_addr & ~7) & svga->vram_display_mask));
}
void cirrus_do_copy(clgd_t *clgd, svga_t *svga, int dst, int src, int w, int h)
{
int sx = 0, sy = 0;
int dx = 0, dy = 0;
int notify = 0;
/* make sure to only copy if it's a plain copy ROP */
if (*cirrus_rop == cirrus_bitblt_rop_fwd_src ||
*cirrus_rop == cirrus_bitblt_rop_bkwd_src)
{
int width, height;
clgd_recalctimings(svga);
width = svga->video_res_x;
height = svga->video_res_y;
/* extra x, y */
sx = (src % cl_gd_ABS(clgd->blt.src_pitch)) / svga->bpp;
sy = (src / cl_gd_ABS(clgd->blt.src_pitch));
dx = (dst % cl_gd_ABS(clgd->blt.dst_pitch)) / svga->bpp;
dy = (dst / cl_gd_ABS(clgd->blt.dst_pitch));
/* normalize width */
w /= svga->bpp;
/* if we're doing a backward copy, we have to adjust
our x/y to be the upper left corner (instead of the lower right corner) */
if (clgd->blt.dst_pitch < 0)
{
sx -= (clgd->blt.width / svga->bpp) - 1;
dx -= (clgd->blt.width / svga->bpp) - 1;
sy -= clgd->blt.height - 1;
dy -= clgd->blt.height - 1;
}
/* are we in the visible portion of memory? */
if (sx >= 0 && sy >= 0 && dx >= 0 && dy >= 0 &&
(sx + w) <= width && (sy + h) <= height &&
(dx + w) <= width && (dy + h) <= height)
{
notify = 1;
}
}
/* we have to flush all prending changes so that the copy
is generated at the appropriate moment in time */
if (notify)
{
svga->fullchange = changeframecount;
svga_recalctimings(svga);
}
/* we don't have to notify the display that this portion has
changed since qemu_console_copy implies this */
cirrus_invalidate_region(clgd, svga, clgd->blt.dst_addr, clgd->blt.dst_pitch, clgd->blt.width, clgd->blt.height);
}
int cirrus_bitblt_videotovideo_copy(clgd_t *clgd, svga_t *svga)
{
if (blit_is_unsafe(clgd, svga)) return 0;
cirrus_do_copy(clgd, svga, clgd->blt.dst_addr - svga->firstline, clgd->blt.src_addr - svga->firstline,
clgd->blt.width, clgd->blt.height);
return 1;
}
void cirrus_bitblt_cputovideo_next(clgd_t *clgd, svga_t *svga)
{
int copy_count;
uint8_t *end_ptr;
if (clgd->src_counter > 0)
{
if (clgd->blt.mode & CIRRUS_BLTMODE_PATTERNCOPY)
{
cirrus_bitblt_common_patterncopy(clgd, svga, clgd->blt.buf);
the_end:
clgd->src_counter = 0;
cirrus_bitblt_reset(clgd, svga);
}
else
{
/* at least one scan line */
do
{
(*cirrus_rop)(clgd, svga, svga->vram + (clgd->blt.dst_addr & svga->vram_display_mask), clgd->blt.buf, 0, 0, clgd->blt.width, 1);
cirrus_invalidate_region(clgd, svga, clgd->blt.dst_addr, 0 , clgd->blt.width, 1);
clgd->blt.dst_addr += clgd->blt.dst_pitch;
clgd->src_counter -= clgd->blt.src_pitch;
if (clgd->src_counter <= 0) goto the_end;
/* more bytes than needed can be transferred because of
word alignment, so we keep them for the next line */
/* XXX: keep alignment to speed up transfer */
end_ptr = clgd->blt.buf + clgd->blt.src_pitch;
copy_count = clgd->src_ptr_end - end_ptr;
memmove(clgd->blt.buf, end_ptr, copy_count);
clgd->src_ptr = clgd->blt.buf + copy_count;
clgd->src_ptr_end = clgd->blt.buf + clgd->blt.src_pitch;
}
while (clgd->src_ptr >= clgd->src_ptr_end);
}
}
}
void cirrus_bitblt_reset(clgd_t *clgd, svga_t *svga)
{
int need_update;
svga->gdcreg[0x31] &= ~(CIRRUS_BLT_START | CIRRUS_BLT_BUSY | CIRRUS_BLT_FIFOUSED);
need_update = clgd->src_ptr != &clgd->blt.buf[0]
|| clgd->src_ptr_end != &clgd->blt.buf[0];
clgd->src_ptr = &clgd->blt.buf[0];
clgd->src_ptr_end = &clgd->blt.buf[0];
clgd->src_counter = 0;
if (!need_update)
return;
mem_mapping_set_handler(&clgd->svga.mapping, cirrus_read, NULL, NULL, cirrus_write, NULL, NULL);
mem_mapping_set_p(&clgd->svga.mapping, clgd);
cirrus_update_memory_access(clgd);
}
int cirrus_bitblt_cputovideo(clgd_t *clgd, svga_t *svga)
{
int w;
clgd->blt.mode &= ~CIRRUS_BLTMODE_MEMSYSSRC;
clgd->src_ptr = &clgd->blt.buf[0];
clgd->src_ptr_end = &clgd->blt.buf[0];
if (clgd->blt.mode & CIRRUS_BLTMODE_PATTERNCOPY)
{
if (clgd->blt.mode & CIRRUS_BLTMODE_COLOREXPAND)
{
clgd->blt.src_pitch = 8;
}
else
{
/* XXX: check for 24 bpp */
clgd->blt.src_pitch = 8 * 8 * clgd->blt.pixel_width;
}
clgd->src_counter = clgd->blt.src_pitch;
}
else
{
if (clgd->blt.mode & CIRRUS_BLTMODE_COLOREXPAND)
{
w = clgd->blt.width / clgd->blt.pixel_width;
if (clgd->blt.modeext & CIRRUS_BLTMODEEXT_DWORDGRANULARITY)
clgd->blt.src_pitch = ((w + 31) >> 5);
else
clgd->blt.src_pitch = ((w + 7) >> 3);
}
else
{
/* always align input size to 32 bit */
clgd->blt.src_pitch = (clgd->blt.width + 3) & ~3;
}
clgd->src_counter = clgd->blt.src_pitch * clgd->blt.height;
}
clgd->src_ptr = clgd->blt.buf;
clgd->src_ptr_end = clgd->blt.buf + clgd->blt.src_pitch;
cirrus_update_memory_access(clgd);
return 1;
}
int cirrus_bitblt_videotocpu(clgd_t *clgd, svga_t *svga)
{
/* XXX */
#ifdef DEBUG_BITBLT
printf("cirrus: bitblt (video to cpu) is not implemented yet\n");
#endif
return 0;
}
int cirrus_bitblt_videotovideo(clgd_t *clgd, svga_t *svga)
{
int ret;
if (clgd->blt.mode & CIRRUS_BLTMODE_PATTERNCOPY)
{
ret = cirrus_bitblt_videotovideo_patterncopy(clgd, svga);
}
else
{
ret = cirrus_bitblt_videotovideo_copy(clgd, svga);
}
if (ret)
cirrus_bitblt_reset(clgd, svga);
return ret;
}
void cirrus_bitblt_start(clgd_t *clgd, svga_t *svga)
{
uint8_t blt_rop;
svga->gdcreg[0x31] |= CIRRUS_BLT_BUSY;
clgd->blt.width = (svga->gdcreg[0x20] | (svga->gdcreg[0x21] << 8)) + 1;
clgd->blt.height = (svga->gdcreg[0x22] | (svga->gdcreg[0x23] << 8)) + 1;
clgd->blt.dst_pitch = (svga->gdcreg[0x24] | (svga->gdcreg[0x25] << 8));
clgd->blt.src_pitch = (svga->gdcreg[0x26] | (svga->gdcreg[0x27] << 8));
clgd->blt.dst_addr = (svga->gdcreg[0x28] | (svga->gdcreg[0x29] << 8) | (svga->gdcreg[0x2a] << 16));
clgd->blt.src_addr = (svga->gdcreg[0x2c] | (svga->gdcreg[0x2d] << 8) | (svga->gdcreg[0x2e] << 16));
clgd->blt.mode = svga->gdcreg[0x30];
clgd->blt.modeext = svga->gdcreg[0x33];
blt_rop = svga->gdcreg[0x32];
switch (clgd->blt.mode & CIRRUS_BLTMODE_PIXELWIDTHMASK)
{
case CIRRUS_BLTMODE_PIXELWIDTH8:
clgd->blt.pixel_width = 1;
break;
case CIRRUS_BLTMODE_PIXELWIDTH16:
clgd->blt.pixel_width = 2;
break;
case CIRRUS_BLTMODE_PIXELWIDTH24:
clgd->blt.pixel_width = 3;
break;
case CIRRUS_BLTMODE_PIXELWIDTH32:
clgd->blt.pixel_width = 4;
break;
default:
goto bitblt_ignore;
}
clgd->blt.mode &= ~CIRRUS_BLTMODE_PIXELWIDTHMASK;
if ((clgd->blt.mode & (CIRRUS_BLTMODE_MEMSYSSRC | CIRRUS_BLTMODE_MEMSYSDEST)) == (CIRRUS_BLTMODE_MEMSYSSRC | CIRRUS_BLTMODE_MEMSYSDEST))
{
goto bitblt_ignore;
}
if ((clgd->blt.modeext & CIRRUS_BLTMODEEXT_SOLIDFILL) &&
(clgd->blt.mode & (CIRRUS_BLTMODE_MEMSYSDEST | CIRRUS_BLTMODE_TRANSPARENTCOMP | CIRRUS_BLTMODE_PATTERNCOPY | CIRRUS_BLTMODE_COLOREXPAND)) ==
(CIRRUS_BLTMODE_PATTERNCOPY | CIRRUS_BLTMODE_COLOREXPAND))
{
cirrus_bitblt_fgcol(clgd, svga);
cirrus_bitblt_solidfill(clgd, svga, blt_rop);
}
else
{
if ((clgd->blt.mode & (CIRRUS_BLTMODE_COLOREXPAND | CIRRUS_BLTMODE_PATTERNCOPY)) == CIRRUS_BLTMODE_COLOREXPAND)
{
if (clgd->blt.mode & CIRRUS_BLTMODE_TRANSPARENTCOMP)
{
if (clgd->blt.modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
cirrus_bitblt_bgcol(clgd, svga);
else
cirrus_bitblt_fgcol(clgd, svga);
cirrus_rop = cirrus_colorexpand_transp[rop_to_index[blt_rop]][clgd->blt.pixel_width - 1];
}
else
{
cirrus_bitblt_fgcol(clgd, svga);
cirrus_bitblt_bgcol(clgd, svga);
cirrus_rop = cirrus_colorexpand[rop_to_index[blt_rop]][clgd->blt.pixel_width - 1];
}
}
else if (clgd->blt.mode & CIRRUS_BLTMODE_PATTERNCOPY)
{
if (clgd->blt.mode & CIRRUS_BLTMODE_COLOREXPAND)
{
if (clgd->blt.mode & CIRRUS_BLTMODE_TRANSPARENTCOMP)
{
if (clgd->blt.modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
cirrus_bitblt_bgcol(clgd, svga);
else
cirrus_bitblt_fgcol(clgd, svga);
cirrus_rop = cirrus_colorexpand_pattern_transp[rop_to_index[blt_rop]][clgd->blt.pixel_width - 1];
}
else
{
cirrus_bitblt_fgcol(clgd, svga);
cirrus_bitblt_bgcol(clgd, svga);
cirrus_rop = cirrus_colorexpand_pattern[rop_to_index[blt_rop]][clgd->blt.pixel_width - 1];
}
}
else
{
cirrus_rop = cirrus_patternfill[rop_to_index[blt_rop]][clgd->blt.pixel_width - 1];
}
}
else
{
if (clgd->blt.mode & CIRRUS_BLTMODE_TRANSPARENTCOMP)
{
if (clgd->blt.pixel_width > 2)
{
goto bitblt_ignore;
}
if (clgd->blt.mode & CIRRUS_BLTMODE_BACKWARDS)
{
clgd->blt.dst_pitch = -clgd->blt.dst_pitch;
clgd->blt.src_pitch = -clgd->blt.src_pitch;
cirrus_rop = cirrus_bkwd_transp_rop[rop_to_index[blt_rop]][clgd->blt.pixel_width - 1];
}
else
{
cirrus_rop = cirrus_fwd_transp_rop[rop_to_index[blt_rop]][clgd->blt.pixel_width - 1];
}
}
else
{
if (clgd->blt.mode & CIRRUS_BLTMODE_BACKWARDS)
{
clgd->blt.dst_pitch = -clgd->blt.dst_pitch;
clgd->blt.src_pitch = -clgd->blt.src_pitch;
cirrus_rop = cirrus_bkwd_rop[rop_to_index[blt_rop]];
}
else
{
cirrus_rop = cirrus_fwd_rop[rop_to_index[blt_rop]];
}
}
}
// setup bitblt engine.
if (clgd->blt.mode & CIRRUS_BLTMODE_MEMSYSSRC)
{
if (!cirrus_bitblt_cputovideo(clgd, svga)) goto bitblt_ignore;
}
else if (clgd->blt.mode & CIRRUS_BLTMODE_MEMSYSDEST)
{
if (!cirrus_bitblt_videotocpu(clgd, svga)) goto bitblt_ignore;
}
else
{
if (!cirrus_bitblt_videotovideo(clgd, svga)) goto bitblt_ignore;
}
}
return;
bitblt_ignore:;
cirrus_bitblt_reset(clgd, svga);
}
void cirrus_write_bitblt(clgd_t *clgd, svga_t *svga, uint8_t reg_value)
{
uint8_t old_value;
old_value = svga->gdcreg[0x31];
svga->gdcreg[0x31] = reg_value;
if (((old_value & CIRRUS_BLT_RESET) != 0) &&
((reg_value & CIRRUS_BLT_RESET) == 0))
{
cirrus_bitblt_reset(clgd, svga);
}
else if (((old_value & CIRRUS_BLT_START) == 0) &&
((reg_value & CIRRUS_BLT_START) != 0))
{
cirrus_bitblt_start(clgd, svga);
}
}
void init_rops()
{
int i = 0;
for(i = 0;i < 256; i++)
rop_to_index[i] = CIRRUS_ROP_NOP_INDEX; /* nop rop */
rop_to_index[CIRRUS_ROP_0] = 0;
rop_to_index[CIRRUS_ROP_SRC_AND_DST] = 1;
rop_to_index[CIRRUS_ROP_NOP] = 2;
rop_to_index[CIRRUS_ROP_SRC_AND_NOTDST] = 3;
rop_to_index[CIRRUS_ROP_NOTDST] = 4;
rop_to_index[CIRRUS_ROP_SRC] = 5;
rop_to_index[CIRRUS_ROP_1] = 6;
rop_to_index[CIRRUS_ROP_NOTSRC_AND_DST] = 7;
rop_to_index[CIRRUS_ROP_SRC_XOR_DST] = 8;
rop_to_index[CIRRUS_ROP_SRC_OR_DST] = 9;
rop_to_index[CIRRUS_ROP_NOTSRC_OR_NOTDST] = 10;
rop_to_index[CIRRUS_ROP_SRC_NOTXOR_DST] = 11;
rop_to_index[CIRRUS_ROP_SRC_OR_NOTDST] = 12;
rop_to_index[CIRRUS_ROP_NOTSRC] = 13;
rop_to_index[CIRRUS_ROP_NOTSRC_OR_DST] = 14;
rop_to_index[CIRRUS_ROP_NOTSRC_AND_NOTDST] = 15;
}

8
src/video/vid_cl_gd_blit.h
View File

@@ -1,8 +0,0 @@
#define le32_to_cpu(x) (x)
#define le16_to_cpu(x) (x)
void cirrus_bitblt_cputovideo_next(clgd_t *clgd, svga_t *svga);
void cirrus_bitblt_reset(clgd_t *clgd, svga_t *svga);
void cirrus_bitblt_start(clgd_t *clgd, svga_t *svga);
void cirrus_write_bitblt(clgd_t *clgd, svga_t *svga, uint8_t reg_value);
void init_rops();

207
src/video/vid_cl_gd_vga_rop.h
View File

@@ -1,207 +0,0 @@
/*
* QEMU Cirrus CLGD 54xx VGA Emulator.
*
* Copyright (c) 2004 Fabrice Bellard
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
inline void glue(rop_8_,ROP_NAME)(uint8_t *dst, uint8_t src)
{
*dst = ROP_FN(*dst, src);
}
inline void glue(rop_16_,ROP_NAME)(uint16_t *dst, uint16_t src)
{
*dst = ROP_FN(*dst, src);
}
inline void glue(rop_32_,ROP_NAME)(uint32_t *dst, uint32_t src)
{
*dst = ROP_FN(*dst, src);
}
#define ROP_OP(d, s) glue(rop_8_,ROP_NAME)(d, s)
#define ROP_OP_16(d, s) glue(rop_16_,ROP_NAME)(d, s)
#define ROP_OP_32(d, s) glue(rop_32_,ROP_NAME)(d, s)
#undef ROP_FN
void
glue(cirrus_bitblt_rop_fwd_, ROP_NAME)(clgd_t *clgd, svga_t *svga,
uint8_t *dst,const uint8_t *src,
int dstpitch,int srcpitch,
int bltwidth,int bltheight)
{
int x,y;
dstpitch -= bltwidth;
srcpitch -= bltwidth;
if (bltheight > 1 && (dstpitch < 0 || srcpitch < 0)) {
return;
}
for (y = 0; y < bltheight; y++) {
for (x = 0; x < bltwidth; x++) {
ROP_OP(dst, *src);
dst++;
src++;
}
dst += dstpitch;
src += srcpitch;
}
}
void
glue(cirrus_bitblt_rop_bkwd_, ROP_NAME)(clgd_t *clgd, svga_t *svga,
uint8_t *dst,const uint8_t *src,
int dstpitch,int srcpitch,
int bltwidth,int bltheight)
{
int x,y;
dstpitch += bltwidth;
srcpitch += bltwidth;
for (y = 0; y < bltheight; y++) {
for (x = 0; x < bltwidth; x++) {
ROP_OP(dst, *src);
dst--;
src--;
}
dst += dstpitch;
src += srcpitch;
}
}
void
glue(glue(cirrus_bitblt_rop_fwd_transp_, ROP_NAME),_8)(clgd_t *clgd, svga_t *svga,
uint8_t *dst,const uint8_t *src,
int dstpitch,int srcpitch,
int bltwidth,int bltheight)
{
int x,y;
uint8_t p;
dstpitch -= bltwidth;
srcpitch -= bltwidth;
for (y = 0; y < bltheight; y++) {
for (x = 0; x < bltwidth; x++) {
p = *dst;
ROP_OP(&p, *src);
if (p != svga->gdcreg[0x34]) *dst = p;
dst++;
src++;
}
dst += dstpitch;
src += srcpitch;
}
}
void
glue(glue(cirrus_bitblt_rop_bkwd_transp_, ROP_NAME),_8)(clgd_t *clgd, svga_t *svga,
uint8_t *dst,const uint8_t *src,
int dstpitch,int srcpitch,
int bltwidth,int bltheight)
{
int x,y;
uint8_t p;
dstpitch += bltwidth;
srcpitch += bltwidth;
for (y = 0; y < bltheight; y++) {
for (x = 0; x < bltwidth; x++) {
p = *dst;
ROP_OP(&p, *src);
if (p != svga->gdcreg[0x34]) *dst = p;
dst--;
src--;
}
dst += dstpitch;
src += srcpitch;
}
}
void
glue(glue(cirrus_bitblt_rop_fwd_transp_, ROP_NAME),_16)(clgd_t *clgd, svga_t *svga,
uint8_t *dst,const uint8_t *src,
int dstpitch,int srcpitch,
int bltwidth,int bltheight)
{
int x,y;
uint8_t p1, p2;
dstpitch -= bltwidth;
srcpitch -= bltwidth;
for (y = 0; y < bltheight; y++) {
for (x = 0; x < bltwidth; x+=2) {
p1 = *dst;
p2 = *(dst+1);
ROP_OP(&p1, *src);
ROP_OP(&p2, *(src + 1));
if ((p1 != svga->gdcreg[0x34]) || (p2 != svga->gdcreg[0x35])) {
*dst = p1;
*(dst+1) = p2;
}
dst+=2;
src+=2;
}
dst += dstpitch;
src += srcpitch;
}
}
void
glue(glue(cirrus_bitblt_rop_bkwd_transp_, ROP_NAME),_16)(clgd_t *clgd, svga_t *svga,
uint8_t *dst,const uint8_t *src,
int dstpitch,int srcpitch,
int bltwidth,int bltheight)
{
int x,y;
uint8_t p1, p2;
dstpitch += bltwidth;
srcpitch += bltwidth;
for (y = 0; y < bltheight; y++) {
for (x = 0; x < bltwidth; x+=2) {
p1 = *(dst-1);
p2 = *dst;
ROP_OP(&p1, *(src - 1));
ROP_OP(&p2, *src);
if ((p1 != svga->gdcreg[0x34]) || (p2 != svga->gdcreg[0x35])) {
*(dst-1) = p1;
*dst = p2;
}
dst-=2;
src-=2;
}
dst += dstpitch;
src += srcpitch;
}
}
#define DEPTH 8
#include "vid_cl_gd_vga_rop2.h"
#define DEPTH 16
#include "vid_cl_gd_vga_rop2.h"
#define DEPTH 24
#include "vid_cl_gd_vga_rop2.h"
#define DEPTH 32
#include "vid_cl_gd_vga_rop2.h"
#undef ROP_NAME
#undef ROP_OP
#undef ROP_OP_16
#undef ROP_OP_32

281
src/video/vid_cl_gd_vga_rop2.h
View File

@@ -1,281 +0,0 @@
/*
* QEMU Cirrus CLGD 54xx VGA Emulator.
*
* Copyright (c) 2004 Fabrice Bellard
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#if DEPTH == 8
#define PUTPIXEL() ROP_OP(&d[0], col)
#elif DEPTH == 16
#define PUTPIXEL() ROP_OP_16((uint16_t *)&d[0], col)
#elif DEPTH == 24
#define PUTPIXEL() ROP_OP(&d[0], col); \
ROP_OP(&d[1], (col >> 8)); \
ROP_OP(&d[2], (col >> 16))
#elif DEPTH == 32
#define PUTPIXEL() ROP_OP_32(((uint32_t *)&d[0]), col)
#else
#error unsupported DEPTH
#endif
void
glue(glue(glue(cirrus_patternfill_, ROP_NAME), _),DEPTH)
(clgd_t *clgd, svga_t *svga, uint8_t * dst,
const uint8_t * src,
int dstpitch, int srcpitch,
int bltwidth, int bltheight)
{
uint8_t *d;
int x, y, pattern_y, pattern_pitch, pattern_x;
unsigned int col;
const uint8_t *src1;
#if DEPTH == 24
int skipleft = svga->gdcreg[0x2f] & 0x1f;
#else
int skipleft = (svga->gdcreg[0x2f] & 0x07) * (DEPTH / 8);
#endif
#if DEPTH == 8
pattern_pitch = 8;
#elif DEPTH == 16
pattern_pitch = 16;
#else
pattern_pitch = 32;
#endif
pattern_y = clgd->blt.src_addr & 7;
for(y = 0; y < bltheight; y++) {
pattern_x = skipleft;
d = dst + skipleft;
src1 = src + pattern_y * pattern_pitch;
for (x = skipleft; x < bltwidth; x += (DEPTH / 8)) {
#if DEPTH == 8
col = src1[pattern_x];
pattern_x = (pattern_x + 1) & 7;
#elif DEPTH == 16
col = ((uint16_t *)(src1 + pattern_x))[0];
pattern_x = (pattern_x + 2) & 15;
#elif DEPTH == 24
{
const uint8_t *src2 = src1 + pattern_x * 3;
col = src2[0] | (src2[1] << 8) | (src2[2] << 16);
pattern_x = (pattern_x + 1) & 7;
}
#else
col = ((uint32_t *)(src1 + pattern_x))[0];
pattern_x = (pattern_x + 4) & 31;
#endif
PUTPIXEL();
d += (DEPTH / 8);
}
pattern_y = (pattern_y + 1) & 7;
dst += dstpitch;
}
}
/* NOTE: srcpitch is ignored */
void
glue(glue(glue(cirrus_colorexpand_transp_, ROP_NAME), _),DEPTH)
(clgd_t *clgd, svga_t *svga, uint8_t * dst,
const uint8_t * src,
int dstpitch, int srcpitch,
int bltwidth, int bltheight)
{
uint8_t *d;
int x, y;
unsigned bits, bits_xor;
unsigned int col;
unsigned bitmask;
unsigned index;
#if DEPTH == 24
int dstskipleft = svga->gdcreg[0x2f] & 0x1f;
int srcskipleft = dstskipleft / 3;
#else
int srcskipleft = svga->gdcreg[0x2f] & 0x07;
int dstskipleft = srcskipleft * (DEPTH / 8);
#endif
if (clgd->blt.modeext & CIRRUS_BLTMODEEXT_COLOREXPINV) {
bits_xor = 0xff;
col = clgd->blt.bg_col;
} else {
bits_xor = 0x00;
col = clgd->blt.fg_col;
}
for(y = 0; y < bltheight; y++) {
bitmask = 0x80 >> srcskipleft;
bits = *src++ ^ bits_xor;
d = dst + dstskipleft;
for (x = dstskipleft; x < bltwidth; x += (DEPTH / 8)) {
if ((bitmask & 0xff) == 0) {
bitmask = 0x80;
bits = *src++ ^ bits_xor;
}
index = (bits & bitmask);
if (index) {
PUTPIXEL();
}
d += (DEPTH / 8);
bitmask >>= 1;
}
dst += dstpitch;
}
}
void
glue(glue(glue(cirrus_colorexpand_, ROP_NAME), _),DEPTH)
(clgd_t *clgd, svga_t *svga, uint8_t * dst,
const uint8_t * src,
int dstpitch, int srcpitch,
int bltwidth, int bltheight)
{
uint32_t colors[2];
uint8_t *d;
int x, y;
unsigned bits;
unsigned int col;
unsigned bitmask;
int srcskipleft = svga->gdcreg[0x2f] & 0x07;
int dstskipleft = srcskipleft * (DEPTH / 8);
colors[0] = clgd->blt.bg_col;
colors[1] = clgd->blt.fg_col;
for(y = 0; y < bltheight; y++) {
bitmask = 0x80 >> srcskipleft;
bits = *src++;
d = dst + dstskipleft;
for (x = dstskipleft; x < bltwidth; x += (DEPTH / 8)) {
if ((bitmask & 0xff) == 0) {
bitmask = 0x80;
bits = *src++;
}
col = colors[!!(bits & bitmask)];
PUTPIXEL();
d += (DEPTH / 8);
bitmask >>= 1;
}
dst += dstpitch;
}
}
void
glue(glue(glue(cirrus_colorexpand_pattern_transp_, ROP_NAME), _),DEPTH)
(clgd_t *clgd, svga_t *svga, uint8_t * dst,
const uint8_t * src,
int dstpitch, int srcpitch,
int bltwidth, int bltheight)
{
uint8_t *d;
int x, y, bitpos, pattern_y;
unsigned int bits, bits_xor;
unsigned int col;
#if DEPTH == 24
int dstskipleft = svga->gdcreg[0x2f] & 0x1f;
int srcskipleft = dstskipleft / 3;
#else
int srcskipleft = svga->gdcreg[0x2f] & 0x07;
int dstskipleft = srcskipleft * (DEPTH / 8);
#endif
if (clgd->blt.modeext & CIRRUS_BLTMODEEXT_COLOREXPINV) {
bits_xor = 0xff;
col = clgd->blt.bg_col;
} else {
bits_xor = 0x00;
col = clgd->blt.fg_col;
}
pattern_y = clgd->blt.src_addr & 7;
for(y = 0; y < bltheight; y++) {
bits = src[pattern_y] ^ bits_xor;
bitpos = 7 - srcskipleft;
d = dst + dstskipleft;
for (x = dstskipleft; x < bltwidth; x += (DEPTH / 8)) {
if ((bits >> bitpos) & 1) {
PUTPIXEL();
}
d += (DEPTH / 8);
bitpos = (bitpos - 1) & 7;
}
pattern_y = (pattern_y + 1) & 7;
dst += dstpitch;
}
}
void
glue(glue(glue(cirrus_colorexpand_pattern_, ROP_NAME), _),DEPTH)
(clgd_t *clgd, svga_t *svga, uint8_t * dst,
const uint8_t * src,
int dstpitch, int srcpitch,
int bltwidth, int bltheight)
{
uint32_t colors[2];
uint8_t *d;
int x, y, bitpos, pattern_y;
unsigned int bits;
unsigned int col;
int srcskipleft = svga->gdcreg[0x2f] & 0x07;
int dstskipleft = srcskipleft * (DEPTH / 8);
colors[0] = clgd->blt.bg_col;
colors[1] = clgd->blt.fg_col;
pattern_y = clgd->blt.src_addr & 7;
for(y = 0; y < bltheight; y++) {
bits = src[pattern_y];
bitpos = 7 - srcskipleft;
d = dst + dstskipleft;
for (x = dstskipleft; x < bltwidth; x += (DEPTH / 8)) {
col = colors[(bits >> bitpos) & 1];
PUTPIXEL();
d += (DEPTH / 8);
bitpos = (bitpos - 1) & 7;
}
pattern_y = (pattern_y + 1) & 7;
dst += dstpitch;
}
}
void
glue(glue(glue(cirrus_fill_, ROP_NAME), _),DEPTH)
(clgd_t *clgd, svga_t *svga,
uint8_t *dst, int dst_pitch,
int width, int height)
{
uint8_t *d, *d1;
uint32_t col;
int x, y;
col = clgd->blt.fg_col;
d1 = dst;
for(y = 0; y < height; y++) {
d = d1;
for(x = 0; x < width; x += (DEPTH / 8)) {
PUTPIXEL();
d += (DEPTH / 8);
}
d1 += dst_pitch;
}
}
#undef DEPTH
#undef PUTPIXEL

121
src/video/vid_cl_ramdac.c
View File

@@ -1,121 +0,0 @@
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Emulation of the Cirrus Logic RAMDAC.
*
* Version: @(#)vid_cl_ramdac.c 1.0.2 2017/11/04
*
* Author: Miran Grca, <mgrca8@gmail.com>
*
* Copyright 2016,2017 Miran Grca.
*/
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <wchar.h>
#include "../86box.h"
#include "../mem.h"
#include "../rom.h"
#include "../device.h"
#include "video.h"
#include "vid_svga.h"
#include "vid_cl_ramdac.h"
#include "vid_cl_gd.h"
#include "vid_cl_gd_blit.h"
void cl_ramdac_out(uint16_t addr, uint8_t val, cl_ramdac_t *ramdac, void *clgd, svga_t *svga)
{
clgd_t *real_clgd = (clgd_t *) clgd;
//pclog("OUT RAMDAC %04X %02X\n",addr,val);
switch (addr)
{
case 0x3C6:
if (ramdac->state == 4)
{
ramdac->state = 0;
ramdac->ctrl = val;
svga_recalctimings(svga);
return;
}
ramdac->state = 0;
break;
case 0x3C7: case 0x3C8:
ramdac->state = 0;
break;
case 0x3C9:
if (svga->seqregs[0x12] & CIRRUS_CURSOR_HIDDENPEL)
{
ramdac->state = 0;
svga->fullchange = changeframecount;
switch (svga->dac_pos)
{
case 0:
real_clgd->hiddenpal[svga->dac_write & 0xf].r = val & 63;
svga->dac_pos++;
break;
case 1:
real_clgd->hiddenpal[svga->dac_write & 0xf].g = val & 63;
svga->dac_pos++;
break;
case 2:
real_clgd->hiddenpal[svga->dac_write & 0xf].b = val & 63;
svga->dac_pos = 0;
svga->dac_write = (svga->dac_write + 1) & 255;
break;
}
return;
}
ramdac->state = 0;
break;
}
svga_out(addr, val, svga);
}
uint8_t cl_ramdac_in(uint16_t addr, cl_ramdac_t *ramdac, void *clgd, svga_t *svga)
{
clgd_t *real_clgd = (clgd_t *) clgd;
//pclog("IN RAMDAC %04X\n",addr);
switch (addr)
{
case 0x3C6:
if (ramdac->state == 4)
{
ramdac->state = 0;
return ramdac->ctrl;
}
ramdac->state++;
break;
case 0x3C7: case 0x3C8:
ramdac->state = 0;
break;
case 0x3C9:
if (svga->seqregs[0x12] & CIRRUS_CURSOR_HIDDENPEL)
{
ramdac->state = 0;
switch (svga->dac_pos)
{
case 0:
svga->dac_pos++;
return real_clgd->hiddenpal[svga->dac_read & 0xf].r;
case 1:
svga->dac_pos++;
return real_clgd->hiddenpal[svga->dac_read & 0xf].g;
case 2:
svga->dac_pos=0;
svga->dac_read = (svga->dac_read + 1) & 255;
return real_clgd->hiddenpal[(svga->dac_read - 1) & 15].b;
}
}
ramdac->state = 0;
break;
}
return svga_in(addr, svga);
}

8
src/video/vid_cl_ramdac.h
View File

@@ -1,8 +0,0 @@
typedef struct cl_ramdac_t
{
int state;
uint8_t ctrl;
} cl_ramdac_t;
void cl_ramdac_out(uint16_t addr, uint8_t val, cl_ramdac_t *ramdac, void *clgd, svga_t *svga);
uint8_t cl_ramdac_in(uint16_t addr, cl_ramdac_t *ramdac, void *clgd, svga_t *svga);

19
src/video/vid_table.c
View File

@@ -8,7 +8,7 @@
*
* Define all known video cards.
*
* Version: @(#)vid_table.c 1.0.18 2018/02/12
* Version: @(#)vid_table.c 1.0.19 2018/02/18
*
* Authors: Miran Grca, <mgrca8@gmail.com>
* Fred N. van Kempen, <decwiz@yahoo.com>
@@ -35,7 +35,7 @@
#include "vid_ati28800.h"
#include "vid_ati_mach64.h"
#include "vid_cga.h"
#include "vid_cl5428.h"
#include "vid_cl54xx.h"
#include "vid_compaq_cga.h"
#include "vid_ega.h"
#include "vid_et4000.h"
@@ -69,8 +69,8 @@ enum {
};
typedef struct {
char name[64];
char internal_name[24];
const char *name;
const char *internal_name;
device_t *device;
int legacy_id;
video_timings_t timing;
@@ -136,10 +136,11 @@ video_cards[] = {
{"[PCI] Trident TGUI9440", "tgui9440_pci", &tgui9440_pci_device, GFX_TGUI9440_PCI, {VIDEO_BUS, 4, 8, 16, 4, 8, 16}},
{"[VLB] ATI Graphics Pro Turbo (Mach64 GX)", "mach64gx_vlb", &mach64gx_vlb_device, GFX_MACH64GX_VLB, {VIDEO_BUS, 2, 2, 1, 20, 20, 21}},
{"[VLB] Cardex Tseng ET4000/w32p", "et4000w32p_vlb", &et4000w32p_cardex_vlb_device, GFX_ET4000W32_CARDEX_VLB, {VIDEO_BUS, 4, 4, 4, 10, 10, 10}},
{"[VLB] Cirrus Logic CL-GD 5429", "cl_gd5429_vlb", &gd5429_device, GFX_CL_GD5429, {VIDEO_BUS, 4, 4, 8, 10, 10, 20}},
#if defined(DEV_BRANCH) && defined(USE_STEALTH32)
{"[VLB] Diamond Stealth 32 (Tseng ET4000/w32p)","stealth32_vlb", &et4000w32p_vlb_device, GFX_ET4000W32_VLB, {VIDEO_BUS, 4, 4, 4, 10, 10, 10}},
#endif
{"[VLB] Diamond SpeedStar PRO (CL-GD5428)", "cl_gd5428_vlb", &gd5428_device, GFX_CL_GD5428, {VIDEO_BUS, 4, 8, 16, 4, 8, 16}},
{"[VLB] Diamond SpeedStar PRO (CL-GD5428)", "cl_gd5428_vlb", &gd5428_device, GFX_CL_GD5428, {VIDEO_BUS, 4, 4, 8, 10, 10, 20}},
{"[VLB] Diamond Stealth 3D 2000 (S3 ViRGE)", "stealth3d_2000_vlb", &s3_virge_vlb_device, GFX_VIRGE_VLB, {VIDEO_BUS, 2, 2, 3, 28, 28, 45}},
{"[VLB] Diamond Stealth 3D 3000 (S3 ViRGE/VX)", "stealth3d_3000_vlb", &s3_virge_988_vlb_device, GFX_VIRGEVX_VLB, {VIDEO_BUS, 2, 2, 4, 26, 26, 42}},
{"[VLB] Diamond Stealth 64 DRAM (S3 Trio64)", "stealth64d_vlb", &s3_diamond_stealth64_vlb_device, GFX_STEALTH64_VLB, {VIDEO_BUS, 2, 2, 4, 26, 26, 42}},
@@ -193,7 +194,7 @@ video_card_available(int card)
char *
video_card_getname(int card)
{
return(video_cards[card].name);
return((char *) video_cards[card].name);
}
@@ -226,7 +227,7 @@ video_card_getid(char *s)
int c = 0;
while (video_cards[c].legacy_id != -1) {
if (!strcmp(video_cards[c].name, s))
if (!strcmp((char *) video_cards[c].name, s))
return(c);
c++;
}
@@ -260,7 +261,7 @@ video_new_to_old(int card)
char *
video_get_internal_name(int card)
{
return(video_cards[card].internal_name);
return((char *) video_cards[card].internal_name);
}
@@ -270,7 +271,7 @@ video_get_video_from_internal_name(char *s)
int c = 0;
while (video_cards[c].legacy_id != -1) {
if (!strcmp(video_cards[c].internal_name, s))
if (!strcmp((char *) video_cards[c].internal_name, s))
return(video_cards[c].legacy_id);
c++;
}

5
src/video/video.h
View File

@@ -8,7 +8,7 @@
*
* Definitions for the video controller module.
*
* Version: @(#)video.h 1.0.16 2018/02/12
* Version: @(#)video.h 1.0.17 2018/02/18
*
* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
@@ -68,7 +68,8 @@ enum {
GFX_MACH64GX_VLB, /* ATI Graphics Pro Turbo (Mach64) VLB */
GFX_MACH64GX_PCI, /* ATI Graphics Pro Turbo (Mach64) PCI */
GFX_MACH64VT2, /* ATI Mach64 VT2 */
GFX_CL_GD5428, /* Diamond SpeedStar PRO (Cirrus Logic CL-GD5428) */
GFX_CL_GD5428, /* Diamond SpeedStar PRO (Cirrus Logic CL-GD 5428) */
GFX_CL_GD5429, /* Cirrus Logic CL-GD 5428 */
#if defined(DEV_BRANCH) && defined(USE_RIVA)
GFX_RIVATNT, /* nVidia Riva TNT */
GFX_RIVATNT2, /* nVidia Riva TNT2 */