From e25fadc138fa3e3d0965bbcf0503d8f59d77ffeb Mon Sep 17 00:00:00 2001
From: TC1995 <mariogplayer90@gmail.com>
Date: Mon, 15 Jan 2024 23:04:36 +0100
Subject: [PATCH] S3 true color update.

Reset bit 4 of the Misc Index register (from port 0xbee8) on mode changes.
---
 src/video/vid_s3.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/video/vid_s3.c b/src/video/vid_s3.c
index 6de3ffce7..54f9047e8 100644
--- a/src/video/vid_s3.c
+++ b/src/video/vid_s3.c
@@ -945,10 +945,6 @@ s3_accel_out_fifo(s3_t *s3, uint16_t port, uint8_t val)
             s3->accel.cmd       = (s3->accel.cmd & 0xff) | (val << 8);
             s3->accel.ssv_state = 0;
             s3->accel_start(-1, 0, 0xffffffff, 0, s3);
-            if (s3->bpp == 3) {
-                if (!(s3->accel.multifunc[0xe] & 0x200) && !(svga->crtc[0x32] & 0x40))
-                    s3->accel.multifunc[0xe] &= ~0x10;
-            }
             break;
 
         case 0x994a:
@@ -2780,6 +2776,10 @@ s3_out(uint16_t addr, uint8_t val, void *priv)
 
                 case 0x50:
                     s3->bpp = (svga->crtc[0x50] >> 4) & 3;
+                    if (s3->bpp == 3) {
+                        if (!(s3->accel.multifunc[0xe] & 0x200)) /*On True Color mode change, reset bit 4 of Misc Index register*/
+                            s3->accel.multifunc[0xe] &= ~0x10;
+                    }
                     break;
 
                 case 0x5c: