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Merge branch 'master' of https://github.com/86Box/86Box

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This commit is contained in:
OBattler
2025-08-02 14:03:20 +02:00
parent 6cfe513d17 ed3231a67c
commit e2b31c2142
225 changed files with 19564 additions and 5314 deletions
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2
src/disk/CMakeLists.txt
View File

@@ -37,7 +37,7 @@ add_library(hdd OBJECT
hdc_ide_w83769f.c
)
add_library(zip OBJECT zip.c)
add_library(rdisk OBJECT rdisk.c)
add_library(mo OBJECT mo.c)

25
src/disk/hdc.c
View File

@@ -79,6 +79,8 @@ static const struct {
{ &xtide_at_2ch_device },
{ &xtide_at_ps2_device },
{ &xtide_at_ps2_2ch_device },
{ &ide_ter_device },
{ &ide_qua_device },
{ &st506_at_wd1003_device },
{ &esdi_at_wd1007vse1_device },
/* MCA */
@@ -89,6 +91,9 @@ static const struct {
{ &ide_vlb_device },
{ &ide_vlb_2ch_device },
/* PCI */
{ &ide_cmd646_ter_qua_device },
{ &ide_cmd648_ter_qua_device },
{ &ide_cmd649_ter_qua_device },
{ &ide_pci_device },
{ &ide_pci_2ch_device },
{ NULL }
@@ -109,18 +114,14 @@ hdc_init(void)
void
hdc_reset(void)
{
hdc_log("HDC: reset(current=%d, internal=%d)\n",
hdc_current[0], (machines[machine].flags & MACHINE_HDC) ? 1 : 0);
for (int i = 0; i < HDC_MAX; i++) {
hdc_log("HDC %i: reset(current=%d, internal=%d)\n", i,
hdc_current[i], hdc_current[i] == HDC_INTERNAL);
/* If we have a valid controller, add its device. */
if (hdc_current[0] > HDC_INTERNAL)
device_add(controllers[hdc_current[0]].device);
/* Now, add the tertiary and/or quaternary IDE controllers. */
if (ide_ter_enabled)
device_add(&ide_ter_device);
if (ide_qua_enabled)
device_add(&ide_qua_device);
/* If we have a valid controller, add its device. */
if (hdc_current[i] > HDC_INTERNAL)
device_add_inst(controllers[hdc_current[i]].device, i + 1);
}
}
const char *
@@ -130,7 +131,7 @@ hdc_get_internal_name(int hdc)
}
int
hdc_get_from_internal_name(char *s)
hdc_get_from_internal_name(const char *s)
{
int c = 0;

27
src/disk/hdc_ide.c
View File

@@ -46,7 +46,7 @@
#include <86box/hdc.h>
#include <86box/hdc_ide.h>
#include <86box/hdd.h>
#include <86box/zip.h>
#include <86box/rdisk.h>
#include <86box/version.h>
/* Bits of 'atastat' */
@@ -234,9 +234,7 @@ static uint8_t ide_qua_pnp_rom[] = {
0x79, 0x00
};
ide_t *ide_drives[IDE_NUM];
int ide_ter_enabled = 0;
int ide_qua_enabled = 0;
ide_t *ide_drives[IDE_NUM] = { 0 };
static void ide_atapi_callback(ide_t *ide);
static void ide_callback(void *priv);
@@ -2828,20 +2826,23 @@ ide_board_close(int board)
ide_log("ide_board_close(%i)\n", board);
if ((ide_boards[board] == NULL) || !ide_boards[board]->inited)
if (ide_boards[board] == NULL)
return;
ide_log("IDE: Closing board %i...\n", board);
timer_stop(&ide_boards[board]->timer);
if (ide_boards[board]->inited) {
timer_stop(&ide_boards[board]->timer);
ide_clear_bus_master(board);
ide_clear_bus_master(board);
}
/* Close hard disk image files (if previously open) */
for (uint8_t d = 0; d < 2; d++) {
c = (board << 1) + d;
ide_boards[board]->ide[d] = NULL;
if (ide_boards[board]->inited)
ide_boards[board]->ide[d] = NULL;
dev = ide_drives[c];
@@ -3265,6 +3266,16 @@ ide_close(UNUSED(void *priv))
}
}
void
ide_hard_reset(void)
{
for (int i = 0; i < IDE_BUS_MAX; i++)
ide_boards[i] = NULL;
for (int i = 0; i < IDE_NUM; i++)
ide_drives[i] = NULL;
}
static uint8_t
mcide_mca_read(const int port, void *priv)
{

14
src/disk/hdc_ide_cmd640.c
View File

@@ -34,7 +34,7 @@
#include <86box/hdc.h>
#include <86box/hdc_ide.h>
#include <86box/hdc_ide_sff8038i.h>
#include <86box/zip.h>
#include <86box/rdisk.h>
#include <86box/mo.h>
typedef struct cmd640_t {
@@ -417,10 +417,10 @@ cmd640_reset(void *priv)
(cdrom[i].ide_channel <= max_channel) && cdrom[i].priv)
scsi_cdrom_reset((scsi_common_t *) cdrom[i].priv);
}
for (i = 0; i < ZIP_NUM; i++) {
if ((zip_drives[i].bus_type == ZIP_BUS_ATAPI) && (zip_drives[i].ide_channel >= min_channel) &&
(zip_drives[i].ide_channel <= max_channel) && zip_drives[i].priv)
zip_reset((scsi_common_t *) zip_drives[i].priv);
for (i = 0; i < RDISK_NUM; i++) {
if ((rdisk_drives[i].bus_type == RDISK_BUS_ATAPI) && (rdisk_drives[i].ide_channel >= min_channel) &&
(rdisk_drives[i].ide_channel <= max_channel) && rdisk_drives[i].priv)
rdisk_reset((scsi_common_t *) rdisk_drives[i].priv);
}
for (i = 0; i < MO_NUM; i++) {
if ((mo_drives[i].bus_type == MO_BUS_ATAPI) && (mo_drives[i].ide_channel >= min_channel) &&
@@ -667,7 +667,7 @@ const device_t ide_cmd640_pci_legacy_only_device = {
};
const device_t ide_cmd640_pci_single_channel_device = {
.name = "CMD PCI-0640B PCI",
.name = "CMD PCI-0640B PCI (Single Channel)",
.internal_name = "ide_cmd640_pci_single_channel",
.flags = DEVICE_PCI,
.local = 0x2000a,
@@ -681,7 +681,7 @@ const device_t ide_cmd640_pci_single_channel_device = {
};
const device_t ide_cmd640_pci_single_channel_sec_device = {
.name = "CMD PCI-0640B PCI",
.name = "CMD PCI-0640B PCI (Single Channel, Secondary)",
.internal_name = "ide_cmd640_pci_single_channel_sec",
.flags = DEVICE_PCI,
.local = 0x4000a,

559
src/disk/hdc_ide_cmd646.c
View File

@@ -34,8 +34,26 @@
#include <86box/hdc.h>
#include <86box/hdc_ide.h>
#include <86box/hdc_ide_sff8038i.h>
#include <86box/zip.h>
#include <86box/rdisk.h>
#include <86box/rom.h>
#include <86box/hdd.h>
#include <86box/scsi_disk.h>
#include <86box/mo.h>
#include "cpu.h"
#include "x86.h"
#define CMD_TYPE_646 0x0000000
#define CMD_TYPE_648 0x0100000
#define CMD_TYPE_649 0x0200000
#define CMD648_JP7 0x0400000 /* Reload subsystem ID on reset. */
#define CMD648_RAID 0x0800000
#define CMD64X_ONBOARD 0x1000000
#define CMD648_BIOS_FILE "roms/hdd/ide/648_1910.bin"
#define CMD649_REV_1914_BIOS_FILE "roms/hdd/ide/649_1914.bin"
#define CMD649_REV_2301_BIOS_FILE "roms/hdd/ide/649_2301.bin"
typedef struct cmd646_t {
uint8_t vlb_idx;
@@ -46,11 +64,17 @@ typedef struct cmd646_t {
uint8_t regs[256];
uint32_t local;
uint32_t rom_addr;
uint32_t rom_addr_size;
uint32_t rom_addr_mask;
int irq_pin;
int has_bios;
int irq_mode[2];
rom_t bios_rom;
sff8038i_t *bm[2];
} cmd646_t;
@@ -80,7 +104,8 @@ cmd646_set_irq_0(uint8_t status, void *priv)
if (!(dev->regs[0x50] & 0x04) || (status & 0x04))
dev->regs[0x50] = (dev->regs[0x50] & ~0x04) | status;
sff_bus_master_set_irq(status, dev->bm[0]);
if (!(dev->local & CMD_TYPE_648) || !(dev->regs[0x71] & 0x10))
sff_bus_master_set_irq(status, dev->bm[0]);
}
static void
@@ -91,7 +116,8 @@ cmd646_set_irq_1(uint8_t status, void *priv)
if (!(dev->regs[0x57] & 0x10) || (status & 0x04))
dev->regs[0x57] = (dev->regs[0x57] & ~0x10) | (status << 2);
sff_bus_master_set_irq(status, dev->bm[1]);
if (!(dev->local & CMD_TYPE_648) || !(dev->regs[0x71] & 0x20))
sff_bus_master_set_irq(status, dev->bm[1]);
}
static int
@@ -116,13 +142,24 @@ cmd646_ide_handlers(cmd646_t *dev)
uint16_t main;
uint16_t side;
int irq_mode[2] = { IRQ_MODE_LEGACY, IRQ_MODE_LEGACY };
int first = 0;
int reg09 = dev->regs[0x09];
int reg50 = dev->regs[0x50];
if ((dev->local & CMD_TYPE_648) && (dev->regs[0x0a] == 0x04) && (dev->regs[0x0b] == 0x01)) {
reg09 = 0xff;
reg50 |= 0x40;
}
if (dev->local & 0x80000)
first += 2;
sff_set_slot(dev->bm[0], dev->pci_slot);
sff_set_slot(dev->bm[1], dev->pci_slot);
ide_pri_disable();
ide_handlers(first, 0);
if ((dev->regs[0x09] & 0x01) && (dev->regs[0x50] & 0x40)) {
if ((reg09 & 0x01) && (reg50 & 0x40)) {
main = (dev->regs[0x11] << 8) | (dev->regs[0x10] & 0xf8);
side = ((dev->regs[0x15] << 8) | (dev->regs[0x14] & 0xfc)) + 2;
} else {
@@ -130,23 +167,28 @@ cmd646_ide_handlers(cmd646_t *dev)
side = 0x3f6;
}
ide_set_base(0, main);
ide_set_side(0, side);
ide_set_base(first, main);
ide_set_side(first, side);
if (dev->regs[0x09] & 0x01)
if (reg09 & 0x01)
irq_mode[0] = IRQ_MODE_PCI_IRQ_PIN;
sff_set_irq_mode(dev->bm[0], irq_mode[0]);
cmd646_log("IDE %i: %04X, %04X, %i\n", first, main, side, irq_mode[0]);
if (dev->regs[0x04] & 0x01)
ide_pri_enable();
int pri_enabled = (dev->regs[0x04] & 0x01);
if (dev->local & CMD_TYPE_648)
pri_enabled = pri_enabled && (dev->regs[0x51] & 0x04);
if (pri_enabled)
ide_handlers(first, 1);
if (dev->single_channel)
return;
ide_sec_disable();
ide_handlers(first + 1, 0);
if ((dev->regs[0x09] & 0x04) && (dev->regs[0x50] & 0x40)) {
if ((reg09 & 0x04) && (reg50 & 0x40)) {
main = (dev->regs[0x19] << 8) | (dev->regs[0x18] & 0xf8);
side = ((dev->regs[0x1d] << 8) | (dev->regs[0x1c] & 0xfc)) + 2;
} else {
@@ -154,16 +196,17 @@ cmd646_ide_handlers(cmd646_t *dev)
side = 0x376;
}
ide_set_base(1, main);
ide_set_side(1, side);
ide_set_base(first + 1, main);
ide_set_side(first + 1, side);
if (dev->regs[0x09] & 0x04)
irq_mode[1] = 1;
if (reg09 & 0x04)
irq_mode[1] = IRQ_MODE_PCI_IRQ_PIN;
sff_set_irq_mode(dev->bm[1], irq_mode[1]);
cmd646_log("IDE %i: %04X, %04X, %i\n", first + 1, main, side, irq_mode[1]);
if ((dev->regs[0x04] & 0x01) && (dev->regs[0x51] & 0x08))
ide_sec_enable();
ide_handlers(first + 1, 1);
}
static void
@@ -175,74 +218,176 @@ cmd646_ide_bm_handlers(cmd646_t *dev)
sff_bus_master_handler(dev->bm[1], (dev->regs[0x04] & 1), base + 8);
}
uint8_t
cmd646_bm_write(uint16_t port, uint8_t val, void *priv)
{
cmd646_t *dev = (cmd646_t *) priv;
uint8_t ret = val;
switch (port & 0x000f) {
case 0x0001:
dev->regs[(port & 0x000f) | 0x70] = val & 0xf0;
if (val & 0x04)
dev->regs[0x50] &= ~0x04;
if (val & 0x08)
dev->regs[0x57] &= ~0x10;
ret &= 0x03;
break;
case 0x0003:
dev->regs[0x73] = val;
break;
case 0x0009:
dev->regs[(port & 0x000f) | 0x70] = (dev->regs[(port & 0x000f) | 0x70] & 0x0f) | (val & 0xf0);
ret &= 0x03;
break;
case 0x000b:
dev->regs[0x7b] = val;
break;
}
return ret;
}
uint8_t
cmd646_bm_read(uint16_t port, uint8_t val, void *priv)
{
cmd646_t *dev = (cmd646_t *) priv;
uint8_t ret = val;
switch (port & 0x000f) {
case 0x0001:
ret = (dev->regs[(port & 0x000f) | 0x70] & 0xf3) | (dev->regs[0x50] & 0x04) | ((dev->regs[0x57] & 0x10) >> 1);
break;
case 0x0002: case 0x000a:
ret |= 0x08;
break;
case 0x0003:
ret = dev->regs[0x73];
break;
case 0x0009:
ret = dev->regs[(port & 0x000f) | 0x70];
break;
case 0x000b:
ret = dev->regs[0x7b];
break;
}
return ret;
}
static void
cmd646_bios_handler(cmd646_t *dev)
{
if ((dev->local & CMD_TYPE_648) && dev->has_bios) {
uint32_t *addr = (uint32_t *) &(dev->regs[0x30]);
*addr &= (~dev->rom_addr_mask) | 0x00000001;
dev->rom_addr = *addr & 0xfffffff0;
cmd646_log("ROM address now: %08X\n", dev->rom_addr);
if ((dev->regs[0x04] & 0x02) && (*addr & 0x00000001))
mem_mapping_set_addr(&dev->bios_rom.mapping, dev->rom_addr, dev->rom_addr_size);
else
mem_mapping_disable(&dev->bios_rom.mapping);
}
}
static void
cmd646_pci_write(int func, int addr, uint8_t val, void *priv)
{
cmd646_t *dev = (cmd646_t *) priv;
cmd646_t *dev = (cmd646_t *) priv;
int reg50 = dev->regs[0x50];
if ((dev->local & CMD_TYPE_648) && (dev->regs[0x0a] == 0x04) && (dev->regs[0x0b] == 0x01))
reg50 |= 0x40;
cmd646_log("[%04X:%08X] (%08X) cmd646_pci_write(%i, %02X, %02X)\n", CS, cpu_state.pc, ESI, func, addr, val);
if (func == 0x00)
switch (addr) {
case 0x04:
dev->regs[addr] = (val & 0x45);
if (dev->has_bios)
dev->regs[addr] = (val & 0x47);
else
dev->regs[addr] = (val & 0x45);
cmd646_ide_handlers(dev);
cmd646_ide_bm_handlers(dev);
cmd646_bios_handler(dev);
break;
case 0x05:
if (dev->local & CMD_TYPE_648)
dev->regs[addr] = (dev->regs[addr] & 0x7e) | (val & 0x01);
break;
case 0x07:
dev->regs[addr] &= ~(val & 0xb1);
if (dev->local & CMD_TYPE_648)
dev->regs[addr] = ((dev->regs[addr] & ~(val & 0xb9)) & 0xbf) | (val & 0x40);
else
dev->regs[addr] &= ~(val & 0xb1);
break;
case 0x09:
if ((dev->regs[addr] & 0x0a) == 0x0a) {
dev->regs[addr] = (dev->regs[addr] & 0x0a) | (val & 0x05);
dev->irq_mode[0] = !!(val & 0x01);
dev->irq_mode[1] = !!(val & 0x04);
if (!(dev->local & CMD_TYPE_648) ||
((dev->regs[0x0a] == 0x01) && (dev->regs[0x0b] == 0x01))) {
if ((dev->regs[addr] & 0x0a) == 0x0a) {
dev->regs[addr] = (dev->regs[addr] & 0x8a) | (val & 0x05);
dev->irq_mode[0] = !!(val & 0x01);
dev->irq_mode[1] = !!(val & 0x04);
cmd646_ide_handlers(dev);
}
}
break;
case 0x0a: case 0x0b:
if ((dev->local & CMD_TYPE_648) && (dev->regs[0x4f] & 0x04)) {
dev->regs[addr] = val;
cmd646_ide_handlers(dev);
}
break;
case 0x10:
if (dev->regs[0x50] & 0x40) {
if (reg50 & 0x40) {
dev->regs[0x10] = (val & 0xf8) | 1;
cmd646_ide_handlers(dev);
}
break;
case 0x11:
if (dev->regs[0x50] & 0x40) {
if (reg50 & 0x40) {
dev->regs[0x11] = val;
cmd646_ide_handlers(dev);
}
break;
case 0x14:
if (dev->regs[0x50] & 0x40) {
if (reg50 & 0x40) {
dev->regs[0x14] = (val & 0xfc) | 1;
cmd646_ide_handlers(dev);
}
break;
case 0x15:
if (dev->regs[0x50] & 0x40) {
if (reg50 & 0x40) {
dev->regs[0x15] = val;
cmd646_ide_handlers(dev);
}
break;
case 0x18:
if (dev->regs[0x50] & 0x40) {
if (reg50 & 0x40) {
dev->regs[0x18] = (val & 0xf8) | 1;
cmd646_ide_handlers(dev);
}
break;
case 0x19:
if (dev->regs[0x50] & 0x40) {
if (reg50 & 0x40) {
dev->regs[0x19] = val;
cmd646_ide_handlers(dev);
}
break;
case 0x1c:
if (dev->regs[0x50] & 0x40) {
if (reg50 & 0x40) {
dev->regs[0x1c] = (val & 0xfc) | 1;
cmd646_ide_handlers(dev);
}
break;
case 0x1d:
if (dev->regs[0x50] & 0x40) {
if (reg50 & 0x40) {
dev->regs[0x1d] = val;
cmd646_ide_handlers(dev);
}
@@ -255,18 +400,42 @@ cmd646_pci_write(int func, int addr, uint8_t val, void *priv)
dev->regs[0x21] = val;
cmd646_ide_bm_handlers(dev);
break;
case 0x2c ... 0x2f:
case 0x8c ... 0x8f:
if (dev->local & CMD_TYPE_648)
dev->regs[(addr & 0x0f) | 0x20] = val;
break;
case 0x30 ... 0x33:
if ((dev->local & CMD_TYPE_648) && dev->has_bios) {
dev->regs[addr] = val;
cmd646_bios_handler(dev);
}
break;
case 0x3c:
dev->regs[0x3c] = val;
break;
case 0x4f:
if (dev->local & CMD_TYPE_648)
dev->regs[addr] = (dev->regs[addr] & 0xfa) | (val & 0x05);
break;
case 0x51:
dev->regs[addr] = val & 0xc8;
if (dev->local & CMD_TYPE_648)
dev->regs[addr] = val & 0xcc;
else
dev->regs[addr] = val & 0xc8;
cmd646_ide_handlers(dev);
break;
case 0x52:
case 0x54:
case 0x56:
case 0x58:
case 0x59:
case 0x5b:
dev->regs[addr] = val;
break;
case 0x59:
if ((dev->local & CMD_TYPE_649) || !(dev->local & CMD_TYPE_648))
dev->regs[addr] = val;
break;
case 0x53:
case 0x55:
dev->regs[addr] = val & 0xc0;
@@ -274,10 +443,32 @@ cmd646_pci_write(int func, int addr, uint8_t val, void *priv)
case 0x57:
dev->regs[addr] = (dev->regs[addr] & 0x10) | (val & 0xcc);
break;
case 0x70 ... 0x77:
case 0x64:
if (dev->local & CMD_TYPE_648)
dev->regs[addr] = (dev->regs[addr] & 0xfc) | (val & 0x03);
break;
case 0x65:
if (dev->local & CMD_TYPE_648)
dev->regs[addr] = (dev->regs[addr] & 0x7f) | (val & 0x80);
break;
case 0x71:
if (dev->local & CMD_TYPE_648)
sff_bus_master_write(addr & 0x0f, val, dev->bm[0]);
else
sff_bus_master_write(addr & 0x0f, val & 0x03, dev->bm[0]);
break;
case 0x70:
case 0x72 ... 0x77:
sff_bus_master_write(addr & 0x0f, val, dev->bm[0]);
break;
case 0x78 ... 0x7f:
case 0x79:
if (dev->local & CMD_TYPE_648)
sff_bus_master_write(addr & 0x0f, val, dev->bm[1]);
else
sff_bus_master_write(addr & 0x0f, val & 0x03, dev->bm[1]);
break;
case 0x78:
case 0x7a ... 0x7f:
sff_bus_master_write(addr & 0x0f, val, dev->bm[1]);
break;
@@ -295,7 +486,9 @@ cmd646_pci_read(int func, int addr, void *priv)
if (func == 0x00) {
ret = dev->regs[addr];
if (addr == 0x50)
if ((addr == 0x09) && (dev->local & CMD_TYPE_648) && (dev->regs[0x0a] == 0x04))
ret = 0x00;
else if (addr == 0x50)
dev->regs[0x50] &= ~0x04;
else if (addr == 0x57)
dev->regs[0x57] &= ~0x10;
@@ -303,6 +496,8 @@ cmd646_pci_read(int func, int addr, void *priv)
ret = sff_bus_master_read(addr & 0x0f, dev->bm[0]);
else if ((addr >= 0x78) && (addr <= 0x7f))
ret = sff_bus_master_read(addr & 0x0f, dev->bm[1]);
else if ((dev->local & CMD_TYPE_648) && (addr >= 0x8c) && (addr <= 0x8f))
ret = dev->regs[(addr & 0x0f) | 0x20];
}
cmd646_log("[%04X:%08X] (%08X) cmd646_pci_read(%i, %02X, %02X)\n", CS, cpu_state.pc, ESI, func, addr, ret);
@@ -310,22 +505,44 @@ cmd646_pci_read(int func, int addr, void *priv)
return ret;
}
static int
check_ch(cmd646_t *dev, int channel)
{
int ret = 0;
int min = 0;
int max = dev->single_channel ? 1 : 3;
if (dev->local & 0x80000) {
min += 4;
max += 4;
}
if ((channel >= min) && (channel <= max))
ret = 1;
return ret;
}
static void
cmd646_reset(void *priv)
{
cmd646_t *dev = (cmd646_t *) priv;
int i = 0;
for (i = 0; i < HDD_NUM; i++) {
if ((hdd[i].bus_type == HDD_BUS_ATAPI) && check_ch(dev, hdd[i].ide_channel) && hdd[i].priv)
scsi_disk_reset((scsi_common_t *) hdd[i].priv);
}
for (i = 0; i < CDROM_NUM; i++) {
if ((cdrom[i].bus_type == CDROM_BUS_ATAPI) && (cdrom[i].ide_channel < 4) && cdrom[i].priv)
if ((cdrom[i].bus_type == CDROM_BUS_ATAPI) && check_ch(dev, cdrom[i].ide_channel) && cdrom[i].priv)
scsi_cdrom_reset((scsi_common_t *) cdrom[i].priv);
}
for (i = 0; i < ZIP_NUM; i++) {
if ((zip_drives[i].bus_type == ZIP_BUS_ATAPI) && (zip_drives[i].ide_channel < 4) && zip_drives[i].priv)
zip_reset((scsi_common_t *) zip_drives[i].priv);
for (i = 0; i < RDISK_NUM; i++) {
if ((rdisk_drives[i].bus_type == RDISK_BUS_ATAPI) && check_ch(dev, rdisk_drives[i].ide_channel) && rdisk_drives[i].priv)
rdisk_reset((scsi_common_t *) rdisk_drives[i].priv);
}
for (i = 0; i < MO_NUM; i++) {
if ((mo_drives[i].bus_type == MO_BUS_ATAPI) && (mo_drives[i].ide_channel < 4) && mo_drives[i].priv)
if ((mo_drives[i].bus_type == MO_BUS_ATAPI) && check_ch(dev, mo_drives[i].ide_channel) && mo_drives[i].priv)
mo_reset((scsi_common_t *) mo_drives[i].priv);
}
@@ -336,16 +553,41 @@ cmd646_reset(void *priv)
dev->regs[0x00] = 0x95; /* CMD */
dev->regs[0x01] = 0x10;
dev->regs[0x02] = 0x46; /* PCI-0646 */
if (dev->local & CMD_TYPE_649)
dev->regs[0x02] = 0x49; /* PCI-0649 */
else if (dev->local & CMD_TYPE_648)
dev->regs[0x02] = 0x48; /* PCI-0648 */
else
dev->regs[0x02] = 0x46; /* PCI-0646 */
dev->regs[0x03] = 0x06;
dev->regs[0x04] = 0x00;
dev->regs[0x06] = 0x80;
dev->regs[0x07] = 0x02; /* DEVSEL timing: 01 medium */
dev->regs[0x09] = dev->local; /* Programming interface */
dev->regs[0x0a] = 0x01; /* IDE controller */
if ((dev->local & CMD_TYPE_648) && (dev->local & CMD648_RAID)) {
dev->regs[0x06] = 0x90;
dev->regs[0x08] = 0x02;
dev->regs[0x09] = 0x00; /* Programming interface */
dev->regs[0x0a] = 0x04; /* RAID controller */
dev->regs[0x50] = 0x40; /* Enable Base address register R/W;
If 0, they return 0 and are read-only 8 */
/* Blank base addresses */
dev->regs[0x10] = 0x01;
dev->regs[0x14] = 0x01;
dev->regs[0x18] = 0x01;
dev->regs[0x1c] = 0x01;
} else {
dev->regs[0x06] = 0x80;
dev->regs[0x09] = dev->local; /* Programming interface */
dev->regs[0x0a] = 0x01; /* IDE controller */
}
dev->regs[0x0b] = 0x01; /* Mass storage controller */
if ((dev->local & 0xffff) == 0x8a) {
if ((dev->local & CMD_TYPE_648) && (dev->local & CMD648_JP7))
for (int i = 0; i < 4; i++)
dev->regs[0x2c + i] = dev->regs[i];
if ((dev->regs[0x09] & 0x8a) == 0x8a) {
dev->regs[0x50] = 0x40; /* Enable Base address register R/W;
If 0, they return 0 and are read-only 8 */
@@ -371,13 +613,47 @@ cmd646_reset(void *priv)
dev->regs[0x51] = 0x08;
dev->regs[0x57] = 0x0c;
dev->regs[0x59] = 0x40;
dev->irq_mode[0] = dev->irq_mode[1] = 0;
if (dev->local & CMD_TYPE_648) {
dev->regs[0x34] = 0x60;
dev->regs[0x4f] = (dev->local & CMD648_JP7) ? 0x02 : 0x00;
dev->regs[0x51] |= 0x04;
if (dev->local & CMD_TYPE_649) {
dev->regs[0x57] |= 0x80;
dev->regs[0x59] = 0x40;
} else
dev->regs[0x57] |= 0xc0;
dev->regs[0x60] = 0x01;
dev->regs[0x62] = 0x21;
dev->regs[0x63] = 0x06;
dev->regs[0x65] = 0x60;
dev->regs[0x67] = 0xf0;
/* 80-pin stuff. */
dev->regs[0x72] = 0x08;
dev->regs[0x7a] = 0x08;
dev->regs[0x79] = 0x83;
} else
dev->regs[0x59] = 0x40;
dev->irq_pin = PCI_INTA;
if ((dev->local & CMD_TYPE_648) && (dev->local & CMD648_RAID))
dev->irq_mode[0] = dev->irq_mode[1] = IRQ_MODE_PCI_IRQ_PIN;
else {
dev->irq_mode[0] = (dev->regs[0x09] & 0x01) ? IRQ_MODE_PCI_IRQ_PIN : IRQ_MODE_LEGACY;
dev->irq_mode[1] = (dev->regs[0x09] & 0x04) ? IRQ_MODE_PCI_IRQ_PIN : IRQ_MODE_LEGACY;
}
dev->irq_pin = PCI_INTA;
cmd646_ide_handlers(dev);
cmd646_ide_bm_handlers(dev);
cmd646_bios_handler(dev);
}
static void
@@ -391,42 +667,147 @@ cmd646_close(void *priv)
static void *
cmd646_init(const device_t *info)
{
cmd646_t *dev = (cmd646_t *) calloc(1, sizeof(cmd646_t));
cmd646_t *dev = (cmd646_t *) calloc(1, sizeof(cmd646_t));
int first = 0;
dev->local = info->local;
device_add(&ide_pci_2ch_device);
if (info->local & 0x80000)
pci_add_card(PCI_ADD_NORMAL, cmd646_pci_read, cmd646_pci_write, dev, &dev->pci_slot);
else
if (info->local & 0x80000) {
first = 2;
device_add(&ide_pci_ter_qua_2ch_device);
} else
device_add(&ide_pci_2ch_device);
if (info->local & CMD64X_ONBOARD)
pci_add_card(PCI_ADD_IDE, cmd646_pci_read, cmd646_pci_write, dev, &dev->pci_slot);
else
pci_add_card(PCI_ADD_NORMAL, cmd646_pci_read, cmd646_pci_write, dev, &dev->pci_slot);
dev->single_channel = !!(info->local & 0x20000);
dev->bm[0] = device_add_inst(&sff8038i_device, 1);
dev->bm[0] = device_add_inst(&sff8038i_device, first + 1);
if (!dev->single_channel)
dev->bm[1] = device_add_inst(&sff8038i_device, 2);
dev->bm[1] = device_add_inst(&sff8038i_device, first + 2);
ide_set_bus_master(0, cmd646_bus_master_dma_0, cmd646_set_irq_0, dev);
ide_set_bus_master(first, cmd646_bus_master_dma_0, cmd646_set_irq_0, dev);
if (!dev->single_channel)
ide_set_bus_master(1, cmd646_bus_master_dma_1, cmd646_set_irq_1, dev);
ide_set_bus_master(first + 1, cmd646_bus_master_dma_1, cmd646_set_irq_1, dev);
sff_set_irq_mode(dev->bm[0], IRQ_MODE_LEGACY);
if (!dev->single_channel)
sff_set_irq_mode(dev->bm[1], IRQ_MODE_LEGACY);
sff_set_slot(dev->bm[0], dev->pci_slot);
sff_set_slot(dev->bm[1], dev->pci_slot);
if (dev->local & CMD_TYPE_648) {
sff_set_ven_handlers(dev->bm[0], cmd646_bm_write, cmd646_bm_read, dev);
sff_set_ven_handlers(dev->bm[1], cmd646_bm_write, cmd646_bm_read, dev);
dev->has_bios = device_get_config_int("bios");
if (dev->has_bios) {
char *fn = NULL;
if (dev->local & CMD_TYPE_649) {
const char *bios_rev = (char *) device_get_config_bios("bios_rev");
fn = (char *) device_get_bios_file(info, bios_rev, 0);
dev->rom_addr_size = device_get_bios_file_size(info, bios_rev);
} else {
fn = CMD648_BIOS_FILE;
dev->rom_addr_size = 0x00004000;
}
dev->rom_addr_mask = dev->rom_addr_size - 1;
rom_init(&dev->bios_rom, fn,
0x000d0000, dev->rom_addr_size, dev->rom_addr_mask, 0, MEM_MAPPING_EXTERNAL);
mem_mapping_disable(&dev->bios_rom.mapping);
}
}
cmd646_reset(dev);
if (dev->local & CMD_TYPE_648)
for (int i = 0; i < 4; i++)
dev->regs[0x2c + i] = dev->regs[i];
return dev;
}
static const device_config_t cmd648_config[] = {
{
.name = "bios",
.description = "Enable BIOS",
.type = CONFIG_BINARY,
.default_string = NULL,
.default_int = 0,
.file_filter = NULL,
.spinner = { 0 },
.selection = { { 0 } },
.bios = { { 0 } }
},
{ .name = "", .description = "", .type = CONFIG_END }
};
// clang-format on
static const device_config_t cmd649_config[] = {
{
.name = "bios",
.description = "Enable BIOS",
.type = CONFIG_BINARY,
.default_string = NULL,
.default_int = 0,
.file_filter = NULL,
.spinner = { 0 },
.selection = { { 0 } },
.bios = { { 0 } }
},
{
.name = "bios_rev",
.description = "BIOS Revision",
.type = CONFIG_BIOS,
.default_string = "rev_2301",
.default_int = 0,
.file_filter = NULL,
.spinner = { 0 },
.bios = {
{
.name = "Revision 1.9.14",
.internal_name = "rev_1914",
.bios_type = BIOS_NORMAL,
.files_no = 1,
.local = 0,
.size = 16384,
.files = { CMD649_REV_2301_BIOS_FILE, "" }
},
{
.name = "Revision 2.3.01",
.internal_name = "rev_2301",
.bios_type = BIOS_NORMAL,
.files_no = 1,
.local = 0,
.size = 65536,
.files = { CMD649_REV_2301_BIOS_FILE, "" }
},
{ .files_no = 0 }
},
},
{ .name = "", .description = "", .type = CONFIG_END }
};
// clang-format on
const device_t ide_cmd646_device = {
.name = "CMD PCI-0646",
.internal_name = "ide_cmd646",
.flags = DEVICE_PCI,
.local = 0x8a,
.local = 0x000008a | CMD64X_ONBOARD,
.init = cmd646_init,
.close = cmd646_close,
.reset = cmd646_reset,
@@ -440,7 +821,7 @@ const device_t ide_cmd646_legacy_only_device = {
.name = "CMD PCI-0646 (Legacy Mode Only)",
.internal_name = "ide_cmd646_legacy_only",
.flags = DEVICE_PCI,
.local = 0x80,
.local = 0x0000080 | CMD64X_ONBOARD,
.init = cmd646_init,
.close = cmd646_close,
.reset = cmd646_reset,
@@ -451,10 +832,10 @@ const device_t ide_cmd646_legacy_only_device = {
};
const device_t ide_cmd646_single_channel_device = {
.name = "CMD PCI-0646",
.name = "CMD PCI-0646 (Single Channel)",
.internal_name = "ide_cmd646_single_channel",
.flags = DEVICE_PCI,
.local = 0x2008a,
.local = 0x002008a | CMD64X_ONBOARD,
.init = cmd646_init,
.close = cmd646_close,
.reset = cmd646_reset,
@@ -463,3 +844,59 @@ const device_t ide_cmd646_single_channel_device = {
.force_redraw = NULL,
.config = NULL
};
const device_t ide_cmd646_ter_qua_device = {
.name = "CMD PCI-0646 (Tertiary and Quaternary)",
.internal_name = "ide_cmd646_ter_qua",
.flags = DEVICE_PCI,
.local = 0x008008f,
.init = cmd646_init,
.close = cmd646_close,
.reset = cmd646_reset,
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t ide_cmd648_ter_qua_device = {
.name = "CMD PCI-0648 (Tertiary and Quaternary)",
.internal_name = "ide_cmd648_ter_qua",
.flags = DEVICE_PCI,
.local = 0x0d8008f,
.init = cmd646_init,
.close = cmd646_close,
.reset = cmd646_reset,
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = cmd648_config
};
const device_t ide_cmd648_ter_qua_onboard_device = {
.name = "CMD PCI-0648 (Tertiary and Quaternary) On-Board",
.internal_name = "ide_cmd648_ter_qua_onboard",
.flags = DEVICE_PCI,
.local = 0x0d8008f | CMD64X_ONBOARD,
.init = cmd646_init,
.close = cmd646_close,
.reset = cmd646_reset,
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t ide_cmd649_ter_qua_device = {
.name = "CMD PCI-0649 (Tertiary and Quaternary)",
.internal_name = "ide_cmd649_ter_qua",
.flags = DEVICE_PCI,
.local = 0x0f8008f,
.init = cmd646_init,
.close = cmd646_close,
.reset = cmd646_reset,
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = cmd649_config
};

12
src/disk/hdc_ide_rz1000.c
View File

@@ -34,7 +34,7 @@
#include <86box/hdc.h>
#include <86box/hdc_ide.h>
#include <86box/hdc_ide_sff8038i.h>
#include <86box/zip.h>
#include <86box/rdisk.h>
#include <86box/mo.h>
typedef struct rz1000_t {
@@ -182,10 +182,10 @@ rz1000_reset(void *priv)
(cdrom[i].ide_channel <= max_channel) && cdrom[i].priv)
scsi_cdrom_reset((scsi_common_t *) cdrom[i].priv);
}
for (i = 0; i < ZIP_NUM; i++) {
if ((zip_drives[i].bus_type == ZIP_BUS_ATAPI) && (zip_drives[i].ide_channel >= min_channel) &&
(zip_drives[i].ide_channel <= max_channel) && zip_drives[i].priv)
zip_reset((scsi_common_t *) zip_drives[i].priv);
for (i = 0; i < RDISK_NUM; i++) {
if ((rdisk_drives[i].bus_type == RDISK_BUS_ATAPI) && (rdisk_drives[i].ide_channel >= min_channel) &&
(rdisk_drives[i].ide_channel <= max_channel) && rdisk_drives[i].priv)
rdisk_reset((scsi_common_t *) rdisk_drives[i].priv);
}
for (i = 0; i < MO_NUM; i++) {
if ((mo_drives[i].bus_type == MO_BUS_ATAPI) && (mo_drives[i].ide_channel >= min_channel) &&
@@ -275,7 +275,7 @@ const device_t ide_rz1000_pci_device = {
};
const device_t ide_rz1000_pci_single_channel_device = {
.name = "PC Technology RZ-1000 PCI",
.name = "PC Technology RZ-1000 PCI (Single Channel)",
.internal_name = "ide_rz1000_pci_single_channel",
.flags = DEVICE_PCI,
.local = 0x20000,

26
src/disk/hdc_ide_sff8038i.c
View File

@@ -42,7 +42,7 @@
#include <86box/hdc.h>
#include <86box/hdc_ide.h>
#include <86box/hdc_ide_sff8038i.h>
#include <86box/zip.h>
#include <86box/rdisk.h>
#include <86box/mo.h>
#include <86box/plat_unused.h>
@@ -118,6 +118,9 @@ sff_bus_master_write(uint16_t port, uint8_t val, void *priv)
sff_log("SFF-8038i Bus master BYTE write: %04X %02X\n", port, val);
if (dev->ven_write != NULL)
val = dev->ven_write(port, val, dev->priv);
switch (port & 7) {
case 0:
sff_log("sff Cmd : val = %02X, old = %02X\n", val, dev->command);
@@ -255,6 +258,9 @@ sff_bus_master_read(uint16_t port, void *priv)
break;
}
if (dev->ven_read != NULL)
ret= dev->ven_read(port, ret, dev->priv);
sff_log("SFF-8038i Bus master BYTE read : %04X %02X\n", port, ret);
return ret;
@@ -489,10 +495,10 @@ sff_reset(void *priv)
cdrom[i].priv)
scsi_cdrom_reset((scsi_common_t *) cdrom[i].priv);
}
for (uint8_t i = 0; i < ZIP_NUM; i++) {
if ((zip_drives[i].bus_type == ZIP_BUS_ATAPI) && (zip_drives[i].ide_channel < 4) &&
zip_drives[i].priv)
zip_reset((scsi_common_t *) zip_drives[i].priv);
for (uint8_t i = 0; i < RDISK_NUM; i++) {
if ((rdisk_drives[i].bus_type == RDISK_BUS_ATAPI) && (rdisk_drives[i].ide_channel < 4) &&
rdisk_drives[i].priv)
rdisk_reset((scsi_common_t *) rdisk_drives[i].priv);
}
for (uint8_t i = 0; i < MO_NUM; i++) {
if ((mo_drives[i].bus_type == MO_BUS_ATAPI) && (mo_drives[i].ide_channel < 4) &&
@@ -569,6 +575,16 @@ sff_set_mirq(sff8038i_t *dev, uint8_t mirq)
dev->mirq = mirq;
}
void
sff_set_ven_handlers(sff8038i_t *dev, uint8_t (*ven_write)(uint16_t port, uint8_t val, void *priv),
uint8_t (*ven_read)(uint16_t port, uint8_t val, void *priv), void *priv)
{
dev->ven_write = ven_write;
dev->ven_read = ven_read;
dev->priv = priv;
}
static void
sff_close(void *priv)
{

10
src/disk/hdc_ide_w83769f.c
View File

@@ -34,7 +34,7 @@
#include <86box/hdc.h>
#include <86box/hdc_ide.h>
#include <86box/hdc_ide_sff8038i.h>
#include <86box/zip.h>
#include <86box/rdisk.h>
#include <86box/mo.h>
typedef struct w83769f_t {
@@ -297,10 +297,10 @@ w83769f_reset(void *priv)
(cdrom[i].ide_channel <= max_channel) && cdrom[i].priv)
scsi_cdrom_reset((scsi_common_t *) cdrom[i].priv);
}
for (i = 0; i < ZIP_NUM; i++) {
if ((zip_drives[i].bus_type == ZIP_BUS_ATAPI) && (zip_drives[i].ide_channel >= min_channel) &&
(zip_drives[i].ide_channel <= max_channel) && zip_drives[i].priv)
zip_reset((scsi_common_t *) zip_drives[i].priv);
for (i = 0; i < RDISK_NUM; i++) {
if ((rdisk_drives[i].bus_type == RDISK_BUS_ATAPI) && (rdisk_drives[i].ide_channel >= min_channel) &&
(rdisk_drives[i].ide_channel <= max_channel) && rdisk_drives[i].priv)
rdisk_reset((scsi_common_t *) rdisk_drives[i].priv);
}
for (i = 0; i < MO_NUM; i++) {
if ((mo_drives[i].bus_type == MO_BUS_ATAPI) && (mo_drives[i].ide_channel >= min_channel) &&

12
src/disk/hdc_st506_xt.c
View File

@@ -1915,7 +1915,7 @@ victor_v86p_available(void)
static const device_config_t dtc_config[] = {
{
.name = "bios_addr",
.description = "BIOS Address",
.description = "BIOS address",
.type = CONFIG_HEX20,
.default_string = NULL,
.default_int = 0xc8000,
@@ -1969,7 +1969,7 @@ static const device_config_t st11_config[] = {
},
{
.name = "bios_addr",
.description = "BIOS Address",
.description = "BIOS address",
.type = CONFIG_HEX20,
.default_string = NULL,
.default_int = 0xc8000,
@@ -2006,7 +2006,7 @@ static const device_config_t st11_config[] = {
static const device_config_t wd_config[] = {
{
.name = "bios_addr",
.description = "BIOS Address",
.description = "BIOS address",
.type = CONFIG_HEX20,
.default_string = NULL,
.default_int = 0xc8000,
@@ -2089,7 +2089,7 @@ static const device_config_t wd_nobios_config[] = {
static const device_config_t wd_rll_config[] = {
{
.name = "bios_addr",
.description = "BIOS Address",
.description = "BIOS address",
.type = CONFIG_HEX20,
.default_string = NULL,
.default_int = 0xc8000,
@@ -2153,7 +2153,7 @@ static const device_config_t wd_rll_config[] = {
static const device_config_t wd1004a_config[] = {
{
.name = "bios_addr",
.description = "BIOS Address",
.description = "BIOS address",
.type = CONFIG_HEX20,
.default_string = NULL,
.default_int = 0xc8000,
@@ -2202,7 +2202,7 @@ static const device_config_t wd1004a_config[] = {
static const device_config_t wd1004_rll_config[] = {
{
.name = "bios_addr",
.description = "BIOS Address",
.description = "BIOS address",
.type = CONFIG_HEX20,
.default_string = NULL,
.default_int = 0xc8000,

2
src/disk/hdc_xta.c
View File

@@ -1281,7 +1281,7 @@ static const device_config_t wdxt150_config[] = {
},
{
.name = "bios_addr",
.description = "BIOS Address",
.description = "BIOS address",
.type = CONFIG_HEX20,
.default_string = NULL,
.default_int = 0xc8000,

2
src/disk/hdc_xtide.c
View File

@@ -341,7 +341,7 @@ static const device_config_t xtide_config[] = {
},
{
.name = "bios_addr",
.description = "BIOS Address",
.description = "BIOS address",
.type = CONFIG_HEX20,
.default_string = NULL,
.default_int = 0xd0000,

21
src/disk/hdd.c
View File

@@ -78,6 +78,12 @@ no_cdrom:
if (!strcmp(str, "scsi"))
return HDD_BUS_SCSI;
if (!strcmp(str, "mitsumi"))
return CDROM_BUS_MITSUMI;
if (!strcmp(str, "mke"))
return CDROM_BUS_MKE;
return 0;
}
@@ -89,6 +95,17 @@ hdd_bus_to_string(int bus, UNUSED(int cdrom))
switch (bus) {
default:
if (cdrom) {
switch (bus) {
case CDROM_BUS_MITSUMI:
s = "mitsumi";
break;
case CDROM_BUS_MKE:
s = "mke";
break;
}
break;
}
case HDD_BUS_DISABLED:
break;
@@ -143,8 +160,12 @@ hdd_seek_get_time(hard_disk_t *hdd, uint32_t dst_addr, uint8_t operation, uint8_
const hdd_zone_t *zone = NULL;
if (hdd->num_zones <= 0) {
#ifdef DO_FATAL
fatal("hdd_seek_get_time(): hdd->num_zones < 0)\n");
return 0.0;
#else
return 1000.0;
#endif
}
for (uint32_t i = 0; i < hdd->num_zones; i++) {
zone = &hdd->zones[i];

1084
src/disk/zip.c → src/disk/rdisk.c
View File

File diff suppressed because it is too large Load Diff