Implement missing IBM, AMD and Cyrix MSRs
This commit is contained in:
Alexander Babikov
139
src/cpu/cpu.c
139
src/cpu/cpu.c
@@ -2590,7 +2590,8 @@ cpu_RDMSR(void)
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/* Cache Region Control Register */
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case 0x1001:
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EAX = msr.ibm_crcr & 0xffffffffff;
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EAX = msr.ibm_crcr & 0xffffffff;
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EDX = (msr.ibm_crcr >> 32) & 0x0000ffff;
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break;
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/* Processor Operation Register */
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@@ -2598,6 +2599,12 @@ cpu_RDMSR(void)
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if ((cpu_s->cpu_type > CPU_IBM386SLC) && cpu_s->multi)
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EAX = msr.ibm_por2 & 0x3f000000;
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break;
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/* Processor Control Register */
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case 0x1004:
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if (cpu_s->cpu_type > CPU_IBM486SLC)
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EAX = msr.ibm_pcr & 0x00d6001a;
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break;
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}
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break;
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@@ -2780,12 +2787,20 @@ cpu_RDMSR(void)
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case CPU_K6_3:
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case CPU_K6_2P:
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case CPU_K6_3P:
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EAX = EDX = 0;
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EAX = 0;
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/* EDX is left unchanged when reading this MSR! */
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if (ECX != 0x82)
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EDX = 0;
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switch (ECX) {
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/* Machine Check Address Register */
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case 0x00000000:
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EAX = msr.mcar & 0xffffffff;
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EDX = msr.mcar >> 32;
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break;
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/* Machine Check Type Register */
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case 0x00000001:
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EAX = msr.mctr & 0xffffffff;
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EDX = msr.mctr >> 32;
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break;
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/* Test Register 12 */
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case 0x0000000e:
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@@ -2796,11 +2811,32 @@ cpu_RDMSR(void)
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EAX = tsc & 0xffffffff;
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EDX = tsc >> 32;
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break;
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/* Array Access Register */
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case 0x00000082:
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if (cpu_s->cpu_type > CPU_5K86)
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goto amd_k_invalid_rdmsr;
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EAX = msr.amd_aar & 0xffffffff;
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/* EDX is left unchanged! */
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break;
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/* Hardware Configuration Register */
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case 0x00000083:
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EAX = msr.amd_hwcr & 0xffffffff;
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EDX = msr.amd_hwcr >> 32;
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break;
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/* Write Allocate Top-of-Memory and Control Register */
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case 0x00000085:
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if (cpu_s->cpu_type != CPU_5K86)
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goto amd_k_invalid_rdmsr;
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EAX = msr.amd_watmcr & 0xffffffff;
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EDX = msr.amd_watmcr >> 32;
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break;
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/* Write Allocate Programmable Memory Range Register */
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case 0x00000086:
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if (cpu_s->cpu_type != CPU_5K86)
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goto amd_k_invalid_rdmsr;
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EAX = msr.amd_wapmrr & 0xffffffff;
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EDX = msr.amd_wapmrr >> 32;
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break;
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/* Extended Feature Enable Register */
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case 0xc0000080:
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EAX = msr.amd_efer & 0xffffffff;
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@@ -3033,16 +3069,37 @@ pentium_invalid_rdmsr:
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case CPU_CxGX1:
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case CPU_Cx6x86MX:
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switch (ECX) {
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/* Machine Check Exception Address */
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case 0x00:
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/* Machine Check Exception Type */
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case 0x01:
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/* Test Data */
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case 0x03:
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EAX = msr.tr3;
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break;
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/* Test Address */
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case 0x04:
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EAX = msr.tr4;
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break;
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/* Test Command/Status */
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case 0x05:
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EAX = msr.tr5;
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break;
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/* Time Stamp Counter */
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case 0x10:
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EAX = tsc & 0xffffffff;
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EDX = tsc >> 32;
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break;
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/* Performance Monitor - Control and Event Select */
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case 0x11:
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EAX = msr.cesr;
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break;
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/* Performance Monitor - Event Counter 0 */
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case 0x12:
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EAX = msr.pmc[0] & 0xffffffff;
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EDX = msr.pmc[0] >> 32;
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break;
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/* Performance Monitor - Event Counter 1 */
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case 0x13:
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EAX = msr.pmc[1] & 0xffffffff;
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EDX = msr.pmc[1] >> 32;
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break;
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}
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cpu_log("RDMSR: ECX = %08X, val = %08X%08X\n", ECX, EDX, EAX);
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break;
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@@ -3331,8 +3388,8 @@ cpu_WRMSR(void)
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switch (cpu_s->cpu_type) {
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case CPU_IBM386SLC:
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case CPU_IBM486BL:
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case CPU_IBM486SLC:
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case CPU_IBM486BL:
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switch (ECX) {
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/* Processor Operation Register */
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case 0x1000:
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@@ -3341,13 +3398,18 @@ cpu_WRMSR(void)
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break;
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/* Cache Region Control Register */
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case 0x1001:
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msr.ibm_crcr = EAX & 0xffffffffff;
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msr.ibm_crcr = EAX | ((uint64_t) (EDX & 0x0000ffff) << 32);
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break;
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/* Processor Operation Register */
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case 0x1002:
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if ((cpu_s->cpu_type > CPU_IBM386SLC) && cpu_s->multi)
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msr.ibm_por2 = EAX & 0x3f000000;
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break;
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/* Processor Control Register */
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case 0x1004:
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if (cpu_s->cpu_type > CPU_IBM486SLC)
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msr.ibm_pcr = EAX & 0x00d6001a;
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break;
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}
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break;
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@@ -3521,22 +3583,45 @@ cpu_WRMSR(void)
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case CPU_K6_3P:
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switch (ECX) {
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/* Machine Check Address Register */
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case 0x00:
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case 0x00000000:
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if (cpu_s->cpu_type > CPU_5K86)
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msr.mcar = EAX | ((uint64_t) EDX << 32);
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break;
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/* Machine Check Type Register */
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case 0x01:
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case 0x00000001:
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if (cpu_s->cpu_type > CPU_5K86)
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msr.mctr = EAX | ((uint64_t) EDX << 32);
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break;
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/* Test Register 12 */
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case 0x0e:
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msr.tr12 = EAX & 0x228;
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case 0x0000000e:
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msr.tr12 = EAX & 0x8;
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break;
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/* Time Stamp Counter */
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case 0x10:
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case 0x00000010:
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tsc = EAX | ((uint64_t) EDX << 32);
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break;
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/* Array Access Register */
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case 0x00000082:
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if (cpu_s->cpu_type > CPU_5K86)
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goto amd_k_invalid_wrmsr;
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msr.amd_aar = EAX | ((uint64_t) EDX << 32);
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break;
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/* Hardware Configuration Register */
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case 0x83:
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case 0x00000083:
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msr.amd_hwcr = EAX | ((uint64_t) EDX << 32);
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break;
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/* Write Allocate Top-of-Memory and Control Register */
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case 0x00000085:
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if (cpu_s->cpu_type != CPU_5K86)
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goto amd_k_invalid_wrmsr;
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msr.amd_watmcr = EAX | ((uint64_t) EDX << 32);
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break;
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/* Write Allocate Programmable Memory Range Register */
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case 0x00000086:
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if (cpu_s->cpu_type != CPU_5K86)
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goto amd_k_invalid_wrmsr;
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msr.amd_wapmrr = EAX | ((uint64_t) EDX << 32);
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break;
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/* Extended Feature Enable Register */
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case 0xc0000080:
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temp = EAX | ((uint64_t) EDX << 32);
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@@ -3757,15 +3842,31 @@ pentium_invalid_wrmsr:
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case CPU_Cx6x86MX:
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cpu_log("WRMSR: ECX = %08X, val = %08X%08X\n", ECX, EDX, EAX);
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switch (ECX) {
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/* Machine Check Exception Address */
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case 0x00:
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/* Machine Check Exception Type */
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case 0x01:
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break;
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/* Test Data */
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case 0x03:
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msr.tr3 = EAX;
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/* Test Address */
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case 0x04:
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msr.tr4 = EAX;
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/* Test Command/Status */
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case 0x05:
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msr.tr5 = EAX & 0x008f0f3b;
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/* Time Stamp Counter */
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case 0x10:
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tsc = EAX | ((uint64_t) EDX << 32);
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break;
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/* Performance Monitor - Control and Event Select */
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case 0x11:
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msr.cesr = EAX & 0x7ff07ff;
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break;
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/* Performance Monitor - Event Counter 0 */
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case 0x12:
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msr.pmc[0] = EAX | ((uint64_t) EDX << 32);
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break;
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/* Performance Monitor - Event Counter 1 */
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case 0x13:
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msr.pmc[1] = EAX | ((uint64_t) EDX << 32);
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break;
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}
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break;
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#endif
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@@ -230,6 +230,7 @@ typedef struct {
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uint64_t ibm_por; /* 0x00001000 - 386SLC and later */
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uint64_t ibm_crcr; /* 0x00001001 - 386SLC and later */
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uint64_t ibm_por2; /* 0x00001002 - 486SLC and later */
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uint64_t ibm_pcr; /* 0x00001004 - 486BL3 */
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/* IDT WinChip C6/2/VIA Cyrix III MSRs */
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uint32_t fcr; /* 0x00000107 (IDT), 0x00001107 (VIA) */
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@@ -239,11 +240,14 @@ typedef struct {
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uint32_t mcr_ctrl; /* 0x00000120 (IDT) */
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/* AMD K5/K6 MSRs */
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uint64_t amd_hwcr; /* 0x00000083 - all K5 and K6 */
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uint64_t amd_aar; /* 0x00000082 - all K5 */
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uint64_t amd_hwcr; /* 0x00000083 - all K5 and all K6 */
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uint64_t amd_watmcr; /* 0x00000085 - K5 Model 1 and later */
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uint64_t amd_wapmrr; /* 0x00000086 - K5 Model 1 and later */
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uint64_t amd_efer; /* 0xc0000080 - all K5 and K6 */
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uint64_t amd_efer; /* 0xc0000080 - all K5 and all K6 */
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uint64_t amd_star; /* 0xc0000081 - K6-2 and later */
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uint64_t amd_whcr; /* 0xc0000082 - all K5 and K6 */
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uint64_t amd_whcr; /* 0xc0000082 - all K5 and all K6 */
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uint64_t amd_uwccr; /* 0xc0000085 - K6-2C and later */
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uint64_t amd_epmr; /* 0xc0000086 - K6-III+/2+ only */
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uint64_t amd_psor; /* 0xc0000087 - K6-2C and later */
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