From e864aa2edcdb25162b360312e89d1b6b6a7c0e75 Mon Sep 17 00:00:00 2001 From: OBattler Date: Mon, 26 Jul 2021 05:02:40 +0200 Subject: [PATCH] PIIX IDE non-bus master BAR's are now only writable on the SMSC Victory/66. --- src/chipset/intel_piix.c | 48 ++++++++++++++++++++++++++-------------- 1 file changed, 32 insertions(+), 16 deletions(-) diff --git a/src/chipset/intel_piix.c b/src/chipset/intel_piix.c index 2c3e0fa89..57f5091c8 100644 --- a/src/chipset/intel_piix.c +++ b/src/chipset/intel_piix.c @@ -613,36 +613,52 @@ piix_write(int func, int addr, uint8_t val, void *priv) fregs[0x0d] = val & 0xf0; break; case 0x10: - fregs[0x10] = (val & 0xf8) | 1; - piix_ide_handlers(dev, 0x01); + if (dev->type == 5) { + fregs[0x10] = (val & 0xf8) | 1; + piix_ide_handlers(dev, 0x01); + } break; case 0x11: - fregs[0x11] = val; - piix_ide_handlers(dev, 0x01); + if (dev->type == 5) { + fregs[0x11] = val; + piix_ide_handlers(dev, 0x01); + } break; case 0x14: - fregs[0x14] = (val & 0xfc) | 1; - piix_ide_handlers(dev, 0x01); + if (dev->type == 5) { + fregs[0x14] = (val & 0xfc) | 1; + piix_ide_handlers(dev, 0x01); + } break; case 0x15: - fregs[0x15] = val; - piix_ide_handlers(dev, 0x01); + if (dev->type == 5) { + fregs[0x15] = val; + piix_ide_handlers(dev, 0x01); + } break; case 0x18: - fregs[0x18] = (val & 0xf8) | 1; - piix_ide_handlers(dev, 0x02); + if (dev->type == 5) { + fregs[0x18] = (val & 0xf8) | 1; + piix_ide_handlers(dev, 0x02); + } break; case 0x19: - fregs[0x19] = val; - piix_ide_handlers(dev, 0x02); + if (dev->type == 5) { + fregs[0x19] = val; + piix_ide_handlers(dev, 0x02); + } break; case 0x1c: - fregs[0x1c] = (val & 0xfc) | 1; - piix_ide_handlers(dev, 0x02); + if (dev->type == 5) { + fregs[0x1c] = (val & 0xfc) | 1; + piix_ide_handlers(dev, 0x02); + } break; case 0x1d: - fregs[0x1d] = val; - piix_ide_handlers(dev, 0x02); + if (dev->type == 5) { + fregs[0x1d] = val; + piix_ide_handlers(dev, 0x02); + } break; case 0x20: fregs[0x20] = (val & 0xf0) | 1;