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Fixed MSR's on AMD CPU's - the VIA machine now works without issues with the high-speed AMD CPU's.

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This commit is contained in:
OBattler
2020-01-16 20:49:58 +01:00
parent 8f17d4ed8d
commit ebf0d1ef3a
7 changed files with 530 additions and 44 deletions
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2
src/cpu/808x.c
View File

@@ -964,6 +964,8 @@ reset_common(int hard)
prefetching = 1; prefetching = 1;
takeint = 0; takeint = 0;
cpu_ven_reset();
} }

118
src/cpu/cpu.c
View File

@@ -191,8 +191,9 @@ uint64_t ecx570_msr = 0;
#if defined(DEV_BRANCH) && defined(USE_AMD_K) #if defined(DEV_BRANCH) && defined(USE_AMD_K)
uint64_t ecx83_msr = 0; /* AMD K5 and K6 MSR's. */ uint64_t ecx83_msr = 0; /* AMD K5 and K6 MSR's. */
uint64_t star = 0; /* These are K6-only. */ uint64_t star = 0; /* AMD K6-2+. */
uint64_t sfmask = 0;
uint64_t amd_efer = 0, amd_whcr = 0; /* AMD K6-2+ registers. */
#endif #endif
int timing_rr; int timing_rr;
@@ -1193,9 +1194,9 @@ cpu_set(void)
case CPU_K5: case CPU_K5:
case CPU_5K86: case CPU_5K86:
#ifdef USE_DYNAREC #ifdef USE_DYNAREC
x86_setopcodes(ops_386, ops_k6_0f, dynarec_ops_386, dynarec_ops_k6_0f); x86_setopcodes(ops_386, ops_pentiummmx_0f, dynarec_ops_386, dynarec_ops_pentiummmx_0f);
#else #else
x86_setopcodes(ops_386, ops_k6_0f); x86_setopcodes(ops_386, ops_pentiummmx_0f);
#endif #endif
timing_rr = 1; /*register dest - register src*/ timing_rr = 1; /*register dest - register src*/
timing_rm = 2; /*register dest - memory src*/ timing_rm = 2; /*register dest - memory src*/
@@ -1214,9 +1215,9 @@ cpu_set(void)
case CPU_K6: case CPU_K6:
#ifdef USE_DYNAREC #ifdef USE_DYNAREC
x86_setopcodes(ops_386, ops_k6_0f, dynarec_ops_386, dynarec_ops_k6_0f); x86_setopcodes(ops_386, ops_pentiummmx_0f, dynarec_ops_386, dynarec_ops_pentiummmx_0f);
#else #else
x86_setopcodes(ops_386, ops_k6_0f); x86_setopcodes(ops_386, ops_pentiummmx_0f);
#endif #endif
timing_rr = 1; /*register dest - register src*/ timing_rr = 1; /*register dest - register src*/
timing_rm = 2; /*register dest - memory src*/ timing_rm = 2; /*register dest - memory src*/
@@ -1801,6 +1802,24 @@ cpu_CPUID(void)
} }
} }
void cpu_ven_reset(void)
{
#if defined(DEV_BRANCH) && defined(USE_AMD_K)
switch (machines[machine].cpu[cpu_manufacturer].cpus[cpu_effective].cpu_type)
{
case CPU_K5:
case CPU_5K86:
case CPU_K6:
amd_efer = amd_whcr = 0ULL;
break;
case CPU_K6_2:
amd_efer = amd_whcr = 0ULL;
star = 0ULL;
break;
}
#endif
}
void cpu_RDMSR() void cpu_RDMSR()
{ {
switch (machines[machine].cpu[cpu_manufacturer].cpus[cpu_effective].cpu_type) switch (machines[machine].cpu[cpu_manufacturer].cpus[cpu_effective].cpu_type)
@@ -1842,24 +1861,57 @@ void cpu_RDMSR()
EAX = EDX = 0; EAX = EDX = 0;
switch (ECX) switch (ECX)
{ {
case 0x0e: case 0x0000000e:
EAX = msr.tr12; EAX = msr.tr12;
break; break;
case 0x10: case 0x00000010:
EAX = tsc & 0xffffffff; EAX = tsc & 0xffffffff;
EDX = tsc >> 32; EDX = tsc >> 32;
break; break;
case 0x83: case 0x00000083:
EAX = ecx83_msr & 0xffffffff; EAX = ecx83_msr & 0xffffffff;
EDX = ecx83_msr >> 32; EDX = ecx83_msr >> 32;
break; break;
case 0xC0000080:
EAX = amd_efer & 0xffffffff;
EDX = amd_efer >> 32;
break;
case 0xC0000082:
EAX = amd_whcr & 0xffffffff;
EDX = amd_whcr >> 32;
break;
default:
x86gpf(NULL, 0);
break;
}
break;
case CPU_K6_2:
EAX = EDX = 0;
switch (ECX)
{
case 0x0000000e:
EAX = msr.tr12;
break;
case 0x00000010:
EAX = tsc & 0xffffffff;
EDX = tsc >> 32;
break;
case 0x00000083:
EAX = ecx83_msr & 0xffffffff;
EDX = ecx83_msr >> 32;
break;
case 0xC0000080:
EAX = amd_efer & 0xffffffff;
EDX = amd_efer >> 32;
break;
case 0xC0000081: case 0xC0000081:
EAX = star & 0xffffffff; EAX = star & 0xffffffff;
EDX = star >> 32; EDX = star >> 32;
break; break;
case 0xC0000084: case 0xC0000082:
EAX = sfmask & 0xffffffff; EAX = amd_whcr & 0xffffffff;
EDX = sfmask >> 32; EDX = amd_whcr >> 32;
break; break;
default: default:
x86gpf(NULL, 0); x86gpf(NULL, 0);
@@ -2082,11 +2134,49 @@ void cpu_WRMSR()
case 0x83: case 0x83:
ecx83_msr = EAX | ((uint64_t)EDX << 32); ecx83_msr = EAX | ((uint64_t)EDX << 32);
break; break;
case 0xC0000080:
temp = EAX | ((uint64_t)EDX << 32);
if (temp & ~1ULL)
x86gpf(NULL, 0);
else
amd_efer = temp;
break;
case 0xC0000082:
amd_whcr = EAX | ((uint64_t)EDX << 32);
break;
default:
x86gpf(NULL, 0);
break;
}
break;
case CPU_K6_2:
switch (ECX)
{
case 0x0e:
msr.tr12 = EAX & 0x228;
break;
case 0x10:
tsc = EAX | ((uint64_t)EDX << 32);
break;
case 0x83:
ecx83_msr = EAX | ((uint64_t)EDX << 32);
break;
case 0xC0000080:
temp = EAX | ((uint64_t)EDX << 32);
if (temp & ~1ULL)
x86gpf(NULL, 0);
else
amd_efer = temp;
break;
case 0xC0000081: case 0xC0000081:
star = EAX | ((uint64_t)EDX << 32); star = EAX | ((uint64_t)EDX << 32);
break; break;
case 0xC0000084: case 0xC0000082:
sfmask = EAX | ((uint64_t)EDX << 32); amd_whcr = EAX | ((uint64_t)EDX << 32);
break;
default:
x86gpf(NULL, 0);
break; break;
} }
break; break;

2
src/cpu/cpu.h
View File

@@ -505,6 +505,8 @@ extern void x87_reset(void);
extern int cpu_effective, cpu_alt_reset; extern int cpu_effective, cpu_alt_reset;
extern void cpu_dynamic_switch(int new_cpu); extern void cpu_dynamic_switch(int new_cpu);
extern void cpu_ven_reset(void);
#endif /*EMU_CPU_H*/ #endif /*EMU_CPU_H*/
#endif #endif

2
src/cpu_new/808x.c
View File

@@ -957,6 +957,8 @@ reset_common(int hard)
prefetching = 1; prefetching = 1;
takeint = 0; takeint = 0;
cpu_ven_reset();
} }

419
src/cpu_new/cpu.c
View File

@@ -196,8 +196,12 @@ uint64_t ecx570_msr = 0;
#endif #endif
uint64_t ecx83_msr = 0; /* AMD K5 and K6 MSR's. */ uint64_t ecx83_msr = 0; /* AMD K5 and K6 MSR's. */
uint64_t star = 0; /* These are K6-only. */ uint64_t star = 0; /* AMD K6-2+. */
uint64_t sfmask = 0;
uint64_t amd_efer = 0, amd_whcr = 0, /* AMD K6-2+ registers. */
amd_uwccr = 0, amd_epmr = 0,
amd_psor = 0, amd_pfir = 0,
amd_l2aar = 0;
int timing_rr; int timing_rr;
int timing_mr, timing_mrl; int timing_mr, timing_mrl;
@@ -1280,9 +1284,9 @@ cpu_set(void)
case CPU_K6: case CPU_K6:
#ifdef USE_DYNAREC #ifdef USE_DYNAREC
x86_setopcodes(ops_386, ops_k6_0f, dynarec_ops_386, dynarec_ops_k6_0f); x86_setopcodes(ops_386, ops_pentiummmx_0f, dynarec_ops_386, dynarec_ops_pentiummmx_0f);
#else #else
x86_setopcodes(ops_386, ops_k6_0f); x86_setopcodes(ops_386, ops_pentiummmx_0f);
#endif #endif
timing_rr = 1; /*register dest - register src*/ timing_rr = 1; /*register dest - register src*/
timing_rm = 2; /*register dest - memory src*/ timing_rm = 2; /*register dest - memory src*/
@@ -1322,6 +1326,7 @@ cpu_set(void)
break; break;
case CPU_K6_2: case CPU_K6_2:
case CPU_K6_2C:
case CPU_K6_3: case CPU_K6_3:
case CPU_K6_2P: case CPU_K6_2P:
case CPU_K6_3P: case CPU_K6_3P:
@@ -1870,6 +1875,7 @@ cpu_CPUID(void)
break; break;
case CPU_K6_2: case CPU_K6_2:
case CPU_K6_2C:
switch (EAX) switch (EAX)
{ {
case 0: case 0:
@@ -2200,6 +2206,44 @@ cpu_CPUID(void)
} }
} }
void cpu_ven_reset(void)
{
switch (machines[machine].cpu[cpu_manufacturer].cpus[cpu_effective].cpu_type)
{
case CPU_K5:
case CPU_5K86:
case CPU_K6:
amd_efer = amd_whcr = 0ULL;
break;
case CPU_K6_2:
amd_efer = amd_whcr = 0ULL;
star = 0ULL;
break;
case CPU_K6_2C:
amd_efer = 2ULL;
amd_whcr = star = 0ULL;
amd_psor = 0x018cULL;
amd_uwccr = 0ULL;
break;
case CPU_K6_3:
amd_efer = 2ULL;
amd_whcr = star = 0ULL;
amd_psor = 0x008cULL;
amd_uwccr = 0ULL;
amd_pfir = amd_l2aar = 0ULL;
break;
case CPU_K6_2P:
case CPU_K6_3P:
amd_efer = 2ULL;
amd_whcr = star = 0ULL;
amd_psor = 0x008cULL;
amd_uwccr = 0ULL;
amd_pfir = amd_l2aar = 0ULL;
amd_epmr = 0ULL;
break;
}
}
void cpu_RDMSR() void cpu_RDMSR()
{ {
switch (machines[machine].cpu[cpu_manufacturer].cpus[cpu_effective].cpu_type) switch (machines[machine].cpu[cpu_manufacturer].cpus[cpu_effective].cpu_type)
@@ -2238,31 +2282,208 @@ void cpu_RDMSR()
case CPU_K5: case CPU_K5:
case CPU_5K86: case CPU_5K86:
case CPU_K6: case CPU_K6:
case CPU_K6_2:
case CPU_K6_3:
case CPU_K6_2P:
case CPU_K6_3P:
EAX = EDX = 0; EAX = EDX = 0;
switch (ECX) switch (ECX)
{ {
case 0x0e: case 0x0000000e:
EAX = msr.tr12; EAX = msr.tr12;
break; break;
case 0x10: case 0x00000010:
EAX = tsc & 0xffffffff; EAX = tsc & 0xffffffff;
EDX = tsc >> 32; EDX = tsc >> 32;
break; break;
case 0x83: case 0x00000083:
EAX = ecx83_msr & 0xffffffff; EAX = ecx83_msr & 0xffffffff;
EDX = ecx83_msr >> 32; EDX = ecx83_msr >> 32;
break; break;
case 0xC0000080:
EAX = amd_efer & 0xffffffff;
EDX = amd_efer >> 32;
break;
case 0xC0000082:
EAX = amd_whcr & 0xffffffff;
EDX = amd_whcr >> 32;
break;
default:
x86gpf(NULL, 0);
break;
}
break;
case CPU_K6_2:
EAX = EDX = 0;
switch (ECX)
{
case 0x0000000e:
EAX = msr.tr12;
break;
case 0x00000010:
EAX = tsc & 0xffffffff;
EDX = tsc >> 32;
break;
case 0x00000083:
EAX = ecx83_msr & 0xffffffff;
EDX = ecx83_msr >> 32;
break;
case 0xC0000080:
EAX = amd_efer & 0xffffffff;
EDX = amd_efer >> 32;
break;
case 0xC0000081: case 0xC0000081:
EAX = star & 0xffffffff; EAX = star & 0xffffffff;
EDX = star >> 32; EDX = star >> 32;
break; break;
case 0xC0000084: case 0xC0000082:
EAX = sfmask & 0xffffffff; EAX = amd_whcr & 0xffffffff;
EDX = sfmask >> 32; EDX = amd_whcr >> 32;
break;
default:
x86gpf(NULL, 0);
break;
}
break;
case CPU_K6_2C:
EAX = EDX = 0;
switch (ECX)
{
case 0x0000000e:
EAX = msr.tr12;
break;
case 0x00000010:
EAX = tsc & 0xffffffff;
EDX = tsc >> 32;
break;
case 0x00000083:
EAX = ecx83_msr & 0xffffffff;
EDX = ecx83_msr >> 32;
break;
case 0xC0000080:
EAX = amd_efer & 0xffffffff;
EDX = amd_efer >> 32;
break;
case 0xC0000081:
EAX = star & 0xffffffff;
EDX = star >> 32;
break;
case 0xC0000082:
EAX = amd_whcr & 0xffffffff;
EDX = amd_whcr >> 32;
break;
case 0xC0000085:
EAX = amd_uwccr & 0xffffffff;
EDX = amd_uwccr >> 32;
break;
case 0xC0000087:
EAX = amd_psor & 0xffffffff;
EDX = amd_psor >> 32;
break;
case 0xC0000088:
EAX = amd_pfir & 0xffffffff;
EDX = amd_pfir >> 32;
break;
default:
x86gpf(NULL, 0);
break;
}
break;
case CPU_K6_3:
EAX = EDX = 0;
switch (ECX)
{
case 0x0000000e:
EAX = msr.tr12;
break;
case 0x00000010:
EAX = tsc & 0xffffffff;
EDX = tsc >> 32;
break;
case 0x00000083:
EAX = ecx83_msr & 0xffffffff;
EDX = ecx83_msr >> 32;
break;
case 0xC0000080:
EAX = amd_efer & 0xffffffff;
EDX = amd_efer >> 32;
break;
case 0xC0000081:
EAX = star & 0xffffffff;
EDX = star >> 32;
break;
case 0xC0000082:
EAX = amd_whcr & 0xffffffff;
EDX = amd_whcr >> 32;
break;
case 0xC0000085:
EAX = amd_uwccr & 0xffffffff;
EDX = amd_uwccr >> 32;
break;
case 0xC0000087:
EAX = amd_psor & 0xffffffff;
EDX = amd_psor >> 32;
break;
case 0xC0000088:
EAX = amd_pfir & 0xffffffff;
EDX = amd_pfir >> 32;
break;
case 0xC0000089:
EAX = amd_l2aar & 0xffffffff;
EDX = amd_l2aar >> 32;
break;
default:
x86gpf(NULL, 0);
break;
}
break;
case CPU_K6_2P:
case CPU_K6_3P:
EAX = EDX = 0;
switch (ECX)
{
case 0x0000000e:
EAX = msr.tr12;
break;
case 0x00000010:
EAX = tsc & 0xffffffff;
EDX = tsc >> 32;
break;
case 0x00000083:
EAX = ecx83_msr & 0xffffffff;
EDX = ecx83_msr >> 32;
break;
case 0xC0000080:
EAX = amd_efer & 0xffffffff;
EDX = amd_efer >> 32;
break;
case 0xC0000081:
EAX = star & 0xffffffff;
EDX = star >> 32;
break;
case 0xC0000082:
EAX = amd_whcr & 0xffffffff;
EDX = amd_whcr >> 32;
break;
case 0xC0000085:
EAX = amd_uwccr & 0xffffffff;
EDX = amd_uwccr >> 32;
break;
case 0xC0000086:
EAX = amd_epmr & 0xffffffff;
EDX = amd_epmr >> 32;
break;
case 0xC0000087:
EAX = amd_psor & 0xffffffff;
EDX = amd_psor >> 32;
break;
case 0xC0000088:
EAX = amd_pfir & 0xffffffff;
EDX = amd_pfir >> 32;
break;
case 0xC0000089:
EAX = amd_l2aar & 0xffffffff;
EDX = amd_l2aar >> 32;
break; break;
default: default:
x86gpf(NULL, 0); x86gpf(NULL, 0);
@@ -2425,6 +2646,8 @@ i686_invalid_rdmsr:
void cpu_WRMSR() void cpu_WRMSR()
{ {
uint64_t temp;
switch (machines[machine].cpu[cpu_manufacturer].cpus[cpu_effective].cpu_type) switch (machines[machine].cpu[cpu_manufacturer].cpus[cpu_effective].cpu_type)
{ {
case CPU_WINCHIP: case CPU_WINCHIP:
@@ -2474,8 +2697,147 @@ void cpu_WRMSR()
case CPU_K5: case CPU_K5:
case CPU_5K86: case CPU_5K86:
case CPU_K6: case CPU_K6:
switch (ECX)
{
case 0x0e:
msr.tr12 = EAX & 0x228;
break;
case 0x10:
tsc = EAX | ((uint64_t)EDX << 32);
break;
case 0x83:
ecx83_msr = EAX | ((uint64_t)EDX << 32);
break;
case 0xC0000080:
temp = EAX | ((uint64_t)EDX << 32);
if (temp & ~1ULL)
x86gpf(NULL, 0);
else
amd_efer = temp;
break;
case 0xC0000082:
amd_whcr = EAX | ((uint64_t)EDX << 32);
break;
default:
x86gpf(NULL, 0);
break;
}
break;
case CPU_K6_2: case CPU_K6_2:
switch (ECX)
{
case 0x0e:
msr.tr12 = EAX & 0x228;
break;
case 0x10:
tsc = EAX | ((uint64_t)EDX << 32);
break;
case 0x83:
ecx83_msr = EAX | ((uint64_t)EDX << 32);
break;
case 0xC0000080:
temp = EAX | ((uint64_t)EDX << 32);
if (temp & ~1ULL)
x86gpf(NULL, 0);
else
amd_efer = temp;
break;
case 0xC0000081:
star = EAX | ((uint64_t)EDX << 32);
break;
case 0xC0000082:
amd_whcr = EAX | ((uint64_t)EDX << 32);
break;
default:
x86gpf(NULL, 0);
break;
}
break;
case CPU_K6_2C:
switch (ECX)
{
case 0x0e:
msr.tr12 = EAX & 0x228;
break;
case 0x10:
tsc = EAX | ((uint64_t)EDX << 32);
break;
case 0x83:
ecx83_msr = EAX | ((uint64_t)EDX << 32);
break;
case 0xC0000080:
temp = EAX | ((uint64_t)EDX << 32);
if (temp & ~0xfULL)
x86gpf(NULL, 0);
else
amd_efer = temp;
break;
case 0xC0000081:
star = EAX | ((uint64_t)EDX << 32);
break;
case 0xC0000082:
amd_whcr = EAX | ((uint64_t)EDX << 32);
break;
case 0xC0000085:
amd_uwccr = EAX | ((uint64_t)EDX << 32);
break;
case 0xC0000087:
amd_psor = EAX | ((uint64_t)EDX << 32);
break;
case 0xC0000088:
amd_pfir = EAX | ((uint64_t)EDX << 32);
break;
default:
x86gpf(NULL, 0);
break;
}
break;
case CPU_K6_3: case CPU_K6_3:
switch (ECX)
{
case 0x0e:
msr.tr12 = EAX & 0x228;
break;
case 0x10:
tsc = EAX | ((uint64_t)EDX << 32);
break;
case 0x83:
ecx83_msr = EAX | ((uint64_t)EDX << 32);
break;
case 0xC0000080:
temp = EAX | ((uint64_t)EDX << 32);
if (temp & ~0x1fULL)
x86gpf(NULL, 0);
else
amd_efer = temp;
break;
case 0xC0000081:
star = EAX | ((uint64_t)EDX << 32);
break;
case 0xC0000082:
amd_whcr = EAX | ((uint64_t)EDX << 32);
break;
case 0xC0000085:
amd_uwccr = EAX | ((uint64_t)EDX << 32);
break;
case 0xC0000087:
amd_psor = EAX | ((uint64_t)EDX << 32);
break;
case 0xC0000088:
amd_pfir = EAX | ((uint64_t)EDX << 32);
break;
case 0xC0000089:
amd_l2aar = EAX | ((uint64_t)EDX << 32);
break;
default:
x86gpf(NULL, 0);
break;
}
break;
case CPU_K6_2P: case CPU_K6_2P:
case CPU_K6_3P: case CPU_K6_3P:
switch (ECX) switch (ECX)
@@ -2489,11 +2851,36 @@ void cpu_WRMSR()
case 0x83: case 0x83:
ecx83_msr = EAX | ((uint64_t)EDX << 32); ecx83_msr = EAX | ((uint64_t)EDX << 32);
break; break;
case 0xC0000080:
temp = EAX | ((uint64_t)EDX << 32);
if (temp & ~0x1fULL)
x86gpf(NULL, 0);
else
amd_efer = temp;
break;
case 0xC0000081: case 0xC0000081:
star = EAX | ((uint64_t)EDX << 32); star = EAX | ((uint64_t)EDX << 32);
break; break;
case 0xC0000084: case 0xC0000082:
sfmask = EAX | ((uint64_t)EDX << 32); amd_whcr = EAX | ((uint64_t)EDX << 32);
break;
case 0xC0000085:
amd_uwccr = EAX | ((uint64_t)EDX << 32);
break;
case 0xC0000086:
amd_epmr = EAX | ((uint64_t)EDX << 32);
break;
case 0xC0000087:
amd_psor = EAX | ((uint64_t)EDX << 32);
break;
case 0xC0000088:
amd_pfir = EAX | ((uint64_t)EDX << 32);
break;
case 0xC0000089:
amd_l2aar = EAX | ((uint64_t)EDX << 32);
break;
default:
x86gpf(NULL, 0);
break; break;
} }
break; break;

13
src/cpu_new/cpu.h
View File

@@ -53,11 +53,12 @@
#define CPU_5K86 28 #define CPU_5K86 28
#define CPU_K6 29 #define CPU_K6 29
#define CPU_K6_2 30 #define CPU_K6_2 30
#define CPU_K6_3 31 #define CPU_K6_2C 31
#define CPU_K6_2P 32 #define CPU_K6_3 32
#define CPU_K6_3P 33 #define CPU_K6_2P 33
#define CPU_PENTIUMPRO 34 /* 686 class CPUs */ #define CPU_K6_3P 34
#define CPU_PENTIUM2D 35 #define CPU_PENTIUMPRO 35 /* 686 class CPUs */
#define CPU_PENTIUM2D 36
#define MANU_INTEL 0 #define MANU_INTEL 0
#define MANU_AMD 1 #define MANU_AMD 1
@@ -500,5 +501,7 @@ extern void x87_reset(void);
extern int cpu_effective, cpu_alt_reset; extern int cpu_effective, cpu_alt_reset;
extern void cpu_dynamic_switch(int new_cpu); extern void cpu_dynamic_switch(int new_cpu);
extern void cpu_ven_reset(void);
#endif /*EMU_CPU_H*/ #endif /*EMU_CPU_H*/

18
src/cpu_new/cpu_table.c
View File

@@ -621,15 +621,15 @@ CPU cpus_K56_SS7[] = {
{"K6-2/266", CPU_K6_2, 266666666, 4, 33333333, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24, 24, 12, 12, 32}, {"K6-2/266", CPU_K6_2, 266666666, 4, 33333333, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 24, 24, 12, 12, 32},
{"K6-2/300", CPU_K6_2, 300000000, 3, 33333333, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27, 27, 9, 9, 36}, {"K6-2/300", CPU_K6_2, 300000000, 3, 33333333, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 27, 27, 9, 9, 36},
{"K6-2/333", CPU_K6_2, 332500000, 7/2, 31666667, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 30, 30, 11, 11, 40}, {"K6-2/333", CPU_K6_2, 332500000, 7/2, 31666667, 0x580, 0x580, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 30, 30, 11, 11, 40},
{"K6-2/350", CPU_K6_2, 350000000, 7/2, 33333333, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 32, 32, 11, 11, 42}, {"K6-2/350", CPU_K6_2C, 350000000, 7/2, 33333333, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 32, 32, 11, 11, 42},
{"K6-2/366", CPU_K6_2, 366666666, 11/2, 33333333, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 33, 33, 17, 17, 44}, {"K6-2/366", CPU_K6_2C, 366666666, 11/2, 33333333, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 33, 33, 17, 17, 44},
{"K6-2/380", CPU_K6_2, 380000000, 4, 31666667, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 34, 34, 12, 12, 46}, {"K6-2/380", CPU_K6_2C, 380000000, 4, 31666667, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 34, 34, 12, 12, 46},
{"K6-2/400", CPU_K6_2, 400000000, 4, 33333333, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 36, 36, 12, 12, 48}, {"K6-2/400", CPU_K6_2C, 400000000, 4, 33333333, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 36, 36, 12, 12, 48},
{"K6-2/450", CPU_K6_2, 450000000, 9/2, 33333333, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 41, 41, 14, 14, 54}, {"K6-2/450", CPU_K6_2C, 450000000, 9/2, 33333333, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 41, 41, 14, 14, 54},
{"K6-2/475", CPU_K6_2, 475000000, 5, 31666667, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 43, 43, 15, 15, 57}, {"K6-2/475", CPU_K6_2C, 475000000, 5, 31666667, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 43, 43, 15, 15, 57},
{"K6-2/500", CPU_K6_2, 500000000, 5, 33333333, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 45, 45, 15, 15, 60}, {"K6-2/500", CPU_K6_2C, 500000000, 5, 33333333, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 45, 45, 15, 15, 60},
{"K6-2/533", CPU_K6_2, 533333333, 11/2, 32323232, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 48, 48, 17, 17, 64}, {"K6-2/533", CPU_K6_2C, 533333333, 11/2, 32323232, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 48, 48, 17, 17, 64},
{"K6-2/550", CPU_K6_2, 550000000, 11/2, 33333333, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 50, 50, 17, 17, 66}, {"K6-2/550", CPU_K6_2C, 550000000, 11/2, 33333333, 0x58c, 0x58c, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 50, 50, 17, 17, 66},
/*AMD K6-2+/K6-3/K6-3+ (Super Socket 7)*/ /*AMD K6-2+/K6-3/K6-3+ (Super Socket 7)*/
{"K6-2+/450", CPU_K6_2P, 450000000, 9/2, 33333333, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 41, 41, 14, 14, 54}, {"K6-2+/450", CPU_K6_2P, 450000000, 9/2, 33333333, 0x5d4, 0x5d4, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 41, 41, 14, 14, 54},