Implemented PCI interrupt controller ports 4D0 and 4D1;
Applied more mainline PCem commits; Repplied the CPU optimization commit alongside the fix commit.
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@@ -265,7 +265,14 @@ uint8_t sb_pro_mixer_read(uint16_t addr, void *p)
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if (!(addr & 1))
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return mixer->index;
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return mixer->regs[mixer->index];
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switch (mixer->index)
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{
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case 0x00: case 0x04: case 0x0a: case 0x0c: case 0x0e:
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case 0x22: case 0x26: case 0x28: case 0x2e:
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return mixer->regs[mixer->index];
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}
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return 0xff;
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}
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void sb_16_mixer_write(uint16_t addr, uint8_t val, void *p)
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@@ -514,6 +514,10 @@ void sb_exec_command(sb_dsp_t *dsp)
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if (dsp->sb_type < SB16) break;
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sb_add_data(dsp, dsp->sb_asp_regs[dsp->sb_data[0]]);
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break;
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case 0xF8:
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if (dsp->sb_type < SB16) break;
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sb_add_data(dsp, 0);
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break;
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case 0xF9:
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if (dsp->sb_type < SB16) break;
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if (dsp->sb_data[0] == 0x0e) sb_add_data(dsp, 0xff);
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