Merge remote-tracking branch 'origin/master' into mke

2025-07-27 02:27:14 +06:00
parent 7392f81536 084af82b1b
commit ecba9783b3
17 changed files with 673 additions and 255 deletions
--- a/src/disk/hdc.c
+++ b/src/disk/hdc.c
@@ -78,6 +78,8 @@ static const struct {
    { &xtide_at_2ch_device         },
    { &xtide_at_ps2_device         },
    { &xtide_at_ps2_2ch_device     },
+    { &ide_ter_device              },
+    { &ide_qua_device              },
    { &st506_at_wd1003_device      },
    { &esdi_at_wd1007vse1_device   },
    /* MCA */
@@ -88,6 +90,8 @@ static const struct {
    { &ide_vlb_device              },
    { &ide_vlb_2ch_device          },
    /* PCI */
+    { &ide_cmd646_ter_qua_device   },
+    { &ide_cmd648_ter_qua_device   },
    { &ide_pci_device              },
    { &ide_pci_2ch_device          },
    { NULL                         }
@@ -108,18 +112,14 @@ hdc_init(void)
 void
 hdc_reset(void)
 {
-    hdc_log("HDC: reset(current=%d, internal=%d)\n",
-            hdc_current[0], (machines[machine].flags & MACHINE_HDC) ? 1 : 0);
+    for (int i = 0; i < HDC_MAX; i++) {
+        hdc_log("HDC %i: reset(current=%d, internal=%d)\n", i,
+                hdc_current[i], hdc_current[i] == HDC_INTERNAL);

-    /* If we have a valid controller, add its device. */
-    if (hdc_current[0] > HDC_INTERNAL)
-        device_add(controllers[hdc_current[0]].device);
-
-    /* Now, add the tertiary and/or quaternary IDE controllers. */
-    if (ide_ter_enabled)
-        device_add(&ide_ter_device);
-    if (ide_qua_enabled)
-        device_add(&ide_qua_device);
+        /* If we have a valid controller, add its device. */
+        if (hdc_current[i] > HDC_INTERNAL)
+            device_add_inst(controllers[hdc_current[i]].device, i + 1);
+    }
 }

 const char *
--- a/src/disk/hdc_ide.c
+++ b/src/disk/hdc_ide.c
@@ -235,8 +235,6 @@ static uint8_t ide_qua_pnp_rom[] = {
 };

 ide_t *ide_drives[IDE_NUM];
-int    ide_ter_enabled = 0;
-int    ide_qua_enabled = 0;

 static void ide_atapi_callback(ide_t *ide);
 static void ide_callback(void *priv);
--- a/src/disk/hdc_ide_cmd640.c
+++ b/src/disk/hdc_ide_cmd640.c
@@ -667,7 +667,7 @@ const device_t ide_cmd640_pci_legacy_only_device = {
 };

 const device_t ide_cmd640_pci_single_channel_device = {
-    .name          = "CMD PCI-0640B PCI",
+    .name          = "CMD PCI-0640B PCI (Single Channel)",
    .internal_name = "ide_cmd640_pci_single_channel",
    .flags         = DEVICE_PCI,
    .local         = 0x2000a,
@@ -681,7 +681,7 @@ const device_t ide_cmd640_pci_single_channel_device = {
 };

 const device_t ide_cmd640_pci_single_channel_sec_device = {
-    .name          = "CMD PCI-0640B PCI",
+    .name          = "CMD PCI-0640B PCI (Single Channel, Secondary)",
    .internal_name = "ide_cmd640_pci_single_channel_sec",
    .flags         = DEVICE_PCI,
    .local         = 0x4000a,
--- a/src/disk/hdc_ide_cmd646.c
+++ b/src/disk/hdc_ide_cmd646.c
@@ -35,7 +35,19 @@
 #include <86box/hdc_ide.h>
 #include <86box/hdc_ide_sff8038i.h>
 #include <86box/rdisk.h>
+#include <86box/hdd.h>
+#include <86box/scsi_disk.h>
 #include <86box/mo.h>
+#include "cpu.h"
+#include "x86.h"
+
+#define CMD_TYPE_646    0x000000
+#define CMD_TYPE_648    0x100000
+
+#define CMD648_JP7      0x200000    /* Reload subsystem ID on reset. */
+#define CMD648_RAID     0x400000
+
+#define CMD64X_ONBOARD  0x800000

 typedef struct cmd646_t {
    uint8_t     vlb_idx;
@@ -80,7 +92,8 @@ cmd646_set_irq_0(uint8_t status, void *priv)
    if (!(dev->regs[0x50] & 0x04) || (status & 0x04))
        dev->regs[0x50] = (dev->regs[0x50] & ~0x04) | status;

-    sff_bus_master_set_irq(status, dev->bm[0]);
+    if (!(dev->local & CMD_TYPE_648) || !(dev->regs[0x71] & 0x10))
+        sff_bus_master_set_irq(status, dev->bm[0]);
 }

 static void
@@ -91,7 +104,8 @@ cmd646_set_irq_1(uint8_t status, void *priv)
    if (!(dev->regs[0x57] & 0x10) || (status & 0x04))
        dev->regs[0x57] = (dev->regs[0x57] & ~0x10) | (status << 2);

-    sff_bus_master_set_irq(status, dev->bm[1]);
+    if (!(dev->local & CMD_TYPE_648) || !(dev->regs[0x71] & 0x20))
+        sff_bus_master_set_irq(status, dev->bm[1]);
 }

 static int
@@ -116,13 +130,24 @@ cmd646_ide_handlers(cmd646_t *dev)
    uint16_t main;
    uint16_t side;
    int      irq_mode[2] = { IRQ_MODE_LEGACY, IRQ_MODE_LEGACY };
+    int      first       = 0;
+    int      reg09       = dev->regs[0x09];
+    int      reg50       = dev->regs[0x50];
+
+    if ((dev->local & CMD_TYPE_648) && (dev->regs[0x0a] == 0x04) && (dev->regs[0x0b] == 0x01)) {
+        reg09 = 0xff;
+        reg50 |= 0x40;
+    }
+
+    if (dev->local & 0x80000)
+        first += 2;

    sff_set_slot(dev->bm[0], dev->pci_slot);
    sff_set_slot(dev->bm[1], dev->pci_slot);

-    ide_pri_disable();
+    ide_handlers(first, 0);

-    if ((dev->regs[0x09] & 0x01) && (dev->regs[0x50] & 0x40)) {
+    if ((reg09 & 0x01) && (reg50 & 0x40)) {
        main = (dev->regs[0x11] << 8) | (dev->regs[0x10] & 0xf8);
        side = ((dev->regs[0x15] << 8) | (dev->regs[0x14] & 0xfc)) + 2;
    } else {
@@ -130,23 +155,28 @@ cmd646_ide_handlers(cmd646_t *dev)
        side = 0x3f6;
    }

-    ide_set_base(0, main);
-    ide_set_side(0, side);
+    ide_set_base(first, main);
+    ide_set_side(first, side);

-    if (dev->regs[0x09] & 0x01)
+    if (reg09 & 0x01)
        irq_mode[0] = IRQ_MODE_PCI_IRQ_PIN;

    sff_set_irq_mode(dev->bm[0], irq_mode[0]);
+    cmd646_log("IDE %i: %04X, %04X, %i\n", first, main, side, irq_mode[0]);

-    if (dev->regs[0x04] & 0x01)
-        ide_pri_enable();
+    int pri_enabled = (dev->regs[0x04] & 0x01);
+    if (dev->local & CMD_TYPE_648)
+        pri_enabled = pri_enabled && (dev->regs[0x51] & 0x04);
+
+    if (pri_enabled)
+        ide_handlers(first, 1);

    if (dev->single_channel)
        return;

-    ide_sec_disable();
+    ide_handlers(first + 1, 0);

-    if ((dev->regs[0x09] & 0x04) && (dev->regs[0x50] & 0x40)) {
+    if ((reg09 & 0x04) && (reg50 & 0x40)) {
        main = (dev->regs[0x19] << 8) | (dev->regs[0x18] & 0xf8);
        side = ((dev->regs[0x1d] << 8) | (dev->regs[0x1c] & 0xfc)) + 2;
    } else {
@@ -154,16 +184,17 @@ cmd646_ide_handlers(cmd646_t *dev)
        side = 0x376;
    }

-    ide_set_base(1, main);
-    ide_set_side(1, side);
+    ide_set_base(first + 1, main);
+    ide_set_side(first + 1, side);

-    if (dev->regs[0x09] & 0x04)
-        irq_mode[1] = 1;
+    if (reg09 & 0x04)
+        irq_mode[1] = IRQ_MODE_PCI_IRQ_PIN;

    sff_set_irq_mode(dev->bm[1], irq_mode[1]);
+    cmd646_log("IDE %i: %04X, %04X, %i\n", first + 1, main, side, irq_mode[1]);

    if ((dev->regs[0x04] & 0x01) && (dev->regs[0x51] & 0x08))
-        ide_sec_enable();
+        ide_handlers(first + 1, 1);
 }

 static void
@@ -175,6 +206,51 @@ cmd646_ide_bm_handlers(cmd646_t *dev)
    sff_bus_master_handler(dev->bm[1], (dev->regs[0x04] & 1), base + 8);
 }

+uint8_t
+cmd646_bm_write(uint16_t port, uint8_t val, void *priv)
+{
+    cmd646_t *dev = (cmd646_t *) priv;
+    uint8_t   ret = val;
+
+    switch (port & 0x000f) {
+        case 0x0001:
+            dev->regs[(port & 0x000f) | 0x70] = val & 0xf0;
+            if (val & 0x04)
+                dev->regs[0x50] &= ~0x04;
+            if (val & 0x08)
+                dev->regs[0x57] &= ~0x10;
+            ret &= 0x03;
+            break; 
+        case 0x0009:
+            dev->regs[(port & 0x000f) | 0x70] = (dev->regs[(port & 0x000f) | 0x70] & 0x0f) | (val & 0xf0);
+            ret &= 0x03;
+            break; 
+   }
+
+   return ret;
+}
+
+uint8_t
+cmd646_bm_read(uint16_t port, uint8_t val, void *priv)
+{
+    cmd646_t *dev = (cmd646_t *) priv;
+    uint8_t   ret = val;
+
+    switch (port & 0x000f) {
+        case 0x0001:
+            ret = (dev->regs[(port & 0x000f) | 0x70] & 0xf3) | (dev->regs[0x50] & 0x04) | ((dev->regs[0x57] & 0x10) >> 1);
+            break;
+        case 0x0002: case 0x000a:
+            ret |= 0x08;
+            break;
+        case 0x0009:
+            ret = dev->regs[(port & 0x000f) | 0x70];
+            break;
+   }
+
+   return ret;
+}
+
 static void
 cmd646_pci_write(int func, int addr, uint8_t val, void *priv)
 {
@@ -192,10 +268,20 @@ cmd646_pci_write(int func, int addr, uint8_t val, void *priv)
                dev->regs[addr] &= ~(val & 0xb1);
                break;
            case 0x09:
-                if ((dev->regs[addr] & 0x0a) == 0x0a) {
-                    dev->regs[addr]  = (dev->regs[addr] & 0x0a) | (val & 0x05);
-                    dev->irq_mode[0] = !!(val & 0x01);
-                    dev->irq_mode[1] = !!(val & 0x04);
+                if (!(dev->local & CMD_TYPE_648) ||
+                    ((dev->regs[0x0a] == 0x01) && (dev->regs[0x0b] == 0x01))) {
+                    if ((dev->regs[addr] & 0x0a) == 0x0a) {
+                        dev->regs[addr]  = (dev->regs[addr] & 0x0a) | (val & 0x05);
+                        dev->regs[addr]  = (dev->regs[addr] & 0x8a) | (val & 0x05);
+                        dev->irq_mode[0] = !!(val & 0x01);
+                        dev->irq_mode[1] = !!(val & 0x04);
+                        cmd646_ide_handlers(dev);
+                    }
+                }
+                break;
+            case 0x0a: case 0x0b:
+                if ((dev->local & CMD_TYPE_648) && (dev->regs[0x4f] & 0x04)) {
+                    dev->regs[addr] = val;
                    cmd646_ide_handlers(dev);
                }
                break;
@@ -255,18 +341,36 @@ cmd646_pci_write(int func, int addr, uint8_t val, void *priv)
                dev->regs[0x21] = val;
                cmd646_ide_bm_handlers(dev);
                break;
+            case 0x2c ... 0x2f:
+            case 0x8c ... 0x8f:
+                if (dev->local & CMD_TYPE_648)
+                    dev->regs[(addr & 0x0f) | 0x20] = val;
+                break;
+            case 0x3c:
+                dev->regs[0x3c] = val;
+                break;
+            case 0x4f:
+                if (dev->local & CMD_TYPE_648)
+                    dev->regs[addr] = (dev->regs[addr] & 0xfa) | (val & 0x05);
+                break;
            case 0x51:
-                dev->regs[addr] = val & 0xc8;
+                if (dev->local & CMD_TYPE_648)
+                    dev->regs[addr] = val & 0xcc;
+                else
+                    dev->regs[addr] = val & 0xc8;
                cmd646_ide_handlers(dev);
                break;
            case 0x52:
            case 0x54:
            case 0x56:
            case 0x58:
-            case 0x59:
            case 0x5b:
                dev->regs[addr] = val;
                break;
+            case 0x59:
+                if (!(dev->local & CMD_TYPE_648))
+                    dev->regs[addr] = val;
+                break;
            case 0x53:
            case 0x55:
                dev->regs[addr] = val & 0xc0;
@@ -274,10 +378,32 @@ cmd646_pci_write(int func, int addr, uint8_t val, void *priv)
            case 0x57:
                dev->regs[addr] = (dev->regs[addr] & 0x10) | (val & 0xcc);
                break;
-            case 0x70 ... 0x77:
+            case 0x64:
+                if (dev->local & CMD_TYPE_648)
+                    dev->regs[addr] = (dev->regs[addr] & 0xfc) | (val & 0x03);
+                break;
+            case 0x65:
+                if (dev->local & CMD_TYPE_648)
+                    dev->regs[addr] = (dev->regs[addr] & 0x7f) | (val & 0x80);
+                break;
+            case 0x71:
+                if (dev->local & CMD_TYPE_648)
+                    sff_bus_master_write(addr & 0x0f, val, dev->bm[0]);
+                else
+                    sff_bus_master_write(addr & 0x0f, val & 0x03, dev->bm[0]);
+                break;
+            case 0x70:
+            case 0x72 ... 0x77:
                sff_bus_master_write(addr & 0x0f, val, dev->bm[0]);
                break;
-            case 0x78 ... 0x7f:
+            case 0x79:
+                if (dev->local & CMD_TYPE_648)
+                    sff_bus_master_write(addr & 0x0f, val, dev->bm[1]);
+                else
+                    sff_bus_master_write(addr & 0x0f, val & 0x03, dev->bm[1]);
+                break;
+            case 0x78:
+            case 0x7a ... 0x7f:
                sff_bus_master_write(addr & 0x0f, val, dev->bm[1]);
                break;

@@ -303,6 +429,8 @@ cmd646_pci_read(int func, int addr, void *priv)
            ret = sff_bus_master_read(addr & 0x0f, dev->bm[0]);
        else if ((addr >= 0x78) && (addr <= 0x7f))
            ret = sff_bus_master_read(addr & 0x0f, dev->bm[1]);
+        else if ((dev->local & CMD_TYPE_648) && (addr >= 0x8c) && (addr <= 0x8f))
+            ret = dev->regs[(addr & 0x0f) | 0x20];
    }

    cmd646_log("[%04X:%08X] (%08X) cmd646_pci_read(%i, %02X, %02X)\n", CS, cpu_state.pc, ESI, func, addr, ret);
@@ -310,22 +438,44 @@ cmd646_pci_read(int func, int addr, void *priv)
    return ret;
 }

+static int
+check_ch(cmd646_t *dev, int channel)
+{
+    int ret = 0;
+    int min = 0;
+    int max = dev->single_channel ? 1 : 3;
+
+    if (dev->local & 0x80000) {
+        min += 4;
+        max += 4;
+    }
+
+    if ((channel >= min) && (channel <= max))
+        ret = 1;
+
+    return ret;
+}
+
 static void
 cmd646_reset(void *priv)
 {
    cmd646_t *dev = (cmd646_t *) priv;
    int       i   = 0;

+    for (i = 0; i < HDD_NUM; i++) {
+        if ((hdd[i].bus_type == HDD_BUS_ATAPI) && check_ch(dev, hdd[i].ide_channel) && hdd[i].priv)
+            scsi_disk_reset((scsi_common_t *) hdd[i].priv);
+    }
    for (i = 0; i < CDROM_NUM; i++) {
-        if ((cdrom[i].bus_type == CDROM_BUS_ATAPI) && (cdrom[i].ide_channel < 4) && cdrom[i].priv)
+        if ((cdrom[i].bus_type == CDROM_BUS_ATAPI) && check_ch(dev, cdrom[i].ide_channel) && cdrom[i].priv)
            scsi_cdrom_reset((scsi_common_t *) cdrom[i].priv);
    }
    for (i = 0; i < RDISK_NUM; i++) {
-        if ((rdisk_drives[i].bus_type == RDISK_BUS_ATAPI) && (rdisk_drives[i].ide_channel < 4) && rdisk_drives[i].priv)
+        if ((rdisk_drives[i].bus_type == RDISK_BUS_ATAPI) && check_ch(dev, rdisk_drives[i].ide_channel) && rdisk_drives[i].priv)
            rdisk_reset((scsi_common_t *) rdisk_drives[i].priv);
    }
    for (i = 0; i < MO_NUM; i++) {
-        if ((mo_drives[i].bus_type == MO_BUS_ATAPI) && (mo_drives[i].ide_channel < 4) && mo_drives[i].priv)
+        if ((mo_drives[i].bus_type == MO_BUS_ATAPI) && check_ch(dev, mo_drives[i].ide_channel) && mo_drives[i].priv)
            mo_reset((scsi_common_t *) mo_drives[i].priv);
    }

@@ -336,16 +486,26 @@ cmd646_reset(void *priv)

    dev->regs[0x00] = 0x95; /* CMD */
    dev->regs[0x01] = 0x10;
-    dev->regs[0x02] = 0x46; /* PCI-0646 */
+    if (dev->local & CMD_TYPE_648)
+        dev->regs[0x02] = 0x48; /* PCI-0648 */
+    else
+        dev->regs[0x02] = 0x46; /* PCI-0646 */
    dev->regs[0x03] = 0x06;
    dev->regs[0x04] = 0x00;
    dev->regs[0x06] = 0x80;
    dev->regs[0x07] = 0x02;       /* DEVSEL timing: 01 medium */
    dev->regs[0x09] = dev->local; /* Programming interface */
-    dev->regs[0x0a] = 0x01;       /* IDE controller */
+    if ((dev->local & CMD_TYPE_648) && (dev->local & CMD648_RAID))
+        dev->regs[0x0a] = 0x04;       /* RAID controller */
+    else
+        dev->regs[0x0a] = 0x01;       /* IDE controller */
    dev->regs[0x0b] = 0x01;       /* Mass storage controller */

-    if ((dev->local & 0xffff) == 0x8a) {
+    if ((dev->local & CMD_TYPE_648) && (dev->local & CMD648_JP7))
+        for (int i = 0; i < 4; i++)
+            dev->regs[0x2c + i] = dev->regs[i];
+
+    if ((dev->regs[0x09] & 0x8a) == 0x8a) {
        dev->regs[0x50] = 0x40; /* Enable Base address register R/W;
                                   If 0, they return 0 and are read-only 8 */

@@ -370,12 +530,38 @@ cmd646_reset(void *priv)
    if (!dev->single_channel)
        dev->regs[0x51] = 0x08;

-    dev->regs[0x57] = 0x0c;
-    dev->regs[0x59] = 0x40;
+    if (dev->local & CMD_TYPE_648) {
+        dev->regs[0x34] = 0x60;
+
+        dev->regs[0x4f] = (dev->local & CMD648_JP7) ? 0x02 : 0x00;
+        dev->regs[0x51] |= 0x04;
+
+        dev->regs[0x60] = 0x01;
+        dev->regs[0x62] = 0x21;
+        dev->regs[0x63] = 0x06;
+        dev->regs[0x65] = 0x60;
+        dev->regs[0x67] = 0xf0;
+
+        /* 80-pin stuff. */
+        dev->regs[0x72] = 0x08;
+        dev->regs[0x7a] = 0x08;
+        dev->regs[0x79] = 0x83;
+    } else
+        dev->regs[0x59] = 0x40;
+
+    dev->regs[0x57] = 0x0c;

-    dev->irq_mode[0] = dev->irq_mode[1] = 0;
    dev->irq_pin                        = PCI_INTA;

+    if ((dev->local & CMD_TYPE_648) && (dev->local & CMD648_RAID))
+        dev->irq_mode[0] = dev->irq_mode[1] = IRQ_MODE_PCI_IRQ_PIN;
+    else {
+        dev->irq_mode[0] = (dev->regs[0x09] & 0x01) ? IRQ_MODE_PCI_IRQ_PIN : IRQ_MODE_LEGACY;
+        dev->irq_mode[1] = (dev->regs[0x09] & 0x04) ? IRQ_MODE_PCI_IRQ_PIN : IRQ_MODE_LEGACY;
+    }
+
+    dev->irq_pin     = PCI_INTA;
+
    cmd646_ide_handlers(dev);
    cmd646_ide_bm_handlers(dev);
 }
@@ -391,34 +577,53 @@ cmd646_close(void *priv)
 static void *
 cmd646_init(const device_t *info)
 {
-    cmd646_t *dev = (cmd646_t *) calloc(1, sizeof(cmd646_t));
+    cmd646_t *dev   = (cmd646_t *) calloc(1, sizeof(cmd646_t));
+    int       first = 0;

    dev->local = info->local;

    device_add(&ide_pci_2ch_device);

-    if (info->local & 0x80000)
-        pci_add_card(PCI_ADD_NORMAL, cmd646_pci_read, cmd646_pci_write, dev, &dev->pci_slot);
-    else
+    if (info->local & 0x80000) {
+        first = 2;
+        device_add(&ide_pci_ter_qua_2ch_device);
+    } else
+        device_add(&ide_pci_2ch_device);
+
+    if (info->local & CMD64X_ONBOARD)
        pci_add_card(PCI_ADD_IDE, cmd646_pci_read, cmd646_pci_write, dev, &dev->pci_slot);
+    else
+        pci_add_card(PCI_ADD_NORMAL, cmd646_pci_read, cmd646_pci_write, dev, &dev->pci_slot);

    dev->single_channel = !!(info->local & 0x20000);

-    dev->bm[0] = device_add_inst(&sff8038i_device, 1);
+    dev->bm[0] = device_add_inst(&sff8038i_device, first + 1);
    if (!dev->single_channel)
-        dev->bm[1] = device_add_inst(&sff8038i_device, 2);
+        dev->bm[1] = device_add_inst(&sff8038i_device, first + 2);

-    ide_set_bus_master(0, cmd646_bus_master_dma_0, cmd646_set_irq_0, dev);
+    ide_set_bus_master(first, cmd646_bus_master_dma_0, cmd646_set_irq_0, dev);
    if (!dev->single_channel)
-        ide_set_bus_master(1, cmd646_bus_master_dma_1, cmd646_set_irq_1, dev);
+        ide_set_bus_master(first + 1, cmd646_bus_master_dma_1, cmd646_set_irq_1, dev);

    sff_set_irq_mode(dev->bm[0], IRQ_MODE_LEGACY);

    if (!dev->single_channel)
        sff_set_irq_mode(dev->bm[1], IRQ_MODE_LEGACY);

+    sff_set_slot(dev->bm[0], dev->pci_slot);
+    sff_set_slot(dev->bm[1], dev->pci_slot);
+
+    if (dev->local & CMD_TYPE_648) {
+        sff_set_ven_handlers(dev->bm[0], cmd646_bm_write, cmd646_bm_read, dev);
+        sff_set_ven_handlers(dev->bm[1], cmd646_bm_write, cmd646_bm_read, dev);
+    }
+
    cmd646_reset(dev);

+    if (dev->local & CMD_TYPE_648)
+        for (int i = 0; i < 4; i++)
+            dev->regs[0x2c + i] = dev->regs[i];
+
    return dev;
 }

@@ -426,7 +631,7 @@ const device_t ide_cmd646_device = {
    .name          = "CMD PCI-0646",
    .internal_name = "ide_cmd646",
    .flags         = DEVICE_PCI,
-    .local         = 0x8a,
+    .local         = 0x8a | CMD64X_ONBOARD,
    .init          = cmd646_init,
    .close         = cmd646_close,
    .reset         = cmd646_reset,
@@ -440,7 +645,7 @@ const device_t ide_cmd646_legacy_only_device = {
    .name          = "CMD PCI-0646 (Legacy Mode Only)",
    .internal_name = "ide_cmd646_legacy_only",
    .flags         = DEVICE_PCI,
-    .local         = 0x80,
+    .local         = 0x80 | CMD64X_ONBOARD,
    .init          = cmd646_init,
    .close         = cmd646_close,
    .reset         = cmd646_reset,
@@ -451,10 +656,52 @@ const device_t ide_cmd646_legacy_only_device = {
 };

 const device_t ide_cmd646_single_channel_device = {
-    .name          = "CMD PCI-0646",
+    .name          = "CMD PCI-0646 (Single Channel)",
    .internal_name = "ide_cmd646_single_channel",
    .flags         = DEVICE_PCI,
-    .local         = 0x2008a,
+    .local         = 0x2008a | CMD64X_ONBOARD,
+    .init          = cmd646_init,
+    .close         = cmd646_close,
+    .reset         = cmd646_reset,
+    .available     = NULL,
+    .speed_changed = NULL,
+    .force_redraw  = NULL,
+    .config        = NULL
+};
+
+const device_t ide_cmd646_ter_qua_device = {
+    .name          = "CMD PCI-0646 (Tertiary and Quaternary)",
+    .internal_name = "ide_cmd646_ter_qua",
+    .flags         = DEVICE_PCI,
+    .local         = 0x8008f,
+    .init          = cmd646_init,
+    .close         = cmd646_close,
+    .reset         = cmd646_reset,
+    .available     = NULL,
+    .speed_changed = NULL,
+    .force_redraw  = NULL,
+    .config        = NULL
+};
+
+const device_t ide_cmd648_ter_qua_device = {
+    .name          = "CMD PCI-0648 (Tertiary and Quaternary)",
+    .internal_name = "ide_cmd648_ter_qua",
+    .flags         = DEVICE_PCI,
+    .local         = 0x78008f,
+    .init          = cmd646_init,
+    .close         = cmd646_close,
+    .reset         = cmd646_reset,
+    .available     = NULL,
+    .speed_changed = NULL,
+    .force_redraw  = NULL,
+    .config        = NULL
+};
+
+const device_t ide_cmd648_ter_qua_onboard_device = {
+    .name          = "CMD PCI-0648 (Tertiary and Quaternary) On-Board",
+    .internal_name = "ide_cmd648_ter_qua_onboard",
+    .flags         = DEVICE_PCI,
+    .local         = 0x78008f | CMD64X_ONBOARD,
    .init          = cmd646_init,
    .close         = cmd646_close,
    .reset         = cmd646_reset,
--- a/src/disk/hdc_ide_rz1000.c
+++ b/src/disk/hdc_ide_rz1000.c
@@ -275,7 +275,7 @@ const device_t ide_rz1000_pci_device = {
 };

 const device_t ide_rz1000_pci_single_channel_device = {
-    .name          = "PC Technology RZ-1000 PCI",
+    .name          = "PC Technology RZ-1000 PCI (Single Channel)",
    .internal_name = "ide_rz1000_pci_single_channel",
    .flags         = DEVICE_PCI,
    .local         = 0x20000,
--- a/src/disk/hdc_ide_sff8038i.c
+++ b/src/disk/hdc_ide_sff8038i.c
@@ -118,6 +118,9 @@ sff_bus_master_write(uint16_t port, uint8_t val, void *priv)

    sff_log("SFF-8038i Bus master BYTE  write: %04X       %02X\n", port, val);

+    if (dev->ven_write != NULL)
+        val = dev->ven_write(port, val, dev->priv);
+
    switch (port & 7) {
        case 0:
            sff_log("sff Cmd   : val = %02X, old = %02X\n", val, dev->command);
@@ -255,6 +258,9 @@ sff_bus_master_read(uint16_t port, void *priv)
            break;
    }

+    if (dev->ven_read != NULL)
+        ret= dev->ven_read(port, ret, dev->priv);
+
    sff_log("SFF-8038i Bus master BYTE  read : %04X       %02X\n", port, ret);

    return ret;
@@ -569,6 +575,16 @@ sff_set_mirq(sff8038i_t *dev, uint8_t mirq)
    dev->mirq = mirq;
 }

+void
+sff_set_ven_handlers(sff8038i_t *dev, uint8_t (*ven_write)(uint16_t port, uint8_t val, void *priv),
+                     uint8_t (*ven_read)(uint16_t port, uint8_t val, void *priv), void *priv)
+{
+    dev->ven_write = ven_write;
+    dev->ven_read  = ven_read;
+
+    dev->priv      = priv;
+}
+
 static void
 sff_close(void *priv)
 {