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This commit is contained in:
Jasmine Iwanek
2023-06-09 23:46:54 -04:00
parent 0d1d069af4
commit ee695e71f9
218 changed files with 6282 additions and 3845 deletions
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60
src/scsi/scsi_aha154x.c
View File

@@ -71,7 +71,7 @@ uint16_t aha_ports[] = {
static uint8_t *aha1542cp_pnp_rom = NULL;
#pragma pack(push, 1)
typedef struct {
typedef struct aha_setup_t {
uint8_t CustomerSignature[20];
uint8_t uAutoRetry;
uint8_t uBoardSwitches;
@@ -163,7 +163,7 @@ aha_eeprom_save(x54x_t *dev)
}
static uint8_t
aha154x_eeprom(x54x_t *dev, uint8_t cmd, uint8_t arg, uint8_t len, uint8_t off, uint8_t *bufp)
aha154x_eeprom(x54x_t *dev, uint8_t cmd, UNUSED(uint8_t arg), uint8_t len, uint8_t off, uint8_t *bufp)
{
uint8_t r = 0xff;
int c;
@@ -217,39 +217,42 @@ aha154x_mmap(x54x_t *dev, uint8_t cmd)
/* Enable the mapper, so, set ROM2 active. */
dev->bios.rom = dev->rom2;
break;
default:
break;
}
return 0;
}
static uint8_t
aha_get_host_id(void *p)
aha_get_host_id(void *priv)
{
x54x_t *dev = (x54x_t *) p;
x54x_t *dev = (x54x_t *) priv;
return dev->nvr[0] & 0x07;
}
static uint8_t
aha_get_irq(void *p)
aha_get_irq(void *priv)
{
x54x_t *dev = (x54x_t *) p;
x54x_t *dev = (x54x_t *) priv;
return (dev->nvr[1] & 0x07) + 9;
}
static uint8_t
aha_get_dma(void *p)
aha_get_dma(void *priv)
{
x54x_t *dev = (x54x_t *) p;
x54x_t *dev = (x54x_t *) priv;
return (dev->nvr[1] >> 4) & 0x07;
}
static uint8_t
aha_cmd_is_fast(void *p)
aha_cmd_is_fast(void *priv)
{
x54x_t *dev = (x54x_t *) p;
x54x_t *dev = (x54x_t *) priv;
if (dev->Command == CMD_BIOS_SCSI)
return 1;
@@ -258,9 +261,9 @@ aha_cmd_is_fast(void *p)
}
static uint8_t
aha_fast_cmds(void *p, uint8_t cmd)
aha_fast_cmds(void *priv, uint8_t cmd)
{
x54x_t *dev = (x54x_t *) p;
x54x_t *dev = (x54x_t *) priv;
if (cmd == CMD_BIOS_SCSI) {
dev->BIOSMailboxReq++;
@@ -271,9 +274,9 @@ aha_fast_cmds(void *p, uint8_t cmd)
}
static uint8_t
aha_param_len(void *p)
aha_param_len(void *priv)
{
x54x_t *dev = (x54x_t *) p;
x54x_t *dev = (x54x_t *) priv;
switch (dev->Command) {
case CMD_BIOS_MBINIT:
@@ -307,9 +310,9 @@ aha_param_len(void *p)
}
static uint8_t
aha_cmds(void *p)
aha_cmds(void *priv)
{
x54x_t *dev = (x54x_t *) p;
x54x_t *dev = (x54x_t *) priv;
MailboxInit_t *mbi;
if (!dev->CmdParamLeft) {
@@ -351,7 +354,9 @@ aha_cmds(void *p)
* and expects a 0x04 back in the INTR
* register. --FvK
*/
/* dev->Interrupt = aha154x_shram(dev,val); */
#if 0
dev->Interrupt = aha154x_shram(dev,val);
#endif
dev->Interrupt = aha154x_shram(dev, dev->CmdBuf[0]);
break;
@@ -451,9 +456,9 @@ aha_cmds(void *p)
}
static void
aha_setup_data(void *p)
aha_setup_data(void *priv)
{
x54x_t *dev = (x54x_t *) p;
x54x_t *dev = (x54x_t *) priv;
ReplyInquireSetupInformation *ReplyISI;
aha_setup_t *aha_setup;
@@ -486,9 +491,9 @@ aha_do_bios_mail(x54x_t *dev)
}
static void
aha_callback(void *p)
aha_callback(void *priv)
{
x54x_t *dev = (x54x_t *) p;
x54x_t *dev = (x54x_t *) priv;
if (dev->BIOSMailboxInit && dev->BIOSMailboxReq)
aha_do_bios_mail(dev);
@@ -551,6 +556,9 @@ aha_mca_write(int port, uint8_t val, void *priv)
case 0x10: /* [1]=xx01 0xxx */
dev->rom_addr = 0xC8000;
break;
default:
break;
}
else {
/* Disabled. */
@@ -696,6 +704,8 @@ aha_pnp_config_changed(uint8_t ld, isapnp_device_config_t *config, void *priv)
break;
#endif
default:
break;
}
}
@@ -997,6 +1007,9 @@ aha_init(const device_t *info)
case 0x0334:
dev->bios_path = "roms/scsi/adaptec/aha1540b320_334.bin";
break;
default:
break;
}
dev->fw_rev = "A005"; /* The 3.2 microcode says A012. */
/* This is configurable from the configuration for the 154xB, the rest of the controllers read it from the EEPROM. */
@@ -1082,6 +1095,9 @@ aha_init(const device_t *info)
mca_add(aha_mca_read, aha_mca_write, aha_mca_feedb, NULL, dev);
dev->ha_bps = 5000000.0; /* normal SCSI */
break;
default:
break;
}
/* Initialize ROM BIOS if needed. */
@@ -1106,7 +1122,7 @@ aha_init(const device_t *info)
}
}
return (dev);
return dev;
}
// clang-format off

187
src/scsi/scsi_buslogic.c
View File

@@ -53,20 +53,20 @@
* configuration parameters.
*/
#pragma pack(push, 1)
typedef struct {
uint8_t aInternalSignature[2];
uint8_t cbInformation;
uint8_t aHostAdaptertype[6];
uint8_t uReserved1;
uint8_t fFloppyEnabled : 1,
fFloppySecondary : 1,
fLevelSensitiveInterrupt : 1,
uReserved2 : 2,
uSystemRAMAreForBIOS : 3;
uint8_t uDMAChannel : 7,
fDMAAutoConfiguration : 1,
uIrqChannel : 7,
fIrqAutoConfiguration : 1;
typedef struct AutoSCSIRam_t {
uint8_t aInternalSignature[2];
uint8_t cbInformation;
uint8_t aHostAdaptertype[6];
uint8_t uReserved1;
uint8_t fFloppyEnabled : 1;
uint8_t fFloppySecondary : 1;
uint8_t fLevelSensitiveInterrupt : 1;
uint8_t uReserved2 : 2;
uint8_t uSystemRAMAreForBIOS : 3;
uint8_t uDMAChannel : 7;
uint8_t fDMAAutoConfiguration : 1;
uint8_t uIrqChannel : 7;
uint8_t fIrqAutoConfiguration : 1;
uint8_t uDMATransferRate;
uint8_t uSCSIId;
uint8_t uSCSIConfiguration;
@@ -142,46 +142,45 @@ typedef struct {
/* Structure for the INQUIRE_EXTENDED_SETUP_INFORMATION. */
#pragma pack(push, 1)
typedef struct {
typedef struct ReplyInquireExtendedSetupInformation_t {
uint8_t uBusType;
uint8_t uBiosAddress;
uint16_t u16ScatterGatherLimit;
uint8_t cMailbox;
uint32_t uMailboxAddressBase;
uint8_t uReserved1 : 2,
fFastEISA : 1,
uReserved2 : 3,
fLevelSensitiveInterrupt : 1,
uReserved3 : 1;
uint8_t uReserved1 : 2;
uint8_t fFastEISA : 1;
uint8_t uReserved2 : 3;
uint8_t fLevelSensitiveInterrupt : 1;
uint8_t uReserved3 : 1;
uint8_t aFirmwareRevision[3];
uint8_t fHostWideSCSI : 1,
fHostDifferentialSCSI : 1,
fHostSupportsSCAM : 1,
fHostUltraSCSI : 1,
fHostSmartTermination : 1,
uReserved4 : 3;
uint8_t fHostWideSCSI : 1;
uint8_t fHostDifferentialSCSI : 1;
uint8_t fHostSupportsSCAM : 1;
uint8_t fHostUltraSCSI : 1;
uint8_t fHostSmartTermination : 1;
uint8_t uReserved4 : 3;
} ReplyInquireExtendedSetupInformation;
#pragma pack(pop)
/* Structure for the INQUIRE_PCI_HOST_ADAPTER_INFORMATION reply. */
#pragma pack(push, 1)
typedef struct {
typedef struct BuslogicPCIInformation_t {
uint8_t IsaIOPort;
uint8_t IRQ;
uint8_t LowByteTerminated : 1,
HighByteTerminated : 1,
uReserved : 2, /* Reserved. */
JP1 : 1, /* Whatever that means. */
JP2 : 1, /* Whatever that means. */
JP3 : 1, /* Whatever that means. */
InformationIsValid : 1;
uint8_t uReserved2; /* Reserved. */
uint8_t LowByteTerminated : 1;
uint8_t HighByteTerminated : 1;
uint8_t uReserved : 2; /* Reserved. */
uint8_t JP1 : 1; /* Whatever that means. */
uint8_t JP2 : 1; /* Whatever that means. */
uint8_t JP3 : 1; /* Whatever that means. */
uint8_t InformationIsValid : 1;
uint8_t uReserved2; /* Reserved. */
} BuslogicPCIInformation_t;
#pragma pack(pop)
#pragma pack(push, 1)
typedef struct
{
typedef struct ESCMD_t {
/** Data length. */
uint32_t DataLength;
/** Data pointer. */
@@ -204,14 +203,14 @@ typedef struct
#pragma pack(pop)
#pragma pack(push, 1)
typedef struct {
typedef struct MailboxInitExtended_t {
uint8_t Count;
uint32_t Address;
} MailboxInitExtended_t;
#pragma pack(pop)
#pragma pack(push, 1)
typedef struct {
typedef struct buslogic_data_t {
rom_t bios;
int ExtendedLUNCCBFormat;
int fAggressiveRoundRobinMode;
@@ -220,11 +219,11 @@ typedef struct {
int MMIOBase;
int chip;
int has_bios;
uint32_t bios_addr,
bios_size,
bios_mask;
uint8_t AutoSCSIROM[32768];
uint8_t SCAMData[65536];
uint32_t bios_addr;
uint32_t bios_size;
uint32_t bios_mask;
uint8_t AutoSCSIROM[32768];
uint8_t SCAMData[65536];
} buslogic_data_t;
#pragma pack(pop)
@@ -325,6 +324,9 @@ BuslogicAutoSCSIRamSetDefaults(x54x_t *dev, uint8_t safe)
case CHIP_BUSLOGIC_PCI_958D_1995_12_30:
memcpy(&(HALR->structured.autoSCSIData.aHostAdaptertype[1]), "958D", 4);
break;
default:
break;
}
HALR->structured.autoSCSIData.fLevelSensitiveInterrupt = (bl->chip == CHIP_BUSLOGIC_PCI_958D_1995_12_30) ? 1 : 0;
@@ -410,14 +412,14 @@ BuslogicInitializeAutoSCSIRam(x54x_t *dev)
buslogic_data_t *bl = (buslogic_data_t *) dev->ven_data;
HALocalRAM *HALR = &bl->LocalRAM;
FILE *f;
FILE *fp;
f = nvr_fopen(BuslogicGetNVRFileName(bl), "rb");
if (f) {
if (fread(&(bl->LocalRAM.structured.autoSCSIData), 1, 64, f) != 64)
fp = nvr_fopen(BuslogicGetNVRFileName(bl), "rb");
if (fp) {
if (fread(&(bl->LocalRAM.structured.autoSCSIData), 1, 64, fp) != 64)
fatal("BuslogicInitializeAutoSCSIRam(): Error reading data\n");
fclose(f);
f = NULL;
fclose(fp);
fp = NULL;
if (bl->chip == CHIP_BUSLOGIC_PCI_958D_1995_12_30) {
x54x_io_remove(dev, dev->Base, 4);
switch (HALR->structured.autoSCSIData.uHostAdapterIoPortAddress) {
@@ -439,9 +441,9 @@ BuslogicInitializeAutoSCSIRam(x54x_t *dev)
}
static void
buslogic_cmd_phase1(void *p)
buslogic_cmd_phase1(void *priv)
{
x54x_t *dev = (x54x_t *) p;
x54x_t *dev = (x54x_t *) priv;
if ((dev->CmdParam == 2) && (dev->Command == 0x90)) {
dev->CmdParamLeft = dev->CmdBuf[1];
@@ -463,9 +465,9 @@ buslogic_cmd_phase1(void *p)
}
static uint8_t
buslogic_get_host_id(void *p)
buslogic_get_host_id(void *priv)
{
x54x_t *dev = (x54x_t *) p;
x54x_t *dev = (x54x_t *) priv;
buslogic_data_t *bl = (buslogic_data_t *) dev->ven_data;
HALocalRAM *HALR = &bl->LocalRAM;
@@ -477,9 +479,9 @@ buslogic_get_host_id(void *p)
}
static uint8_t
buslogic_get_irq(void *p)
buslogic_get_irq(void *priv)
{
x54x_t *dev = (x54x_t *) p;
x54x_t *dev = (x54x_t *) priv;
buslogic_data_t *bl = (buslogic_data_t *) dev->ven_data;
uint8_t bl_irq[7] = { 0, 9, 10, 11, 12, 14, 15 };
@@ -493,9 +495,9 @@ buslogic_get_irq(void *p)
}
static uint8_t
buslogic_get_dma(void *p)
buslogic_get_dma(void *priv)
{
x54x_t *dev = (x54x_t *) p;
x54x_t *dev = (x54x_t *) priv;
buslogic_data_t *bl = (buslogic_data_t *) dev->ven_data;
uint8_t bl_dma[4] = { 0, 5, 6, 7 };
@@ -511,9 +513,9 @@ buslogic_get_dma(void *p)
}
static uint8_t
buslogic_param_len(void *p)
buslogic_param_len(void *priv)
{
x54x_t *dev = (x54x_t *) p;
x54x_t *dev = (x54x_t *) priv;
buslogic_data_t *bl = (buslogic_data_t *) dev->ven_data;
switch (dev->Command) {
@@ -577,10 +579,10 @@ BuslogicSCSIBIOSDMATransfer(x54x_t *dev, ESCMD *ESCSICmd, uint8_t TargetID, int
if (dir && ((ESCSICmd->DataDirection == CCB_DATA_XFER_OUT) || (ESCSICmd->DataDirection == 0x00))) {
buslogic_log("BusLogic BIOS DMA: Reading %i bytes from %08X\n", TransferLength, Address);
dma_bm_read(Address, (uint8_t *) sd->sc->temp_buffer, TransferLength, transfer_size);
dma_bm_read(Address, sd->sc->temp_buffer, TransferLength, transfer_size);
} else if (!dir && ((ESCSICmd->DataDirection == CCB_DATA_XFER_IN) || (ESCSICmd->DataDirection == 0x00))) {
buslogic_log("BusLogic BIOS DMA: Writing %i bytes at %08X\n", TransferLength, Address);
dma_bm_write(Address, (uint8_t *) sd->sc->temp_buffer, TransferLength, transfer_size);
dma_bm_write(Address, sd->sc->temp_buffer, TransferLength, transfer_size);
}
}
}
@@ -666,9 +668,9 @@ BuslogicSCSIBIOSRequestSetup(x54x_t *dev, uint8_t *CmdBuf, uint8_t *DataInBuf, u
}
static uint8_t
buslogic_cmds(void *p)
buslogic_cmds(void *priv)
{
x54x_t *dev = (x54x_t *) p;
x54x_t *dev = (x54x_t *) priv;
buslogic_data_t *bl = (buslogic_data_t *) dev->ven_data;
HALocalRAM *HALR = &bl->LocalRAM;
@@ -827,6 +829,9 @@ buslogic_cmds(void *p)
case CHIP_BUSLOGIC_PCI_958D_1995_12_30:
ReplyIESI->uBusType = 'E'; /* PCI style */
break;
default:
break;
}
ReplyIESI->uBiosAddress = 0xd8;
ReplyIESI->u16ScatterGatherLimit = 8192;
@@ -1012,9 +1017,9 @@ buslogic_cmds(void *p)
}
static void
buslogic_setup_data(void *p)
buslogic_setup_data(void *priv)
{
x54x_t *dev = (x54x_t *) p;
x54x_t *dev = (x54x_t *) priv;
ReplyInquireSetupInformation *ReplyISI;
buslogic_setup_t *bl_setup;
buslogic_data_t *bl = (buslogic_data_t *) dev->ven_data;
@@ -1048,13 +1053,16 @@ buslogic_setup_data(void *p)
case CHIP_BUSLOGIC_PCI_958D_1995_12_30:
bl_setup->uHostBusType = 'F';
break;
default:
break;
}
}
static uint8_t
buslogic_is_aggressive_mode(void *p)
buslogic_is_aggressive_mode(void *priv)
{
x54x_t *dev = (x54x_t *) p;
x54x_t *dev = (x54x_t *) priv;
buslogic_data_t *bl = (buslogic_data_t *) dev->ven_data;
buslogic_log("Buslogic: Aggressive mode = %d\n", bl->fAggressiveRoundRobinMode);
@@ -1063,9 +1071,9 @@ buslogic_is_aggressive_mode(void *p)
}
static uint8_t
buslogic_interrupt_type(void *p)
buslogic_interrupt_type(void *priv)
{
x54x_t *dev = (x54x_t *) p;
x54x_t *dev = (x54x_t *) priv;
buslogic_data_t *bl = (buslogic_data_t *) dev->ven_data;
if ((bl->chip == CHIP_BUSLOGIC_ISA_542B_1991_12_14) || (bl->chip == CHIP_BUSLOGIC_ISA_545S_1992_10_05) || (bl->chip == CHIP_BUSLOGIC_ISA_542BH_1993_05_23) || (bl->chip == CHIP_BUSLOGIC_VLB_445S_1993_11_16) || (bl->chip == CHIP_BUSLOGIC_MCA_640A_1993_05_23))
@@ -1075,9 +1083,9 @@ buslogic_interrupt_type(void *p)
}
static void
buslogic_reset(void *p)
buslogic_reset(void *priv)
{
x54x_t *dev = (x54x_t *) p;
x54x_t *dev = (x54x_t *) priv;
buslogic_data_t *bl = (buslogic_data_t *) dev->ven_data;
bl->ExtendedLUNCCBFormat = 0;
@@ -1108,9 +1116,9 @@ BuslogicBIOSUpdate(buslogic_data_t *bl)
}
static uint8_t
BuslogicPCIRead(int func, int addr, void *p)
BuslogicPCIRead(UNUSED(int func), int addr, void *priv)
{
x54x_t *dev = (x54x_t *) p;
x54x_t *dev = (x54x_t *) priv;
#ifdef ENABLE_BUSLOGIC_LOG
buslogic_data_t *bl = (buslogic_data_t *) dev->ven_data;
#endif
@@ -1175,28 +1183,28 @@ BuslogicPCIRead(int func, int addr, void *p)
case 0x31: /* PCI_ROMBAR 15:11 */
buslogic_log("BT-958D: BIOS BAR 01 = %02X\n", (buslogic_pci_bar[2].addr_regs[1] & bl->bios_mask));
return buslogic_pci_bar[2].addr_regs[1];
break;
case 0x32: /* PCI_ROMBAR 23:16 */
buslogic_log("BT-958D: BIOS BAR 02 = %02X\n", buslogic_pci_bar[2].addr_regs[2]);
return buslogic_pci_bar[2].addr_regs[2];
break;
case 0x33: /* PCI_ROMBAR 31:24 */
buslogic_log("BT-958D: BIOS BAR 03 = %02X\n", buslogic_pci_bar[2].addr_regs[3]);
return buslogic_pci_bar[2].addr_regs[3];
break;
case 0x3C:
return dev->Irq;
case 0x3D:
return PCI_INTA;
default:
break;
}
return 0;
}
static void
BuslogicPCIWrite(int func, int addr, uint8_t val, void *p)
BuslogicPCIWrite(UNUSED(int func), int addr, uint8_t val, void *priv)
{
x54x_t *dev = (x54x_t *) p;
x54x_t *dev = (x54x_t *) priv;
buslogic_data_t *bl = (buslogic_data_t *) dev->ven_data;
uint8_t valxor;
@@ -1224,7 +1232,7 @@ BuslogicPCIWrite(int func, int addr, uint8_t val, void *p)
case 0x10:
val &= 0xe0;
val |= 1;
/*FALLTHROUGH*/
[[fallthrough]];
case 0x11:
case 0x12:
@@ -1248,7 +1256,7 @@ BuslogicPCIWrite(int func, int addr, uint8_t val, void *p)
case 0x14:
val &= 0xe0;
/*FALLTHROUGH*/
[[fallthrough]];
case 0x15:
case 0x16:
@@ -1259,7 +1267,9 @@ BuslogicPCIWrite(int func, int addr, uint8_t val, void *p)
/* Then let's set the PCI regs. */
buslogic_pci_bar[1].addr_regs[addr & 3] = val;
/* Then let's calculate the new I/O base. */
// bl->MMIOBase = buslogic_pci_bar[1].addr & 0xffffffe0;
#if 0
bl->MMIOBase = buslogic_pci_bar[1].addr & 0xffffffe0;
#endif
/* Give it a 4 kB alignment as that's this emulator's granularity. */
buslogic_pci_bar[1].addr &= 0xffffc000;
bl->MMIOBase = buslogic_pci_bar[1].addr & 0xffffc000;
@@ -1292,6 +1302,9 @@ BuslogicPCIWrite(int func, int addr, uint8_t val, void *p)
} else
dev->Irq = 0;
return;
default:
break;
}
}
@@ -1386,6 +1399,9 @@ buslogic_mca_write(int port, uint8_t val, void *priv)
case 0x20: /* [0]=001x xxxx */
bl->bios_addr = 0xC4000;
break;
default:
break;
}
else {
/* Disabled. */
@@ -1497,9 +1513,9 @@ buslogic_mca_feedb(void *priv)
}
void
BuslogicDeviceReset(void *p)
BuslogicDeviceReset(void *priv)
{
x54x_t *dev = (x54x_t *) p;
x54x_t *dev = (x54x_t *) priv;
buslogic_data_t *bl = (buslogic_data_t *) dev->ven_data;
x54x_device_reset(dev);
@@ -1684,6 +1700,9 @@ buslogic_init(const device_t *info)
dev->ha_bps = 20000000.0; /* ultra SCSI */
dev->max_id = 15; /* wide SCSI */
break;
default:
break;
}
if ((dev->Base != 0) && !(dev->card_bus & DEVICE_MCA) && !(dev->card_bus & DEVICE_PCI)) {

59
src/scsi/scsi_cdrom.c
View File

@@ -42,8 +42,7 @@
#include <86box/version.h>
#pragma pack(push, 1)
typedef struct
{
typedef struct gesn_cdb_t {
uint8_t opcode;
uint8_t polled;
uint8_t reserved2[2];
@@ -53,8 +52,7 @@ typedef struct
uint8_t control;
} gesn_cdb_t;
typedef struct
{
typedef struct gesn_event_header_t {
uint16_t len;
uint8_t notification_class;
uint8_t supported_events;
@@ -565,6 +563,9 @@ scsi_cdrom_atapi_phase_to_scsi(scsi_cdrom_t *dev)
return 1;
case 3:
return 7;
default:
break;
}
} else {
if ((dev->phase & 3) == 3)
@@ -577,9 +578,9 @@ scsi_cdrom_atapi_phase_to_scsi(scsi_cdrom_t *dev)
}
static uint32_t
scsi_cdrom_get_channel(void *p, int channel)
scsi_cdrom_get_channel(void *priv, int channel)
{
scsi_cdrom_t *dev = (scsi_cdrom_t *) p;
scsi_cdrom_t *dev = (scsi_cdrom_t *) priv;
if (!dev)
return channel + 1;
@@ -591,9 +592,9 @@ scsi_cdrom_get_channel(void *p, int channel)
}
static uint32_t
scsi_cdrom_get_volume(void *p, int channel)
scsi_cdrom_get_volume(void *priv, int channel)
{
scsi_cdrom_t *dev = (scsi_cdrom_t *) p;
scsi_cdrom_t *dev = (scsi_cdrom_t *) priv;
if (!dev)
return 255;
@@ -682,7 +683,7 @@ scsi_cdrom_drive_status_load(scsi_cdrom_t *dev)
}
static uint8_t
scsi_cdrom_drive_status_read(scsi_cdrom_t *dev, uint8_t page_control, uint8_t page, uint8_t pos)
scsi_cdrom_drive_status_read(scsi_cdrom_t *dev, UNUSED(uint8_t page_control), uint8_t page, uint8_t pos)
{
return dev->ms_drive_status_pages_saved.pages[page][pos];
}
@@ -735,12 +736,12 @@ scsi_cdrom_mode_sense_read(scsi_cdrom_t *dev, uint8_t page_control, uint8_t page
case 0:
case 3:
return dev->ms_pages_saved_sony.pages[page][pos];
break;
case 1:
return scsi_cdrom_mode_sense_pages_changeable_sony.pages[page][pos];
break;
case 2:
return scsi_cdrom_mode_sense_pages_default_sony_scsi.pages[page][pos];
default:
break;
}
} else {
@@ -748,16 +749,17 @@ scsi_cdrom_mode_sense_read(scsi_cdrom_t *dev, uint8_t page_control, uint8_t page
case 0:
case 3:
return dev->ms_pages_saved.pages[page][pos];
break;
case 1:
return scsi_cdrom_mode_sense_pages_changeable.pages[page][pos];
break;
case 2:
if (dev->drv->bus_type == CDROM_BUS_SCSI)
return scsi_cdrom_mode_sense_pages_default_scsi.pages[page][pos];
else
return scsi_cdrom_mode_sense_pages_default.pages[page][pos];
default:
break;
}
}
@@ -881,7 +883,7 @@ scsi_cdrom_update_request_length(scsi_cdrom_t *dev, int len, int block_len)
break;
}
}
/* FALLTHROUGH */
[[fallthrough]];
default:
dev->packet_len = len;
@@ -957,7 +959,7 @@ scsi_cdrom_command_common(scsi_cdrom_t *dev)
scsi_cdrom_log("CD-ROM %i: Seek period: %" PRIu64 " us\n",
dev->id, (uint64_t) period);
dev->callback += period;
/*FALLTHROUGH*/
[[fallthrough]];
case 0x25:
case 0x42:
case 0x43:
@@ -1116,7 +1118,7 @@ scsi_cdrom_data_command_finish(scsi_cdrom_t *dev, int len, int block_len, int al
}
static void
scsi_cdrom_sense_clear(scsi_cdrom_t *dev, int command)
scsi_cdrom_sense_clear(scsi_cdrom_t *dev, UNUSED(int command))
{
scsi_cdrom_sense_key = scsi_cdrom_asc = scsi_cdrom_ascq = 0;
}
@@ -1495,9 +1497,9 @@ scsi_cdrom_read_dvd_structure(scsi_cdrom_t *dev, int format, const uint8_t *pack
}
static void
scsi_cdrom_insert(void *p)
scsi_cdrom_insert(void *priv)
{
scsi_cdrom_t *dev = (scsi_cdrom_t *) p;
scsi_cdrom_t *dev = (scsi_cdrom_t *) priv;
if (!dev)
return;
@@ -1934,7 +1936,7 @@ begin:
/* IMPORTANT: Convert the command to new read CD
for pass through purposes. */
dev->current_cdb[0] = GPCMD_READ_CD;
/*FALLTHROUGH*/
[[fallthrough]];
case GPCMD_READ_6:
case GPCMD_READ_10:
@@ -2012,6 +2014,9 @@ begin:
return;
}
break;
default:
break;
}
if (!dev->sector_len) {
@@ -2549,6 +2554,9 @@ begin:
pos = (cdb[2] << 24) | (cdb[3] << 16) | (cdb[4] << 8) | cdb[5];
len = (cdb[6] << 24) | (cdb[7] << 16) | (cdb[8] << 8) | cdb[9];
break;
default:
break;
}
if ((dev->drv->host_drive < 1) || (dev->drv->cd_status <= CD_STATUS_DATA_ONLY)) {
@@ -2767,6 +2775,9 @@ begin:
case 3: /* Load the disc (close tray). */
cdrom_reload(dev->id);
break;
default:
break;
}
scsi_cdrom_command_complete(dev);
@@ -3105,6 +3116,9 @@ atapi_out:
case GPCMD_SEEK_10:
pos = (cdb[2] << 24) | (cdb[3] << 16) | (cdb[4] << 8) | cdb[5];
break;
default:
break;
}
dev->drv->seek_diff = ABS((int) (pos - dev->drv->seek_pos));
if (cdb[0] == GPCMD_SEEK_10) {
@@ -3439,6 +3453,9 @@ scsi_cdrom_phase_data_out(scsi_common_t *sc)
}
}
break;
default:
break;
}
scsi_cdrom_command_stop((scsi_common_t *) dev);
@@ -3446,9 +3463,9 @@ scsi_cdrom_phase_data_out(scsi_common_t *sc)
}
static void
scsi_cdrom_close(void *p)
scsi_cdrom_close(void *priv)
{
scsi_cdrom_t *dev = (scsi_cdrom_t *) p;
scsi_cdrom_t *dev = (scsi_cdrom_t *) priv;
if (dev)
free(dev);

3
src/scsi/scsi_device.c
View File

@@ -25,6 +25,7 @@
#include <86box/hdd.h>
#include <86box/scsi.h>
#include <86box/scsi_device.h>
#include <86box/plat_unused.h>
scsi_device_t scsi_devices[SCSI_BUS_MAX][SCSI_ID_MAX];
@@ -97,7 +98,7 @@ scsi_device_valid(scsi_device_t *dev)
}
int
scsi_device_cdb_length(scsi_device_t *dev)
scsi_device_cdb_length(UNUSED(scsi_device_t *dev))
{
/* Right now, it's 12 for all devices. */
return 12;

68
src/scsi/scsi_disk.c
View File

@@ -182,9 +182,9 @@ scsi_disk_mode_sense_read(scsi_disk_t *dev, uint8_t page_control, uint8_t page,
case 2:
case 3:
switch (pos) {
default:
case 0:
case 1:
default:
return scsi_disk_mode_sense_pages_default.pages[page][pos];
case 2:
case 6:
@@ -201,6 +201,8 @@ scsi_disk_mode_sense_read(scsi_disk_t *dev, uint8_t page_control, uint8_t page,
case 5:
return dev->drv->hpc & 0xff;
}
default:
break;
}
else if (page == GPMODE_FORMAT_DEVICE_PAGE)
@@ -210,9 +212,9 @@ scsi_disk_mode_sense_read(scsi_disk_t *dev, uint8_t page_control, uint8_t page,
case 2:
case 3:
switch (pos) {
default:
case 0:
case 1:
default:
return scsi_disk_mode_sense_pages_default.pages[page][pos];
/* Actual sectors + the 1 "alternate sector" we report. */
case 10:
@@ -220,6 +222,8 @@ scsi_disk_mode_sense_read(scsi_disk_t *dev, uint8_t page_control, uint8_t page,
case 11:
return (dev->drv->spt + 1) & 0xff;
}
default:
break;
}
else
@@ -229,6 +233,9 @@ scsi_disk_mode_sense_read(scsi_disk_t *dev, uint8_t page_control, uint8_t page,
return dev->ms_pages_saved.pages[page][pos];
case 2:
return scsi_disk_mode_sense_pages_default.pages[page][pos];
default:
break;
}
return 0;
@@ -306,7 +313,7 @@ scsi_disk_command_write_dma(scsi_disk_t *dev)
}
static void
scsi_disk_data_command_finish(scsi_disk_t *dev, int len, int block_len, int alloc_len, int direction)
scsi_disk_data_command_finish(scsi_disk_t *dev, int len, UNUSED(int block_len), int alloc_len, int direction)
{
scsi_disk_log("SCSI HD %i: Finishing command (%02X): %i, %i, %i, %i, %i\n", dev->id,
dev->current_cdb[0], len, block_len, alloc_len, direction, dev->request_length);
@@ -325,7 +332,7 @@ scsi_disk_data_command_finish(scsi_disk_t *dev, int len, int block_len, int allo
}
static void
scsi_disk_sense_clear(scsi_disk_t *dev, int command)
scsi_disk_sense_clear(scsi_disk_t *dev, UNUSED(int command))
{
scsi_disk_sense_key = scsi_disk_asc = scsi_disk_ascq = 0;
}
@@ -500,7 +507,7 @@ scsi_disk_request_sense_for_scsi(scsi_common_t *sc, uint8_t *buffer, uint8_t all
}
static void
scsi_disk_set_buf_len(scsi_disk_t *dev, int32_t *BufLen, int32_t *src_len)
scsi_disk_set_buf_len(UNUSED(scsi_disk_t *dev), int32_t *BufLen, int32_t *src_len)
{
if (*BufLen == -1)
*BufLen = *src_len;
@@ -590,7 +597,7 @@ scsi_disk_command(scsi_common_t *sc, uint8_t *cdb)
scsi_disk_invalid_field(dev);
return;
}
/*FALLTHROUGH*/
[[fallthrough]];
case GPCMD_SCSI_RESERVE:
case GPCMD_SCSI_RELEASE:
case GPCMD_TEST_UNIT_READY:
@@ -661,6 +668,9 @@ scsi_disk_command(scsi_common_t *sc, uint8_t *cdb)
dev->sector_len = (((uint32_t) cdb[6]) << 24) | (((uint32_t) cdb[7]) << 16) | (((uint32_t) cdb[8]) << 8) | ((uint32_t) cdb[9]);
dev->sector_pos = (((uint32_t) cdb[2]) << 24) | (((uint32_t) cdb[3]) << 16) | (((uint32_t) cdb[4]) << 8) | ((uint32_t) cdb[5]);
break;
default:
break;
}
if ((dev->sector_pos > last_sector) /* || ((dev->sector_pos + dev->sector_len - 1) > last_sector)*/) {
@@ -737,6 +747,9 @@ scsi_disk_command(scsi_common_t *sc, uint8_t *cdb)
dev->sector_len = (((uint32_t) cdb[6]) << 24) | (((uint32_t) cdb[7]) << 16) | (((uint32_t) cdb[8]) << 8) | ((uint32_t) cdb[9]);
dev->sector_pos = (((uint32_t) cdb[2]) << 24) | (((uint32_t) cdb[3]) << 16) | (((uint32_t) cdb[4]) << 8) | ((uint32_t) cdb[5]);
break;
default:
break;
}
if ((dev->sector_pos > last_sector) /* ||
@@ -1001,6 +1014,9 @@ atapi_out:
case GPCMD_SEEK_10:
pos = (cdb[2] << 24) | (cdb[3] << 16) | (cdb[4] << 8) | cdb[5];
break;
default:
break;
}
scsi_disk_seek(dev, pos);
@@ -1046,26 +1062,26 @@ scsi_disk_command_stop(scsi_common_t *sc)
static uint8_t
scsi_disk_phase_data_out(scsi_common_t *sc)
{
scsi_disk_t *dev = (scsi_disk_t *) sc;
uint8_t scsi_bus = (dev->drv->scsi_id >> 4) & 0x0f;
uint8_t scsi_id = dev->drv->scsi_id & 0x0f;
int i;
int32_t *BufLen = &scsi_devices[scsi_bus][scsi_id].buffer_length;
uint32_t last_sector = hdd_image_get_last_sector(dev->id);
uint32_t c;
uint32_t h;
uint32_t s;
uint32_t last_to_write = 0;
uint16_t block_desc_len;
uint16_t pos;
uint16_t param_list_len;
uint8_t hdr_len;
uint8_t val;
uint8_t old_val;
uint8_t ch;
uint8_t error = 0;
uint8_t page;
uint8_t page_len;
scsi_disk_t *dev = (scsi_disk_t *) sc;
uint8_t scsi_bus = (dev->drv->scsi_id >> 4) & 0x0f;
uint8_t scsi_id = dev->drv->scsi_id & 0x0f;
int i;
const int32_t *BufLen = &scsi_devices[scsi_bus][scsi_id].buffer_length;
uint32_t last_sector = hdd_image_get_last_sector(dev->id);
uint32_t c;
uint32_t h;
uint32_t s;
uint32_t last_to_write = 0;
uint16_t block_desc_len;
uint16_t pos;
uint16_t param_list_len;
uint8_t hdr_len;
uint8_t val;
uint8_t old_val;
uint8_t ch;
uint8_t error = 0;
uint8_t page;
uint8_t page_len;
if (!*BufLen) {
scsi_disk_set_phase(dev, SCSI_PHASE_STATUS);

72
src/scsi/scsi_ncr5380.c
View File

@@ -93,9 +93,15 @@
#define STATUS_BUFFER_NOT_READY 0x04
#define STATUS_53C80_ACCESSIBLE 0x80
typedef struct {
uint8_t icr, mode, tcr, data_wait;
uint8_t isr, output_data, target_id, tx_data;
typedef struct ncr_t {
uint8_t icr;
uint8_t mode;
uint8_t tcr;
uint8_t data_wait;
uint8_t isr;
uint8_t output_data;
uint8_t target_id;
uint8_t tx_data;
uint8_t msglun;
uint8_t command[20];
@@ -103,12 +109,19 @@ typedef struct {
int msgout_pos;
int is_msgout;
int dma_mode, cur_bus, bus_in, new_phase;
int state, clear_req, wait_data, wait_complete;
int command_pos, data_pos;
int dma_mode;
int cur_bus;
int bus_in;
int new_phase;
int state;
int clear_req;
int wait_data;
int wait_complete;
int command_pos;
int data_pos;
} ncr_t;
typedef struct {
typedef struct t128_t {
uint8_t ctrl;
uint8_t status;
uint8_t buffer[512];
@@ -121,14 +134,15 @@ typedef struct {
int bios_enabled;
} t128_t;
typedef struct {
typedef struct ncr5380_t {
ncr_t ncr;
t128_t t128;
const char *name;
uint8_t buffer[128];
uint8_t int_ram[0x40], ext_ram[0x600];
uint8_t int_ram[0x40];
uint8_t ext_ram[0x600];
uint32_t rom_addr;
uint16_t base;
@@ -440,7 +454,9 @@ ncr_bus_update(void *priv, int bus)
if (ncr->command_pos == cmd_len[(ncr->command[0] >> 5) & 7]) {
if (ncr->is_msgout) {
ncr->is_msgout = 0;
// ncr->command[1] = (ncr->command[1] & 0x1f) | (ncr->msglun << 5);
#if 0
ncr->command[1] = (ncr->command[1] & 0x1f) | (ncr->msglun << 5);
#endif
}
/*Reset data position to default*/
@@ -565,6 +581,9 @@ ncr_bus_update(void *priv, int bus)
SET_BUS_STATE(ncr, SCSI_PHASE_COMMAND);
}
break;
default:
break;
}
ncr->bus_in = bus;
@@ -823,7 +842,7 @@ ncr_read(uint16_t port, void *priv)
ncr_log("NCR5380 read(%04x)=%02x\n", port & 7, ret);
return (ret);
return ret;
}
/* Memory-mapped I/O READ handler. */
@@ -899,8 +918,14 @@ memio_read(uint32_t addr, void *priv)
case 0x3983:
ret = 0xff;
break;
default:
break;
}
break;
default:
break;
}
#if ENABLE_NCR5380_LOG
@@ -976,8 +1001,14 @@ memio_write(uint32_t addr, uint8_t val, void *priv)
ncr_dev->status_ctrl &= ~STATUS_BUFFER_NOT_READY;
}
break;
default:
break;
}
break;
default:
break;
}
}
@@ -995,7 +1026,7 @@ t130b_read(uint32_t addr, void *priv)
ret = ncr_dev->ext_ram[addr & 0x7f];
ncr_log("MEM: Reading %02X from %08X\n", ret, addr);
return (ret);
return ret;
}
/* Memory-mapped I/O WRITE handler for the Trantor T130B. */
@@ -1039,10 +1070,13 @@ t130b_in(uint16_t port, void *priv)
case 0x0f:
ret = ncr_read(port, ncr_dev);
break;
default:
break;
}
ncr_log("I/O: Reading %02X from %04X\n", ret, port);
return (ret);
return ret;
}
static void
@@ -1075,6 +1109,9 @@ t130b_out(uint16_t port, uint8_t val, void *priv)
case 0x0f:
ncr_write(port, val, ncr_dev);
break;
default:
break;
}
}
@@ -1325,6 +1362,9 @@ ncr_callback(void *priv)
}
ncr_dma_initiator_receive(ncr_dev, ncr, dev);
break;
default:
break;
}
ncr_bus_read(ncr_dev);
@@ -1457,6 +1497,9 @@ rt1000b_mc_write(int port, uint8_t val, void *priv)
case 0xe0:
ncr_dev->rom_addr = 0xd8000;
break;
default:
break;
}
mem_mapping_set_addr(&ncr_dev->bios_rom.mapping, ncr_dev->rom_addr, 0x4000);
@@ -1577,6 +1620,9 @@ ncr_init(const device_t *info)
memio_write, NULL, NULL,
ncr_dev->bios_rom.rom, MEM_MAPPING_EXTERNAL, ncr_dev);
break;
default:
break;
}
sprintf(temp, "%s: BIOS=%05X", ncr_dev->name, ncr_dev->rom_addr);

152
src/scsi/scsi_ncr53c8xx.c
View File

@@ -204,7 +204,7 @@ typedef enum {
SCSI_STATE_WRITE_MESSAGE
} scsi_state_t;
typedef struct {
typedef struct ncr53c8xx_t {
char *nvr_path;
uint8_t pci_slot;
uint8_t chip, wide;
@@ -291,9 +291,16 @@ typedef struct {
uint32_t dbc;
uint32_t dsp;
uint32_t dsps;
uint32_t scratcha, scratchb, scratchc, scratchd;
uint32_t scratche, scratchf, scratchg, scratchh;
uint32_t scratchi, scratchj;
uint32_t scratcha;
uint32_t scratchb;
uint32_t scratchc;
uint32_t scratchd;
uint32_t scratche;
uint32_t scratchf;
uint32_t scratchg;
uint32_t scratchh;
uint32_t scratchi;
uint32_t scratchj;
int last_level;
void *hba_private;
uint32_t buffer_pos;
@@ -479,7 +486,7 @@ ncr53c8xx_write(ncr53c8xx_t *dev, uint32_t addr, uint8_t *buf, uint32_t len)
}
static __inline uint32_t
read_dword(ncr53c8xx_t *dev, uint32_t addr)
read_dword(UNUSED(ncr53c8xx_t *dev), uint32_t addr)
{
uint32_t buf;
ncr53c8xx_log("Reading the next DWORD from memory (%08X)...\n", addr);
@@ -578,7 +585,7 @@ ncr53c8xx_set_phase(ncr53c8xx_t *dev, int phase)
}
static void
ncr53c8xx_bad_phase(ncr53c8xx_t *dev, int out, int new_phase)
ncr53c8xx_bad_phase(ncr53c8xx_t *dev, UNUSED(int out), int new_phase)
{
/* Trigger a phase mismatch. */
ncr53c8xx_log("Phase mismatch interrupt\n");
@@ -603,7 +610,7 @@ ncr53c8xx_disconnect(ncr53c8xx_t *dev)
}
static void
ncr53c8xx_bad_selection(ncr53c8xx_t *dev, uint32_t id)
ncr53c8xx_bad_selection(ncr53c8xx_t *dev, UNUSED(uint32_t id))
{
ncr53c8xx_log("Selected absent target %d\n", id);
ncr53c8xx_script_scsi_interrupt(dev, 0, NCR_SIST1_STO);
@@ -863,7 +870,7 @@ ncr53c8xx_skip_msgbytes(ncr53c8xx_t *dev, unsigned int n)
}
static void
ncr53c8xx_bad_message(ncr53c8xx_t *dev, uint8_t msg)
ncr53c8xx_bad_message(ncr53c8xx_t *dev, UNUSED(uint8_t msg))
{
ncr53c8xx_log("Unimplemented message 0x%02x\n", msg);
ncr53c8xx_set_phase(dev, PHASE_MI);
@@ -1191,6 +1198,9 @@ again:
if (insn & (1 << 10))
dev->carry = 0;
break;
default:
break;
}
} else {
reg = ((insn >> 16) & 0x7f) | (insn & 0x80);
@@ -1216,6 +1226,9 @@ again:
else
op1 = data8;
break;
default:
break;
}
switch (operator) {
@@ -1252,6 +1265,9 @@ again:
else
dev->carry = op0 < op1;
break;
default:
break;
}
switch (opcode) {
@@ -1262,6 +1278,9 @@ again:
case 6: /* To SFBR */
dev->sfbr = op0;
break;
default:
break;
}
}
break;
@@ -1403,9 +1422,9 @@ ncr53c8xx_execute_script(ncr53c8xx_t *dev)
}
static void
ncr53c8xx_callback(void *p)
ncr53c8xx_callback(void *priv)
{
ncr53c8xx_t *dev = (ncr53c8xx_t *) p;
ncr53c8xx_t *dev = (ncr53c8xx_t *) priv;
if (!dev->sstop) {
if (dev->waiting)
@@ -1559,7 +1578,9 @@ ncr53c8xx_reg_writeb(ncr53c8xx_t *dev, uint32_t offset, uint8_t val)
ncr53c8xx_log("Woken by SIGP\n");
dev->waiting = 0;
dev->dsp = dev->dnad;
/* ncr53c8xx_execute_script(dev); */
#if 0
ncr53c8xx_execute_script(dev);
#endif
}
if ((val & NCR_ISTAT_SRST) && !(tmp & NCR_ISTAT_SRST)) {
ncr53c8xx_soft_reset(dev);
@@ -1978,6 +1999,9 @@ ncr53c8xx_reg_readb(ncr53c8xx_t *dev, uint32_t offset)
CASE_GET_REG32_COND(scratchh, 0x74)
CASE_GET_REG32_COND(scratchi, 0x78)
CASE_GET_REG32_COND(scratchj, 0x7c)
default:
break;
}
ncr53c8xx_log("readb 0x%x\n", offset);
return 0;
@@ -1987,16 +2011,17 @@ ncr53c8xx_reg_readb(ncr53c8xx_t *dev, uint32_t offset)
}
static uint8_t
ncr53c8xx_io_readb(uint16_t addr, void *p)
ncr53c8xx_io_readb(uint16_t addr, void *priv)
{
ncr53c8xx_t *dev = (ncr53c8xx_t *) p;
ncr53c8xx_t *dev = (ncr53c8xx_t *) priv;
return ncr53c8xx_reg_readb(dev, addr & 0xff);
}
static uint16_t
ncr53c8xx_io_readw(uint16_t addr, void *p)
ncr53c8xx_io_readw(uint16_t addr, void *priv)
{
ncr53c8xx_t *dev = (ncr53c8xx_t *) p;
ncr53c8xx_t *dev = (ncr53c8xx_t *) priv;
uint16_t val;
addr &= 0xff;
@@ -2006,9 +2031,9 @@ ncr53c8xx_io_readw(uint16_t addr, void *p)
}
static uint32_t
ncr53c8xx_io_readl(uint16_t addr, void *p)
ncr53c8xx_io_readl(uint16_t addr, void *priv)
{
ncr53c8xx_t *dev = (ncr53c8xx_t *) p;
ncr53c8xx_t *dev = (ncr53c8xx_t *) priv;
uint32_t val;
addr &= 0xff;
@@ -2020,25 +2045,28 @@ ncr53c8xx_io_readl(uint16_t addr, void *p)
}
static void
ncr53c8xx_io_writeb(uint16_t addr, uint8_t val, void *p)
ncr53c8xx_io_writeb(uint16_t addr, uint8_t val, void *priv)
{
ncr53c8xx_t *dev = (ncr53c8xx_t *) p;
ncr53c8xx_t *dev = (ncr53c8xx_t *) priv;
ncr53c8xx_reg_writeb(dev, addr & 0xff, val);
}
static void
ncr53c8xx_io_writew(uint16_t addr, uint16_t val, void *p)
ncr53c8xx_io_writew(uint16_t addr, uint16_t val, void *priv)
{
ncr53c8xx_t *dev = (ncr53c8xx_t *) p;
ncr53c8xx_t *dev = (ncr53c8xx_t *) priv;
addr &= 0xff;
ncr53c8xx_reg_writeb(dev, addr, val & 0xff);
ncr53c8xx_reg_writeb(dev, addr + 1, (val >> 8) & 0xff);
}
static void
ncr53c8xx_io_writel(uint16_t addr, uint32_t val, void *p)
ncr53c8xx_io_writel(uint16_t addr, uint32_t val, void *priv)
{
ncr53c8xx_t *dev = (ncr53c8xx_t *) p;
ncr53c8xx_t *dev = (ncr53c8xx_t *) priv;
addr &= 0xff;
ncr53c8xx_reg_writeb(dev, addr, val & 0xff);
ncr53c8xx_reg_writeb(dev, addr + 1, (val >> 8) & 0xff);
@@ -2047,17 +2075,17 @@ ncr53c8xx_io_writel(uint16_t addr, uint32_t val, void *p)
}
static void
ncr53c8xx_mmio_writeb(uint32_t addr, uint8_t val, void *p)
ncr53c8xx_mmio_writeb(uint32_t addr, uint8_t val, void *priv)
{
ncr53c8xx_t *dev = (ncr53c8xx_t *) p;
ncr53c8xx_t *dev = (ncr53c8xx_t *) priv;
ncr53c8xx_reg_writeb(dev, addr & 0xff, val);
}
static void
ncr53c8xx_mmio_writew(uint32_t addr, uint16_t val, void *p)
ncr53c8xx_mmio_writew(uint32_t addr, uint16_t val, void *priv)
{
ncr53c8xx_t *dev = (ncr53c8xx_t *) p;
ncr53c8xx_t *dev = (ncr53c8xx_t *) priv;
addr &= 0xff;
ncr53c8xx_reg_writeb(dev, addr, val & 0xff);
@@ -2065,9 +2093,9 @@ ncr53c8xx_mmio_writew(uint32_t addr, uint16_t val, void *p)
}
static void
ncr53c8xx_mmio_writel(uint32_t addr, uint32_t val, void *p)
ncr53c8xx_mmio_writel(uint32_t addr, uint32_t val, void *priv)
{
ncr53c8xx_t *dev = (ncr53c8xx_t *) p;
ncr53c8xx_t *dev = (ncr53c8xx_t *) priv;
addr &= 0xff;
ncr53c8xx_reg_writeb(dev, addr, val & 0xff);
@@ -2077,17 +2105,17 @@ ncr53c8xx_mmio_writel(uint32_t addr, uint32_t val, void *p)
}
static uint8_t
ncr53c8xx_mmio_readb(uint32_t addr, void *p)
ncr53c8xx_mmio_readb(uint32_t addr, void *priv)
{
ncr53c8xx_t *dev = (ncr53c8xx_t *) p;
ncr53c8xx_t *dev = (ncr53c8xx_t *) priv;
return ncr53c8xx_reg_readb(dev, addr & 0xff);
}
static uint16_t
ncr53c8xx_mmio_readw(uint32_t addr, void *p)
ncr53c8xx_mmio_readw(uint32_t addr, void *priv)
{
ncr53c8xx_t *dev = (ncr53c8xx_t *) p;
ncr53c8xx_t *dev = (ncr53c8xx_t *) priv;
uint16_t val;
addr &= 0xff;
@@ -2097,9 +2125,9 @@ ncr53c8xx_mmio_readw(uint32_t addr, void *p)
}
static uint32_t
ncr53c8xx_mmio_readl(uint32_t addr, void *p)
ncr53c8xx_mmio_readl(uint32_t addr, void *priv)
{
ncr53c8xx_t *dev = (ncr53c8xx_t *) p;
ncr53c8xx_t *dev = (ncr53c8xx_t *) priv;
uint32_t val;
addr &= 0xff;
@@ -2112,57 +2140,57 @@ ncr53c8xx_mmio_readl(uint32_t addr, void *p)
}
static void
ncr53c8xx_ram_writeb(uint32_t addr, uint8_t val, void *p)
ncr53c8xx_ram_writeb(uint32_t addr, uint8_t val, void *priv)
{
ncr53c8xx_t *dev = (ncr53c8xx_t *) p;
ncr53c8xx_t *dev = (ncr53c8xx_t *) priv;
dev->ram[addr & 0x0fff] = val;
}
static void
ncr53c8xx_ram_writew(uint32_t addr, uint16_t val, void *p)
ncr53c8xx_ram_writew(uint32_t addr, uint16_t val, void *priv)
{
ncr53c8xx_ram_writeb(addr, val & 0xff, p);
ncr53c8xx_ram_writeb(addr + 1, (val >> 8) & 0xff, p);
ncr53c8xx_ram_writeb(addr, val & 0xff, priv);
ncr53c8xx_ram_writeb(addr + 1, (val >> 8) & 0xff, priv);
}
static void
ncr53c8xx_ram_writel(uint32_t addr, uint32_t val, void *p)
ncr53c8xx_ram_writel(uint32_t addr, uint32_t val, void *priv)
{
ncr53c8xx_ram_writeb(addr, val & 0xff, p);
ncr53c8xx_ram_writeb(addr + 1, (val >> 8) & 0xff, p);
ncr53c8xx_ram_writeb(addr + 2, (val >> 16) & 0xff, p);
ncr53c8xx_ram_writeb(addr + 3, (val >> 24) & 0xff, p);
ncr53c8xx_ram_writeb(addr, val & 0xff, priv);
ncr53c8xx_ram_writeb(addr + 1, (val >> 8) & 0xff, priv);
ncr53c8xx_ram_writeb(addr + 2, (val >> 16) & 0xff, priv);
ncr53c8xx_ram_writeb(addr + 3, (val >> 24) & 0xff, priv);
}
static uint8_t
ncr53c8xx_ram_readb(uint32_t addr, void *p)
ncr53c8xx_ram_readb(uint32_t addr, void *priv)
{
ncr53c8xx_t *dev = (ncr53c8xx_t *) p;
ncr53c8xx_t *dev = (ncr53c8xx_t *) priv;
return dev->ram[addr & 0x0fff];
}
static uint16_t
ncr53c8xx_ram_readw(uint32_t addr, void *p)
ncr53c8xx_ram_readw(uint32_t addr, void *priv)
{
uint16_t val;
val = ncr53c8xx_ram_readb(addr, p);
val |= ncr53c8xx_ram_readb(addr + 1, p) << 8;
val = ncr53c8xx_ram_readb(addr, priv);
val |= ncr53c8xx_ram_readb(addr + 1, priv) << 8;
return val;
}
static uint32_t
ncr53c8xx_ram_readl(uint32_t addr, void *p)
ncr53c8xx_ram_readl(uint32_t addr, void *priv)
{
uint32_t val;
val = ncr53c8xx_ram_readb(addr, p);
val |= ncr53c8xx_ram_readb(addr + 1, p) << 8;
val |= ncr53c8xx_ram_readb(addr + 2, p) << 16;
val |= ncr53c8xx_ram_readb(addr + 3, p) << 24;
val = ncr53c8xx_ram_readb(addr, priv);
val |= ncr53c8xx_ram_readb(addr + 1, priv) << 8;
val |= ncr53c8xx_ram_readb(addr + 2, priv) << 16;
val |= ncr53c8xx_ram_readb(addr + 3, priv) << 24;
return val;
}
@@ -2246,9 +2274,9 @@ uint8_t ncr53c8xx_pci_regs[256];
bar_t ncr53c8xx_pci_bar[4];
static uint8_t
ncr53c8xx_pci_read(int func, int addr, void *p)
ncr53c8xx_pci_read(UNUSED(int func), int addr, void *priv)
{
ncr53c8xx_t *dev = (ncr53c8xx_t *) p;
ncr53c8xx_t *dev = (ncr53c8xx_t *) priv;
ncr53c8xx_log("NCR53c8xx: Reading register %02X\n", addr & 0xff);
@@ -2341,15 +2369,18 @@ ncr53c8xx_pci_read(int func, int addr, void *p)
return 0x11;
case 0x3F:
return 0x40;
default:
break;
}
return 0;
}
static void
ncr53c8xx_pci_write(int func, int addr, uint8_t val, void *p)
ncr53c8xx_pci_write(UNUSED(int func), int addr, uint8_t val, void *priv)
{
ncr53c8xx_t *dev = (ncr53c8xx_t *) p;
ncr53c8xx_t *dev = (ncr53c8xx_t *) priv;
uint8_t valxor;
ncr53c8xx_log("NCR53c8xx: Write value %02X to register %02X\n", val, addr & 0xff);
@@ -2479,6 +2510,9 @@ ncr53c8xx_pci_write(int func, int addr, uint8_t val, void *p)
ncr53c8xx_pci_regs[addr] = val;
dev->irq = val;
return;
default:
break;
}
}

73
src/scsi/scsi_pcscsi.c
View File

@@ -149,7 +149,7 @@
#define SBAC_STATUS (1 << 24)
#define SBAC_PABTEN (1 << 25)
typedef struct {
typedef struct esp_t {
mem_mapping_t mmio_mapping;
mem_mapping_t ram_mapping;
char *nvr_path;
@@ -188,10 +188,10 @@ typedef struct {
int mca;
uint16_t Base;
uint8_t HostID, DmaChannel;
uint8_t HostID;
uint8_t DmaChannel;
struct
{
struct {
uint8_t mode;
uint8_t status;
int pos;
@@ -952,9 +952,9 @@ esp_write_response(esp_t *dev)
}
static void
esp_callback(void *p)
esp_callback(void *priv)
{
esp_t *dev = (esp_t *) p;
esp_t *dev = (esp_t *) priv;
if (dev->dma_enabled || dev->do_cmd || ((dev->rregs[ESP_CMD] & CMD_CMD) == CMD_PAD)) {
if ((dev->rregs[ESP_CMD] & CMD_CMD) == CMD_TI) {
@@ -1029,7 +1029,7 @@ esp_reg_write(esp_t *dev, uint32_t saddr, uint32_t val)
switch (saddr) {
case ESP_TCHI:
dev->tchi_written = 1;
/* fall through */
[[fallthrough]];
case ESP_TCLO:
case ESP_TCMID:
esp_log("Transfer count regs %02x = %i\n", saddr, val);
@@ -1134,6 +1134,9 @@ esp_reg_write(esp_t *dev, uint32_t saddr, uint32_t val)
esp_log("ESP Disable Selection\n");
esp_raise_irq(dev);
break;
default:
break;
}
break;
case ESP_WBUSID:
@@ -1259,6 +1262,9 @@ esp_pci_dma_write(esp_t *dev, uint16_t saddr, uint32_t val)
dev->dma_regs[DMA_STAT] &= ~(val & mask);
}
break;
default:
break;
}
}
@@ -1361,44 +1367,49 @@ esp_io_pci_write(esp_t *dev, uint32_t addr, uint32_t val, unsigned int size)
}
static void
esp_pci_io_writeb(uint16_t addr, uint8_t val, void *p)
esp_pci_io_writeb(uint16_t addr, uint8_t val, void *priv)
{
esp_t *dev = (esp_t *) p;
esp_t *dev = (esp_t *) priv;
esp_io_pci_write(dev, addr, val, 1);
}
static void
esp_pci_io_writew(uint16_t addr, uint16_t val, void *p)
esp_pci_io_writew(uint16_t addr, uint16_t val, void *priv)
{
esp_t *dev = (esp_t *) p;
esp_t *dev = (esp_t *) priv;
esp_io_pci_write(dev, addr, val, 2);
}
static void
esp_pci_io_writel(uint16_t addr, uint32_t val, void *p)
esp_pci_io_writel(uint16_t addr, uint32_t val, void *priv)
{
esp_t *dev = (esp_t *) p;
esp_t *dev = (esp_t *) priv;
esp_io_pci_write(dev, addr, val, 4);
}
static uint8_t
esp_pci_io_readb(uint16_t addr, void *p)
esp_pci_io_readb(uint16_t addr, void *priv)
{
esp_t *dev = (esp_t *) p;
esp_t *dev = (esp_t *) priv;
return esp_io_pci_read(dev, addr, 1);
}
static uint16_t
esp_pci_io_readw(uint16_t addr, void *p)
esp_pci_io_readw(uint16_t addr, void *priv)
{
esp_t *dev = (esp_t *) p;
esp_t *dev = (esp_t *) priv;
return esp_io_pci_read(dev, addr, 2);
}
static uint32_t
esp_pci_io_readl(uint16_t addr, void *p)
esp_pci_io_readl(uint16_t addr, void *priv)
{
esp_t *dev = (esp_t *) p;
esp_t *dev = (esp_t *) priv;
return esp_io_pci_read(dev, addr, 4);
}
@@ -1549,6 +1560,9 @@ dc390_write_eeprom(esp_t *dev, int ena, int clk, int dat)
esp_log("EEPROM Write enable command\n");
eeprom->wp = 0;
break;
default:
break;
}
} else {
esp_log("EEPROM Read, write or erase word\n");
@@ -1622,9 +1636,9 @@ uint8_t esp_pci_regs[256];
bar_t esp_pci_bar[2];
static uint8_t
esp_pci_read(int func, int addr, void *p)
esp_pci_read(UNUSED(int func), int addr, void *priv)
{
esp_t *dev = (esp_t *) p;
esp_t *dev = (esp_t *) priv;
// esp_log("ESP PCI: Reading register %02X\n", addr & 0xff);
@@ -1695,15 +1709,18 @@ esp_pci_read(int func, int addr, void *p)
case 0x40 ... 0x4f:
return esp_pci_regs[addr];
default:
break;
}
return 0;
}
static void
esp_pci_write(int func, int addr, uint8_t val, void *p)
esp_pci_write(UNUSED(int func), int addr, uint8_t val, void *priv)
{
esp_t *dev = (esp_t *) p;
esp_t *dev = (esp_t *) priv;
uint8_t valxor;
int eesk;
int eedi;
@@ -1799,11 +1816,14 @@ esp_pci_write(int func, int addr, uint8_t val, void *p)
case 0x40 ... 0x4f:
esp_pci_regs[addr] = val;
return;
default:
break;
}
}
static void *
dc390_init(const device_t *info)
dc390_init(UNUSED(const device_t *info))
{
esp_t *dev;
@@ -1872,6 +1892,9 @@ ncr53c90_in(uint16_t port, void *priv)
case 0x0c:
ret = dev->dma_86c01.status;
break;
default:
break;
}
}
@@ -1995,7 +2018,7 @@ ncr53c90_mca_feedb(void *priv)
}
static void *
ncr53c90_mca_init(const device_t *info)
ncr53c90_mca_init(UNUSED(const device_t *info))
{
esp_t *dev;

49
src/scsi/scsi_spock.c
View File

@@ -286,9 +286,9 @@ spock_add_to_period(spock_t *scsi, int TransferLength)
}
static void
spock_write(uint16_t port, uint8_t val, void *p)
spock_write(uint16_t port, uint8_t val, void *priv)
{
spock_t *scsi = (spock_t *) p;
spock_t *scsi = (spock_t *) priv;
spock_log("spock_write: port=%04x val=%02x %04x:%04x\n", port, val, CS, cpu_state.pc);
@@ -320,13 +320,16 @@ spock_write(uint16_t port, uint8_t val, void *p)
scsi->basic_ctrl = val;
spock_rethink_irqs(scsi);
break;
default:
break;
}
}
static void
spock_writew(uint16_t port, uint16_t val, void *p)
spock_writew(uint16_t port, uint16_t val, void *priv)
{
spock_t *scsi = (spock_t *) p;
spock_t *scsi = (spock_t *) priv;
switch (port & 7) {
case 0: /*Command Interface Register*/
@@ -339,15 +342,18 @@ spock_writew(uint16_t port, uint16_t val, void *p)
scsi->cir_pending[3] = val >> 8;
scsi->cir_status |= 2;
break;
default:
break;
}
spock_log("spock_writew: port=%04x val=%04x\n", port, val);
}
static uint8_t
spock_read(uint16_t port, void *p)
spock_read(uint16_t port, void *priv)
{
spock_t *scsi = (spock_t *) p;
spock_t *scsi = (spock_t *) priv;
uint8_t temp = 0xff;
switch (port & 7) {
@@ -378,6 +384,9 @@ spock_read(uint16_t port, void *p)
temp |= STATUS_CMD_FULL;
}
break;
default:
break;
}
spock_log("spock_read: port=%04x val=%02x %04x(%05x):%04x.\n", port, temp, CS, cs, cpu_state.pc);
@@ -385,9 +394,9 @@ spock_read(uint16_t port, void *p)
}
static uint16_t
spock_readw(uint16_t port, void *p)
spock_readw(uint16_t port, void *priv)
{
spock_t *scsi = (spock_t *) p;
spock_t *scsi = (spock_t *) priv;
uint16_t temp = 0xffff;
switch (port & 7) {
@@ -397,6 +406,9 @@ spock_readw(uint16_t port, void *p)
case 2: /*Command Interface Register*/
temp = scsi->cir_pending[2] | (scsi->cir_pending[3] << 8);
break;
default:
break;
}
spock_log("spock_readw: port=%04x val=%04x\n", port, temp);
@@ -797,6 +809,9 @@ spock_execute_cmd(spock_t *scsi, scb_t *scb)
scsi->scsi_state = SCSI_STATE_SELECT;
scsi->scb_state = 2;
return;
default:
break;
}
break;
@@ -843,6 +858,9 @@ spock_execute_cmd(spock_t *scsi, scb_t *scb)
spock_log("Complete SCB ID = %d.\n", scsi->attention & 0x0f);
}
break;
default:
break;
}
} while (scsi->scb_state != old_scb_state);
}
@@ -1000,6 +1018,9 @@ spock_callback(void *priv)
case CMD_RESET:
spock_process_imm_cmd(scsi);
break;
default:
break;
}
break;
@@ -1024,6 +1045,9 @@ spock_callback(void *priv)
scsi->irq_status = 0;
spock_clear_irq(scsi, scsi->attention & 0x0f);
break;
default:
break;
}
}
}
@@ -1097,7 +1121,7 @@ spock_mca_reset(void *priv)
}
static void *
spock_init(const device_t *info)
spock_init(UNUSED(const device_t *info))
{
spock_t *scsi = malloc(sizeof(spock_t));
memset(scsi, 0x00, sizeof(spock_t));
@@ -1117,6 +1141,9 @@ spock_init(const device_t *info)
rom_init_interleaved(&scsi->bios_rom, SPOCK_U68_1990_ROM, SPOCK_U69_1990_ROM,
0xc8000, 0x8000, 0x7fff, 0x4000, MEM_MAPPING_EXTERNAL);
break;
default:
break;
}
mem_mapping_disable(&scsi->bios_rom.mapping);
@@ -1142,9 +1169,9 @@ spock_init(const device_t *info)
}
static void
spock_close(void *p)
spock_close(void *priv)
{
spock_t *scsi = (spock_t *) p;
spock_t *scsi = (spock_t *) priv;
if (scsi) {
free(scsi);

24
src/scsi/scsi_x54x.c
View File

@@ -238,6 +238,9 @@ completion_code(uint8_t *sense)
case ASC_MEDIUM_NOT_PRESENT:
ret = 0xaa;
break;
default:
break;
}
return ret;
@@ -483,6 +486,7 @@ x54x_bios_command(x54x_t *x54x, uint8_t max_id, BIOSCMD *cmd, int8_t islba)
default:
x54x_log("BIOS: Unimplemented command: %02X\n", cmd->command);
[[fallthrough]];
case 0x05: /* Format Track, invalid since SCSI has no tracks */
case 0x0a: /* ???? */
case 0x0b: /* ???? */
@@ -605,7 +609,9 @@ static void
x54x_mbi(x54x_t *dev)
{
Req_t *req = &dev->Req;
// uint32_t CCBPointer = req->CCBPointer;
#if 0
uint32_t CCBPointer = req->CCBPointer;
#endif
addr24_t CCBPointer;
CCBU *CmdBlock = &(req->CmdBlock);
uint8_t HostStatus = req->HostStatus;
@@ -1035,7 +1041,7 @@ x54x_notify(x54x_t *dev)
}
static void
x54x_req_setup(x54x_t *dev, uint32_t CCBPointer, Mailbox32_t *Mailbox32)
x54x_req_setup(x54x_t *dev, uint32_t CCBPointer, UNUSED(Mailbox32_t *Mailbox32))
{
Req_t *req = &dev->Req;
uint8_t id;
@@ -1161,9 +1167,11 @@ x54x_mbo_process(x54x_t *dev)
} else if (!dev->MailboxIsBIOS && (mb32.u.out.ActionCode == MBO_ABORT)) {
x54x_log("Abort Mailbox Command\n");
x54x_req_abort(dev, mb32.CCBPointer);
} /* else {
#if 0
} else {
x54x_log("Invalid action code: %02X\n", mb32.u.out.ActionCode);
} */
#endif
}
if ((mb32.u.out.ActionCode == MBO_START) || (!dev->MailboxIsBIOS && (mb32.u.out.ActionCode == MBO_ABORT))) {
/* We got the mailbox, decrease the number of pending requests. */
@@ -1282,7 +1290,9 @@ x54x_cmd_callback(void *priv)
period = (1000000.0 / dev->ha_bps) * ((double) dev->temp_period);
timer_on(&dev->timer, dev->media_period + period + 10.0, 0);
// x54x_log("Temporary period: %lf us (%" PRIi64 " periods)\n", dev->timer.period, dev->temp_period);
#if 0
x54x_log("Temporary period: %lf us (%" PRIi64 " periods)\n", dev->timer.period, dev->temp_period);
#endif
}
static uint8_t
@@ -1292,8 +1302,8 @@ x54x_in(uint16_t port, void *priv)
uint8_t ret;
switch (port & 3) {
case 0:
default:
case 0:
ret = dev->Status;
break;
@@ -1329,8 +1339,8 @@ x54x_in(uint16_t port, void *priv)
ret = dev->Geometry;
else {
switch (dev->Geometry) {
case 0:
default:
case 0:
ret = 'A';
break;
case 1: