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Fixed the "minor bug fix" in the AT / PS/2 keyboard controller, reworked PS/2 keyboard controller IRQ latches, and correctly disabled memory top remaps if there's more than (16 MB - remap size) RAM (fixes segmentation faults on some machines with 16+ MB of RAM).

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This commit is contained in:
OBattler
2023-04-11 23:21:52 +02:00
parent 5da3e78fc1
commit ef17003f1b
17 changed files with 194 additions and 107 deletions
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4
src/chipset/ali1489.c
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@@ -180,6 +180,9 @@ ali1489_defaults(ali1489_t *dev)
dev->regs[0x3d] = 0x01;
dev->regs[0x40] = 0x03;
pic_kbd_latch(0x01);
pic_mouse_latch(0x00);
ali1489_shadow_recalc(dev);
cpu_cache_int_enabled = 0;
cpu_cache_ext_enabled = 0;
@@ -295,6 +298,7 @@ ali1489_write(uint16_t addr, uint8_t val, void *priv)
case 0x2a: /* I/O Recovery Register */
dev->regs[dev->index] = val;
pic_mouse_latch(val & 0x80);
break;
case 0x2b: /* Turbo Function Register */

10
src/chipset/ali1543.c
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@@ -153,7 +153,8 @@ ali1533_write(int func, int addr, uint8_t val, void *priv)
case 0x41:
/* TODO: Bit 7 selects keyboard controller type:
0 = AT, 1 = PS/2 */
keyboard_at_set_mouse_scan((val & 0x40) ? 1 : 0);
pic_kbd_latch(!!(val & 0x80));
pic_mouse_latch(!!(val & 0x40));
dev->pci_conf[addr] = val & 0xbf;
break;
@@ -454,9 +455,7 @@ ali1533_read(int func, int addr, void *priv)
ret = 0x00;
else {
ret = dev->pci_conf[addr];
if (addr == 0x41)
ret |= (keyboard_at_get_mouse_scan() << 2);
else if (addr == 0x58)
if (addr == 0x58)
ret = (ret & 0xbf) | (dev->ide_dev_enable ? 0x40 : 0x00);
else if ((dev->type == 1) && ((addr >= 0x7c) && (addr <= 0xff)) && !dev->pmu_dev_enable) {
dev->pmu_dev_enable = 1;
@@ -1510,7 +1509,8 @@ ali1543_reset(void *priv)
dev->pci_conf[0x0a] = 0x01;
dev->pci_conf[0x0b] = 0x06;
ali1533_write(0, 0x48, 0x00, dev); // Disables all IRQ's
ali1533_write(0, 0x41, 0x00, dev); /* Disables the keyboard and mouse IRQ latch. */
ali1533_write(0, 0x48, 0x00, dev); /* Disables all IRQ's. */
ali1533_write(0, 0x44, 0x00, dev);
ali1533_write(0, 0x4d, 0x00, dev);
ali1533_write(0, 0x53, 0x00, dev);

6
src/chipset/ali6117.c
View File

@@ -302,6 +302,7 @@ ali6117_reg_write(uint16_t addr, uint8_t val, void *priv)
case 0x36:
val &= 0xf0;
val |= dev->regs[dev->reg_offset];
pic_mouse_latch(val & 0x40);
break;
case 0x37:
@@ -426,6 +427,8 @@ ali6117_reset(void *priv)
/* On-board memory 15-16M is enabled by default. */
mem_set_mem_state_both(0x00f00000, 0x00100000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
ali6117_bank_recalc(dev);
pic_mouse_latch(0x00);
}
}
@@ -475,6 +478,9 @@ ali6117_init(const device_t *info)
}
}
if (!(dev->local & 0x08))
pic_kbd_latch(0x01);
ali6117_reset(dev);
if (!(dev->local & 0x08))

4
src/chipset/ims8848.c
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@@ -30,6 +30,7 @@
#include <86box/mem.h>
#include <86box/smram.h>
#include <86box/pci.h>
#include <86box/pic.h>
#include <86box/port_92.h>
#include <86box/chipset.h>
@@ -388,6 +389,9 @@ ims8848_init(const device_t *info)
ims8848_reset(dev);
pic_kbd_latch(0x01);
pic_mouse_latch(0x01);
return dev;
}

10
src/chipset/intel_420ex.c
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@@ -31,6 +31,7 @@
#include <86box/mem.h>
#include <86box/smram.h>
#include <86box/pci.h>
#include <86box/pic.h>
#include <86box/timer.h>
#include <86box/pit.h>
#include <86box/port_92.h>
@@ -217,6 +218,7 @@ i420ex_write(int func, int addr, uint8_t val, void *priv)
break;
case 0x4e:
dev->regs[addr] = (val & 0xf7);
pic_mouse_latch(!!(val & 0x10));
break;
case 0x50:
dev->regs[addr] = (val & 0x0f);
@@ -387,7 +389,8 @@ i420ex_reset_hard(void *priv)
dev->regs[0x4c] = 0x4d;
dev->regs[0x4e] = 0x03;
/* Bits 2:1 of register 50h are 00 is 25 MHz, and 01 if 33 MHz, 10 and 11 are reserved. */
pic_mouse_latch(0x00);
/* Bits 2:1 of register 50h are 00 is 25 MHz, and 01 if 33 MHz, 10 and 11 are reserved. */
if (cpu_busspeed >= 33333333)
dev->regs[0x50] |= 0x02;
dev->regs[0x51] = 0x80;
@@ -436,6 +439,9 @@ i420ex_reset(void *p)
i420ex_write(0, 0x48, 0x00, p);
/* Disable the PIC mouse latch. */
i420ex_write(0, 0x4e, 0x03, p);
for (i = 0; i < 7; i++)
i420ex_write(0, 0x59 + i, 0x00, p);
@@ -520,6 +526,8 @@ i420ex_init(const device_t *info)
i420ex_reset_hard(dev);
pic_kbd_latch(0x01);
return dev;
}

17
src/chipset/intel_piix.c
View File

@@ -512,7 +512,7 @@ piix_write(int func, int addr, uint8_t val, void *priv)
break;
case 0x4e:
fregs[0x4e] = val;
keyboard_at_set_mouse_scan((val & 0x10) ? 1 : 0);
pic_mouse_latch(!!(val & 0x10));
if (dev->type >= 4)
kbc_alias_update_io_mapping(dev);
break;
@@ -1159,9 +1159,7 @@ piix_read(int func, int addr, void *priv)
if ((func <= dev->max_func) || ((func == 1) && (dev->max_func == 0))) {
fregs = (uint8_t *) dev->regs[func];
ret = fregs[addr];
if ((func == 0) && (addr == 0x4e))
ret |= keyboard_at_get_mouse_scan();
else if ((func == 2) && (addr == 0xff))
if ((func == 2) && (addr == 0xff))
ret |= 0xef;
piix_log("PIIX function %i read: %02X from %02X\n", func, ret, addr);
@@ -1277,6 +1275,7 @@ piix_reset_hard(piix_t *dev)
fregs[0x0e] = ((dev->type > 1) || (dev->rev != 2)) ? 0x80 : 0x00;
fregs[0x4c] = 0x4d;
fregs[0x4e] = 0x03;
pic_mouse_latch(0x00);
fregs[0x60] = fregs[0x61] = fregs[0x62] = fregs[0x63] = 0x80;
fregs[0x64] = (dev->type > 3) ? 0x10 : 0x00;
fregs[0x69] = 0x02;
@@ -1446,6 +1445,9 @@ piix_reset(void *p)
piix_write(0, 0xa8, 0x0f, p);
}
/* Disable the PIC mouse latch. */
piix_write(0, 0x4e, 0x03, p);
if (dev->type == 5)
piix_write(0, 0xe1, 0x40, p);
piix_write(1, 0x04, 0x00, p);
@@ -1532,9 +1534,8 @@ piix_speed_changed(void *priv)
timer_on_auto(&dev->fast_off_timer, ((double) cpu_fast_off_val + 1) * dev->fast_off_period);
}
static void
*
piix_init(const device_t *info)
static void *
piix_init(const device_t *info)
{
piix_t *dev = (piix_t *) malloc(sizeof(piix_t));
memset(dev, 0, sizeof(piix_t));
@@ -1680,6 +1681,8 @@ static void
// device_add(&i8254_sec_device);
pic_kbd_latch(0x01);
return dev;
}

8
src/chipset/intel_sio.c
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@@ -27,6 +27,7 @@
#include <86box/dma.h>
#include <86box/mem.h>
#include <86box/pci.h>
#include <86box/pic.h>
#include <86box/timer.h>
#include <86box/pit.h>
#include <86box/port_92.h>
@@ -201,6 +202,7 @@ sio_write(int func, int addr, uint8_t val, void *priv)
case 0x4c:
case 0x4d:
dev->regs[addr] = (val & 0x7f);
pic_mouse_latch(!!(val & 0x10));
break;
case 0x4f:
dev->regs[addr] = val;
@@ -392,6 +394,7 @@ sio_reset_hard(void *priv)
dev->regs[0x4b] = 0x0f;
dev->regs[0x4c] = 0x56;
dev->regs[0x4d] = 0x40;
pic_mouse_latch(0x00);
dev->regs[0x4e] = 0x07;
dev->regs[0x4f] = 0x4f;
dev->regs[0x57] = 0x04;
@@ -444,6 +447,9 @@ sio_reset(void *p)
{
sio_t *dev = (sio_t *) p;
/* Disable the PIC mouse latch. */
sio_write(0, 0x4d, 0x40, p);
sio_write(0, 0x57, 0x04, p);
dma_set_params(1, 0xffffffff);
@@ -538,6 +544,8 @@ sio_init(const device_t *info)
// device_add(&i8254_sec_device);
pic_kbd_latch(0x01);
return dev;
}

4
src/chipset/sis_5571.c
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@@ -29,6 +29,7 @@
#include <86box/dma.h>
#include <86box/mem.h>
#include <86box/pci.h>
#include <86box/pic.h>
#include <86box/port_92.h>
#include <86box/hdc_ide.h>
#include <86box/hdc_ide_sff8038i.h>
@@ -725,6 +726,9 @@ sis_5571_init(const device_t *info)
sis_5571_reset(dev);
pic_kbd_latch(0x01);
pic_mouse_latch(0x01);
return dev;
}

3
src/chipset/umc_8886.c
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@@ -374,6 +374,9 @@ umc_8886_init(const device_t *info)
umc_8886_reset(dev);
pic_kbd_latch(0x01);
pic_mouse_latch(0x01);
return dev;
}

11
src/chipset/via_pipc.c
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@@ -222,6 +222,9 @@ pipc_reset_hard(void *priv)
dev->pci_isa_regs[0x0b] = 0x06;
dev->pci_isa_regs[0x0e] = 0x80;
pic_kbd_latch(0x01);
pic_mouse_latch(dev->local >= VIA_PIPC_586B);
dev->pci_isa_regs[0x48] = 0x01;
dev->pci_isa_regs[0x4a] = 0x04;
dev->pci_isa_regs[0x4f] = 0x03;
@@ -1063,6 +1066,11 @@ pipc_write(int func, int addr, uint8_t val, void *priv)
break;
case 0x44:
if (dev->local <= VIA_PIPC_586B)
pic_mouse_latch(val & 0x01);
break;
case 0x47:
if (val & 0x01)
trc_write(0x0047, (val & 0x80) ? 0x06 : 0x04, NULL);
@@ -1585,6 +1593,9 @@ pipc_reset(void *p)
else
pipc_write(1, 0x40, 0x00, p);
if (dev->local < VIA_PIPC_586B)
pipc_write(0, 0x44, 0x00, p);
pipc_write(0, 0x77, 0x00, p);
}