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Added the NCR 53C810 PCI SCSI controller;

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Fixed the behavior of the CD-ROM GET CONFIGURATION command when unimplemented features are requested;
Fixed the behavior of the CD-ROM READ DVD STRUCTURE command in some situations and made it correctly report 05/30/02 for incompatible format;
Reworked the PS/2 Model 80 Type 2 memory handling a bit;
The emulator now allocates the few MB of space needed for pages for the entire 4 GB RAM space at the startup and only memset's it to 0 on hard reset - should make sure DMA page reads from/writes to memory-mapped devices no longer crash the emulator on invalidating the memory range;
Applied app applicable PCem patches;
The PS/1 Model 2133 now also applies PS/2-style NMI mask handling - fixes the 486 recompiler on this machine;
Added the missing #include of "cpu/cpu.h" in io.c, fixes compiling when I/O tracing is enabled.
This commit is contained in:
OBattler
2017-12-10 15:16:24 +01:00
parent c7946fbce7
commit f050810e2f
20 changed files with 397 additions and 129 deletions
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35
src/dma.c
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@@ -194,6 +194,21 @@ static uint8_t dma_ps2_read(uint16_t addr, void *priv)
temp = (dma.xfr_channel & 4) ? (dma16.cc[dma.xfr_channel & 3] & 0xff) : (dma.cc[dma.xfr_channel] & 0xff);
dma.byte_ptr = (dma.byte_ptr + 1) & 1;
break;
case 6: /*Read DMA status*/
if (dma.byte_ptr)
{
temp = dma16.stat_rq | (dma16.stat << 4);
dma16.stat = 0;
dma16.stat_rq = 0;
}
else
{
temp = dma.stat_rq | (dma.stat << 4);
dma.stat = 0;
dma.stat_rq = 0;
}
dma.byte_ptr = (dma.byte_ptr + 1) & 1;
break;
case 7: /*Mode*/
temp = (dma.xfr_channel & 4) ? dma16.ps2_mode[dma.xfr_channel & 3] : dma.ps2_mode[dma.xfr_channel];
break;
@@ -551,6 +566,7 @@ int dma_channel_read(int channel)
return DMA_NODATA;
temp = _dma_read(dma.ac[channel]);
dma.stat_rq |= (1 << channel);
if (dma.mode[channel] & 0x20)
{
@@ -594,6 +610,7 @@ int dma_channel_read(int channel)
temp = _dma_read(dma16.ac[channel]) |
(_dma_read(dma16.ac[channel] + 1) << 8);
dma16.stat_rq |= (1 << channel);
if (dma16.mode[channel] & 0x20)
{
@@ -646,6 +663,7 @@ int dma_channel_write(int channel, uint16_t val)
return DMA_NODATA;
_dma_write(dma.ac[channel], val);
dma.stat_rq |= (1 << channel);
if (dma.mode[channel] & 0x20)
{
@@ -688,6 +706,7 @@ int dma_channel_write(int channel, uint16_t val)
_dma_write(dma16.ac[channel], val);
_dma_write(dma16.ac[channel] + 1, val >> 8);
dma16.stat_rq |= (1 << channel);
if (dma16.mode[channel] & 0x20)
{
@@ -738,11 +757,23 @@ int dma_mode(int channel)
/* DMA Bus Master Page Read/Write */
void DMAPageRead(uint32_t PhysAddress, char *DataRead, uint32_t TotalSize)
{
memcpy(DataRead, &ram[PhysAddress], TotalSize);
int i = 0;
// memcpy(DataRead, &ram[PhysAddress], TotalSize);
for (i = 0; i < TotalSize; i++)
DataRead[i] = mem_readb_phys(PhysAddress + i);
}
void DMAPageWrite(uint32_t PhysAddress, const char *DataWrite, uint32_t TotalSize)
{
int i = 0;
// mem_invalidate_range(PhysAddress, PhysAddress + TotalSize - 1);
// memcpy(&ram[PhysAddress], DataWrite, TotalSize);
for (i = 0; i < TotalSize; i++)
mem_writeb_phys(PhysAddress + i, DataWrite[i]);
mem_invalidate_range(PhysAddress, PhysAddress + TotalSize - 1);
memcpy(&ram[PhysAddress], DataWrite, TotalSize);
}