Added the NCR 53C810 PCI SCSI controller;
Fixed the behavior of the CD-ROM GET CONFIGURATION command when unimplemented features are requested; Fixed the behavior of the CD-ROM READ DVD STRUCTURE command in some situations and made it correctly report 05/30/02 for incompatible format; Reworked the PS/2 Model 80 Type 2 memory handling a bit; The emulator now allocates the few MB of space needed for pages for the entire 4 GB RAM space at the startup and only memset's it to 0 on hard reset - should make sure DMA page reads from/writes to memory-mapped devices no longer crash the emulator on invalidating the memory range; Applied app applicable PCem patches; The PS/1 Model 2133 now also applies PS/2-style NMI mask handling - fixes the 486 recompiler on this machine; Added the missing #include of "cpu/cpu.h" in io.c, fixes compiling when I/O tracing is enabled.
This commit is contained in:
@@ -11,6 +11,7 @@
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#include "../pit.h"
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#include "../mca.h"
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#include "../mem.h"
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#include "../nmi.h"
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#include "../rom.h"
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#include "../device.h"
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#include "../nvr.h"
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@@ -38,6 +39,7 @@ static struct
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mem_mapping_t shadow_mapping;
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mem_mapping_t split_mapping;
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mem_mapping_t split_mapping_2;
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mem_mapping_t expansion_mapping;
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uint8_t (*planar_read)(uint16_t port);
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@@ -84,30 +86,61 @@ static void ps2_write_shadow_raml(uint32_t addr, uint32_t val, void *priv)
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static uint8_t ps2_read_split_ram(uint32_t addr, void *priv)
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{
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addr = (addr & 0x3ffff) + 0xa0000;
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addr = (addr & 0x1ffff) + 0x80000;
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return mem_read_ram(addr, priv);
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}
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static uint16_t ps2_read_split_ramw(uint32_t addr, void *priv)
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{
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addr = (addr & 0x3ffff) + 0xa0000;
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addr = (addr & 0x1ffff) + 0x80000;
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return mem_read_ramw(addr, priv);
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}
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static uint32_t ps2_read_split_raml(uint32_t addr, void *priv)
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{
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addr = (addr & 0x3ffff) + 0xa0000;
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addr = (addr & 0x1ffff) + 0x80000;
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return mem_read_raml(addr, priv);
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}
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static void ps2_write_split_ram(uint32_t addr, uint8_t val, void *priv)
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{
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addr = (addr & 0x3ffff) + 0xa0000;
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addr = (addr & 0x1ffff) + 0x80000;
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mem_write_ram(addr, val, priv);
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}
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static void ps2_write_split_ramw(uint32_t addr, uint16_t val, void *priv)
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{
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addr = (addr & 0x3ffff) + 0xa0000;
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addr = (addr & 0x1ffff) + 0x80000;
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mem_write_ramw(addr, val, priv);
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}
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static void ps2_write_split_raml(uint32_t addr, uint32_t val, void *priv)
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{
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addr = (addr & 0x1ffff) + 0x80000;
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mem_write_raml(addr, val, priv);
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}
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static uint8_t ps2_read_split_2_ram(uint32_t addr, void *priv)
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{
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addr = (addr & 0x3ffff) + 0xa0000;
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return mem_read_ram(addr, priv);
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}
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static uint16_t ps2_read_split_2_ramw(uint32_t addr, void *priv)
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{
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addr = (addr & 0x3ffff) + 0xa0000;
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return mem_read_ramw(addr, priv);
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}
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static uint32_t ps2_read_split_2_raml(uint32_t addr, void *priv)
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{
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addr = (addr & 0x3ffff) + 0xa0000;
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return mem_read_raml(addr, priv);
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}
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static void ps2_write_split_2_ram(uint32_t addr, uint8_t val, void *priv)
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{
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addr = (addr & 0x3ffff) + 0xa0000;
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mem_write_ram(addr, val, priv);
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}
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static void ps2_write_split_2_ramw(uint32_t addr, uint16_t val, void *priv)
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{
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addr = (addr & 0x3ffff) + 0xa0000;
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mem_write_ramw(addr, val, priv);
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}
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static void ps2_write_split_2_raml(uint32_t addr, uint32_t val, void *priv)
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{
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addr = (addr & 0x3ffff) + 0xa0000;
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mem_write_raml(addr, val, priv);
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@@ -645,21 +678,39 @@ static void ps2_mca_board_model_55sx_init()
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static void mem_encoding_update()
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{
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if (ps2.split_addr >= mem_size*1024)
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mem_mapping_disable(&ps2.split_mapping);
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mem_mapping_disable(&ps2.split_mapping);
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mem_mapping_disable(&ps2.split_mapping_2);
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ps2.split_addr = (ps2.mem_regs[0] & 0xf) << 20;
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ps2.split_addr = ((uint32_t) (ps2.mem_regs[0] & 0xf)) << 20;
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if (ps2.mem_regs[1] & 2)
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if (ps2.mem_regs[1] & 2) {
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mem_set_mem_state(0xe0000, 0x20000, MEM_READ_EXTERNAL | MEM_WRITE_INTERNAL);
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else
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pclog("PS/2 Model 80-111: ROM space enabled\n");
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} else {
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mem_set_mem_state(0xe0000, 0x20000, MEM_READ_INTERNAL | MEM_WRITE_DISABLED);
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pclog("PS/2 Model 80-111: ROM space disabled\n");
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}
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if (ps2.mem_regs[1] & 4) {
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mem_mapping_set_addr(&ram_low_mapping, 0x00000, 0x80000);
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pclog("PS/2 Model 80-111: 00080000- 0009FFFF disabled\n");
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} else {
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mem_mapping_set_addr(&ram_low_mapping, 0x00000, 0xa0000);
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pclog("PS/2 Model 80-111: 00080000- 0009FFFF enabled\n");
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}
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if (!(ps2.mem_regs[1] & 8))
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{
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if (ps2.split_addr >= mem_size*1024)
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mem_mapping_set_addr(&ps2.split_mapping, ps2.split_addr, 256*1024);
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}
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if (ps2.mem_regs[1] & 4) {
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mem_mapping_set_addr(&ps2.split_mapping, ps2.split_addr, 128*1024);
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mem_mapping_set_addr(&ps2.split_mapping_2, ps2.split_addr+(128*1024), 256*1024);
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} else
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mem_mapping_set_addr(&ps2.split_mapping_2, ps2.split_addr, 256*1024);
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pclog("PS/2 Model 80-111: Split memory block enabled at %08X\n", ps2.split_addr);
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} else {
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pclog("PS/2 Model 80-111: Split memory block disabled\n");
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}
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}
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static uint8_t mem_encoding_read(uint16_t addr, void *p)
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@@ -711,7 +762,7 @@ static void ps2_mca_board_model_80_type2_init(int is486)
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mem_remap_top_256k();
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ps2.split_addr = mem_size * 1024;
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mca_init(24);
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mca_init(8);
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ps2.planar_read = model_80_read;
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ps2.planar_write = model_80_write;
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@@ -721,42 +772,69 @@ static void ps2_mca_board_model_80_type2_init(int is486)
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io_sethandler(0x00e0, 0x0002, mem_encoding_read, NULL, NULL, mem_encoding_write, NULL, NULL, NULL);
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ps2.mem_regs[1] = 2;
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/* Note by Kotori: I rewrote this because the original code was using
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Model 80 Type 1-style 1 MB memory card settings, which are *NOT*
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supported by Model 80 Type 2. */
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switch (mem_size/1024)
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{
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case 1:
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ps2.option[1] = 0x0c;
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ps2.option[1] = 0x0e; /* 11 10 = 0 2 */
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ps2.mem_regs[1] = 0xd2; /* 01 = 1 (first) */
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ps2.mem_regs[0] = 0xf0; /* 11 = invalid */
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break;
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case 2:
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ps2.option[1] = 0x0e;
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ps2.option[1] = 0x0e; /* 11 10 = 0 2 */
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ps2.mem_regs[1] = 0xc2; /* 00 = 2 */
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ps2.mem_regs[0] = 0xf0; /* 11 = invalid */
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break;
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case 3:
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ps2.option[1] = 0x02;
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ps2.option[1] = 0x0a; /* 10 10 = 2 2 */
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ps2.mem_regs[1] = 0xc2; /* 00 = 2 */
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ps2.mem_regs[0] = 0xd0; /* 01 = 1 (first) */
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break;
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case 4:
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default:
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ps2.option[1] = 0x0a;
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ps2.option[1] = 0x0a; /* 10 10 = 2 2 */
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ps2.mem_regs[1] = 0xc2; /* 00 = 2 */
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ps2.mem_regs[0] = 0xc0; /* 00 = 2 */
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break;
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}
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ps2.mem_regs[0] |= ((mem_size/1024) & 0x0f);
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mem_mapping_add(&ps2.split_mapping,
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(mem_size+256) * 1024,
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256*1024,
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128*1024,
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ps2_read_split_ram,
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ps2_read_split_ramw,
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ps2_read_split_raml,
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ps2_write_split_ram,
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ps2_write_split_ramw,
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ps2_write_split_raml,
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&ram[0xa0000],
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&ram[0x80000],
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MEM_MAPPING_INTERNAL,
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NULL);
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mem_mapping_disable(&ps2.split_mapping);
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mem_mapping_add(&ps2.split_mapping_2,
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(mem_size+384) * 1024,
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256*1024,
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ps2_read_split_2_ram,
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ps2_read_split_2_ramw,
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ps2_read_split_2_raml,
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ps2_write_split_2_ram,
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ps2_write_split_2_ramw,
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ps2_write_split_2_raml,
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&ram[0xa0000],
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MEM_MAPPING_INTERNAL,
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NULL);
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mem_mapping_disable(&ps2.split_mapping_2);
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if ((mem_size > 4096) && !is486)
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{
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/* Only 4 MB supported on planar, create a memory expansion card for the rest */
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mem_mapping_set_addr(&ram_high_mapping, 0x100000, 0x400000);
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mem_mapping_set_addr(&ram_high_mapping, 0x100000, 0x300000);
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ps2.mem_pos_regs[0] = 0xff;
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ps2.mem_pos_regs[1] = 0xfc;
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@@ -764,31 +842,33 @@ static void ps2_mca_board_model_80_type2_init(int is486)
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switch (mem_size/1024)
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{
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case 5:
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ps2.mem_pos_regs[4] = 0xfc;
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ps2.mem_pos_regs[4] = 0xfc; /* 11 11 11 00 = 0 0 0 1 */
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break;
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case 6:
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ps2.mem_pos_regs[4] = 0xfe;
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ps2.mem_pos_regs[4] = 0xfe; /* 11 11 11 10 = 0 0 0 2 */
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break;
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case 7:
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ps2.mem_pos_regs[4] = 0xf2;
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ps2.mem_pos_regs[4] = 0xf2; /* 11 11 00 10 = 0 0 1 2 */
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break;
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case 8:
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ps2.mem_pos_regs[4] = 0xfa;
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ps2.mem_pos_regs[4] = 0xfa; /* 11 11 10 10 = 0 0 2 2 */
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break;
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case 9:
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ps2.mem_pos_regs[4] = 0xca;
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ps2.mem_pos_regs[4] = 0xca; /* 11 00 10 10 = 0 1 2 2 */
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break;
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case 10:
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ps2.mem_pos_regs[4] = 0xea;
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ps2.mem_pos_regs[4] = 0xea; /* 11 10 10 10 = 0 2 2 2 */
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break;
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case 11:
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ps2.mem_pos_regs[4] = 0x2a;
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ps2.mem_pos_regs[4] = 0x2a; /* 00 10 10 10 = 1 2 2 2 */
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break;
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case 12:
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ps2.mem_pos_regs[4] = 0xaa;
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ps2.mem_pos_regs[4] = 0xaa; /* 10 10 10 10 = 2 2 2 2 */
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break;
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}
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pclog("ps2.mem_pos_regs[4] = %08X\n", ps2.mem_pos_regs[4]);
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mca_add(ps2_mem_expansion_read, ps2_mem_expansion_write, NULL);
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mem_mapping_add(&ps2.expansion_mapping,
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0x400000,
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@@ -821,6 +901,8 @@ machine_ps2_common_init(machine_t *model)
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pic2_init();
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pit_ps2_init();
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nmi_mask = 0x80;
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}
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