claunia/86Box
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Added emulation of Cardex ET4000/W32p with ICS/SDAC RAMDAC;

Browse Source 
Fixed ET4000/W32p clock (for non-Diamond variants) and banking extension;
Brought the code on par with the mainline;
Fixed names of the two Cardex ET4000/W32p variants per the BIOS'es;
Brought ET4000AX unknown RAMDAC back in line with the mainline (reverted bogus "fix" by Win9xFan);
Made 15bpp and 16bpp colors more accurate.
This commit is contained in:
OBattler
2016-07-23 01:48:47 +02:00
parent 0d1e5c7439
commit f41bbb6ba8
16 changed files with 452 additions and 119 deletions
Download Patch File Download Diff File Expand all files Collapse all files

110
src/vid_stg_ramdac.c
View File

@@ -7,10 +7,39 @@
static int stg_state_read[2][8] = {{1,2,3,4,0,0,0,0}, {1,2,3,4,5,6,7,7}};
static int stg_state_write[8] = {0,0,0,0,0,6,7,7};
static int stg_state_indexed = 0;
void stg_ramdac_set_bpp(svga_t *svga, stg_ramdac_t *ramdac)
{
int oldbpp = svga->bpp;
if (ramdac->command & 0x8)
{
switch (ramdac->regs[3])
{
case 0: case 5: case 7: svga->bpp = 8; break;
case 1: case 2: case 8: svga->bpp = 15; break;
case 3: case 6: svga->bpp = 16; break;
case 4: case 9: svga->bpp = 24; break;
default: svga->bpp = 8; break;
}
}
else
{
switch (ramdac->command >> 5)
{
case 0: svga->bpp = 8; break;
case 5: svga->bpp = 15; break;
case 6: svga->bpp = 16; break;
case 7: svga->bpp = 24; break;
default: svga->bpp = 8; break;
}
}
svga_recalctimings(svga);
}
void stg_ramdac_out(uint16_t addr, uint8_t val, stg_ramdac_t *ramdac, svga_t *svga)
{
int didwrite;
int didwrite, old;
//if (CS!=0xC000) pclog("OUT RAMDAC %04X %02X %i %04X:%04X\n",addr,val,stg_ramdac.magic_count,CS,pc);
switch (addr)
{
@@ -20,8 +49,20 @@ void stg_ramdac_out(uint16_t addr, uint8_t val, stg_ramdac_t *ramdac, svga_t *sv
case 0: case 1: case 2: case 3:
break;
case 4:
old = ramdac->command;
ramdac->command = val;
/*pclog("Write RAMDAC command %02X\n",val);*/
if ((old ^ val) & 8)
{
stg_ramdac_set_bpp(svga, ramdac);
}
else
{
if ((old ^ val) & 0xE0)
{
stg_ramdac_set_bpp(svga, ramdac);
}
}
// pclog("Write RAMDAC command %02X\n",val);
break;
case 5:
ramdac->index = (ramdac->index & 0xff00) | val;
@@ -30,38 +71,17 @@ void stg_ramdac_out(uint16_t addr, uint8_t val, stg_ramdac_t *ramdac, svga_t *sv
ramdac->index = (ramdac->index & 0xff) | (val << 8);
break;
case 7:
#ifndef RELEASE_BUILD
pclog("Write RAMDAC reg %02X %02X\n", ramdac->index, val);
#endif
if (ramdac->index < 0x100)
// pclog("Write RAMDAC reg %02X %02X\n", ramdac->index, val);
if (ramdac->index < 0x100)
{
ramdac->regs[ramdac->index] = val;
}
if ((ramdac->index == 3) && (ramdac->command & 8)) stg_ramdac_set_bpp(svga, ramdac);
ramdac->index++;
break;
}
didwrite = (ramdac->magic_count >= 4);
ramdac->magic_count = stg_state_write[ramdac->magic_count & 7];
if (ramdac->command & 8)
{
switch (ramdac->regs[3])
{
case 0: case 5: case 7: svga->bpp = 8; break;
case 1: case 2: case 8: svga->bpp = 15; break;
case 3: case 6: svga->bpp = 16; break;
case 4: case 9: svga->bpp = 24; break;
default: svga->bpp = 8; break;
}
}
else
{
switch (ramdac->command >> 5)
{
case 0: svga->bpp = 8; break;
case 5: svga->bpp = 15; break;
case 6: svga->bpp = 16; break;
case 7: svga->bpp = 24; break;
default: svga->bpp = 8; break;
}
}
if (didwrite) return;
break;
case 0x3c7: case 0x3c8: case 0x3c9:
@@ -93,15 +113,18 @@ uint8_t stg_ramdac_in(uint16_t addr, stg_ramdac_t *ramdac, svga_t *svga)
temp = ramdac->index >> 8;
break;
case 7:
// pclog("Read RAMDAC index %04X\n",stg_ramdac.index);
// pclog("Read RAMDAC index %04X\n",ramdac->index);
switch (ramdac->index)
{
case 0:
temp = 0x44;
break;
case 1:
temp = 0x02;
temp = 0x03;
break;
case 7:
temp = 0x88;
break;
default:
if (ramdac->index < 0x100) temp = ramdac->regs[ramdac->index];
else temp = 0xff;
@@ -112,7 +135,7 @@ uint8_t stg_ramdac_in(uint16_t addr, stg_ramdac_t *ramdac, svga_t *svga)
}
ramdac->magic_count = stg_state_read[(ramdac->command & 0x10) ? 1 : 0][ramdac->magic_count & 7];
return temp;
case 0x3c8: case 0x3c9:
case 0x3c7: case 0x3c8: case 0x3c9:
ramdac->magic_count=0;
break;
}
@@ -124,14 +147,31 @@ float stg_getclock(int clock, void *p)
stg_ramdac_t *ramdac = (stg_ramdac_t *)p;
float t;
int m, n1, n2;
float d;
// pclog("STG_Getclock %i %04X\n", clock, ramdac->regs[clock]);
if (clock == 0) return 25175000.0;
if (clock == 1) return 28322000.0;
clock ^= 1; /*Clocks 2 and 3 seem to be reversed*/
m = (ramdac->regs[clock] & 0x7f) + 2;
n1 = ((ramdac->regs[clock] >> 8) & 0x1f) + 2;
n2 = ((ramdac->regs[clock] >> 13) & 0x07);
t = (14318184.0 * ((float)m / (float)n1)) / (float)(1 << n2);
m = (ramdac->regs[clock] & 0x7f) + 2; /* B+2 */
n1 = ((ramdac->regs[clock] >> 8) & 0x1f) + 2; /* N1+2 */
n2 = ((ramdac->regs[clock] >> 13) & 0x07); /* D */
switch (n2)
{
case 0:
d = 1.0;
break;
case 1:
d = 2.0;
break;
case 2:
d = 4.0;
break;
case 3:
d = 8.0;
break;
}
// t = (14318184.0 * ((float)m / (float)n1)) / (float)(1 << n2);
t = (14318184.0 * ((float)m / d)) / (float)n1;
// pclog("STG clock %i %i %i %f %04X %f %i\n", m, n1, n2, t, ramdac->regs[2], 14318184.0 * ((float)m / (float)n1), 1 << n2);
return t;
}