diff --git a/src/chipset/intel_4x0.c b/src/chipset/intel_4x0.c
index 863234137..f920f83a7 100644
--- a/src/chipset/intel_4x0.c
+++ b/src/chipset/intel_4x0.c
@@ -55,7 +55,7 @@ typedef struct
     uint8_t	pm2_cntrl,
 		smram_locked, max_drb,
 		drb_unit, drb_default;
-    uint8_t	regs[2][256], regs_locked[2][256];
+    uint8_t	regs[256], regs_locked[256];
     int		type;
 } i4x0_t;
 
@@ -137,7 +137,7 @@ i4x0_smram_handler_phase0(i4x0_t *dev)
 static void
 i4x0_smram_handler_phase1(i4x0_t *dev)
 {
-    uint8_t *regs = (uint8_t *) dev->regs[0];
+    uint8_t *regs = (uint8_t *) dev->regs;
     uint32_t tom = (mem_size << 10);
 
     uint32_t s, base[2] = { 0x000a0000, 0x00020000 };
@@ -273,8 +273,8 @@ static void
 i4x0_write(int func, int addr, uint8_t val, void *priv)
 {
     i4x0_t *dev = (i4x0_t *) priv;
-    uint8_t *regs = (uint8_t *) dev->regs[func];
-    uint8_t *regs_l = (uint8_t *) dev->regs_locked[func];
+    uint8_t *regs = (uint8_t *) dev->regs;
+    uint8_t *regs_l = (uint8_t *) dev->regs_locked;
     int i;
 
     if (func)
@@ -1256,7 +1256,7 @@ i4x0_read(int func, int addr, void *priv)
 {
     i4x0_t *dev = (i4x0_t *) priv;
     uint8_t ret = 0xff;
-    uint8_t *regs = (uint8_t *) dev->regs[func];
+    uint8_t *regs = (uint8_t *) dev->regs;
 
     if (func)
 	  ret = 0xff;
@@ -1290,15 +1290,15 @@ i4x0_reset(void *priv)
 	i4x0_write(0, 0x60 + i, dev->drb_default, priv);
 
     if (dev->type >= INTEL_430FX) {
-	dev->regs[0][0x72] &= 0xef;	/* Forcibly unlock the SMRAM register. */
+	dev->regs[0x72] &= 0xef;	/* Forcibly unlock the SMRAM register. */
 	i4x0_write(0, 0x72, 0x02, priv);
     } else {
-	dev->regs[0][0x72] &= 0xf7;	/* Forcibly unlock the SMRAM register. */
+	dev->regs[0x72] &= 0xf7;	/* Forcibly unlock the SMRAM register. */
 	i4x0_write(0, 0x72, 0x00, priv);
     }
 
     if ((dev->type == INTEL_440LX) || (dev->type == INTEL_440BX) || (dev->type == INTEL_440ZX)) {
-	memset(dev->regs_locked[0], 0x00, 256 * sizeof(uint8_t));
+	memset(dev->regs_locked, 0x00, 256 * sizeof(uint8_t));
     }
 }
 
@@ -1322,7 +1322,7 @@ static void
 
     dev->type = info->local & 0xff;
 
-    regs = (uint8_t *) dev->regs[0];
+    regs = (uint8_t *) dev->regs;
 
     regs[0x00] = 0x86; regs[0x01] = 0x80; /*Intel*/
 
diff --git a/src/chipset/via_apollo.c b/src/chipset/via_apollo.c
index 929759fe0..ec9210813 100644
--- a/src/chipset/via_apollo.c
+++ b/src/chipset/via_apollo.c
@@ -28,8 +28,8 @@
 #include <86box/mem.h>
 #include <86box/io.h>
 #include <86box/rom.h>
-#include <86box/pci.h>
 #include <86box/device.h>
+#include <86box/pci.h>
 #include <86box/keyboard.h>
 #include <86box/chipset.h>
 #include <86box/spd.h>
@@ -38,7 +38,7 @@
 typedef struct via_apollo_t
 {
     uint16_t id;
-    uint8_t pci_conf[2][256];
+    uint8_t pci_conf[256];
 } via_apollo_t;
 
 
@@ -84,80 +84,52 @@ static void
 via_apollo_setup(via_apollo_t *dev)
 {
     /* Host Bridge */
-    dev->pci_conf[0][0x00] = 0x06; /*VIA*/
-    dev->pci_conf[0][0x01] = 0x11;
-    dev->pci_conf[0][0x02] = dev->id & 0xff;
-    dev->pci_conf[0][0x03] = (dev->id >> 8);
+    dev->pci_conf[0x00] = 0x06; /*VIA*/
+    dev->pci_conf[0x01] = 0x11;
+    dev->pci_conf[0x02] = dev->id & 0xff;
+    dev->pci_conf[0x03] = (dev->id >> 8);
 
-    dev->pci_conf[0][0x04] = 6;
-    dev->pci_conf[0][0x05] = 0;
+    dev->pci_conf[0x04] = 6;
+    dev->pci_conf[0x05] = 0;
 
-    dev->pci_conf[0][0x06] = 0x90;
-    dev->pci_conf[0][0x07] = 0x02;
+    dev->pci_conf[0x06] = 0x90;
+    dev->pci_conf[0x07] = 0x02;
 
     if (dev->id == 0x0597)
-	dev->pci_conf[0][0x08] = 1;	/* Production Silicon ("Revision B") */
-    dev->pci_conf[0][0x09] = 0;
-    dev->pci_conf[0][0x0a] = 0;
-    dev->pci_conf[0][0x0b] = 6;
-    dev->pci_conf[0][0x0c] = 0;
-    dev->pci_conf[0][0x0d] = 0;
-    dev->pci_conf[0][0x0e] = 0;
-    dev->pci_conf[0][0x0f] = 0;
-    dev->pci_conf[0][0x10] = 0x08;
-    dev->pci_conf[0][0x34] = 0xa0;
+	dev->pci_conf[0x08] = 1;	/* Production Silicon ("Revision B") */
+    dev->pci_conf[0x09] = 0;
+    dev->pci_conf[0x0a] = 0;
+    dev->pci_conf[0x0b] = 6;
+    dev->pci_conf[0x0c] = 0;
+    dev->pci_conf[0x0d] = 0;
+    dev->pci_conf[0x0e] = 0;
+    dev->pci_conf[0x0f] = 0;
+    dev->pci_conf[0x10] = 0x08;
+    dev->pci_conf[0x34] = 0xa0;
 
     if (dev->id == 0x0691) {
-    	dev->pci_conf[0][0x56] = 0x01;
-	dev->pci_conf[0][0x57] = 0x01;
+    	dev->pci_conf[0x56] = 0x01;
+	dev->pci_conf[0x57] = 0x01;
     }
-    dev->pci_conf[0][0x5a] = 0x01;
-    dev->pci_conf[0][0x5b] = 0x01;
-    dev->pci_conf[0][0x5c] = 0x01;
-    dev->pci_conf[0][0x5d] = 0x01;
-    dev->pci_conf[0][0x5e] = 0x01;
-    dev->pci_conf[0][0x5f] = 0x01;
+    dev->pci_conf[0x5a] = 0x01;
+    dev->pci_conf[0x5b] = 0x01;
+    dev->pci_conf[0x5c] = 0x01;
+    dev->pci_conf[0x5d] = 0x01;
+    dev->pci_conf[0x5e] = 0x01;
+    dev->pci_conf[0x5f] = 0x01;
 
-    dev->pci_conf[0][0x64] = 0xec;
-    dev->pci_conf[0][0x65] = 0xec;
-    dev->pci_conf[0][0x66] = 0xec;
+    dev->pci_conf[0x64] = 0xec;
+    dev->pci_conf[0x65] = 0xec;
+    dev->pci_conf[0x66] = 0xec;
     if (dev->id == 0x0691)
-	dev->pci_conf[0][0x67] = 0xec;	/* DRAM Timing for Banks 6,7. */
-    dev->pci_conf[0][0x6b] = 0x01;
+	dev->pci_conf[0x67] = 0xec;	/* DRAM Timing for Banks 6,7. */
+    dev->pci_conf[0x6b] = 0x01;
 
-    dev->pci_conf[0][0xa0] = 0x02;
-    dev->pci_conf[0][0xa2] = 0x10;
-    dev->pci_conf[0][0xa4] = 0x03;
-    dev->pci_conf[0][0xa5] = 0x02;
-    dev->pci_conf[0][0xa7] = 0x07;
-
-    /* PCI-to-PCI Bridge */
-
-    dev->pci_conf[1][0x00] = 0x06; /*VIA*/
-    dev->pci_conf[1][0x01] = 0x11;
-    dev->pci_conf[1][0x02] = dev->id & 0xff;
-    dev->pci_conf[1][0x03] = (dev->id >> 8) | 0x80;
-
-    dev->pci_conf[1][0x04] = 7;
-    dev->pci_conf[1][0x05] = 0;
-
-    dev->pci_conf[1][0x06] = 0x20;
-    dev->pci_conf[1][0x07] = 0x02;
-
-    dev->pci_conf[1][0x09] = 0;
-    dev->pci_conf[1][0x0a] = 4;
-    dev->pci_conf[1][0x0b] = 6;
-    dev->pci_conf[1][0x0c] = 0;
-    dev->pci_conf[1][0x0d] = 0;
-    dev->pci_conf[1][0x0e] = 1;
-    dev->pci_conf[1][0x0f] = 0;
-
-    dev->pci_conf[1][0x1c] = 0xf0;
-
-    dev->pci_conf[1][0x20] = 0xf0;
-    dev->pci_conf[1][0x21] = 0xff;
-    dev->pci_conf[1][0x24] = 0xf0;
-    dev->pci_conf[1][0x25] = 0xff;
+    dev->pci_conf[0xa0] = 0x02;
+    dev->pci_conf[0xa2] = 0x10;
+    dev->pci_conf[0xa4] = 0x03;
+    dev->pci_conf[0xa5] = 0x02;
+    dev->pci_conf[0xa7] = 0x07;
 }
 
 
@@ -185,98 +157,98 @@ via_apollo_host_bridge_write(int func, int addr, uint8_t val, void *priv)
 
     switch(addr) {
 	case 0x04:
-		dev->pci_conf[0][0x04] = (dev->pci_conf[0][0x04] & ~0x40) | (val & 0x40);
+		dev->pci_conf[0x04] = (dev->pci_conf[0x04] & ~0x40) | (val & 0x40);
 		break;
 	case 0x07:
-		dev->pci_conf[0][0x07] &= ~(val & 0xb0);
+		dev->pci_conf[0x07] &= ~(val & 0xb0);
 		break;
 	case 0x0d:
-		dev->pci_conf[0][0x0d] = (dev->pci_conf[0][0x0d] & ~0x07) | (val & 0x07);
-		dev->pci_conf[0][0x75] = (dev->pci_conf[0][0x75] & ~0x30) | ((val & 0x06) << 3);
+		dev->pci_conf[0x0d] = (dev->pci_conf[0x0d] & ~0x07) | (val & 0x07);
+		dev->pci_conf[0x75] = (dev->pci_conf[0x75] & ~0x30) | ((val & 0x06) << 3);
 		break;
 
 	case 0x12:	/* Graphics Aperture Base */
-		dev->pci_conf[0][0x12] = (val & 0xf0);
+		dev->pci_conf[0x12] = (val & 0xf0);
 		break;
 	case 0x13:	/* Graphics Aperture Base */
-		dev->pci_conf[0][0x13] = val;
+		dev->pci_conf[0x13] = val;
 		break;
 
 	case 0x50:	/* Cache Control 1 */
 		if (dev->id == 0x0691)
-			dev->pci_conf[0][0x50] = val;
+			dev->pci_conf[0x50] = val;
 		else
-			dev->pci_conf[0][0x50] = (dev->pci_conf[0][0x50] & ~0xf8) | (val & 0xf8);
+			dev->pci_conf[0x50] = (dev->pci_conf[0x50] & ~0xf8) | (val & 0xf8);
 		break;
 	case 0x51:	/* Cache Control 2 */
 		if (dev->id == 0x0691)
-			dev->pci_conf[0][0x51] = val;
+			dev->pci_conf[0x51] = val;
 		else
-			dev->pci_conf[0][0x51] = (dev->pci_conf[0][0x51] & ~0xeb) | (val & 0xeb);
+			dev->pci_conf[0x51] = (dev->pci_conf[0x51] & ~0xeb) | (val & 0xeb);
 		break;
 	case 0x52:	/* Non_Cacheable Control */
 		if (dev->id == 0x0691)
-			dev->pci_conf[0][0x52] = (dev->pci_conf[0][0x52] & ~0x9f) | (val & 0x9f);
+			dev->pci_conf[0x52] = (dev->pci_conf[0x52] & ~0x9f) | (val & 0x9f);
 		else
-			dev->pci_conf[0][0x52] = (dev->pci_conf[0][0x52] & ~0xf5) | (val & 0xf5);
+			dev->pci_conf[0x52] = (dev->pci_conf[0x52] & ~0xf5) | (val & 0xf5);
 		break;
 	case 0x53:	/* System Performance Control */
 		if (dev->id == 0x0691)
-			dev->pci_conf[0][0x53] = val;
+			dev->pci_conf[0x53] = val;
 		else
-			dev->pci_conf[0][0x53] = (dev->pci_conf[0][0x53] & ~0xf0) | (val & 0xf0);
+			dev->pci_conf[0x53] = (dev->pci_conf[0x53] & ~0xf0) | (val & 0xf0);
 		break;
 
 	case 0x56: case 0x57: case 0x5a: case 0x5b: case 0x5c: case 0x5d: case 0x5e: case 0x5f: /* DRAM Row Ending Address */
 		if (dev->id >= 0x0691)
-			spd_write_drbs(dev->pci_conf[0], 0x5a, 0x56, 8);
+			spd_write_drbs(dev->pci_conf, 0x5a, 0x56, 8);
 		else if (addr >= 0x5a)
-			spd_write_drbs(dev->pci_conf[0], 0x5a, 0x5f, 8);
+			spd_write_drbs(dev->pci_conf, 0x5a, 0x5f, 8);
 		break;
 
 	case 0x58:
 		if (dev->id == 0x0597)
-			dev->pci_conf[0][0x58] = (dev->pci_conf[0][0x58] & ~0xee) | (val & 0xee);
+			dev->pci_conf[0x58] = (dev->pci_conf[0x58] & ~0xee) | (val & 0xee);
 		else
-			dev->pci_conf[0][0x58] = val;
+			dev->pci_conf[0x58] = val;
 		break;
 	case 0x59:
 		if (dev->id == 0x0691)
-			dev->pci_conf[0][0x59] = val;
+			dev->pci_conf[0x59] = val;
 		else
-			dev->pci_conf[0][0x59] = (dev->pci_conf[0][0x59] & ~0xf0) | (val & 0xf0);
+			dev->pci_conf[0x59] = (dev->pci_conf[0x59] & ~0xf0) | (val & 0xf0);
 		break;
 
 	case 0x61:	/* Shadow RAM Control 1 */
-		if ((dev->pci_conf[0][0x61] ^ val) & 0x03)
+		if ((dev->pci_conf[0x61] ^ val) & 0x03)
 			apollo_map(0xc0000, 0x04000, val & 0x03);
-		if ((dev->pci_conf[0][0x61] ^ val) & 0x0c)
+		if ((dev->pci_conf[0x61] ^ val) & 0x0c)
 			apollo_map(0xc4000, 0x04000, (val & 0x0c) >> 2);
-		if ((dev->pci_conf[0][0x61] ^ val) & 0x30)
+		if ((dev->pci_conf[0x61] ^ val) & 0x30)
 			apollo_map(0xc8000, 0x04000, (val & 0x30) >> 4);
-		if ((dev->pci_conf[0][0x61] ^ val) & 0xc0)
+		if ((dev->pci_conf[0x61] ^ val) & 0xc0)
 			apollo_map(0xcc000, 0x04000, (val & 0xc0) >> 6);
-		dev->pci_conf[0][0x61] = val;
+		dev->pci_conf[0x61] = val;
 		break;
 	case 0x62:	/* Shadow RAM Control 2 */
-		if ((dev->pci_conf[0][0x62] ^ val) & 0x03)
+		if ((dev->pci_conf[0x62] ^ val) & 0x03)
 			apollo_map(0xd0000, 0x04000, val & 0x03);
-		if ((dev->pci_conf[0][0x62] ^ val) & 0x0c)
+		if ((dev->pci_conf[0x62] ^ val) & 0x0c)
 			apollo_map(0xd4000, 0x04000, (val & 0x0c) >> 2);
-		if ((dev->pci_conf[0][0x62] ^ val) & 0x30)
+		if ((dev->pci_conf[0x62] ^ val) & 0x30)
 			apollo_map(0xd8000, 0x04000, (val & 0x30) >> 4);
-		if ((dev->pci_conf[0][0x62] ^ val) & 0xc0)
+		if ((dev->pci_conf[0x62] ^ val) & 0xc0)
 			apollo_map(0xdc000, 0x04000, (val & 0xc0) >> 6);
-		dev->pci_conf[0][0x62] = val;
+		dev->pci_conf[0x62] = val;
 		break;
 	case 0x63:	/* Shadow RAM Control 3 */
-		if ((dev->pci_conf[0][0x63] ^ val) & 0x30) {
+		if ((dev->pci_conf[0x63] ^ val) & 0x30) {
 			apollo_map(0xf0000, 0x10000, (val & 0x30) >> 4);
 			shadowbios = (((val & 0x30) >> 4) & 0x02);
 		}
-		if ((dev->pci_conf[0][0x63] ^ val) & 0xc0)
+		if ((dev->pci_conf[0x63] ^ val) & 0xc0)
 			apollo_map(0xe0000, 0x10000, (val & 0xc0) >> 6);
-		dev->pci_conf[0][0x63] = val;
+		dev->pci_conf[0x63] = val;
 		if (smram[0].size != 0x00000000) {
 			mem_set_mem_state_smram_ex(0, smram[0].host_base, smram[0].size, 0x00);
 			mem_set_mem_state_smram_ex(1, smram[0].host_base, smram[0].size, 0x00);
@@ -340,151 +312,91 @@ via_apollo_host_bridge_write(int func, int addr, uint8_t val, void *priv)
 		break;
 	case 0x68:
 		if (dev->id == 0x0597)
-			dev->pci_conf[0][0x68] = (dev->pci_conf[0][0x6b] & ~0xfe) | (val & 0xfe);
+			dev->pci_conf[0x68] = (dev->pci_conf[0x6b] & ~0xfe) | (val & 0xfe);
 		else if (dev->id == 0x0598)
-			dev->pci_conf[0][0x68] = val;
+			dev->pci_conf[0x68] = val;
 		else
-			dev->pci_conf[0][0x68] = (dev->pci_conf[0][0x6b] & ~0xfd) | (val & 0xfd);
+			dev->pci_conf[0x68] = (dev->pci_conf[0x6b] & ~0xfd) | (val & 0xfd);
 		break;
 	case 0x6b:
 		if (dev->id == 0x0691)
-			dev->pci_conf[0][0x6b] = (dev->pci_conf[0][0x6b] & ~0xcf) | (val & 0xcf);
+			dev->pci_conf[0x6b] = (dev->pci_conf[0x6b] & ~0xcf) | (val & 0xcf);
 		else
-			dev->pci_conf[0][0x6b] = (dev->pci_conf[0][0x6b] & ~0xc1) | (val & 0xc1);
+			dev->pci_conf[0x6b] = (dev->pci_conf[0x6b] & ~0xc1) | (val & 0xc1);
 		break;
 	case 0x6c:
 		if (dev->id == 0x0597)
-			dev->pci_conf[0][0x6c] = (dev->pci_conf[0][0x6c] & ~0x1f) | (val & 0x1f);
+			dev->pci_conf[0x6c] = (dev->pci_conf[0x6c] & ~0x1f) | (val & 0x1f);
 		else if (dev->id == 0x0598)
-			dev->pci_conf[0][0x6c] = (dev->pci_conf[0][0x6c] & ~0x7f) | (val & 0x7f);
+			dev->pci_conf[0x6c] = (dev->pci_conf[0x6c] & ~0x7f) | (val & 0x7f);
 		else
-			dev->pci_conf[0][0x6c] = val;
+			dev->pci_conf[0x6c] = val;
 		break;
 	case 0x6d:
 		if (dev->id == 0x0597)
-			dev->pci_conf[0][0x6d] = (dev->pci_conf[0][0x6d] & ~0x0f) | (val & 0x0f);
+			dev->pci_conf[0x6d] = (dev->pci_conf[0x6d] & ~0x0f) | (val & 0x0f);
 		else if (dev->id == 0x0598)
-			dev->pci_conf[0][0x6d] = (dev->pci_conf[0][0x6d] & ~0x7f) | (val & 0x7f);
+			dev->pci_conf[0x6d] = (dev->pci_conf[0x6d] & ~0x7f) | (val & 0x7f);
 		else
-			dev->pci_conf[0][0x6d] = val;
+			dev->pci_conf[0x6d] = val;
 		break;
 	case 0x6e:
-		dev->pci_conf[0][0x6e] = (dev->pci_conf[0][0x6e] & ~0xb7) | (val & 0xb7);
+		dev->pci_conf[0x6e] = (dev->pci_conf[0x6e] & ~0xb7) | (val & 0xb7);
 		break;
 
 	case 0x70:
 		if (dev->id == 0x0597)
-			dev->pci_conf[0][0x70] = (dev->pci_conf[0][0x70] & ~0xf1) | (val & 0xf1);
+			dev->pci_conf[0x70] = (dev->pci_conf[0x70] & ~0xf1) | (val & 0xf1);
 		else
-			dev->pci_conf[0][0x70] = val;
+			dev->pci_conf[0x70] = val;
 		break;
 	case 0x74:
-		dev->pci_conf[0][0x74] = (dev->pci_conf[0][0x74] & ~0xc0) | (val & 0xc0);
+		dev->pci_conf[0x74] = (dev->pci_conf[0x74] & ~0xc0) | (val & 0xc0);
 		break;
 	case 0x75:
-		dev->pci_conf[0][0x75] = (dev->pci_conf[0][0x75] & ~0xcf) | (val & 0xcf);
+		dev->pci_conf[0x75] = (dev->pci_conf[0x75] & ~0xcf) | (val & 0xcf);
 		break;
 	case 0x76:
-		dev->pci_conf[0][0x76] = (dev->pci_conf[0][0x76] & ~0xf0) | (val & 0xf0);
+		dev->pci_conf[0x76] = (dev->pci_conf[0x76] & ~0xf0) | (val & 0xf0);
 		break;
 	case 0x77:
-		dev->pci_conf[0][0x77] = (dev->pci_conf[0][0x77] & ~0xc0) | (val & 0xc0);
+		dev->pci_conf[0x77] = (dev->pci_conf[0x77] & ~0xc0) | (val & 0xc0);
 		break;
 	case 0x7e:
-		dev->pci_conf[0][0x7e] = (dev->pci_conf[0][0x7e] & ~0x3f) | (val & 0x3f);
+		dev->pci_conf[0x7e] = (dev->pci_conf[0x7e] & ~0x3f) | (val & 0x3f);
 		break;
 
 	case 0x80:
-		dev->pci_conf[0][0x80] = (dev->pci_conf[0][0x80] & ~0x8f) | (val & 0x8f);
+		dev->pci_conf[0x80] = (dev->pci_conf[0x80] & ~0x8f) | (val & 0x8f);
 		break;
 	case 0x84:
 		/* The datasheet first mentions 7-0 but then says 3-0 are reserved -
 		   - minimum of 16 MB for the graphics aperture? */
-		dev->pci_conf[0][0x84] = (dev->pci_conf[0][0x84] & ~0xf0) | (val & 0xf0);
+		dev->pci_conf[0x84] = (dev->pci_conf[0x84] & ~0xf0) | (val & 0xf0);
 		break;
 	case 0x88:
-		dev->pci_conf[0][0x88] = (dev->pci_conf[0][0x88] & ~0x07) | (val & 0x07);
+		dev->pci_conf[0x88] = (dev->pci_conf[0x88] & ~0x07) | (val & 0x07);
 		break;
 	case 0x89:
-		dev->pci_conf[0][0x89] = (dev->pci_conf[0][0x89] & ~0xf0) | (val & 0xf0);
+		dev->pci_conf[0x89] = (dev->pci_conf[0x89] & ~0xf0) | (val & 0xf0);
 		break;
 
 	case 0xa8:
-		dev->pci_conf[0][0xa8] = (dev->pci_conf[0][0xa8] & ~0x03) | (val & 0x03);
+		dev->pci_conf[0xa8] = (dev->pci_conf[0xa8] & ~0x03) | (val & 0x03);
 		break;
 	case 0xa9:
-		dev->pci_conf[0][0xa9] = (dev->pci_conf[0][0xa9] & ~0x03) | (val & 0x03);
+		dev->pci_conf[0xa9] = (dev->pci_conf[0xa9] & ~0x03) | (val & 0x03);
 		break;
 	case 0xac:
-		dev->pci_conf[0][0xac] = (dev->pci_conf[0][0xac] & ~0x0f) | (val & 0x0f);
+		dev->pci_conf[0xac] = (dev->pci_conf[0xac] & ~0x0f) | (val & 0x0f);
 		break;
 	case 0xfc:
 		if (dev->id > 0x0597)
-			dev->pci_conf[0][0xfc] = (dev->pci_conf[0][0xfc] & ~0x01) | (val & 0x01);
+			dev->pci_conf[0xfc] = (dev->pci_conf[0xfc] & ~0x01) | (val & 0x01);
 		break;
 
 	default:
-		dev->pci_conf[0][addr] = val;
-		break;
-    }
-}
-
-
-static void
-via_apollo_pci_bridge_write(int func, int addr, uint8_t val, void *priv)
-{
-    via_apollo_t *dev = (via_apollo_t *) priv;
-
-    if (func != 1)
-	return;
-
-    /*Read-only addresses*/
-
-    if ((addr < 4) || ((addr >= 5) && (addr < 7)) ||
-	((addr >= 8) && (addr < 0x18)) || (addr == 0x1b) ||
-	((addr >= 0x1e) && (addr < 0x20)) || ((addr >= 0x28) && (addr < 0x3e)) ||
-	(addr == 0x3f) || (addr >= 0x43))
-	return;
-
-    switch(addr) {
-	case 0x04:
-		dev->pci_conf[1][0x04] = (dev->pci_conf[1][0x04] & ~0x47) | (val & 0x47);
-		break;
-	case 0x07:
-		dev->pci_conf[1][0x07] &= ~(val & 0x30);
-		break;
-
-	case 0x20:	/* Memory Base */
-		dev->pci_conf[1][0x20] = val & 0xf0;
-		break;
-	case 0x22:	/* Memory Limit */
-		dev->pci_conf[1][0x22] = val & 0xf0;
-		break;
-	case 0x24:	/* Prefetchable Memory Base */
-		dev->pci_conf[1][0x24] = val & 0xf0;
-		break;
-	case 0x26:	/* Prefetchable Memory Limit */
-		dev->pci_conf[1][0x26] = val & 0xf0;
-		break;
-
-	case 0x3e:
-		dev->pci_conf[0][0x3e] = (dev->pci_conf[0][0x3e] & ~0x06) | (val & 0x06);
-		break;
-
-	case 0x41:
-		dev->pci_conf[0][0x41] = (dev->pci_conf[0][0x41] & ~0xfe) | (val & 0xfe);
-		break;
-	case 0x42:
-		if (dev->id == 0x0597)
-			dev->pci_conf[0][0x42] = (dev->pci_conf[0][0x42] & ~0xec) | (val & 0xec);
-		else if (dev->id == 0x0598)
-			dev->pci_conf[0][0x42] = (dev->pci_conf[0][0x42] & ~0xfc) | (val & 0xfc);
-		else
-			dev->pci_conf[0][0x42] = (dev->pci_conf[0][0x42] & ~0xf4) | (val & 0xf4);
-		break;
-
-	default:
-		dev->pci_conf[1][addr] = val;
+		dev->pci_conf[addr] = val;
 		break;
     }
 }
@@ -498,10 +410,7 @@ via_apollo_read(int func, int addr, void *priv)
 
     switch(func) {
         case 0:
-		ret = dev->pci_conf[0][addr];
-		break;
-        case 1:
-		ret = dev->pci_conf[1][addr];
+		ret = dev->pci_conf[addr];
 		break;
     }
 
@@ -516,9 +425,6 @@ via_apollo_write(int func, int addr, uint8_t val, void *priv)
 	case 0:
 		via_apollo_host_bridge_write(func, addr, val, priv);
 		break;
-	case 1:
-		via_apollo_pci_bridge_write(func, addr, val, priv);
-		break;
     }
 }
 
@@ -541,6 +447,14 @@ via_apollo_init(const device_t *info)
     pci_add_card(PCI_ADD_NORTHBRIDGE, via_apollo_read, via_apollo_write, dev);
 
     dev->id = info->local;
+
+    if (dev->id == 0x0597)
+    	device_add(&via_vp3_agp_device);
+    else if (dev->id == 0x0598)
+    	device_add(&via_mvp3_agp_device);
+    else if (dev->id == 0x0691)
+    	device_add(&via_apro_agp_device);
+
     via_apollo_setup(dev);
     via_apollo_reset(dev);
 
diff --git a/src/device/pci_bridge.c b/src/device/pci_bridge.c
index 367e36834..e459aa009 100644
--- a/src/device/pci_bridge.c
+++ b/src/device/pci_bridge.c
@@ -36,7 +36,12 @@
 #define AGP_BRIDGE_INTEL_440LX	0x80867181
 #define AGP_BRIDGE_INTEL_440BX	0x80867191
 #define AGP_BRIDGE_INTEL_440GX	0x808671a1
-#define AGP_BRIDGE(x)		((x) >= AGP_BRIDGE_INTEL_440LX)
+#define AGP_BRIDGE_VIA_597	0x11068597
+#define AGP_BRIDGE_VIA_598	0x11068598
+#define AGP_BRIDGE_VIA_691	0x11068691
+
+#define AGP_BRIDGE_VIA(x)	(((x) >> 4) == 0x1106)
+#define AGP_BRIDGE(x)		((x) >= AGP_BRIDGE_VIA_597)
 
 
 typedef struct
@@ -97,6 +102,12 @@ pci_bridge_write(int func, int addr, uint8_t val, void *priv)
 		val &= 0x03;
 		break;
 
+	case 0x18:
+		/* Parent bus number is always 0 on AGP bridges. */
+		if (AGP_BRIDGE(dev->local))
+			return;
+		break;
+
 	case 0x19:
 		/* Set our bus number. */
 		pci_bridge_log("PCI Bridge %d: switching from bus %02X to %02X\n", dev->bus_index, dev->regs[addr], val);
@@ -112,31 +123,53 @@ pci_bridge_write(int func, int addr, uint8_t val, void *priv)
 		break;
 
 	case 0x3e:
-		val &= 0xef;
+		if (AGP_BRIDGE_VIA(dev->local))
+			val &= 0x0c;
+		else if (AGP_BRIDGE(dev->local))
+			val &= 0x0f;
+		else if (dev->local == PCI_BRIDGE_DEC_21150)
+			val &= 0xef;
 		break;
 
 	case 0x3f:
-		val &= 0x0f;
+		if (dev->local == AGP_BRIDGE_INTEL_440LX)
+			val &= 0x02;
+		else if (AGP_BRIDGE(dev->local))
+			return;
+		else if (dev->local == PCI_BRIDGE_DEC_21150)
+			val &= 0x0f;
 		break;
 
 	case 0x40:
-		val &= 0x32;
+		if (dev->local == PCI_BRIDGE_DEC_21150)
+			val &= 0x32;
 		break;
 
 	case 0x41:
-		val &= 0x07;
+		if (AGP_BRIDGE_VIA(dev->local))
+			val &= 0x7e;
+		else if (dev->local == PCI_BRIDGE_DEC_21150)
+			val &= 0x07;
+		break;
+
+	case 0x42:
+		if (AGP_BRIDGE_VIA(dev->local))
+			val &= 0xfe;
 		break;
 
 	case 0x43:
-		val &= 0x03;
+		if (dev->local == PCI_BRIDGE_DEC_21150)
+			val &= 0x03;
 		break;
 
 	case 0x64:
-		val &= 0x7e;
+		if (dev->local == PCI_BRIDGE_DEC_21150)
+			val &= 0x7e;
 		break;
 
 	case 0x69:
-		val &= 0x3f;
+		if (dev->local == PCI_BRIDGE_DEC_21150)
+			val &= 0x3f;
 		break;
     }
 
@@ -167,6 +200,8 @@ pci_bridge_reset(void *priv)
 
     pci_bridge_log("PCI Bridge %d: reset()\n", dev->bus_index);
 
+    memset(dev->regs, 0, sizeof(dev->regs));
+
     /* IDs */
     dev->regs[0x00] = dev->local >> 16;
     dev->regs[0x01] = dev->local >> 24;
@@ -190,6 +225,13 @@ pci_bridge_reset(void *priv)
 		dev->regs[0x06] = 0x20;
 		dev->regs[0x07] = dev->regs[0x08] = 0x02;
 		break;
+
+	case AGP_BRIDGE_VIA_597:
+	case AGP_BRIDGE_VIA_691:
+		dev->regs[0x04] = 0x07;
+		dev->regs[0x06] = 0x20;
+		dev->regs[0x07] = 0x02;
+		break;
     }
 
     dev->regs[0x0a] = 0x04; /* PCI-PCI bridge */
@@ -204,8 +246,10 @@ pci_bridge_reset(void *priv)
 	dev->regs[0x1c] = dev->regs[0x1d] = 0x01;
     }
 
-    dev->regs[0x1e] = AGP_BRIDGE(dev->local) ? 0xa0 : 0x80;
-    dev->regs[0x1f] = 0x02;
+    if (!AGP_BRIDGE_VIA(dev->local)) {
+	dev->regs[0x1e] = AGP_BRIDGE(dev->local) ? 0xa0 : 0x80;
+	dev->regs[0x1f] = 0x02;
+    }
 
     /* prefetchable memory limits */
     if (AGP_BRIDGE(dev->local)) {
@@ -323,3 +367,45 @@ const device_t i440gx_agp_device =
     NULL,
     NULL
 };
+
+const device_t via_vp3_agp_device =
+{
+    "VIA Apollo VP3 AGP Bridge",
+    DEVICE_PCI,
+    AGP_BRIDGE_VIA_597,
+    pci_bridge_init,
+    NULL,
+    pci_bridge_reset,
+    NULL,
+    NULL,
+    NULL,
+    NULL
+};
+
+const device_t via_mvp3_agp_device =
+{
+    "VIA Apollo MVP3 AGP Bridge",
+    DEVICE_PCI,
+    AGP_BRIDGE_VIA_598,
+    pci_bridge_init,
+    NULL,
+    pci_bridge_reset,
+    NULL,
+    NULL,
+    NULL,
+    NULL
+};
+
+const device_t via_apro_agp_device =
+{
+    "VIA Apollo Pro AGP Bridge",
+    DEVICE_PCI,
+    AGP_BRIDGE_VIA_691,
+    pci_bridge_init,
+    NULL,
+    pci_bridge_reset,
+    NULL,
+    NULL,
+    NULL,
+    NULL
+};
diff --git a/src/include/86box/pci.h b/src/include/86box/pci.h
index 131471cb0..361231b7c 100644
--- a/src/include/86box/pci.h
+++ b/src/include/86box/pci.h
@@ -122,6 +122,9 @@ extern const device_t dec21150_device;
 extern const device_t i440lx_agp_device;
 extern const device_t i440bx_agp_device;
 extern const device_t i440gx_agp_device;
+extern const device_t via_vp3_agp_device;
+extern const device_t via_mvp3_agp_device;
+extern const device_t via_apro_agp_device;
 #endif