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Added the CMD640 (but the associated PB520R is not yet properly done, needs the 82091AA, so it's disabled until I implement it), fixed initialization of the IDE registers on the SMSC southbridge, bumped up the number of emulated serial ports to 4 (was 2), and added the ability to properly have multiple W83977's on a single machine.

Browse Source
This commit is contained in:
OBattler
2020-07-08 04:24:25 +02:00
parent 4bb10138d9
commit f696dc69ad
14 changed files with 634 additions and 40 deletions
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5
src/chipset/intel_piix.c
View File

@@ -1040,7 +1040,10 @@ piix_reset_hard(piix_t *dev)
fregs[0x09] = 0x80; fregs[0x09] = 0x80;
fregs[0x0a] = 0x01; fregs[0x0b] = 0x01; fregs[0x0a] = 0x01; fregs[0x0b] = 0x01;
if (dev->type == 5) { if (dev->type == 5) {
fregs[0x10] = fregs[0x14] = fregs[0x18] = fregs[0x1c] = 0x01; fregs[0x10] = 0xf1; fregs[0x11] = 0x01;
fregs[0x14] = 0xf5; fregs[0x15] = 0x03;
fregs[0x18] = 0x71; fregs[0x19] = 0x01;
fregs[0x1c] = 0x75; fregs[0x1d] = 0x03;
} }
fregs[0x20] = 0x01; fregs[0x20] = 0x01;
if (dev->type == 5) { if (dev->type == 5) {

6
src/config.c
View File

@@ -745,7 +745,7 @@ load_ports(void)
char temp[512]; char temp[512];
int c, d; int c, d;
for (c = 0; c < 2; c++) { for (c = 0; c < 4; c++) {
sprintf(temp, "serial%d_enabled", c + 1); sprintf(temp, "serial%d_enabled", c + 1);
serial_enabled[c] = !!config_get_int(cat, temp, 1); serial_enabled[c] = !!config_get_int(cat, temp, 1);
} }
@@ -1352,6 +1352,8 @@ config_load(void)
hdc_current = hdc_get_from_internal_name("none"); hdc_current = hdc_get_from_internal_name("none");
serial_enabled[0] = 1; serial_enabled[0] = 1;
serial_enabled[1] = 1; serial_enabled[1] = 1;
serial_enabled[2] = 0;
serial_enabled[3] = 0;
lpt_ports[0].enabled = 1; lpt_ports[0].enabled = 1;
lpt_ports[1].enabled = 0; lpt_ports[1].enabled = 0;
lpt_ports[2].enabled = 0; lpt_ports[2].enabled = 0;
@@ -1709,7 +1711,7 @@ save_ports(void)
char temp[512]; char temp[512];
int c, d; int c, d;
for (c = 0; c < 2; c++) { for (c = 0; c < 4; c++) {
sprintf(temp, "serial%d_enabled", c + 1); sprintf(temp, "serial%d_enabled", c + 1);
if (serial_enabled[c]) if (serial_enabled[c])
config_delete_var(cat, temp); config_delete_var(cat, temp);

19
src/device/serial.c
View File

@@ -684,9 +684,13 @@ serial_init(const device_t *info)
dev->sd = &(serial_devices[next_inst]); dev->sd = &(serial_devices[next_inst]);
dev->sd->serial = dev; dev->sd->serial = dev;
serial_reset_port(dev); serial_reset_port(dev);
if (next_inst || (info->flags & DEVICE_PCJR)) if (next_inst == 3)
serial_setup(dev, SERIAL4_ADDR, SERIAL4_IRQ);
else if (next_inst == 2)
serial_setup(dev, SERIAL3_ADDR, SERIAL3_IRQ);
else if ((next_inst == 1) || (info->flags & DEVICE_PCJR))
serial_setup(dev, SERIAL2_ADDR, SERIAL2_IRQ); serial_setup(dev, SERIAL2_ADDR, SERIAL2_IRQ);
else else if (next_inst == 0)
serial_setup(dev, SERIAL1_ADDR, SERIAL1_IRQ); serial_setup(dev, SERIAL1_ADDR, SERIAL1_IRQ);
/* Default to 1200,N,7. */ /* Default to 1200,N,7. */
@@ -716,8 +720,17 @@ serial_standalone_init(void) {
if (next_inst == 0) { if (next_inst == 0) {
device_add_inst(&i8250_device, 1); device_add_inst(&i8250_device, 1);
device_add_inst(&i8250_device, 2); device_add_inst(&i8250_device, 2);
} else if (next_inst == 1) device_add_inst(&i8250_device, 3);
device_add_inst(&i8250_device, 4);
} else if (next_inst == 1) {
device_add_inst(&i8250_device, 2); device_add_inst(&i8250_device, 2);
device_add_inst(&i8250_device, 3);
device_add_inst(&i8250_device, 4);
} else if (next_inst == 2) {
device_add_inst(&i8250_device, 3);
device_add_inst(&i8250_device, 4);
} else
device_add_inst(&i8250_device, 4);
}; };

462
src/disk/hdc_ide_cmd640.c Normal file
View File

@@ -0,0 +1,462 @@
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the CMD PCI-0640B controller.
* Authors: Miran Grca, <mgrca8@gmail.com>
*
* Copyright 2020 Miran Grca.
*/
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/cdrom.h>
#include <86box/scsi_device.h>
#include <86box/scsi_cdrom.h>
#include <86box/dma.h>
#include <86box/io.h>
#include <86box/device.h>
#include <86box/keyboard.h>
#include <86box/mem.h>
#include <86box/pci.h>
#include <86box/pic.h>
#include <86box/timer.h>
#include <86box/hdc.h>
#include <86box/hdc_ide.h>
#include <86box/hdc_ide_sff8038i.h>
#include <86box/zip.h>
typedef struct
{
uint8_t vlb_idx, id,
in_cfg,
regs[256];
int slot, irq_mode[2],
irq_pin, irq_line;
} cmd640_t;
static int next_id = 0;
void
cmd640_set_irq(int channel, void *priv)
{
cmd640_t *dev = (cmd640_t *) priv;
dev->regs[0x50] &= ~0x04;
dev->regs[0x50] |= (channel >> 4);
channel &= 0x01;
if (dev->regs[0x50] & 0x04) {
if (dev->irq_mode[channel] == 1)
pci_set_irq(dev->slot, dev->irq_pin);
else
picint(1 << (14 + channel));
} else {
if (dev->irq_mode[channel] == 1)
pci_clear_irq(dev->slot, dev->irq_pin);
else
picintc(1 << (14 + channel));
}
}
static void
cmd640_ide_handlers(cmd640_t *dev)
{
uint16_t main, side;
ide_pri_disable();
if ((dev->regs[0x09] & 0x01) && (dev->regs[0x50] & 0x40)) {
main = (dev->regs[0x11] << 8) | (dev->regs[0x10] & 0xf8);
side = ((dev->regs[0x15] << 8) | (dev->regs[0x14] & 0xfc)) + 2;
} else {
main = 0x1f0;
side = 0x3f6;
}
ide_set_base(0, main);
ide_set_side(0, side);
if (dev->regs[0x04] & 0x01)
ide_pri_enable();
ide_sec_disable();
if ((dev->regs[0x09] & 0x04) && (dev->regs[0x50] & 0x40)) {
main = (dev->regs[0x19] << 8) | (dev->regs[0x18] & 0xf8);
side = ((dev->regs[0x1d] << 8) | (dev->regs[0x1c] & 0xfc)) + 2;
} else {
main = 0x170;
side = 0x376;
}
ide_set_base(1, main);
ide_set_side(1, side);
if ((dev->regs[0x04] & 0x01) && (dev->regs[0x51] & 0x08))
ide_sec_enable();
}
static void
cmd640_common_write(int addr, uint8_t val, cmd640_t *dev)
{
switch (addr) {
case 0x51:
dev->regs[addr] = val;
cmd640_ide_handlers(dev);
break;
case 0x52: case 0x54: case 0x56: case 0x58:
case 0x59:
dev->regs[addr] = val;
break;
case 0x53: case 0x55:
dev->regs[addr] = val & 0xc0;
break;
case 0x57:
dev->regs[addr] = val & 0xdc;
break;
}
}
static void
cmd640_vlb_write(uint16_t addr, uint8_t val, void *priv)
{
cmd640_t *dev = (cmd640_t *) priv;
addr &= 0x00ff;
switch (addr) {
case 0x0078:
if (dev->in_cfg)
dev->vlb_idx = val;
else if ((dev->regs[0x50] & 0x80) && (val == dev->id))
dev->in_cfg = 1;
break;
case 0x007c:
cmd640_common_write(dev->vlb_idx, val, dev);
if (dev->regs[0x50] & 0x80)
dev->in_cfg = 0;
break;
}
}
static void
cmd640_vlb_writew(uint16_t addr, uint16_t val, void *priv)
{
cmd640_vlb_write(addr, val & 0xff, priv);
cmd640_vlb_write(addr + 1, val >> 8, priv);
}
static void
cmd640_vlb_writel(uint16_t addr, uint32_t val, void *priv)
{
cmd640_vlb_writew(addr, val & 0xffff, priv);
cmd640_vlb_writew(addr + 2, val >> 16, priv);
}
static uint8_t
cmd640_vlb_read(uint16_t addr, void *priv)
{
uint8_t ret = 0xff;
cmd640_t *dev = (cmd640_t *) priv;
addr &= 0x00ff;
switch (addr) {
case 0x0078:
if (dev->in_cfg)
ret = dev->vlb_idx;
break;
case 0x007c:
ret = dev->regs[dev->vlb_idx];
if (dev->vlb_idx == 0x50)
dev->regs[0x50] &= ~0x04;
if (dev->regs[0x50] & 0x80)
dev->in_cfg = 0;
break;
}
return ret;
}
static uint16_t
cmd640_vlb_readw(uint16_t addr, void *priv)
{
uint16_t ret = 0xffff;
ret = cmd640_vlb_read(addr, priv);
ret |= (cmd640_vlb_read(addr + 1, priv) << 8);
return ret;
}
static uint32_t
cmd640_vlb_readl(uint16_t addr, void *priv)
{
uint32_t ret = 0xffffffff;
ret = cmd640_vlb_readw(addr, priv);
ret |= (cmd640_vlb_readw(addr + 2, priv) << 16);
return ret;
}
static void
cmd640_pci_write(int func, int addr, uint8_t val, void *priv)
{
cmd640_t *dev = (cmd640_t *) priv;
if (func == 0x00) switch (addr) {
case 0x04:
dev->regs[addr] = (val & 0x41);
cmd640_ide_handlers(dev);
break;
case 0x07:
dev->regs[addr] &= ~(val & 0x80);
break;
case 0x09:
if ((dev->regs[addr] & 0x0a) == 0x0a) {
dev->regs[addr] = (dev->regs[addr] & 0x0a) | (val & 0x05);
dev->irq_mode[0] = !!(val & 0x01);
dev->irq_mode[1] = !!(val & 0x04);
cmd640_ide_handlers(dev);
}
break;
case 0x10:
if (dev->regs[0x50] & 0x40) {
dev->regs[0x10] = (val & 0xf8) | 1;
cmd640_ide_handlers(dev);
}
break;
case 0x11:
if (dev->regs[0x50] & 0x40) {
dev->regs[0x11] = val;
cmd640_ide_handlers(dev);
}
break;
case 0x14:
if (dev->regs[0x50] & 0x40) {
dev->regs[0x14] = (val & 0xfc) | 1;
cmd640_ide_handlers(dev);
}
break;
case 0x15:
if (dev->regs[0x50] & 0x40) {
dev->regs[0x15] = val;
cmd640_ide_handlers(dev);
}
break;
case 0x18:
if (dev->regs[0x50] & 0x40) {
dev->regs[0x18] = (val & 0xf8) | 1;
cmd640_ide_handlers(dev);
}
break;
case 0x19:
if (dev->regs[0x50] & 0x40) {
dev->regs[0x19] = val;
cmd640_ide_handlers(dev);
}
break;
case 0x1c:
if (dev->regs[0x50] & 0x40) {
dev->regs[0x1c] = (val & 0xfc) | 1;
cmd640_ide_handlers(dev);
}
break;
case 0x1d:
if (dev->regs[0x50] & 0x40) {
dev->regs[0x1d] = val;
cmd640_ide_handlers(dev);
}
break;
default:
cmd640_common_write(addr, val, dev);
break;
}
}
static uint8_t
cmd640_pci_read(int func, int addr, void *priv)
{
cmd640_t *dev = (cmd640_t *) priv;
uint8_t ret = 0xff;
if (func == 0x00) {
ret = dev->regs[addr];
if (addr == 0x50)
dev->regs[0x50] &= ~0x04;
}
return ret;
}
static void
cmd640_reset(void *p)
{
int i = 0;
for (i = 0; i < CDROM_NUM; i++) {
if ((cdrom[i].bus_type == CDROM_BUS_ATAPI) &&
(cdrom[i].ide_channel < 4) && cdrom[i].priv)
scsi_cdrom_reset((scsi_common_t *) cdrom[i].priv);
}
for (i = 0; i < ZIP_NUM; i++) {
if ((zip_drives[i].bus_type == ZIP_BUS_ATAPI) &&
(zip_drives[i].ide_channel < 4) && zip_drives[i].priv)
zip_reset((scsi_common_t *) zip_drives[i].priv);
}
cmd640_set_irq(0x00, p);
cmd640_set_irq(0x01, p);
}
static void
cmd640_close(void *priv)
{
cmd640_t *dev = (cmd640_t *) priv;
free(dev);
next_id = 0;
}
static void *
cmd640_init(const device_t *info)
{
cmd640_t *dev = (cmd640_t *) malloc(sizeof(cmd640_t));
memset(dev, 0x00, sizeof(cmd640_t));
dev->id = next_id | 0x60;
dev->regs[0x50] = 0x02; /* Revision 02 */
dev->regs[0x50] |= (next_id << 3); /* Device ID: 00 = 60h, 01 = 61h, 10 = 62h, 11 = 63h */
dev->regs[0x59] = 0x40;
if (info->flags & DEVICE_PCI) {
if (info->local == 0x0a) {
dev->regs[0x50] |= 0x40; /* Enable Base address register R/W;
If 0, they return 0 and are read-only 8 */
}
dev->regs[0x00] = 0x95; /* CMD */
dev->regs[0x01] = 0x10;
dev->regs[0x02] = 0x40; /* PCI-0640B */
dev->regs[0x03] = 0x06;
dev->regs[0x07] = 0x02; /* DEVSEL timing: 01 medium */
dev->regs[0x08] = 0x02; /* Revision 02 */
dev->regs[0x09] = info->local; /* Programming interface */
dev->regs[0x0a] = 0x01; /* IDE controller */
dev->regs[0x0b] = 0x01; /* Mass storage controller */
/* Base addresses (1F0, 3F4, 170, 374) */
if (dev->regs[0x50] & 0x40) {
dev->regs[0x10] = 0xf1; dev->regs[0x11] = 0x01;
dev->regs[0x14] = 0xf5; dev->regs[0x15] = 0x03;
dev->regs[0x18] = 0x71; dev->regs[0x19] = 0x01;
dev->regs[0x1c] = 0x75; dev->regs[0x1d] = 0x03;
}
dev->regs[0x3c] = 0x14; /* IRQ 14 */
dev->regs[0x3d] = 0x01; /* INTA */
device_add(&ide_vlb_2ch_device);
dev->slot = pci_add_card(PCI_ADD_NORMAL, cmd640_pci_read, cmd640_pci_write, dev);
dev->irq_mode[0] = dev->irq_mode[1] = 0;
dev->irq_pin = PCI_INTA;
dev->irq_line = 14;
ide_set_bus_master(0, NULL, cmd640_set_irq, dev);
ide_set_bus_master(1, NULL, cmd640_set_irq, dev);
/* The CMD PCI-0640B IDE controller has no DMA capability,
so set our devices IDE devices to force ATA-3 (no DMA). */
ide_board_set_force_ata3(0, 1);
ide_board_set_force_ata3(1, 1);
ide_pri_disable();
} else if (info->flags & DEVICE_VLB) {
if (info->local == 0x0078)
dev->regs[0x50] |= 0x20; /* 0 = 178h, 17Ch; 1 = 078h, 07Ch */
/* If bit 7 is 1, then device ID has to be written on port x78h before
accessing the configuration registers */
dev->in_cfg = 1; /* Configuration register are accessible */
device_add(&ide_pci_2ch_device);
io_sethandler(0x0078, 0x0008,
cmd640_vlb_read, cmd640_vlb_readw, cmd640_vlb_readl,
cmd640_vlb_write, cmd640_vlb_writew, cmd640_vlb_writel,
dev);
}
ide_sec_disable();
next_id++;
return dev;
}
const device_t ide_cmd640_vlb_device = {
"CMD PCI-0640B VLB",
DEVICE_VLB,
0x0078,
cmd640_init, cmd640_close, NULL,
NULL, NULL, NULL,
NULL
};
const device_t ide_cmd640_vlb_178_device = {
"CMD PCI-0640B VLB (Port 178h)",
DEVICE_VLB,
0x0178,
cmd640_init, cmd640_close, NULL,
NULL, NULL, NULL,
NULL
};
const device_t ide_cmd640_pci_device = {
"CMD PCI-0640B PCI",
DEVICE_PCI,
0x0a,
cmd640_init, cmd640_close, cmd640_reset,
NULL, NULL, NULL,
NULL
};
const device_t ide_cmd640_pci_legacy_only_device = {
"CMD PCI-0640B PCI (Legacy Mode Only)",
DEVICE_PCI,
0x00,
cmd640_init, cmd640_close, cmd640_reset,
NULL, NULL, NULL,
NULL
};

4
src/include/86box/86box.h
View File

@@ -21,8 +21,8 @@
/* Configuration values. */ /* Configuration values. */
#define SERIAL_MAX 2 #define SERIAL_MAX 4
#define PARALLEL_MAX 1 #define PARALLEL_MAX 3
#define SCREEN_RES_X 640 #define SCREEN_RES_X 640
#define SCREEN_RES_Y 480 #define SCREEN_RES_Y 480

5
src/include/86box/hdc.h
View File

@@ -50,6 +50,11 @@ extern const device_t ide_vlb_2ch_device; /* vlb_ide_2ch */
extern const device_t ide_pci_device; /* pci_ide */ extern const device_t ide_pci_device; /* pci_ide */
extern const device_t ide_pci_2ch_device; /* pci_ide_2ch */ extern const device_t ide_pci_2ch_device; /* pci_ide_2ch */
extern const device_t ide_cmd640_vlb_device; /* CMD PCI-640B VLB */
extern const device_t ide_cmd640_vlb_178_device; /* CMD PCI-640B VLB (Port 178h) */
extern const device_t ide_cmd640_pci_device; /* CMD PCI-640B PCI */
extern const device_t ide_cmd640_pci_legacy_only_device; /* CMD PCI-640B PCI (Legacy Mode Only) */
extern const device_t ide_opti611_vlb_device; /* OPTi 82c611/611A VLB */ extern const device_t ide_opti611_vlb_device; /* OPTi 82c611/611A VLB */
extern const device_t ide_ter_device; extern const device_t ide_ter_device;

8
src/include/86box/resource.h
View File

@@ -164,9 +164,11 @@
#define IDC_COMBO_LPT3 1112 #define IDC_COMBO_LPT3 1112
#define IDC_CHECK_SERIAL1 1113 #define IDC_CHECK_SERIAL1 1113
#define IDC_CHECK_SERIAL2 1114 #define IDC_CHECK_SERIAL2 1114
#define IDC_CHECK_PARALLEL1 1115 #define IDC_CHECK_SERIAL3 1115
#define IDC_CHECK_PARALLEL2 1116 #define IDC_CHECK_SERIAL4 1116
#define IDC_CHECK_PARALLEL3 1117 #define IDC_CHECK_PARALLEL1 1117
#define IDC_CHECK_PARALLEL2 1118
#define IDC_CHECK_PARALLEL3 1119
#define IDC_OTHER_PERIPH 1120 /* other periph config */ #define IDC_OTHER_PERIPH 1120 /* other periph config */
#define IDC_COMBO_SCSI 1121 #define IDC_COMBO_SCSI 1121

4
src/include/86box/serial.h
View File

@@ -32,6 +32,10 @@
#define SERIAL1_IRQ 4 #define SERIAL1_IRQ 4
#define SERIAL2_ADDR 0x02f8 #define SERIAL2_ADDR 0x02f8
#define SERIAL2_IRQ 3 #define SERIAL2_IRQ 3
#define SERIAL3_ADDR 0x03e8
#define SERIAL3_IRQ 4
#define SERIAL4_ADDR 0x02e8
#define SERIAL4_IRQ 3
struct serial_device_s; struct serial_device_s;

35
src/machine/m_at_socket4_5.c
View File

@@ -160,6 +160,38 @@ machine_at_valuepointp60_init(const machine_t *model)
} }
#endif #endif
int
machine_at_pb502r_init(const machine_t *model)
{
int ret;
ret = bios_load_linear_combined(L"roms/machines/revenge/1009af2_.bio",
L"roms/machines/revenge/1009af2_.bi1", 0x1c000, 128);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_2 | PCI_NO_IRQ_STEERING);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x01, PCI_CARD_SPECIAL, 0, 0, 0, 0);
pci_register_slot(0x06, PCI_CARD_NORMAL, 3, 2, 1, 4);
pci_register_slot(0x0E, PCI_CARD_NORMAL, 2, 1, 3, 4);
pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 3, 2, 4);
pci_register_slot(0x02, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
device_add(&i430lx_device);
device_add(&keyboard_ps2_pci_device);
device_add(&sio_device);
device_add(&ide_cmd640_pci_device);
device_add(&fdc37c665_device);
device_add(&intel_flash_bxt_device);
return ret;
}
int int
machine_at_opti560l_init(const machine_t *model) machine_at_opti560l_init(const machine_t *model)
{ {
@@ -190,6 +222,7 @@ machine_at_opti560l_init(const machine_t *model)
return ret; return ret;
} }
#if defined(DEV_BRANCH) && defined(USE_DELLXP60) #if defined(DEV_BRANCH) && defined(USE_DELLXP60)
int int
machine_at_dellxp60_init(const machine_t *model) // Doesn't like the regular SMC 665 machine_at_dellxp60_init(const machine_t *model) // Doesn't like the regular SMC 665
@@ -222,6 +255,7 @@ machine_at_dellxp60_init(const machine_t *model) // Doesn't like the regular SMC
} }
#endif #endif
int int
machine_at_p5mp3_init(const machine_t *model) machine_at_p5mp3_init(const machine_t *model)
{ {
@@ -252,6 +286,7 @@ machine_at_p5mp3_init(const machine_t *model)
return ret; return ret;
} }
int int
machine_at_586mc1_init(const machine_t *model) machine_at_586mc1_init(const machine_t *model)
{ {

3
src/machine/machine_table.c
View File

@@ -250,6 +250,9 @@ const machine_t machines[] = {
#endif #endif
{ "[i430LX] ASUS P/I-P5MP3", "p5mp3", MACHINE_TYPE_SOCKET4, {{"Intel", cpus_Pentium5V}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 2, 192, 2, 127, machine_at_p5mp3_init, NULL }, { "[i430LX] ASUS P/I-P5MP3", "p5mp3", MACHINE_TYPE_SOCKET4, {{"Intel", cpus_Pentium5V}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 2, 192, 2, 127, machine_at_p5mp3_init, NULL },
{ "[i430LX] Micro Star 586MC1", "586mc1", MACHINE_TYPE_SOCKET4, {{"Intel", cpus_Pentium5V}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 2, 128, 2, 127, machine_at_586mc1_init, NULL }, { "[i430LX] Micro Star 586MC1", "586mc1", MACHINE_TYPE_SOCKET4, {{"Intel", cpus_Pentium5V}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 2, 128, 2, 127, machine_at_586mc1_init, NULL },
#ifdef UNFINISHED
{ "[i430LX] Packard Bell PB520R", "pb520r", MACHINE_TYPE_SOCKET4, {{"Intel", cpus_Pentium5V}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC | MACHINE_VIDEO, 2, 128, 2, 127, machine_at_pb520r_init, at_pb520r_get_device },
#endif
/* Socket 5 machines */ /* Socket 5 machines */
/* 430NX */ /* 430NX */

94
src/sio/sio_w83977f.c
View File

@@ -39,7 +39,8 @@
typedef struct { typedef struct {
uint8_t tries, regs[48], uint8_t id, tries,
regs[48],
dev_regs[256][208]; dev_regs[256][208];
int locked, rw_locked, int locked, rw_locked,
cur_reg, base_address, cur_reg, base_address,
@@ -49,6 +50,9 @@ typedef struct {
} w83977f_t; } w83977f_t;
static int next_id = 0;
static void w83977f_write(uint16_t port, uint8_t val, void *priv); static void w83977f_write(uint16_t port, uint8_t val, void *priv);
static uint8_t w83977f_read(uint16_t port, void *priv); static uint8_t w83977f_read(uint16_t port, void *priv);
@@ -86,6 +90,9 @@ w83977f_fdc_handler(w83977f_t *dev)
{ {
uint16_t io_base = (dev->dev_regs[0][0x30] << 8) | dev->dev_regs[0][0x31]; uint16_t io_base = (dev->dev_regs[0][0x30] << 8) | dev->dev_regs[0][0x31];
if (dev->id == 1)
return;
fdc_remove(dev->fdc); fdc_remove(dev->fdc);
if ((dev->dev_regs[0][0x00] & 0x01) && (dev->regs[0x22] & 0x01) && (io_base >= 0x100) && (io_base <= 0xff8)) if ((dev->dev_regs[0][0x00] & 0x01) && (dev->regs[0x22] & 0x01) && (io_base >= 0x100) && (io_base <= 0xff8))
@@ -105,12 +112,21 @@ w83977f_lpt_handler(w83977f_t *dev)
if (io_len == 8) if (io_len == 8)
io_mask = 0xff8; io_mask = 0xff8;
lpt1_remove(); if (dev->id == 1) {
lpt2_remove();
if ((dev->dev_regs[1][0x00] & 0x01) && (dev->regs[0x22] & 0x08) && (io_base >= 0x100) && (io_base <= io_mask)) if ((dev->dev_regs[1][0x00] & 0x01) && (dev->regs[0x22] & 0x08) && (io_base >= 0x100) && (io_base <= io_mask))
lpt1_init(io_base); lpt2_init(io_base);
lpt1_irq(dev->dev_regs[1][0x40] & 0x0f); lpt2_irq(dev->dev_regs[1][0x40] & 0x0f);
} else {
lpt1_remove();
if ((dev->dev_regs[1][0x00] & 0x01) && (dev->regs[0x22] & 0x08) && (io_base >= 0x100) && (io_base <= io_mask))
lpt1_init(io_base);
lpt1_irq(dev->dev_regs[1][0x40] & 0x0f);
}
} }
@@ -249,6 +265,9 @@ w83977f_write(uint16_t port, uint8_t val, void *priv)
case 0xf0: case 0xf0:
switch (ld) { switch (ld) {
case 0x00: case 0x00:
if (dev->id == 1)
break;
if (valxor & 0x20) if (valxor & 0x20)
fdc_update_drv2en(dev->fdc, (val & 0x20) ? 0 : 1); fdc_update_drv2en(dev->fdc, (val & 0x20) ? 0 : 1);
if (valxor & 0x10) if (valxor & 0x10)
@@ -269,6 +288,9 @@ w83977f_write(uint16_t port, uint8_t val, void *priv)
case 0xf1: case 0xf1:
switch (ld) { switch (ld) {
case 0x00: case 0x00:
if (dev->id == 1)
break;
if (valxor & 0xc0) if (valxor & 0xc0)
fdc_update_boot_drive(dev->fdc, (val & 0xc0) >> 6); fdc_update_boot_drive(dev->fdc, (val & 0xc0) >> 6);
if (valxor & 0x0c) if (valxor & 0x0c)
@@ -283,6 +305,9 @@ w83977f_write(uint16_t port, uint8_t val, void *priv)
case 0xf2: case 0xf2:
switch (ld) { switch (ld) {
case 0x00: case 0x00:
if (dev->id == 1)
break;
if (valxor & 0xc0) if (valxor & 0xc0)
fdc_update_rwc(dev->fdc, 3, (val & 0xc0) >> 6); fdc_update_rwc(dev->fdc, 3, (val & 0xc0) >> 6);
if (valxor & 0x30) if (valxor & 0x30)
@@ -297,6 +322,9 @@ w83977f_write(uint16_t port, uint8_t val, void *priv)
case 0xf4: case 0xf5: case 0xf6: case 0xf7: case 0xf4: case 0xf5: case 0xf6: case 0xf7:
switch (ld) { switch (ld) {
case 0x00: case 0x00:
if (dev->id == 1)
break;
if (valxor & 0x18) if (valxor & 0x18)
fdc_update_drvrate(dev->fdc, dev->cur_reg & 0x03, (val & 0x18) >> 3); fdc_update_drvrate(dev->fdc, dev->cur_reg & 0x03, (val & 0x18) >> 3);
break; break;
@@ -358,7 +386,11 @@ w83977f_reset(w83977f_t *dev)
dev->dev_regs[0][0x00] = 0x01; dev->dev_regs[0][0x00] = 0x01;
if (!dev->type) if (!dev->type)
dev->dev_regs[0][0x01] = 0x02; dev->dev_regs[0][0x01] = 0x02;
dev->dev_regs[0][0x30] = 0x03; dev->dev_regs[0][0x31] = 0xf0; if (next_id == 1) {
dev->dev_regs[0][0x30] = 0x03; dev->dev_regs[0][0x31] = 0x70;
} else {
dev->dev_regs[0][0x30] = 0x03; dev->dev_regs[0][0x31] = 0xf0;
}
dev->dev_regs[0][0x40] = 0x06; dev->dev_regs[0][0x40] = 0x06;
if (!dev->type) if (!dev->type)
dev->dev_regs[0][0x41] = 0x02; /* Read-only */ dev->dev_regs[0][0x41] = 0x02; /* Read-only */
@@ -369,8 +401,13 @@ w83977f_reset(w83977f_t *dev)
dev->dev_regs[1][0x00] = 0x01; dev->dev_regs[1][0x00] = 0x01;
if (!dev->type) if (!dev->type)
dev->dev_regs[1][0x01] = 0x02; dev->dev_regs[1][0x01] = 0x02;
dev->dev_regs[1][0x30] = 0x03; dev->dev_regs[1][0x31] = 0x78; if (next_id == 1) {
dev->dev_regs[1][0x40] = 0x07; dev->dev_regs[1][0x30] = 0x02; dev->dev_regs[1][0x31] = 0x78;
dev->dev_regs[1][0x40] = 0x05;
} else {
dev->dev_regs[1][0x30] = 0x03; dev->dev_regs[1][0x31] = 0x78;
dev->dev_regs[1][0x40] = 0x07;
}
if (!dev->type) if (!dev->type)
dev->dev_regs[1][0x41] = 0x01 /*0x02*/; /* Read-only */ dev->dev_regs[1][0x41] = 0x01 /*0x02*/; /* Read-only */
dev->dev_regs[1][0x44] = 0x04; dev->dev_regs[1][0x44] = 0x04;
@@ -380,7 +417,11 @@ w83977f_reset(w83977f_t *dev)
dev->dev_regs[2][0x00] = 0x01; dev->dev_regs[2][0x00] = 0x01;
if (!dev->type) if (!dev->type)
dev->dev_regs[2][0x01] = 0x02; dev->dev_regs[2][0x01] = 0x02;
dev->dev_regs[2][0x30] = 0x03; dev->dev_regs[2][0x31] = 0xf8; if (next_id == 1) {
dev->dev_regs[2][0x30] = 0x03; dev->dev_regs[2][0x31] = 0xe8;
} else {
dev->dev_regs[2][0x30] = 0x03; dev->dev_regs[2][0x31] = 0xf8;
}
dev->dev_regs[2][0x40] = 0x04; dev->dev_regs[2][0x40] = 0x04;
if (!dev->type) if (!dev->type)
dev->dev_regs[2][0x41] = 0x02; /* Read-only */ dev->dev_regs[2][0x41] = 0x02; /* Read-only */
@@ -389,7 +430,11 @@ w83977f_reset(w83977f_t *dev)
dev->dev_regs[3][0x00] = 0x01; dev->dev_regs[3][0x00] = 0x01;
if (!dev->type) if (!dev->type)
dev->dev_regs[3][0x01] = 0x02; dev->dev_regs[3][0x01] = 0x02;
dev->dev_regs[3][0x30] = 0x02; dev->dev_regs[3][0x31] = 0xf8; if (next_id == 1) {
dev->dev_regs[3][0x30] = 0x02; dev->dev_regs[3][0x31] = 0xe8;
} else {
dev->dev_regs[3][0x30] = 0x02; dev->dev_regs[3][0x31] = 0xf8;
}
dev->dev_regs[3][0x40] = 0x03; dev->dev_regs[3][0x40] = 0x03;
if (!dev->type) if (!dev->type)
dev->dev_regs[3][0x41] = 0x02; /* Read-only */ dev->dev_regs[3][0x41] = 0x02; /* Read-only */
@@ -461,12 +506,18 @@ w83977f_reset(w83977f_t *dev)
dev->dev_regs[10][0xc0] = 0x8f; dev->dev_regs[10][0xc0] = 0x8f;
} }
fdc_reset(dev->fdc); if (next_id == 1) {
serial_setup(dev->uart[0], SERIAL3_ADDR, SERIAL3_IRQ);
serial_setup(dev->uart[1], SERIAL4_ADDR, SERIAL4_IRQ);
} else {
fdc_reset(dev->fdc);
serial_setup(dev->uart[0], SERIAL1_ADDR, SERIAL1_IRQ); serial_setup(dev->uart[0], SERIAL1_ADDR, SERIAL1_IRQ);
serial_setup(dev->uart[1], SERIAL2_ADDR, SERIAL2_IRQ); serial_setup(dev->uart[1], SERIAL2_ADDR, SERIAL2_IRQ);
w83977f_fdc_handler(dev);
}
w83977f_fdc_handler(dev);
w83977f_lpt_handler(dev); w83977f_lpt_handler(dev);
w83977f_serial_handler(dev, 0); w83977f_serial_handler(dev, 0);
w83977f_serial_handler(dev, 1); w83977f_serial_handler(dev, 1);
@@ -483,6 +534,8 @@ w83977f_close(void *priv)
{ {
w83977f_t *dev = (w83977f_t *) priv; w83977f_t *dev = (w83977f_t *) priv;
next_id = 0;
free(dev); free(dev);
} }
@@ -496,13 +549,20 @@ w83977f_init(const device_t *info)
dev->type = info->local & 0x0f; dev->type = info->local & 0x0f;
dev->hefras = info->local & 0x40; dev->hefras = info->local & 0x40;
dev->fdc = device_add(&fdc_at_smc_device); dev->id = next_id;
dev->uart[0] = device_add_inst(&ns16550_device, 1); if (next_id == 1)
dev->uart[1] = device_add_inst(&ns16550_device, 2); dev->hefras ^= 0x40;
else
dev->fdc = device_add(&fdc_at_smc_device);
dev->uart[0] = device_add_inst(&ns16550_device, (next_id << 1) + 1);
dev->uart[1] = device_add_inst(&ns16550_device, (next_id << 1) + 2);
w83977f_reset(dev); w83977f_reset(dev);
next_id++;
return dev; return dev;
} }

14
src/win/86Box.rc
View File

@@ -459,7 +459,7 @@ BEGIN
PUSHBUTTON "Configure",IDC_CONFIGURE_NET,214,43,46,12 PUSHBUTTON "Configure",IDC_CONFIGURE_NET,214,43,46,12
END END
DLG_CFG_PORTS DIALOG DISCARDABLE 97, 0, 267, 117 DLG_CFG_PORTS DIALOG DISCARDABLE 97, 0, 267, 135
STYLE DS_CONTROL | WS_CHILD STYLE DS_CONTROL | WS_CHILD
FONT 9, "Segoe UI" FONT 9, "Segoe UI"
BEGIN BEGIN
@@ -479,13 +479,17 @@ BEGIN
BS_AUTOCHECKBOX | WS_TABSTOP,7,64,94,10 BS_AUTOCHECKBOX | WS_TABSTOP,7,64,94,10
CONTROL "Serial port 2",IDC_CHECK_SERIAL2,"Button", CONTROL "Serial port 2",IDC_CHECK_SERIAL2,"Button",
BS_AUTOCHECKBOX | WS_TABSTOP,147,64,94,10 BS_AUTOCHECKBOX | WS_TABSTOP,147,64,94,10
CONTROL "Serial port 3",IDC_CHECK_SERIAL3,"Button",
BS_AUTOCHECKBOX | WS_TABSTOP,7,82,94,10
CONTROL "Serial port 4",IDC_CHECK_SERIAL4,"Button",
BS_AUTOCHECKBOX | WS_TABSTOP,147,82,94,10
CONTROL "Parallel port 1",IDC_CHECK_PARALLEL1,"Button", CONTROL "Parallel port 1",IDC_CHECK_PARALLEL1,"Button",
BS_AUTOCHECKBOX | WS_TABSTOP,7,82,94,10
CONTROL "Parallel port 2",IDC_CHECK_PARALLEL2,"Button",
BS_AUTOCHECKBOX | WS_TABSTOP,147,82,94,10
CONTROL "Parallel port 3",IDC_CHECK_PARALLEL3,"Button",
BS_AUTOCHECKBOX | WS_TABSTOP,7,100,94,10 BS_AUTOCHECKBOX | WS_TABSTOP,7,100,94,10
CONTROL "Parallel port 2",IDC_CHECK_PARALLEL2,"Button",
BS_AUTOCHECKBOX | WS_TABSTOP,147,100,94,10
CONTROL "Parallel port 3",IDC_CHECK_PARALLEL3,"Button",
BS_AUTOCHECKBOX | WS_TABSTOP,7,118,94,10
END END
DLG_CFG_PERIPHERALS DIALOG DISCARDABLE 97, 0, 267, 220 DLG_CFG_PERIPHERALS DIALOG DISCARDABLE 97, 0, 267, 220

3
src/win/Makefile.mingw
View File

@@ -647,7 +647,8 @@ HDDOBJ := hdd.o \
hdc_xta.o \ hdc_xta.o \
hdc_esdi_at.o hdc_esdi_mca.o \ hdc_esdi_at.o hdc_esdi_mca.o \
hdc_xtide.o hdc_ide.o \ hdc_xtide.o hdc_ide.o \
hdc_ide_opti611.o hdc_ide_sff8038i.o hdc_ide_opti611.o \
hdc_ide_cmd640.o hdc_ide_sff8038i.o
CDROMOBJ := cdrom.o \ CDROMOBJ := cdrom.o \
cdrom_image_backend.o cdrom_image.o cdrom_image_backend.o cdrom_image.o

12
src/win/win_settings.c
View File

@@ -94,7 +94,7 @@ static char temp_pcap_dev[522];
/* Ports category */ /* Ports category */
static int temp_lpt_devices[3]; static int temp_lpt_devices[3];
static int temp_serial[2], temp_lpt[3]; static int temp_serial[4], temp_lpt[3];
/* Other peripherals category */ /* Other peripherals category */
static int temp_fdc_card, temp_hdc, temp_scsi_card, temp_ide_ter, temp_ide_qua; static int temp_fdc_card, temp_hdc, temp_scsi_card, temp_ide_ter, temp_ide_qua;
@@ -262,7 +262,7 @@ win_settings_init(void)
temp_lpt_devices[i] = lpt_ports[i].device; temp_lpt_devices[i] = lpt_ports[i].device;
temp_lpt[i] = lpt_ports[i].enabled; temp_lpt[i] = lpt_ports[i].enabled;
} }
for (i = 0; i < 2; i++) for (i = 0; i < 4; i++)
temp_serial[i] = serial_enabled[i]; temp_serial[i] = serial_enabled[i];
/* Other peripherals category */ /* Other peripherals category */
@@ -372,7 +372,7 @@ win_settings_changed(void)
i = i || (temp_lpt_devices[j] != lpt_ports[j].device); i = i || (temp_lpt_devices[j] != lpt_ports[j].device);
i = i || (temp_lpt[j] != lpt_ports[j].enabled); i = i || (temp_lpt[j] != lpt_ports[j].enabled);
} }
for (j = 0; j < 2; j++) for (j = 0; j < 4; j++)
i = i || (temp_serial[j] != serial_enabled[j]); i = i || (temp_serial[j] != serial_enabled[j]);
/* Peripherals category */ /* Peripherals category */
@@ -484,7 +484,7 @@ win_settings_save(void)
lpt_ports[i].device = temp_lpt_devices[i]; lpt_ports[i].device = temp_lpt_devices[i];
lpt_ports[i].enabled = temp_lpt[i]; lpt_ports[i].enabled = temp_lpt[i];
} }
for (i = 0; i < 2; i++) for (i = 0; i < 4; i++)
serial_enabled[i] = temp_serial[i]; serial_enabled[i] = temp_serial[i];
/* Peripherals category */ /* Peripherals category */
@@ -1563,7 +1563,7 @@ win_settings_ports_proc(HWND hdlg, UINT message, WPARAM wParam, LPARAM lParam)
EnableWindow(h, temp_lpt[i] ? TRUE : FALSE); EnableWindow(h, temp_lpt[i] ? TRUE : FALSE);
} }
for (i = 0; i < 2; i++) { for (i = 0; i < 4; i++) {
h=GetDlgItem(hdlg, IDC_CHECK_SERIAL1 + i); h=GetDlgItem(hdlg, IDC_CHECK_SERIAL1 + i);
SendMessage(h, BM_SETCHECK, temp_serial[i], 0); SendMessage(h, BM_SETCHECK, temp_serial[i], 0);
} }
@@ -1602,7 +1602,7 @@ win_settings_ports_proc(HWND hdlg, UINT message, WPARAM wParam, LPARAM lParam)
temp_lpt[i] = SendMessage(h, BM_GETCHECK, 0, 0); temp_lpt[i] = SendMessage(h, BM_GETCHECK, 0, 0);
} }
for (i = 0; i < 2; i++) { for (i = 0; i < 4; i++) {
h = GetDlgItem(hdlg, IDC_CHECK_SERIAL1 + i); h = GetDlgItem(hdlg, IDC_CHECK_SERIAL1 + i);
temp_serial[i] = SendMessage(h, BM_GETCHECK, 0, 0); temp_serial[i] = SendMessage(h, BM_GETCHECK, 0, 0);
} }