Merge branch '86Box:master' into nec-v20

.ci/Jenkinsfile

@@ -113,9 +113,9 @@ def gitClone(repository, branch) {
 		} else if (env.GIT_COMMIT != scmVars.GIT_COMMIT) {
 			/* Checkout the commit read from the polling log. */
 			if (isUnix())
-				sh returnStatus: true, script: "git checkout ${env.GIT_COMMIT}"
+				sh(returnStatus: true, script: "git checkout ${env.GIT_COMMIT}")
 			else
-				bat returnStatus: true, script: "git checkout ${env.GIT_COMMIT}"
+				bat(returnStatus: true, script: "git checkout ${env.GIT_COMMIT}")
 		}
 		println "[-] Using git commit [${env.GIT_COMMIT}]"
 
@@ -130,14 +130,14 @@ def gitClone(repository, branch) {
 
 def removeDir(dir) {
 	if (isUnix())
-		return sh(returnStatus: true, script: "rm -rf \"$dir\"")
+		return sh(returnStatus: true, script: "rm -rf '$dir'")
 	else
 		return bat(returnStatus: true, script: "rd /s /q \"$dir\"")
 }
 
 def runBuild(args) {
 	if (isUnix())
-		return sh(returnStatus: true, script: "chmod u+x \"$WORKSPACE/.ci/build.sh\" && exec \"$WORKSPACE/.ci/build.sh\" $args")
+		return sh(returnStatus: true, script: "chmod u+x '$WORKSPACE/.ci/build.sh' && exec '$WORKSPACE/.ci/build.sh' $args")
 	else
 		return bat(returnStatus: true, script: "C:\\msys64\\msys2_shell.cmd -msys2 -defterm -here -no-start -c 'exec \"\$(cygpath -u \\'%WORKSPACE%\\')/.ci/build.sh\" $args'")
 }
@@ -173,8 +173,10 @@ pipeline {
 
 			steps {
 				script {
-					/* Extract the polled commit from the polling log, so that git checkout can be used
-					   to avoid JENKINS-20518 race conditions caused by two pushes too close together. */
+					/* Extract the polled commit from the polling log, so that git checkout
+					   can be used to avoid JENKINS-20518 race conditions caused by the
+					   webhook being triggered more than once in a short period of time.
+					   This is a backup strategy for FilterProxy's webhook queuing. */
 					node('master') { /* must run on master node to read polling log */
 						/* Ignore exceptions as this is not really critical. */
 						try {
@@ -215,7 +217,7 @@ pipeline {
 					/* Create source tarball. */
 					try {
 						retry(10) {
-							node('Linux') {
+							node('Linux || macOS') {
 								/* Run git clone. */
 								gitClone(repository[buildBranch], branch[buildBranch])
 

.ci/build.sh

@@ -52,9 +52,22 @@ make_tar() {
 	# Install dependencies.
 	if ! which tar xz > /dev/null 2>&1
 	then
-		which apt-get > /dev/null 2>&1 && DEBIAN_FRONTEND=noninteractive sudo apt-get install -y tar xz-utils
+		if which apt-get > /dev/null 2>&1
+		then
+			sudo apt-get update
+			DEBIAN_FRONTEND=noninteractive sudo apt-get install -y tar xz-utils
+			sudo apt-get clean
+		elif which port > /dev/null 2>&1
+		then
+			sudo port selfupdate
+			sudo port install gnutar xz
+		fi
 	fi
 
+	# Use MacPorts gnutar (if installed) on macOS.
+	local tar_cmd=tar
+	which gnutar > /dev/null 2>&1 && local tar_cmd=gnutar
+
 	# Determine the best supported compression type.
 	local compression_flag=
 	local compression_ext=
@@ -80,7 +93,7 @@ make_tar() {
 	# --uid/gid (bsdtar) or even none at all (MSYS2 bsdtar). Account for such
 	# flag differences by checking if they're mentioned on the help text.
 	local ownership_flags=
-	local tar_help=$(tar --help 2>&1)
+	local tar_help=$("$tar_cmd" --help 2>&1)
 	if echo $tar_help | grep -q -- --owner
 	then
 		local ownership_flags="--owner=0 --group=0"
@@ -90,7 +103,7 @@ make_tar() {
 	fi
 
 	# Run tar.
-	tar -c $compression_flag -f "$1$compression_ext" $ownership_flags *
+	"$tar_cmd" -c $compression_flag -f "$1$compression_ext" $ownership_flags *
 	return $?
 }
 

src/acpi.c

@@ -20,6 +20,7 @@
 #include <stdlib.h>
 #include <string.h>
 #include <wchar.h>
+#include <stdbool.h>
 #define HAVE_STDARG_H
 #include <86box/86box.h>
 #include "cpu.h"
@@ -37,10 +38,11 @@
 #include <86box/acpi.h>
 #include <86box/machine.h>
 #include <86box/i2c.h>
-
+#include <86box/video.h>
 
 int acpi_rtc_status = 0;
 
+static double cpu_to_acpi;
 
 #ifdef ENABLE_ACPI_LOG
 int acpi_do_log = ENABLE_ACPI_LOG;
@@ -61,6 +63,50 @@ acpi_log(const char *fmt, ...)
 #define acpi_log(fmt, ...)
 #endif
 
+static uint64_t acpi_clock_get() {
+    return tsc * cpu_to_acpi;
+}
+
+static uint32_t acpi_timer_get(acpi_t *dev) {
+    uint64_t clock = acpi_clock_get();
+    if (dev->regs.timer32)
+        return clock & 0xffffffff;
+    else
+        return clock & 0xffffff;
+}
+
+static double acpi_get_overflow_period(acpi_t *dev) {
+    uint64_t timer = acpi_clock_get();
+    uint64_t overflow_time;
+
+    if (dev->regs.timer32) {
+        overflow_time = (timer + 0x80000000LL) & ~0x7fffffffLL;
+    } else {
+        overflow_time = (timer + 0x800000LL) & ~0x7fffffLL;
+    }
+
+    uint64_t time_to_overflow = overflow_time - timer;
+
+    return ((double)time_to_overflow / (double)ACPI_TIMER_FREQ) * 1000000.0;
+}
+
+static void
+acpi_timer_overflow(void *priv)
+{
+    acpi_t *dev = (acpi_t *) priv;
+    dev->regs.pmsts |= TMROF_STS;
+    acpi_update_irq(dev);
+}
+
+static void
+acpi_timer_update(acpi_t *dev, bool enable)
+{
+    if (enable) {
+        timer_on_auto(&dev->timer, acpi_get_overflow_period(dev));
+    } else {
+        timer_stop(&dev->timer);
+    }
+}
 
 void
 acpi_update_irq(acpi_t *dev)
@@ -84,6 +130,8 @@ acpi_update_irq(acpi_t *dev)
 	else
 		pci_clear_mirq(0xf0 | dev->irq_line, 1);
     }
+
+    acpi_timer_update(dev, (dev->regs.pmen & TMROF_EN) && !(dev->regs.pmsts & TMROF_STS));
 }
 
 
@@ -96,12 +144,12 @@ acpi_raise_smi(void *priv, int do_smi)
 	if ((dev->vendor == VEN_VIA) || (dev->vendor == VEN_VIA_596B)) {
 		if ((!dev->regs.smi_lock || !dev->regs.smi_active)) {
 			if (do_smi)
-				smi_line = 1;
+				smi_raise();
 			dev->regs.smi_active = 1;
 		}
 	} else if ((dev->vendor == VEN_INTEL) || (dev->vendor == VEN_ALI)) {
 		if (do_smi)
-			smi_line = 1;
+			smi_raise();
 		/* Clear bit 16 of GLBCTL. */
 		if (dev->vendor == VEN_INTEL)
 			dev->regs.glbctl &= ~0x00010000;
@@ -109,7 +157,7 @@ acpi_raise_smi(void *priv, int do_smi)
 			dev->regs.ali_soft_smi = 1;
 	} else if (dev->vendor == VEN_SMC) {
 		if (do_smi)
-			smi_line = 1;
+			smi_raise();
 	}
     }
 }
@@ -145,7 +193,7 @@ acpi_reg_read_common_regs(int size, uint16_t addr, void *p)
 		break;
 	case 0x08: case 0x09: case 0x0a: case 0x0b:
 		/* PMTMR - Power Management Timer Register (IO) */
-		ret = (dev->regs.timer_val >> shift32) & 0xff;
+		ret = (acpi_timer_get(dev) >> shift32) & 0xff;
 #ifdef USE_DYNAREC
 		if (cpu_use_dynarec)
 			update_tsc();
@@ -1282,33 +1330,6 @@ acpi_update_aux_io_mapping(acpi_t *dev, uint32_t base, int chipset_en)
     }
 }
 
-
-static void
-acpi_timer_count(void *priv)
-{
-    acpi_t *dev = (acpi_t *) priv;
-    int overflow;
-    uint32_t old;
-
-    old = dev->regs.timer_val;
-    dev->regs.timer_val++;
-
-    if (dev->regs.timer32)
-	overflow = (old ^ dev->regs.timer_val) & 0x80000000;
-    else {
-	dev->regs.timer_val &= 0x00ffffff;
-	overflow = (old ^ dev->regs.timer_val) & 0x00800000;
-    }
-
-    if (overflow) {
-	dev->regs.pmsts |= TMROF_EN;
-	acpi_update_irq(dev);
-    }
-
-    timer_advance_u64(&dev->timer, ACPICONST);
-}
-
-
 static void
 acpi_timer_resume(void *priv)
 {
@@ -1338,9 +1359,6 @@ void
 acpi_set_timer32(acpi_t *dev, uint8_t timer32)
 {
     dev->regs.timer32 = timer32;
-
-    if (!dev->regs.timer32)
-	dev->regs.timer_val &= 0x00ffffff;
 }
 
 
@@ -1431,7 +1449,7 @@ acpi_apm_out(uint16_t port, uint8_t val, void *p)
 		dev->apm->cmd = val;
 		// acpi_raise_smi(dev, dev->apm->do_smi);
 		if (dev->apm->do_smi)
-			smi_line = 1;
+			smi_raise();
 		dev->regs.ali_soft_smi = 1;
 	} else if (port == 0x0003)
 		dev->apm->stat = val;
@@ -1524,9 +1542,12 @@ static void
 acpi_speed_changed(void *priv)
 {
     acpi_t *dev = (acpi_t *) priv;
+    cpu_to_acpi = ACPI_TIMER_FREQ / cpuclock;
+    bool timer_enabled = timer_is_enabled(&dev->timer);
+    timer_stop(&dev->timer);
 
-    timer_disable(&dev->timer);
-    timer_set_delay_u64(&dev->timer, ACPICONST);
+    if (timer_enabled)
+        timer_on_auto(&dev->timer, acpi_get_overflow_period(dev));
 }
 
 
@@ -1541,7 +1562,7 @@ acpi_close(void *priv)
 	i2c_gpio_close(dev->i2c);
     }
 
-    timer_disable(&dev->timer);
+    timer_stop(&dev->timer);
 
     free(dev);
 }
@@ -1556,6 +1577,7 @@ acpi_init(const device_t *info)
     if (dev == NULL) return(NULL);
     memset(dev, 0x00, sizeof(acpi_t));
 
+    cpu_to_acpi = ACPI_TIMER_FREQ / cpuclock;
     dev->vendor = info->local;
 
     dev->irq_line = 9;
@@ -1604,8 +1626,7 @@ acpi_init(const device_t *info)
 		break;
     }
 
-    timer_add(&dev->timer, acpi_timer_count, dev, 0);
-    timer_set_delay_u64(&dev->timer, ACPICONST);
+    timer_add(&dev->timer, acpi_timer_overflow, dev, 0);
     timer_add(&dev->resume_timer, acpi_timer_resume, dev, 0);
 
     acpi_reset(dev);

src/apm.c

@@ -67,7 +67,7 @@ apm_out(uint16_t port, uint8_t val, void *p)
     if (port == 0x0000) {
 	dev->cmd = val;
 	if (dev->do_smi)
-    		smi_line = 1;
+    		smi_raise();
     } else
 	dev->stat = val;
 }

src/chipset/ali1489.c

@@ -197,7 +197,9 @@ ali1489_defaults(ali1489_t *dev)
 
     picintc(1 << 10);
     picintc(1 << 15);
+#ifdef OLD_NMI_BEHAVIOR
     nmi = 0;
+#endif
     smi_line = 0;
     in_smm = 0;
 
@@ -316,10 +318,10 @@ ali1489_write(uint16_t addr, uint8_t val, void *priv)
 					if (((val & 0x14) == 0x14) && !(old & 0x08) && (val & 0x08)) {
 						switch (dev->regs[0x35] & 0x30) {
 							case 0x00:
-								smi_line = 1;
+								smi_raise();
 								break;
 							case 0x10:
-								nmi = 1;
+								nmi_raise();
 								break;
 							case 0x20:
 								picint(1 << 15);

src/chipset/contaq_82c59x.c

@@ -242,7 +242,7 @@ contaq_82c59x_write(uint16_t addr, uint8_t val, void *priv)
 				dev->regs[dev->index] = val;
 				if (val & 0x80) {
 					if (dev->regs[0x65] & 0x80)
-						smi_line = 1;
+						smi_raise();
 					dev->smi_status[0] |= 0x10;
 				}
 				break;

src/chipset/ims8848.c

@@ -230,7 +230,7 @@ ims8848_write(uint16_t addr, uint8_t val, void *priv)
 					if (dev->idx == 0x1b) {
 						ims8848_smram(dev);
 						if (!(old & 0x10) && (val & 0x10))
-							smi_line = 1;
+							smi_raise();
 					} else if (dev->idx == 0x1c)
 						pci_set_irq_routing(PCI_INTA, (val >> 4) ? (val >> 4) : PCI_IRQ_DISABLED);
 					break;

src/chipset/intel_420ex.c

@@ -19,6 +19,7 @@
 #include <string.h>
 #include <wchar.h>
 #include <86box/86box.h>
+#include "cpu.h"
 #include <86box/device.h>
 #include <86box/io.h>
 #include <86box/apm.h>
@@ -316,10 +317,8 @@ i420ex_write(int func, int addr, uint8_t val, void *priv)
 				dev->fast_off_period = PCICLK * 32768.0;
 				break;
 		}
-		cpu_fast_off_count = dev->regs[0xa8] + 1;
-		timer_disable(&dev->fast_off_timer);
-		if (dev->fast_off_period != 0.0)
-			timer_on_auto(&dev->fast_off_timer, dev->fast_off_period);
+		cpu_fast_off_count = cpu_fast_off_val + 1;
+		cpu_fast_off_period_set(cpu_fast_off_val, dev->fast_off_period);
 		break;
 	case 0xa2:
 		dev->regs[addr] = val & 0xff;
@@ -347,9 +346,7 @@ i420ex_write(int func, int addr, uint8_t val, void *priv)
 		dev->regs[addr] = val & 0xff;
 		cpu_fast_off_val = val;
 		cpu_fast_off_count = val + 1;
-		timer_disable(&dev->fast_off_timer);
-		if (dev->fast_off_period != 0.0)
-			timer_on_auto(&dev->fast_off_timer, dev->fast_off_period);
+		cpu_fast_off_period_set(cpu_fast_off_val, dev->fast_off_period);
 		break;
     }
 }
@@ -422,13 +419,8 @@ i420ex_fast_off_count(void *priv)
 
     cpu_fast_off_count--;
 
-    if (cpu_fast_off_count == 0) {
-	smi_line = 1;
-	dev->regs[0xaa] |= 0x20;
-	cpu_fast_off_count = dev->regs[0xa8] + 1;
-    }
-
-    timer_on_auto(&dev->fast_off_timer, dev->fast_off_period);
+    smi_raise();
+    dev->regs[0xaa] |= 0x20;
 }
 
 
@@ -513,6 +505,8 @@ i420ex_init(const device_t *info)
     cpu_fast_off_val = dev->regs[0xa8];
     cpu_fast_off_count = cpu_fast_off_val + 1;
 
+    cpu_register_fast_off_handler(&dev->fast_off_timer);
+
     dev->apm = device_add(&apm_pci_device);
     /* APM intercept handler to update 82420EX SMI status on APM SMI. */
     io_sethandler(0x00b2, 0x0001, NULL, NULL, NULL, i420ex_apm_out, NULL, NULL, dev);

src/chipset/intel_piix.c

@@ -628,10 +628,8 @@ piix_write(int func, int addr, uint8_t val, void *priv)
 					dev->fast_off_period = PCICLK * 32768.0;
 					break;
 			}
-			cpu_fast_off_count = fregs[0xa8] + 1;
-			timer_disable(&dev->fast_off_timer);
-			if (dev->fast_off_period != 0.0)
-				timer_on_auto(&dev->fast_off_timer, dev->fast_off_period);
+			cpu_fast_off_count = cpu_fast_off_val + 1;
+			cpu_fast_off_period_set(cpu_fast_off_val, dev->fast_off_period);
 		}
 		break;
 	case 0xa2:
@@ -679,9 +677,7 @@ piix_write(int func, int addr, uint8_t val, void *priv)
 			fregs[addr] = val & 0xff;
 			cpu_fast_off_val = val;
 			cpu_fast_off_count = val + 1;
-			timer_disable(&dev->fast_off_timer);
-			if (dev->fast_off_period != 0.0)
-				timer_on_auto(&dev->fast_off_timer, dev->fast_off_period);
+			cpu_fast_off_period_set(cpu_fast_off_val, dev->fast_off_period);
 		}
 		break;
 	case 0xaa:
@@ -1331,15 +1327,8 @@ piix_fast_off_count(void *priv)
 {
     piix_t *dev = (piix_t *) priv;
 
-    cpu_fast_off_count--;
-
-    if (cpu_fast_off_count == 0) {
-	smi_line = 1;
-	dev->regs[0][0xaa] |= 0x20;
-	cpu_fast_off_count = dev->regs[0][0xa8] + 1;
-    }
-
-    timer_on_auto(&dev->fast_off_timer, dev->fast_off_period);
+    smi_raise();
+    dev->regs[0][0xaa] |= 0x20;
 }
 
 
@@ -1446,7 +1435,7 @@ piix_speed_changed(void *priv)
 
     timer_stop(&dev->fast_off_timer);
     if (te)
-	timer_on_auto(&dev->fast_off_timer, dev->fast_off_period);
+	timer_on_auto(&dev->fast_off_timer, ((double) cpu_fast_off_val + 1) * dev->fast_off_period);
 }
 
 
@@ -1510,6 +1499,7 @@ static void
     if (dev->type < 4) {
 	cpu_fast_off_val = dev->regs[0][0xa8];
 	cpu_fast_off_count = cpu_fast_off_val + 1;
+	cpu_register_fast_off_handler(&dev->fast_off_timer);
     } else
 	cpu_fast_off_val = cpu_fast_off_count = 0;
 

src/chipset/intel_sio.c

@@ -18,6 +18,7 @@
 #include <string.h>
 #include <wchar.h>
 #include <86box/86box.h>
+#include "cpu.h"
 #include <86box/device.h>
 #include <86box/io.h>
 #include <86box/apm.h>
@@ -264,10 +265,8 @@ sio_write(int func, int addr, uint8_t val, void *priv)
 					dev->fast_off_period = PCICLK * 32768.0;
 					break;
 			}
-			cpu_fast_off_count = dev->regs[0xa8] + 1;
-			timer_disable(&dev->fast_off_timer);
-			if (dev->fast_off_period != 0.0)
-				timer_on_auto(&dev->fast_off_timer, dev->fast_off_period);
+			cpu_fast_off_count = cpu_fast_off_val + 1;
+			cpu_fast_off_period_set(cpu_fast_off_val, dev->fast_off_period);
 		}
 		break;
 	case 0xa2:
@@ -306,9 +305,7 @@ sio_write(int func, int addr, uint8_t val, void *priv)
 		dev->regs[addr] = val & 0xff;
 		cpu_fast_off_val = val;
 		cpu_fast_off_count = val + 1;
-		timer_disable(&dev->fast_off_timer);
-		if (dev->fast_off_period != 0.0)
-			timer_on_auto(&dev->fast_off_timer, dev->fast_off_period);
+		cpu_fast_off_period_set(cpu_fast_off_val, dev->fast_off_period);
 		break;
     }
 }
@@ -429,15 +426,8 @@ sio_fast_off_count(void *priv)
 {
     sio_t *dev = (sio_t *) priv;
 
-    cpu_fast_off_count--;
-
-    if (cpu_fast_off_count == 0) {
-	smi_line = 1;
-	dev->regs[0xaa] |= 0x20;
-	cpu_fast_off_count = dev->regs[0xa8] + 1;
-    }
-
-    timer_on_auto(&dev->fast_off_timer, dev->fast_off_period);
+    smi_raise();
+    dev->regs[0xaa] |= 0x20;
 }
 
 
@@ -513,6 +503,8 @@ sio_init(const device_t *info)
     if (dev->id == 0x03) {
 	cpu_fast_off_val = dev->regs[0xa8];
 	cpu_fast_off_count = cpu_fast_off_val + 1;
+
+	cpu_register_fast_off_handler(&dev->fast_off_timer);
     } else
 	cpu_fast_off_val = cpu_fast_off_count = 0;
 

src/chipset/opti895.c

@@ -175,7 +175,7 @@ opti895_write(uint16_t addr, uint8_t val, void *priv)
 
 				case 0xe1:
 					if ((val & 0x08) && (dev->regs[0xe0] & 0x01)) {
-						smi_line = 1;
+						smi_raise();
 						dev->forced_green = 1;
 						break;
 					}

src/chipset/sis_5511.c

@@ -225,7 +225,7 @@ sis_5511_write(int func, int addr, uint8_t val, void *priv)
 	case 0x60:
 		dev->pci_conf[addr] = val & 0x3e;
 		if ((dev->pci_conf[0x68] & 1) && (val & 2)) {
-			smi_line = 1;
+			smi_raise();
 			dev->pci_conf[0x69] |= 1;
 		}
 		break;

src/chipset/sis_5571.c

@@ -288,7 +288,7 @@ memory_pci_bridge_write(int func, int addr, uint8_t val, void *priv)
 
 		if ((dev->pci_conf[0x9b] & 1) && !!(val & 2))
 		{
-			smi_line = 1;
+			smi_raise();
 			dev->pci_conf[0x9d] |= 1;
 		}
 		break;

src/chipset/sis_85c496.c

@@ -390,7 +390,7 @@ sis_85c49x_pci_write(int func, int addr, uint8_t val, void *priv)
 			if (dev->pci_conf[0x80] & 0x10)
 				picint(1 << smm_irq[dev->pci_conf[0x81] & 0x03]);
 			else
-				smi_line = 1;
+				smi_raise();
 			smi_block = 1;
 			dev->pci_conf[0xa0] |= 0x10;
 		}

src/chipset/sis_85c4xx.c

@@ -104,7 +104,7 @@ sis_85c4xx_sw_smi_out(uint16_t port, uint8_t val, void *priv)
 
     if (dev->regs[0x18] & 0x02) {
 	if (dev->regs[0x0b] & 0x10)
-		smi_line = 1;
+		smi_raise();
 	else
 		picint(1 << ((dev->regs[0x0b] & 0x08) ? 15 : 12));
 	soft_reset_mask = 1;

src/chipset/sis_85c50x.c

@@ -176,7 +176,7 @@ sis_85c50x_write(int func, int addr, uint8_t val, void *priv)
 	case 0x60:	/* SMI */
 		if ((dev->pci_conf[0x68] & 0x01) && !(dev->pci_conf[addr] & 0x02) && (val & 0x02)) {
 			dev->pci_conf[0x69] |= 0x01;
-			smi_line = 1;
+			smi_raise();
 		}
 		dev->pci_conf[addr] = val & 0x3e;
 		break;

src/chipset/umc_8886.c

@@ -232,7 +232,7 @@ umc_8886_write(int func, int addr, uint8_t val, void *priv)
 					if (dev->pci_conf_sb[0][0x46] & 0x40)
 						picint(1 << ((dev->pci_conf_sb[0][0x46] & 0x80) ? 15 : 10));
 					else
-						smi_line = 1;
+						smi_raise();
 					dev->pci_conf_sb[0][0xa3] |= 0x04;
 				}
 

src/chipset/via_pipc.c

@@ -728,8 +728,10 @@ pipc_fmnmi_read(uint16_t addr, void *priv)
     if  (dev->ac97_regs[0][0x48] & 0x01) {
 	if (dev->ac97_regs[0][0x48] & 0x04)
 		smi_line = 0;
+#ifdef OLD_NMI_BEHAVIOR
 	else
 		nmi = 0;
+#endif
     }
 #endif
 
@@ -788,9 +790,9 @@ pipc_fm_write(uint16_t addr, uint8_t val, void *priv)
 	/* Fire NMI/SMI if enabled. */
 	if (dev->ac97_regs[0][0x48] & 0x01) {
 		if (dev->ac97_regs[0][0x48] & 0x04)
-			smi_line = 1;
+			smi_raise();
 		else
-			nmi = 1;
+			nmi_raise();
 	}
     }
 #else

src/chipset/via_vt82c49x.c

@@ -234,7 +234,7 @@ vt82c49x_write(uint16_t addr, uint8_t val, void *priv)
 			case 0x54:
 				if ((dev->regs[0x5b] & 0x80) && (valxor & 0x01) && (val & 0x01)) {
 					if (dev->regs[0x5b] & 0x20)
-						smi_line = 1;
+						smi_raise();
 					else
 						picint(1 << 15);
 					dev->regs[0x55] = 0x01;

src/cpu/386.c

@@ -210,9 +210,6 @@ exec386(int cycs)
 				loadcs(readmemw(0, addr + 2));
 			}
 		} else if (nmi && nmi_enable && nmi_mask) {
-			if (is486 && (cpu_fast_off_flags & 0x20000000))
-				cpu_fast_off_count = cpu_fast_off_val + 1;
-
 			cpu_state.oldpc = cpu_state.pc;
 			x86_int(2);
 			nmi_enable = 0;

src/cpu/386_common.c

@@ -22,6 +22,7 @@
 #include <86box/fdd.h>
 #include <86box/fdc.h>
 #include <86box/keyboard.h>
+#include <86box/timer.h>
 #include "386_common.h"
 #include "x86_flags.h"
 #include "x86seg.h"
@@ -71,6 +72,9 @@ int smm_in_hlt = 0, smi_block = 0;
 uint32_t addr64, addr64_2;
 uint32_t addr64a[8], addr64a_2[8];
 
+static pc_timer_t *cpu_fast_off_timer = NULL;
+static double cpu_fast_off_period = 0.0;
+
 
 #define AMD_SYSCALL_EIP	(msr.star & 0xFFFFFFFF)
 #define AMD_SYSCALL_SB	((msr.star >> 32) & 0xFFFF)
@@ -1183,9 +1187,6 @@ enter_smm(int in_hlt)
 void
 enter_smm_check(int in_hlt)
 {
-    if (smi_line && (cpu_fast_off_flags & 0x80000000))
-	cpu_fast_off_count = cpu_fast_off_val + 1;
-
     if ((in_smm == 0) && smi_line) {
 #ifdef ENABLE_386_COMMON_LOG
 	x386_common_log("SMI while not in SMM\n");
@@ -1840,6 +1841,60 @@ sysret(uint32_t fetchdat)
 }
 
 
+void
+cpu_register_fast_off_handler(void *timer)
+{
+    cpu_fast_off_timer = (pc_timer_t *) timer;
+}
+
+
+void
+cpu_fast_off_advance(void)
+{
+    timer_disable(cpu_fast_off_timer);
+    if (cpu_fast_off_period != 0.0)
+	timer_on_auto(cpu_fast_off_timer, cpu_fast_off_period);
+}
+
+
+void
+cpu_fast_off_period_set(uint16_t val, double period)
+{
+    cpu_fast_off_period = ((double) (val + 1)) * period;
+    cpu_fast_off_advance();
+}
+
+
+void
+cpu_fast_off_reset(void)
+{
+    if (cpu_fast_off_timer)
+	timer_disable(cpu_fast_off_timer);
+
+    cpu_register_fast_off_handler(NULL);
+    cpu_fast_off_period = 0.0;
+    cpu_fast_off_advance();
+}
+
+
+void
+smi_raise(void)
+{
+    if (is486 && (cpu_fast_off_flags & 0x80000000))
+	cpu_fast_off_advance();
+
+    smi_line = 1;
+}
+
+
+void
+nmi_raise(void)
+{
+    if (is486 && (cpu_fast_off_flags & 0x20000000))
+	cpu_fast_off_advance();
+}
+
+
 #ifndef USE_DYNAREC
 /* This is for compatibility with new x87 code. */
 void codegen_set_rounding_mode(int mode)

src/cpu/386_dynarec.c

@@ -819,9 +819,6 @@ exec386_dynarec(int cycs)
 		if (smi_line)
 			enter_smm_check(0);
 		else if (nmi && nmi_enable && nmi_mask) {
-			if (is486 && (cpu_fast_off_flags & 0x20000000))
-				cpu_fast_off_count = cpu_fast_off_val + 1;
-
 #ifndef USE_NEW_DYNAREC
 			oldcs = CS;
 #endif

src/cpu/cpu.h

@@ -743,4 +743,12 @@ extern uint8_t	do_translate, do_translate2;
 
 extern void	reset_808x(int hard);
 
+extern void	cpu_register_fast_off_handler(void *timer);
+extern void	cpu_fast_off_advance(void);
+extern void	cpu_fast_off_period_set(uint16_t vla, double period);
+extern void	cpu_fast_off_reset(void);
+
+extern void	smi_raise();
+extern void	nmi_raise();
+
 #endif	/*EMU_CPU_H*/

src/disk/hdc_ide_opti611.c

@@ -152,7 +152,7 @@ opti611_ide_write(uint16_t addr, uint8_t val, void *priv)
     uint8_t smibe = (addr & 0x0003);
 
     if (dev->regs[0x03] & 0x02) {
-	smi_line = 1;
+	smi_raise();
 	dev->regs[0x02] = smia9 | smia2 | smibe;
 	dev->regs[0x04] = val;
     }
@@ -169,7 +169,7 @@ opti611_ide_writew(uint16_t addr, uint16_t val, void *priv)
     uint8_t smibe = (addr & 0x0002) | 0x0001;
 
     if (dev->regs[0x03] & 0x02) {
-	smi_line = 1;
+	smi_raise();
 	dev->regs[0x02] = smia9 | smia2 | smibe;
 	dev->regs[0x04] = 0x00;
     }
@@ -185,7 +185,7 @@ opti611_ide_writel(uint16_t addr, uint32_t val, void *priv)
     uint8_t smia2 = (!!(addr & 0x0004)) << 4;
 
     if (dev->regs[0x03] & 0x02) {
-	smi_line = 1;
+	smi_raise();
 	dev->regs[0x02] = smia9 | smia2 | 0x0003;
 	dev->regs[0x04] = 0x00;
     }
@@ -202,7 +202,7 @@ opti611_ide_read(uint16_t addr, void *priv)
     uint8_t smibe = (addr & 0x0003);
 
     if (dev->regs[0x03] & 0x02) {
-	smi_line = 1;
+	smi_raise();
 	dev->regs[0x02] = smia9 | smia2 | smibe;
 	dev->regs[0x04] = 0x00;
     }
@@ -229,7 +229,7 @@ opti611_ide_readw(uint16_t addr, void *priv)
     }
 
     if (dev->regs[0x03] & 0x02) {
-	smi_line = 1;
+	smi_raise();
 	dev->regs[0x02] = smia9 | smia2 | smibe;
 	dev->regs[0x04] = 0x00;
     }
@@ -247,7 +247,7 @@ opti611_ide_readl(uint16_t addr, void *priv)
     uint8_t smia2 = (!!(addr & 0x0004)) << 4;
 
     if (dev->regs[0x03] & 0x02) {
-	smi_line = 1;
+	smi_raise();
 	dev->regs[0x02] = smia9 | smia2 | 0x0003;
 	dev->regs[0x04] = 0x00;
     }

src/include/86box/acpi.h

@@ -76,10 +76,9 @@ typedef struct
 			devsts, glben,
 			glbctl, devctl,
 			padsts, paden,
-			gptren, gptimer, timer_val,
+			gptren, gptimer,
 			gpo_val, gpi_val,
 			extsmi_val, pad0;
-    uint64_t		tmr_overflow_time;
 } acpi_regs_t;
 
 

src/include/86box/pit.h

@@ -70,7 +70,7 @@ extern uint64_t	PITCONST, ISACONST,
 		HERCCONST,
 		VGACONST1,
 		VGACONST2,
-		RTCCONST, ACPICONST;
+		RTCCONST;
 
 extern int	refresh_at_enable;
 

src/machine/m_amstrad.c

@@ -1068,7 +1068,9 @@ vid_in_200(uint16_t addr, void *priv)
 	case 0x03dd:
 		ret = vid->crtc_index;		/* Read NMI reason */
 		vid->crtc_index &= 0x1f;	/* Reset NMI reason */
+#ifdef OLD_NMI_BEHAVIOR
 		nmi = 0;			/* And reset NMI flag */
+#endif
 		return(ret);
 
 	case 0x03de:
@@ -1106,7 +1108,7 @@ vid_out_200(uint16_t addr, uint8_t val, void *priv)
 		if (!(vid->operation_ctrl & 0x40) && mda->crtcreg <= 11) {
 			vid->crtc_index = 0x20 | (mda->crtcreg & 0x1f);
 			if (vid->operation_ctrl & 0x80)
-				nmi = 1;
+				nmi_raise();
 			vid->reg_3df = val;
 			return;
 		}
@@ -1127,7 +1129,7 @@ vid_out_200(uint16_t addr, uint8_t val, void *priv)
 		vid->crtc_index &= 0x1F;
 		vid->crtc_index |= 0x80;
 		if (vid->operation_ctrl & 0x80)
-			nmi = 1;
+			nmi_raise();
 		return;
 
 /* 	CGA writes ============================================================== */
@@ -1138,7 +1140,7 @@ vid_out_200(uint16_t addr, uint8_t val, void *priv)
 		if (!(vid->operation_ctrl & 0x40) && cga->crtcreg <= 11) {
 			vid->crtc_index = 0x20 | (cga->crtcreg & 0x1f);
 			if (vid->operation_ctrl & 0x80)
-				nmi = 1;
+				nmi_raise();
 			vid->reg_3df = val;
 			return;
 		}
@@ -1160,7 +1162,7 @@ vid_out_200(uint16_t addr, uint8_t val, void *priv)
 		vid->crtc_index &= 0x1f;
 		vid->crtc_index |= 0x80;
 		if (vid->operation_ctrl & 0x80)
-			nmi = 1;
+			nmi_raise();
 		else
 			set_lcd_cols(val);
 		return;
@@ -1174,7 +1176,7 @@ vid_out_200(uint16_t addr, uint8_t val, void *priv)
 		if (val & 0x80) {
 			vid->operation_ctrl = val;
 			vid->crtc_index |= 0x40;
-			nmi = 1;
+			nmi_raise();
 			return;
 		}
                 timer_disable(&vid->cga.timer);

src/machine/machine.c

@@ -105,6 +105,9 @@ machine_init_ex(int m)
 
 	/* Reset any ISA memory cards. */
 	isamem_reset();
+
+	/* Reset the fast off stuff. */
+	cpu_fast_off_reset();
     }
 
     /* All good, boot the machine! */

src/nvr_at.c

@@ -496,6 +496,8 @@ timer_load_count(nvr_t *nvr)
     int c = nvr->regs[RTC_REGA] & REGA_RS;
     local_t *local = (local_t *) nvr->data;
 
+    timer_disable(&local->rtc_timer);
+
     if ((nvr->regs[RTC_REGA] & 0x70) != 0x20) {
 	local->state = 0;
 	return;
@@ -509,9 +511,11 @@ timer_load_count(nvr_t *nvr)
 		break;
 	case 1: case 2:
 		local->count = 1 << (c + 6);
+		timer_set_delay_u64(&local->rtc_timer, (local->count) * RTCCONST);
 		break;
 	default:
 		local->count = 1 << (c - 1);
+		timer_set_delay_u64(&local->rtc_timer, (local->count) * RTCCONST);
 		break;
     }
 }
@@ -523,20 +527,16 @@ timer_intr(void *priv)
     nvr_t *nvr = (nvr_t *)priv;
     local_t *local = (local_t *)nvr->data;
 
-    timer_advance_u64(&local->rtc_timer, RTCCONST);
-
     if (local->state == 1) {
-	if (--local->count == 0) {
-		timer_load_count(nvr);
+	timer_load_count(nvr);
 
-		nvr->regs[RTC_REGC] |= REGC_PF;
-		if (nvr->regs[RTC_REGB] & REGB_PIE) {
-			nvr->regs[RTC_REGC] |= REGC_IRQF;
+	nvr->regs[RTC_REGC] |= REGC_PF;
+	if (nvr->regs[RTC_REGB] & REGB_PIE) {
+		nvr->regs[RTC_REGC] |= REGC_IRQF;
 
-			/* Generate an interrupt. */
-			if (nvr->irq != -1)
-				picint(1 << nvr->irq);
-		}
+		/* Generate an interrupt. */
+		if (nvr->irq != -1)
+			picint(1 << nvr->irq);
 	}
     }
 }
@@ -809,6 +809,7 @@ nvr_read(uint16_t addr, void *priv)
     return(ret);
 }
 
+
 /* Secondary NVR write - used by SMC. */
 static void
 nvr_sec_write(uint16_t addr, uint8_t val, void *priv)
@@ -824,6 +825,7 @@ nvr_sec_read(uint16_t addr, void *priv)
     return nvr_read(0x72 + (addr & 1), priv);
 }
 
+
 /* Reset the RTC state to 1980/01/01 00:00. */
 static void
 nvr_reset(nvr_t *nvr)
@@ -883,8 +885,7 @@ nvr_at_speed_changed(void *priv)
     nvr_t *nvr = (nvr_t *) priv;
     local_t *local = (local_t *) nvr->data;
 
-    timer_disable(&local->rtc_timer);
-    timer_set_delay_u64(&local->rtc_timer, RTCCONST);
+    timer_load_count(nvr);
 
     timer_disable(&local->update_timer);
     if (local->ecount > 0ULL)
@@ -1081,7 +1082,6 @@ nvr_at_init(const device_t *info)
 		nvr->regs[RTC_REGA] = (nvr->regs[RTC_REGA] & 0x8f) | 0x20;
 	nvr_at_reset(nvr);
 	timer_load_count(nvr);
-	timer_set_delay_u64(&local->rtc_timer, RTCCONST);
 
 	/* Set up the I/O handler for this device. */
 	io_sethandler(0x0070, 2,

src/pic.c

@@ -223,7 +223,7 @@ find_best_interrupt(pic_t *dev)
 		intr += 8;
 
 	if (cpu_fast_off_flags & (1u << intr))
-		cpu_fast_off_count = cpu_fast_off_val + 1;
+		cpu_fast_off_advance();
     }
 
     return ret;
@@ -608,7 +608,7 @@ picint_common(uint16_t num, int level, int set)
 
     if (set) {
 	if (smi_irq_mask & num) {
-		smi_line = 1;
+		smi_raise();
 		smi_irq_status |= num;
 	}
 

src/pit.c

@@ -1039,7 +1039,6 @@ pit_set_clock(int clock)
     VGACONST1 = (uint64_t) (cpuclock / 25175000.0 * (double)(1ull << 32));
     VGACONST2 = (uint64_t) (cpuclock / 28322000.0 * (double)(1ull << 32));
     RTCCONST = (uint64_t) (cpuclock / 32768.0 * (double)(1ull << 32));
-    ACPICONST = (uint64_t) (cpuclock / 3579545.0 * (double)(1ull << 32));
 
     TIMER_USEC = (uint64_t)((cpuclock / 1000000.0) * (double)(1ull << 32));
 

src/sound/snd_audiopci.c

@@ -306,7 +306,9 @@ es1371_reset(void *p)
     es1371_t *dev = (es1371_t *) p;
     int       i;
 
+#ifdef OLD_NMI_BEHAVIOR
     nmi = 0;
+#endif
 
     /* Interrupt/Chip Select Control Register, Address 00H
        Addressable as byte, word, longword */
@@ -1240,7 +1242,7 @@ capture_event(es1371_t *dev, int type, int rw, uint16_t port)
         dev->legacy_ctrl &= ~LEGACY_EVENT_TYPE_RW;
     dev->legacy_ctrl |= ((port << LEGACY_EVENT_ADDR_SHIFT) & LEGACY_EVENT_ADDR_MASK);
     dev->legacy_ctrl &= ~LEGACY_INT;
-    nmi = 1;
+    nmi_raise();
 }
 
 static void

src/sound/snd_gus.c

@@ -452,11 +452,15 @@ writegus(uint16_t addr, uint8_t val, void *p)
                         gus->irqstatus &= ~8;
                     if (!(val & 0x20)) {
                         gus->ad_status &= ~0x18;
+#ifdef OLD_NMI_BEHAVIOR
                         nmi = 0;
+#endif
                     }
                     if (!(val & 0x02)) {
                         gus->ad_status &= ~0x01;
+#ifdef OLD_NMI_BEHAVIOR
                         nmi = 0;
+#endif
                     }
                     gus->tctrl   = val;
                     gus->sb_ctrl = val;
@@ -492,7 +496,7 @@ writegus(uint16_t addr, uint8_t val, void *p)
                 gus->ad_status |= 0x01;
                 if (gus->sb_ctrl & 0x02) {
                     if (gus->sb_nmi)
-                        nmi = 1;
+                        nmi_raise();
                     else if (gus->irq != -1)
                         picint(1 << gus->irq);
                 }
@@ -568,7 +572,7 @@ writegus(uint16_t addr, uint8_t val, void *p)
             gus->ad_status |= 0x08;
             if (gus->sb_ctrl & 0x20) {
                 if (gus->sb_nmi)
-                    nmi = 1;
+                    nmi_raise();
                 else if (gus->irq != -1)
                     picint(1 << gus->irq);
             }
@@ -580,7 +584,7 @@ writegus(uint16_t addr, uint8_t val, void *p)
             gus->ad_status |= 0x10;
             if (gus->sb_ctrl & 0x20) {
                 if (gus->sb_nmi)
-                    nmi = 1;
+                    nmi_raise();
                 else if (gus->irq != -1)
                     picint(1 << gus->irq);
             }
@@ -832,7 +836,9 @@ readgus(uint16_t addr, void *p)
 
         case 0x209:
             gus->ad_status &= ~0x01;
+#ifdef OLD_NMI_BEHAVIOR
             nmi = 0;
+#endif
             /*FALLTHROUGH*/
         case 0x389:
             val = gus->ad_data;

src/usb.c

@@ -173,7 +173,7 @@ ohci_mmio_write(uint32_t addr, uint8_t val, void *p)
     		if (val & 0x08) {
     			dev->ohci_mmio[0x0f] = 0x40;
 			if ((dev->ohci_mmio[0x13] & 0xc0) == 0xc0)
-				smi_line = 1;
+				smi_raise();
 		}
 
     		/* bit HostControllerReset must be cleared for the controller to be seen as initialized */

src/video/vid_sigma.c

@@ -208,7 +208,7 @@ sigma_out(uint16_t addr, uint8_t val, void *p)
 	/* If set to NMI on video I/O... */
 	if (sigma->enable_nmi && (sigma->sigma_ctl & CTL_NMI)) {
 		sigma->lastport |= 0x80; 	/* Card raised NMI */
-		nmi = 1;
+		nmi_raise();
 	}
 	/* For CRTC emulation, the card BIOS sets the value to be
 	 * read from port 0x3D1 like this */
@@ -245,7 +245,9 @@ sigma_out(uint16_t addr, uint8_t val, void *p)
 		sigma->lastport &= 0x7F;
 		return;
 	case 0x2DC:	/* Reset NMI */
+#ifdef OLD_NMI_BEHAVIOR
 		nmi = 0;
+#endif
 		sigma->lastport &= 0x7F;
 		return;
 	case 0x2DD:	/* Page in RAM at 0xC1800 */