Sierra RAMDAC now correctly ignores writes of 0xFF to the command register;

BT485 dummy code now passes reads and writes to the generic SVGA handler;
Minor S3 changes;
ATI Mach64/GX now has an 8 MB RAM option.
This commit is contained in:
OBattler
2016-07-25 01:15:51 +02:00
parent 9190c42123
commit ff7e0880d1
5 changed files with 22 additions and 19 deletions

View File

@@ -921,7 +921,9 @@ uint8_t s3_in(uint16_t addr, void *p)
switch (svga->crtcreg)
{
case 0x2d: return 0x88; /*Extended chip ID*/
case 0x2e: return s3->id_ext; /*New chip ID*/
case 0x2e:
if ((s3->chip != S3_TRIO32) && (s3->chip != S3_TRIO64)) return 0xFF;
return s3->id_ext; /*New chip ID*/
case 0x2f: return 0; /*Revision level*/
case 0x30: return s3->id; /*Chip ID*/
case 0x31: return (svga->crtc[0x31] & 0xcf) | ((s3->ma_ext & 3) << 4);
@@ -2493,18 +2495,10 @@ static device_config_t s3_miro_vision964_config[] =
.description = "2 MB",
.value = 2
},
{
.description = "3 MB",
.value = 2
},
{
.description = "4 MB",
.value = 4
},
{
.description = "6 MB",
.value = 4
},
{
.description = "8 MB",
.value = 8