OBattler
72c1c36ec6
OPTi 5x7 no longer does excess logging, running of timers on the recompiler is now done on every fourth AT KBC port 61h read instead of every 3F4h read, added some safety precautions to io.c to handle the cases where a handler removes itself, implmented the STPC ELCR and refresh control, and fixed the messed up register reading in the PC87307 and PC87309 implementations.
2020-07-10 02:05:49 +02:00
OBattler
39a46797d2
Fixed shadowing on the OPTi 82c5x7, OPTi 82c495 now has Port 92h, and implemented the OPTi 82c611/611A VLB IDE controlled required by the Excalibur.
2020-07-07 20:43:28 +02:00
nerd73
546f0a83e7
Implement C0000-DFFFF shadowing on the OPTi 5x7 chipset
2020-06-29 22:06:27 -06:00
nerd73
09ffa05f89
Improvements to the OPTi 597 machine.
...
- Add emulation of the FDC37C661 Super I/O
- Fix Pentium VLB timing (was running VLB at 2x bus speed instead of 1/2 bus speed)
- Fix the cache register on the OPTi 5x7 chipset
- The actual minimum RAM amount is 2 MB, not 1 MB.
- Fix chipset naming consistency
2020-06-23 15:04:10 -06:00
nerd73
51572530ff
Remove waitstates from register 02.
2020-06-05 10:28:03 -06:00
nerd73
3f0adb5211
Add the AMI Excalibur, a VLB OPTi 596/597 machine.
...
Also adds emulation of the OPTi 5x7 chipset, and introduces a clock divider for VLB on 64-bit bus systems.
2020-06-05 10:22:59 -06:00
