OBattler
12e4d1b083
SoftFloat: Correctly treat +INF and -INF as equal on 8087 and 287, fixes 287 detection in MCPDiag.
2024-03-26 23:29:06 +01:00
OBattler
0b0cb84bf7
FPU: Re-enabled SoftFloat on 808x and implement the missing FBLD instruction, closes #4300 .
2024-03-25 19:59:26 +01:00
OBattler
244038b84c
LOCK: It is sometimes legal when cpu_mod == 3, fixes hangs with Compaq Portable III 386 TEST.
2024-03-03 21:24:00 +01:00
OBattler
71ecdc1b55
No longer raise TS# when (CS & 0xFFF8) is zero and (CS & 0x0004) is not, fixes #4214 .
2024-02-29 06:52:45 +01:00
OBattler
6de7c7cd5e
Fixed LOCK legality with prefixes, closes #4189 .
2024-02-23 07:10:15 +01:00
OBattler
fcabd353d9
Check IOPL on 286 task segments.
2024-02-22 00:56:28 +01:00
OBattler
733c26d04a
Return no mask when the TSS type is 286, closes #4177 .
2024-02-19 19:09:35 +01:00
OBattler
e3e30e7536
Fixed a very stupid typo in the 286/386 version of the LOCK instruction that was breaking OS/2 Warp 3.0.
2024-02-19 15:41:49 +01:00
OBattler
19f6954410
Reverted some CPU-related changes.
2024-02-19 15:20:59 +01:00
Miran Grča
f7c995738c
Fixed a bug in the 386 implementation of LOCK.
2024-02-14 02:29:31 +01:00
OBattler
2ab99dda0b
Made LOCK instruction legality more accurate on 386, closes #4132 .
2024-02-10 03:05:56 +01:00
OBattler
3f8952a558
More (S)VGA horizontal blanking fixes and CPU CR0 bit 4 fixes.
2024-02-09 18:02:33 +01:00
OBattler
30e7a49558
Fix compile-breaking mistakes in cpu/386.c.
2024-02-09 12:15:28 +01:00
OBattler
5a3d74d64f
286/386 interpreter fixes - the correct opcode arrays are now used and fixed the debug registers.
2024-02-09 12:14:35 +01:00
Alexander Babikov
996769095b
Implement most missing P6 MSRs
...
Remove the 6 extraneous performance counter MSRs which
haven't existed on P6
2024-02-07 12:31:43 +05:00
Alexander Babikov
e54b57641c
Implement missing IBM, AMD and Cyrix MSRs
2024-02-07 12:31:42 +05:00
Alexander Babikov
65f40ca71d
Implement missing WinChip C6/2 and Cyrix III MSRs
2024-02-07 12:31:42 +05:00
Alexander Babikov
1b9bf568f2
Implement missing Pentium MSRs
...
Includes obscure behavior, like undocumented "high" MSRs
2024-02-07 12:31:41 +05:00
Alexander Babikov
8143ccdc9b
K5 reorganization
...
Rename SSA/5 to Model 0 and 5k86 to Model 1/2/3 and swap their ordering
Remove the Model 0 CPUs from the Model 1 (5k86) table
2024-02-07 12:31:40 +05:00
Alexander Babikov
8520e6be85
Show actual clocks for CPUs w/ Performance Ratings
2024-02-07 12:31:40 +05:00
Alexander Babikov
2a3d13d306
Various consistency changes
2024-02-07 12:31:39 +05:00
Alexander Babikov
1e4455d98c
Add comments with MSR and CPUID flag names
...
Reorganize the MSR struct
2024-02-07 12:31:38 +05:00
Alexander Babikov
b860156350
Remove an accidentally committed duplicate file
2024-02-07 12:31:38 +05:00
Alexander Babikov
1bb31f3937
Remove the AP61 hack completely
...
It's no longer needed
2024-02-07 12:31:37 +05:00
Alexander Babikov
963525ff2e
Correct the CPUID SEP bit on AMD K6-2 and later
...
They use the standard bit 11, not he AMD-specific bit 10
2024-02-07 12:31:37 +05:00
Alexander Babikov
aef257378e
Add PGE to AMD K5 and K6-2C/III/2+/III+
2024-02-07 12:31:36 +05:00
Alexander Babikov
37cf0b6845
Separate Pentium and Cx6x86 MSR handling
2024-02-07 12:31:35 +05:00
Alexander Babikov
a1540eee92
Remove the machine check CPUID flag from the P24T
2024-02-07 12:31:35 +05:00
Alexander Babikov
032a161c4a
Implement IDT/VIA FCR2 CPUID family/model spoofing
2024-02-07 12:31:34 +05:00
Alexander Babikov
2da7b196ac
Rename unnamed MSR vars to real names where known
2024-02-07 12:31:34 +05:00
OBattler
ecd90616f1
Removed an unnecessary CPU operations table.
2024-02-06 19:51:02 +01:00
OBattler
cbf1749a25
Fixed the reported CPU inacuracies, closes #4121 .
2024-02-06 19:50:21 +01:00
Alexander Babikov
68a73dffe0
Give the Compaq Deskpro 386 its own set of CPUs
...
Both BIOSes can now take a 16, 20 or 25 MHz 386DX,
with the 16 MHz one paired with a 287 FPU.
Also remove unused CPU packages from the enum
2024-02-05 03:22:54 +05:00
Alexander Babikov
795e1bce23
Change CR0 bit 4 behavior:
...
Now it's always hardcoded to 1, unless the CPU
is 386DX with no or 287 FPU
2024-02-05 03:22:52 +05:00
Alexander Babikov
d7e125c16e
Migrate configs for the Gigabyte Socket 4/5 machines ( #4111 )
...
* Bring back machine migration
And add migration for the Gigabyte Socket 4 and 5 machines
* Fix the GA-586IS's internal name
* Remove legacy CPU tables for very old builds
Since backward compatibility with pre-build 2654 configs has been
removed, remove forward compatibility with these builds as well
2024-02-03 16:08:18 -03:00
OBattler
91494bab97
808x: Fix the flags at the end of the ADC and SBB instructions, fixes #4103 .
2024-02-03 04:33:42 +01:00
OBattler
3ceda105ef
ALi M6117 CPU fixes.
2024-02-02 05:31:33 +01:00
OBattler
0a5d25fdde
Memory: Disable _mem_exec in phys() accesses when not using the 486+ interpreter or dynamic recompiler, and write protect support in preparation for the WD76C10 rewrite.
2024-02-02 05:25:40 +01:00
OBattler
cd03b6a31c
Packard Bell machines: PS/2 mouse commands now suspend dynamic recompilation until the response byte is read, fixes #552 .
2024-01-25 21:47:15 +01:00
OBattler
9107c2fa25
Added the AOpen AP61 and fixed floppies on the LG IBM 440 FX.
2024-01-24 04:56:31 +01:00
OBattler
bd2ef6855a
A CPU change in preparation for the AOpen AP61.
2024-01-21 20:21:52 +01:00
OBattler
2cbfc8e047
808x: Clear prefetch queue on soft reset, fixes the CTRL+ALT+DEL hang on Amstrad 808x machines, fixes #408 .
2024-01-15 04:32:52 +01:00
OBattler
f2971a132f
Disable the debug registers on 486+.
2024-01-14 21:47:52 +01:00
Cacodemon345
d8330a0c46
No need to translate EIP
2024-01-15 02:14:00 +06:00
Cacodemon345
a7be107e9b
Fix address compare
2024-01-15 01:22:50 +06:00
Cacodemon345
911deeab1a
Fix single-step trap flag setting
2024-01-15 01:09:52 +06:00
Cacodemon345
8c6fc11bb2
Fix TSS trap-bit handling
2024-01-15 00:05:48 +06:00
Cacodemon345
128a2f2b5d
And finally exec386
2024-01-14 21:21:02 +06:00
Cacodemon345
b884ef825c
And 386.c
2024-01-14 20:58:29 +06:00
Cacodemon345
55f03f63e5
More oversight fixing
2024-01-14 20:12:53 +06:00
