Some dynarec backends (x86-64, arm64) expect the offset between cpu_state and CR0 to within a certain limit, otherwise they crashes (e.g: "host_x86_MOV64_REG_ABS - out of range").
Move CR0 to the end of cpu_state, make sure the offset is within limit.
Helps NT4 and Win95 with dynarec on.
- Disabled the 'is486' flag and moved them to 386 timings
- Disabled cache on startup, enable-able later
- RapidCAD fixes (permanently disable L1, correct EDX reset)
Now Slot1 motherboards can access the Celeron processors at the Intel/PGA370 category
Added the Packard Bell Bora Pro. A 440ZX based AMI board. It's just a MSI 6168 with the AMI PB OEM BIOS slapped in it. It reports excessive amounts of RAM and also looks for an SDRAM serial(which is not a huge deal).
Roms can be found on the roms PR
This adds preliminary emulation of the first-gen Samuel core, used in the VIA Cyrix III CPU, at clock speeds from 66 to 700 MHz. This also moves the 440BX emulation out of the dev-branch.
Things working:
- CPUID
- Windows 98SE
- Timings seem identical between WinChip/W2's integer section and this
Things left to do:
- 3DNow on old dynarec
- Half-speed FPU (currently simulated with WinChip 1 timings instead of WinChip 2)
